sound/soc/codecs/ac108.h

   1 /*
   2  * ac108.h --  ac108 ALSA Soc Audio driver
   3  *
   4  * Author: panjunwen
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #ifndef _AC108_H
  13 #define _AC108_H
  14
  15
  16 /*** AC108 Codec Register Define***/
  17
  18 //Chip Reset
  19 #define CHIP_RST                        0x00
  20 #define CHIP_RST_VAL            0x12
  21
  22 //Power Control
  23 #define PWR_CTRL1                       0x01
  24 #define PWR_CTRL2                       0x02
  25 #define PWR_CTRL3                       0x03
  26 #define PWR_CTRL4                       0x04
  27 #define PWR_CTRL5                       0x05
  28 #define PWR_CTRL6                       0x06
  29 #define PWR_CTRL7                       0x07
  30 #define PWR_CTRL8                       0x08
  31 #define PWR_CTRL9                       0x09
  32
  33 //PLL Configure Control
  34 #define PLL_CTRL1                       0x10
  35 #define PLL_CTRL2                       0x11
  36 #define PLL_CTRL3                       0x12
  37 #define PLL_CTRL4                       0x13
  38 #define PLL_CTRL5                       0x14
  39 #define PLL_CTRL6                       0x16
  40 #define PLL_CTRL7                       0x17
  41 #define PLL_LOCK_CTRL           0x18
  42
  43 //System Clock Control
  44 #define SYSCLK_CTRL                     0x20
  45 #define MOD_CLK_EN                      0x21
  46 #define MOD_RST_CTRL            0x22
  47 #define DSM_CLK_CTRL            0x25
  48
  49 //I2S Common Control
  50 #define I2S_CTRL                        0x30
  51 #define I2S_BCLK_CTRL           0x31
  52 #define I2S_LRCK_CTRL1          0x32
  53 #define I2S_LRCK_CTRL2          0x33
  54 #define I2S_FMT_CTRL1           0x34
  55 #define I2S_FMT_CTRL2           0x35
  56 #define I2S_FMT_CTRL3           0x36
  57
  58 //I2S TX1 Control
  59 #define I2S_TX1_CTRL1           0x38
  60 #define I2S_TX1_CTRL2           0x39
  61 #define I2S_TX1_CTRL3           0x3A
  62 #define I2S_TX1_CHMP_CTRL1      0x3C
  63 #define I2S_TX1_CHMP_CTRL2      0x3D
  64 #define I2S_TX1_CHMP_CTRL3      0x3E
  65 #define I2S_TX1_CHMP_CTRL4      0x3F
  66
  67 //I2S TX2 Control
  68 #define I2S_TX2_CTRL1           0x40
  69 #define I2S_TX2_CTRL2           0x41
  70 #define I2S_TX2_CTRL3           0x42
  71 #define I2S_TX2_CHMP_CTRL1      0x44
  72 #define I2S_TX2_CHMP_CTRL2      0x45
  73 #define I2S_TX2_CHMP_CTRL3      0x46
  74 #define I2S_TX2_CHMP_CTRL4      0x47
  75
  76 //I2S RX1 Control
  77 #define I2S_RX1_CTRL1           0x50
  78 #define I2S_RX1_CHMP_CTRL1      0x54
  79 #define I2S_RX1_CHMP_CTRL2      0x55
  80 #define I2S_RX1_CHMP_CTRL3      0x56
  81 #define I2S_RX1_CHMP_CTRL4      0x57
  82
  83 //I2S Loopback Debug
  84 #define I2S_LPB_DEBUG           0x58
  85
  86 //ADC Common Control
  87 #define ADC_SPRC                        0x60
  88 #define ADC_DIG_EN                      0x61
  89 #define DMIC_EN                         0x62
  90 #define ADC_DSR                         0x63
  91 #define ADC_FIR                         0x64
  92 #define ADC_DDT_CTRL            0x65
  93
  94 //HPF Control
  95 #define HPF_EN                          0x66
  96 #define HPF_COEF_REGH1          0x67
  97 #define HPF_COEF_REGH2          0x68
  98 #define HPF_COEF_REGL1          0x69
  99 #define HPF_COEF_REGL2          0x6A
 100 #define HPF_GAIN_REGH1          0x6B
 101 #define HPF_GAIN_REGH2          0x6C
 102 #define HPF_GAIN_REGL1          0x6D
 103 #define HPF_GAIN_REGL2          0x6E
 104
 105 //ADC Digital Channel Volume Control
 106 #define ADC1_DVOL_CTRL          0x70
 107 #define ADC2_DVOL_CTRL          0x71
 108 #define ADC3_DVOL_CTRL          0x72
 109 #define ADC4_DVOL_CTRL          0x73
 110
 111 //ADC Digital Mixer Source and Gain Control
 112 #define ADC1_DMIX_SRC           0x76
 113 #define ADC2_DMIX_SRC           0x77
 114 #define ADC3_DMIX_SRC           0x78
 115 #define ADC4_DMIX_SRC           0x79
 116
 117 //ADC Digital Debug Control
 118 #define ADC_DIG_DEBUG           0x7F
 119
 120 //I2S Pad Drive Control
 121 #define I2S_DAT_PADDRV_CTRL     0x80
 122 #define I2S_CLK_PADDRV_CTRL     0x81
 123
 124 //Analog PGA Control
 125 #define ANA_PGA1_CTRL           0x90
 126 #define ANA_PGA2_CTRL           0x91
 127 #define ANA_PGA3_CTRL           0x92
 128 #define ANA_PGA4_CTRL           0x93
 129
 130 //MIC Offset Control
 131 #define MIC_OFFSET_CTRL1        0x96
 132 #define MIC_OFFSET_CTRL2        0x97
 133 #define MIC1_OFFSET_STATU1      0x98
 134 #define MIC1_OFFSET_STATU2      0x99
 135 #define MIC2_OFFSET_STATU1      0x9A
 136 #define MIC2_OFFSET_STATU2      0x9B
 137 #define MIC3_OFFSET_STATU1      0x9C
 138 #define MIC3_OFFSET_STATU2      0x9D
 139 #define MIC4_OFFSET_STATU1      0x9E
 140 #define MIC4_OFFSET_STATU2      0x9F
 141
 142 //ADC1 Analog Control
 143 #define ANA_ADC1_CTRL1          0xA0
 144 #define ANA_ADC1_CTRL2          0xA1
 145 #define ANA_ADC1_CTRL3          0xA2
 146 #define ANA_ADC1_CTRL4          0xA3
 147 #define ANA_ADC1_CTRL5          0xA4
 148 #define ANA_ADC1_CTRL6          0xA5
 149 #define ANA_ADC1_CTRL7          0xA6
 150
 151 //ADC2 Analog Control
 152 #define ANA_ADC2_CTRL1          0xA7
 153 #define ANA_ADC2_CTRL2          0xA8
 154 #define ANA_ADC2_CTRL3          0xA9
 155 #define ANA_ADC2_CTRL4          0xAA
 156 #define ANA_ADC2_CTRL5          0xAB
 157 #define ANA_ADC2_CTRL6          0xAC
 158 #define ANA_ADC2_CTRL7          0xAD
 159
 160 //ADC3 Analog Control
 161 #define ANA_ADC3_CTRL1          0xAE
 162 #define ANA_ADC3_CTRL2          0xAF
 163 #define ANA_ADC3_CTRL3          0xB0
 164 #define ANA_ADC3_CTRL4          0xB1
 165 #define ANA_ADC3_CTRL5          0xB2
 166 #define ANA_ADC3_CTRL6          0xB3
 167 #define ANA_ADC3_CTRL7          0xB4
 168
 169 //ADC4 Analog Control
 170 #define ANA_ADC4_CTRL1          0xB5
 171 #define ANA_ADC4_CTRL2          0xB6
 172 #define ANA_ADC4_CTRL3          0xB7
 173 #define ANA_ADC4_CTRL4          0xB8
 174 #define ANA_ADC4_CTRL5          0xB9
 175 #define ANA_ADC4_CTRL6          0xBA
 176 #define ANA_ADC4_CTRL7          0xBB
 177
 178 //GPIO Configure
 179 #define GPIO_CFG1                       0xC0
 180 #define GPIO_CFG2                       0xC1
 181 #define GPIO_DAT                        0xC2
 182 #define GPIO_DRV                        0xC3
 183 #define GPIO_PULL                       0xC4
 184 #define GPIO_INT_CFG            0xC5
 185 #define GPIO_INT_EN                     0xC6
 186 #define GPIO_INT_STATUS         0xC7
 187
 188 //Misc
 189 #define BGTC_DAT                        0xD1
 190 #define BGVC_DAT                        0xD2
 191 #define PRNG_CLK_CTRL           0xDF
 192
 193
 194
 195 /*** AC108 Codec Register Bit Define***/
 196
 197 /*PWR_CTRL1*/
 198 #define CP12_CTRL                               4
 199 #define CP12_SENSE_SELECT               3
 200
 201 /*PWR_CTRL2*/
 202 #define CP12_SENSE_FILT                 6
 203 #define CP12_COMP_FF_EN                 3
 204 #define CP12_FORCE_ENABLE               2
 205 #define CP12_FORCE_RSTB                 1
 206
 207 /*PWR_CTRL3*/
 208 #define LDO33DIG_CTRL                   0
 209
 210 /*PWR_CTRL6*/
 211 #define LDO33ANA_2XHDRM                 2
 212 #define LDO33ANA_ENABLE                 0
 213
 214 /*PWR_CTRL7*/
 215 #define VREF_SEL                                3
 216 #define VREF_FASTSTART_ENABLE   1
 217 #define VREF_ENABLE                             0
 218
 219 /*PWR_CTRL9*/
 220 #define VREFP_FASTSTART_ENABLE  7
 221 #define VREFP_RESCTRL                   5
 222 #define VREFP_LPMODE                    4
 223 #define IGEN_TRIM                               1
 224 #define VREFP_ENABLE                    0
 225
 226
 227 /*PLL_CTRL1*/
 228 #define PLL_IBIAS                               4
 229 #define PLL_NDET                                3
 230 #define PLL_LOCKED_STATUS               2
 231 #define PLL_COM_EN                              1
 232 #define PLL_EN                                  0
 233
 234 /*PLL_CTRL2*/
 235 #define PLL_PREDIV2                             5
 236 #define PLL_PREDIV1                             0
 237
 238 /*PLL_CTRL3*/
 239 #define PLL_LOOPDIV_MSB                 0
 240
 241 /*PLL_CTRL4*/
 242 #define PLL_LOOPDIV_LSB                 0
 243
 244 /*PLL_CTRL5*/
 245 #define PLL_POSTDIV2                    5
 246 #define PLL_POSTDIV1                    0
 247
 248 /*PLL_CTRL6*/
 249 #define PLL_LDO                                 6
 250 #define PLL_CP                                  0
 251
 252 /*PLL_CTRL7*/
 253 #define PLL_CAP                                 6
 254 #define PLL_RES                                 4
 255 #define PLL_TEST_EN                             0
 256
 257 /*PLL_LOCK_CTRL*/
 258 #define LOCK_LEVEL1                             2
 259 #define LOCK_LEVEL2                             1
 260 #define PLL_LOCK_EN                             0
 261
 262
 263 /*SYSCLK_CTRL*/
 264 #define PLLCLK_EN                               7
 265 #define PLLCLK_SRC                              4
 266 #define SYSCLK_SRC                              3
 267 #define SYSCLK_EN                               0
 268
 269 /*MOD_CLK_EN & MOD_RST_CTRL*/
 270 #define I2S                                             7
 271 #define ADC_DIGITAL                             4
 272 #define MIC_OFFSET_CALIBRATION  1
 273 #define ADC_ANALOG                              0
 274
 275 /*DSM_CLK_CTRL*/
 276 #define MIC_OFFSET_DIV                  4
 277 #define DSM_CLK_SEL                             0
 278
 279
 280 /*I2S_CTRL*/
 281 #define BCLK_IOEN                               7
 282 #define LRCK_IOEN                               6
 283 #define SDO2_EN                                 5
 284 #define SDO1_EN                                 4
 285 #define TXEN                                    2
 286 #define RXEN                                    1
 287 #define GEN                                             0
 288
 289 /*I2S_BCLK_CTRL*/
 290 #define EDGE_TRANSFER                   5
 291 #define BCLK_POLARITY                   4
 292 #define BCLKDIV                                 0
 293
 294 /*I2S_LRCK_CTRL1*/
 295 #define LRCK_POLARITY                   4
 296 #define LRCK_PERIODH                    0
 297
 298 /*I2S_LRCK_CTRL2*/
 299 #define LRCK_PERIODL                    0
 300
 301 /*I2S_FMT_CTRL1*/
 302 #define ENCD_SEL                                6
 303 #define MODE_SEL                                4
 304 #define TX2_OFFSET                              3
 305 #define TX1_OFFSET                              2
 306 #define TX_SLOT_HIZ                             1
 307 #define TX_STATE                                0
 308
 309 /*I2S_FMT_CTRL2*/
 310 #define SLOT_WIDTH_SEL                  4
 311 #define SAMPLE_RESOLUTION               0
 312
 313 /*I2S_FMT_CTRL3*/
 314 #define TX_MLS                                  7
 315 #define SEXT                                    5
 316 #define OUT2_MUTE                               4
 317 #define OUT1_MUTE                               3
 318 #define LRCK_WIDTH                              2
 319 #define TX_PDM                                  0
 320
 321
 322 /*I2S_TX1_CTRL1*/
 323 #define TX1_CHSEL                               0
 324
 325 /*I2S_TX1_CTRL2*/
 326 #define TX1_CH8_EN                              7
 327 #define TX1_CH7_EN                              6
 328 #define TX1_CH6_EN                              5
 329 #define TX1_CH5_EN                              4
 330 #define TX1_CH4_EN                              3
 331 #define TX1_CH3_EN                              2
 332 #define TX1_CH2_EN                              1
 333 #define TX1_CH1_EN                              0
 334
 335 /*I2S_TX1_CTRL3*/
 336 #define TX1_CH16_EN                             7
 337 #define TX1_CH15_EN                             6
 338 #define TX1_CH14_EN                             5
 339 #define TX1_CH13_EN                             4
 340 #define TX1_CH12_EN                             3
 341 #define TX1_CH11_EN                             2
 342 #define TX1_CH10_EN                             1
 343 #define TX1_CH9_EN                              0
 344
 345 /*I2S_TX1_CHMP_CTRL1*/
 346 #define TX1_CH4_MAP                             6
 347 #define TX1_CH3_MAP                             4
 348 #define TX1_CH2_MAP                             2
 349 #define TX1_CH1_MAP                             0
 350
 351 /*I2S_TX1_CHMP_CTRL2*/
 352 #define TX1_CH8_MAP                             6
 353 #define TX1_CH7_MAP                             4
 354 #define TX1_CH6_MAP                             2
 355 #define TX1_CH5_MAP                             0
 356
 357 /*I2S_TX1_CHMP_CTRL3*/
 358 #define TX1_CH12_MAP                    6
 359 #define TX1_CH11_MAP                    4
 360 #define TX1_CH10_MAP                    2
 361 #define TX1_CH9_MAP                             0
 362
 363 /*I2S_TX1_CHMP_CTRL4*/
 364 #define TX1_CH16_MAP                    6
 365 #define TX1_CH15_MAP                    4
 366 #define TX1_CH14_MAP                    2
 367 #define TX1_CH13_MAP                    0
 368
 369
 370 /*I2S_TX2_CTRL1*/
 371 #define TX2_CHSEL                               0
 372
 373 /*I2S_TX2_CHMP_CTRL1*/
 374 #define TX2_CH4_MAP                             6
 375 #define TX2_CH3_MAP                             4
 376 #define TX2_CH2_MAP                             2
 377 #define TX2_CH1_MAP                             0
 378
 379 /*I2S_TX2_CHMP_CTRL2*/
 380 #define TX2_CH8_MAP                             6
 381 #define TX2_CH7_MAP                             4
 382 #define TX2_CH6_MAP                             2
 383 #define TX2_CH5_MAP                             0
 384
 385 /*I2S_TX2_CHMP_CTRL3*/
 386 #define TX2_CH12_MAP                    6
 387 #define TX2_CH11_MAP                    4
 388 #define TX2_CH10_MAP                    2
 389 #define TX2_CH9_MAP                             0
 390
 391 /*I2S_TX2_CHMP_CTRL4*/
 392 #define TX2_CH16_MAP                    6
 393 #define TX2_CH15_MAP                    4
 394 #define TX2_CH14_MAP                    2
 395 #define TX2_CH13_MAP                    0
 396
 397
 398 /*I2S_RX1_CTRL1*/
 399 #define RX1_CHSEL                               0
 400
 401 /*I2S_RX1_CHMP_CTRL1*/
 402 #define RX1_CH4_MAP                             6
 403 #define RX1_CH3_MAP                             4
 404 #define RX1_CH2_MAP                             2
 405 #define RX1_CH1_MAP                             0
 406
 407 /*I2S_RX1_CHMP_CTRL2*/
 408 #define RX1_CH8_MAP                             6
 409 #define RX1_CH7_MAP                             4
 410 #define RX1_CH6_MAP                             2
 411 #define RX1_CH5_MAP                             0
 412
 413 /*I2S_RX1_CHMP_CTRL3*/
 414 #define RX1_CH12_MAP                    6
 415 #define RX1_CH11_MAP                    4
 416 #define RX1_CH10_MAP                    2
 417 #define RX1_CH9_MAP                             0
 418
 419 /*I2S_RX1_CHMP_CTRL4*/
 420 #define RX1_CH16_MAP                    6
 421 #define RX1_CH15_MAP                    4
 422 #define RX1_CH14_MAP                    2
 423 #define RX1_CH13_MAP                    0
 424
 425
 426 /*I2S_LPB_DEBUG*/
 427 #define I2S_LPB_DEBUG_EN                0
 428
 429
 430 /*ADC_SPRC*/
 431 #define ADC_FS_I2S1                             0
 432
 433 /*ADC_DIG_EN*/
 434 #define DG_EN                                   4
 435 #define ENAD4                                   3
 436 #define ENAD3                                   2
 437 #define ENAD2                                   1
 438 #define ENAD1                                   0
 439
 440 /*DMIC_EN*/
 441 #define DMIC2_EN                                1
 442 #define DMIC1_EN                                0
 443
 444 /*ADC_DSR*/
 445 #define DIG_ADC4_SRS                    6
 446 #define DIG_ADC3_SRS                    4
 447 #define DIG_ADC2_SRS                    2
 448 #define DIG_ADC1_SRS                    0
 449
 450 /*ADC_DDT_CTRL*/
 451 #define ADOUT_DLY_EN                    2
 452 #define ADOUT_DTS                               0
 453
 454
 455 /*HPF_EN*/
 456 #define DIG_ADC4_HPF_EN                 3
 457 #define DIG_ADC3_HPF_EN                 2
 458 #define DIG_ADC2_HPF_EN                 1
 459 #define DIG_ADC1_HPF_EN                 0
 460
 461
 462 /*ADC1_DMIX_SRC*/
 463 #define ADC1_ADC4_DMXL_GC               7
 464 #define ADC1_ADC3_DMXL_GC               6
 465 #define ADC1_ADC2_DMXL_GC               5
 466 #define ADC1_ADC1_DMXL_GC               4
 467 #define ADC1_ADC4_DMXL_SRC              3
 468 #define ADC1_ADC3_DMXL_SRC              2
 469 #define ADC1_ADC2_DMXL_SRC              1
 470 #define ADC1_ADC1_DMXL_SRC              0
 471
 472 /*ADC2_DMIX_SRC*/
 473 #define ADC2_ADC4_DMXL_GC               7
 474 #define ADC2_ADC3_DMXL_GC               6
 475 #define ADC2_ADC2_DMXL_GC               5
 476 #define ADC2_ADC1_DMXL_GC               4
 477 #define ADC2_ADC4_DMXL_SRC              3
 478 #define ADC2_ADC3_DMXL_SRC              2
 479 #define ADC2_ADC2_DMXL_SRC              1
 480 #define ADC2_ADC1_DMXL_SRC              0
 481
 482 /*ADC3_DMIX_SRC*/
 483 #define ADC3_ADC4_DMXL_GC               7
 484 #define ADC3_ADC3_DMXL_GC               6
 485 #define ADC3_ADC2_DMXL_GC               5
 486 #define ADC3_ADC1_DMXL_GC               4
 487 #define ADC3_ADC4_DMXL_SRC              3
 488 #define ADC3_ADC3_DMXL_SRC              2
 489 #define ADC3_ADC2_DMXL_SRC              1
 490 #define ADC3_ADC1_DMXL_SRC              0
 491
 492 /*ADC4_DMIX_SRC*/
 493 #define ADC4_ADC4_DMXL_GC               7
 494 #define ADC4_ADC3_DMXL_GC               6
 495 #define ADC4_ADC2_DMXL_GC               5
 496 #define ADC4_ADC1_DMXL_GC               4
 497 #define ADC4_ADC4_DMXL_SRC              3
 498 #define ADC4_ADC3_DMXL_SRC              2
 499 #define ADC4_ADC2_DMXL_SRC              1
 500 #define ADC4_ADC1_DMXL_SRC              0
 501
 502
 503 /*ADC_DIG_DEBUG*/
 504 #define ADC_PTN_SEL                             0
 505
 506
 507 /*I2S_DAT_PADDRV_CTRL*/
 508 #define TX2_DAT_DRV                             4
 509 #define TX1_DAT_DRV                             0
 510
 511 /*I2S_CLK_PADDRV_CTRL*/
 512 #define LRCK_DRV                                4
 513 #define BCLK_DRV                                0
 514
 515
 516 /*ANA_PGA1_CTRL*/
 517 #define ADC1_ANALOG_PGA                 1
 518 #define ADC1_ANALOG_PGA_STEP    0
 519
 520 /*ANA_PGA2_CTRL*/
 521 #define ADC2_ANALOG_PGA                 1
 522 #define ADC2_ANALOG_PGA_STEP    0
 523
 524 /*ANA_PGA3_CTRL*/
 525 #define ADC3_ANALOG_PGA                 1
 526 #define ADC3_ANALOG_PGA_STEP    0
 527
 528 /*ANA_PGA4_CTRL*/
 529 #define ADC4_ANALOG_PGA                 1
 530 #define ADC4_ANALOG_PGA_STEP    0
 531
 532
 533 /*MIC_OFFSET_CTRL1*/
 534 #define MIC_OFFSET_CAL_EN4              3
 535 #define MIC_OFFSET_CAL_EN3              2
 536 #define MIC_OFFSET_CAL_EN2              1
 537 #define MIC_OFFSET_CAL_EN1              0
 538
 539 /*MIC_OFFSET_CTRL2*/
 540 #define MIC_OFFSET_CAL_GAIN             3
 541 #define MIC_OFFSET_CAL_CHANNEL  1
 542 #define MIC_OFFSET_CAL_EN_ONCE  0
 543
 544 /*MIC1_OFFSET_STATU1*/
 545 #define MIC1_OFFSET_CAL_DONE    7
 546 #define MIC1_OFFSET_CAL_RUN_STA 6
 547 #define MIC1_OFFSET_MSB                 0
 548
 549 /*MIC1_OFFSET_STATU2*/
 550 #define MIC1_OFFSET_LSB                 0
 551
 552 /*MIC2_OFFSET_STATU1*/
 553 #define MIC2_OFFSET_CAL_DONE    7
 554 #define MIC2_OFFSET_CAL_RUN_STA 6
 555 #define MIC2_OFFSET_MSB                 0
 556
 557 /*MIC2_OFFSET_STATU2*/
 558 #define MIC2_OFFSET_LSB                 0
 559
 560 /*MIC3_OFFSET_STATU1*/
 561 #define MIC3_OFFSET_CAL_DONE    7
 562 #define MIC3_OFFSET_CAL_RUN_STA 6
 563 #define MIC3_OFFSET_MSB                 0
 564
 565 /*MIC3_OFFSET_STATU2*/
 566 #define MIC3_OFFSET_LSB                 0
 567
 568 /*MIC4_OFFSET_STATU1*/
 569 #define MIC4_OFFSET_CAL_DONE    7
 570 #define MIC4_OFFSET_CAL_RUN_STA 6
 571 #define MIC4_OFFSET_MSB                 0
 572
 573 /*MIC4_OFFSET_STATU2*/
 574 #define MIC4_OFFSET_LSB                 0
 575
 576
 577 /*ANA_ADC1_CTRL1*/
 578 #define ADC1_PGA_BYPASS                 7
 579 #define ADC1_PGA_BYP_RCM                6
 580 #define ADC1_PGA_CTRL_RCM               4
 581 #define ADC1_PGA_MUTE                   3
 582 #define ADC1_DSM_ENABLE                 2
 583 #define ADC1_PGA_ENABLE                 1
 584 #define ADC1_MICBIAS_EN                 0
 585
 586 /*ANA_ADC1_CTRL3*/
 587 #define ADC1_ANA_CAL_EN                 5
 588 #define ADC1_SEL_OUT_EDGE               3
 589 #define ADC1_DSM_DISABLE                2
 590 #define ADC1_VREFP_DISABLE              1
 591 #define ADC1_AAF_DISABLE                0
 592
 593 /*ANA_ADC1_CTRL6*/
 594 #define PGA_CTRL_TC                             6
 595 #define PGA_CTRL_RC                             4
 596 #define PGA_CTRL_I_LIN                  2
 597 #define PGA_CTRL_I_IN                   0
 598
 599 /*ANA_ADC1_CTRL7*/
 600 #define PGA_CTRL_HI_Z                   7
 601 #define PGA_CTRL_SHORT_RF               6
 602 #define PGA_CTRL_VCM_VG                 4
 603 #define PGA_CTRL_VCM_IN                 0
 604
 605
 606 /*ANA_ADC2_CTRL1*/
 607 #define ADC2_PGA_BYPASS                 7
 608 #define ADC2_PGA_BYP_RCM                6
 609 #define ADC2_PGA_CTRL_RCM               4
 610 #define ADC2_PGA_MUTE                   3
 611 #define ADC2_DSM_ENABLE                 2
 612 #define ADC2_PGA_ENABLE                 1
 613 #define ADC2_MICBIAS_EN                 0
 614
 615 /*ANA_ADC2_CTRL3*/
 616 #define ADC2_ANA_CAL_EN                 5
 617 #define ADC2_SEL_OUT_EDGE               3
 618 #define ADC2_DSM_DISABLE                2
 619 #define ADC2_VREFP_DISABLE              1
 620 #define ADC2_AAF_DISABLE                0
 621
 622 /*ANA_ADC2_CTRL6*/
 623 #define PGA_CTRL_IBOOST                 7
 624 #define PGA_CTRL_IQCTRL                 6
 625 #define PGA_CTRL_OABIAS                 4
 626 #define PGA_CTRL_CMLP_DIS               3
 627 #define PGA_CTRL_PDB_RIN                2
 628 #define PGA_CTRL_PEAKDET                0
 629
 630 /*ANA_ADC2_CTRL7*/
 631 #define AAF_LPMODE_EN                   7
 632 #define AAF_STG2_IB_SEL                 4
 633 #define AAFDSM_IB_DIV2                  3
 634 #define AAF_STG1_IB_SEL                 0
 635
 636
 637 /*ANA_ADC3_CTRL1*/
 638 #define ADC3_PGA_BYPASS                 7
 639 #define ADC3_PGA_BYP_RCM                6
 640 #define ADC3_PGA_CTRL_RCM               4
 641 #define ADC3_PGA_MUTE                   3
 642 #define ADC3_DSM_ENABLE                 2
 643 #define ADC3_PGA_ENABLE                 1
 644 #define ADC3_MICBIAS_EN                 0
 645
 646 /*ANA_ADC3_CTRL3*/
 647 #define ADC3_ANA_CAL_EN                 5
 648 #define ADC3_INVERT_CLK                 4
 649 #define ADC3_SEL_OUT_EDGE               3
 650 #define ADC3_DSM_DISABLE                2
 651 #define ADC3_VREFP_DISABLE              1
 652 #define ADC3_AAF_DISABLE                0
 653
 654 /*ANA_ADC3_CTRL7*/
 655 #define DSM_COMP_IB_SEL                 6
 656 #define DSM_OTA_CTRL                    4
 657 #define DSM_LPMODE                              3
 658 #define DSM_OTA_IB_SEL                  0
 659
 660
 661 /*ANA_ADC4_CTRL1*/
 662 #define ADC4_PGA_BYPASS                 7
 663 #define ADC4_PGA_BYP_RCM                6
 664 #define ADC4_PGA_CTRL_RCM               4
 665 #define ADC4_PGA_MUTE                   3
 666 #define ADC4_DSM_ENABLE                 2
 667 #define ADC4_PGA_ENABLE                 1
 668 #define ADC4_MICBIAS_EN                 0
 669
 670 /*ANA_ADC4_CTRL3*/
 671 #define ADC4_ANA_CAL_EN                 5
 672 #define ADC4_SEL_OUT_EDGE               3
 673 #define ADC4_DSM_DISABLE                2
 674 #define ADC4_VREFP_DISABLE              1
 675 #define ADC4_AAF_DISABLE                0
 676
 677 /*ANA_ADC4_CTRL6*/
 678 #define DSM_DEMOFF                              5
 679 #define DSM_EN_DITHER                   4
 680 #define DSM_VREFP_LPMODE                2
 681 #define DSM_VREFP_OUTCTRL               0
 682
 683 /*ANA_ADC4_CTRL7*/
 684 #define CK8M_EN                                 5
 685 #define OSC_EN                                  4
 686 #define ADC4_CLK_GATING                 3
 687 #define ADC3_CLK_GATING                 2
 688 #define ADC2_CLK_GATING                 1
 689 #define ADC1_CLK_GATING                 0
 690
 691
 692 /*GPIO_CFG1*/
 693 #define GPIO2_SELECT                    4
 694 #define GPIO1_SELECT                    0
 695
 696 /*GPIO_CFG2*/
 697 #define GPIO4_SELECT                    4
 698 #define GPIO3_SELECT                    0
 699
 700 /*GPIO_DAT*///order???
 701 #define GPIO4_DAT                               3
 702 #define GPIO3_DAT                               2
 703 #define GPIO2_DAT                               1
 704 #define GPIO1_DAT                               0
 705
 706 /*GPIO_DRV*/
 707 #define GPIO4_DRV                               6
 708 #define GPIO3_DRV                               4
 709 #define GPIO2_DRV                               2
 710 #define GPIO1_DRV                               0
 711
 712 /*GPIO_PULL*/
 713 #define GPIO4_PULL                              6
 714 #define GPIO3_PULL                              4
 715 #define GPIO2_PULL                              2
 716 #define GPIO1_PULL                              0
 717
 718 /*GPIO_INT_CFG*/
 719 #define GPIO4_EINT_CFG                  6
 720 #define GPIO3_EINT_CFG                  4
 721 #define GPIO2_EINT_CFG                  2
 722 #define GPIO1_EINT_CFG                  0
 723
 724 /*GPIO_INT_EN*///order???
 725 #define GPIO4_EINT_EN                   3
 726 #define GPIO3_EINT_EN                   2
 727 #define GPIO2_EINT_EN                   1
 728 #define GPIO1_EINT_EN                   0
 729
 730 /*GPIO_INT_STATUS*///order???
 731 #define GPIO4_EINT_STA                  3
 732 #define GPIO3_EINT_STA                  2
 733 #define GPIO2_EINT_STA                  1
 734 #define GPIO1_EINT_STA                  0
 735
 736
 737 /*PRNG_CLK_CTRL*/
 738 #define PRNG_CLK_EN                             1
 739 #define PRNG_CLK_POS                    0
 740
 741
 742
 743 /*** Some Config Value ***/
 744
 745 //[SYSCLK_CTRL]: PLLCLK_SRC
 746 #define PLLCLK_SRC_MCLK                 0
 747 #define PLLCLK_SRC_BCLK                 1
 748 #define PLLCLK_SRC_GPIO2                2
 749 #define PLLCLK_SRC_GPIO3                3
 750
 751 //[SYSCLK_CTRL]: SYSCLK_SRC
 752 #define SYSCLK_SRC_MCLK                 0
 753 #define SYSCLK_SRC_PLL                  1
 754
 755 //I2S BCLK POLARITY Control
 756 #define BCLK_NORMAL_DRIVE_N_SAMPLE_P    0
 757 #define BCLK_INVERT_DRIVE_P_SAMPLE_N    1
 758
 759 //I2S LRCK POLARITY Control
 760 #define LRCK_LEFT_LOW_RIGHT_HIGH                0
 761 #define LRCK_LEFT_HIGH_RIGHT_LOW                1
 762
 763 //I2S Format Selection
 764 #define PCM_FORMAT                                              0
 765 #define LEFT_JUSTIFIED_FORMAT                   1
 766 #define RIGHT_JUSTIFIED_FORMAT                  2
 767
 768
 769 //I2S data protocol types
 770
 771 #define IS_ENCODING_MODE                 0
 772
 773 #endif
 774