4 * (C) Copyright 2017-2018
5 * Seeed Technology Co., Ltd. <www.seeedstudio.com>
7 * PeterYang <linsheng.yang@seeed.cc>
9 * (C) Copyright 2010-2017
10 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
11 * huangxin <huangxin@reuuimllatech.com>
13 * some simple description for this code
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
21 #ifndef __AC101_REGS_H__
22 #define __AC101_REGS_H__
33 #define CHIP_AUDIO_RST 0x0
36 #define SYSCLK_CTRL 0x3
37 #define MOD_CLK_ENA 0x4
38 #define MOD_RST_CTRL 0x5
39 #define AIF_SR_CTRL 0x6
41 #define AIF1_CLK_CTRL 0x10
42 #define AIF1_ADCDAT_CTRL 0x11
43 #define AIF1_DACDAT_CTRL 0x12
44 #define AIF1_MXR_SRC 0x13
45 #define AIF1_VOL_CTRL1 0x14
46 #define AIF1_VOL_CTRL2 0x15
47 #define AIF1_VOL_CTRL3 0x16
48 #define AIF1_VOL_CTRL4 0x17
49 #define AIF1_MXR_GAIN 0x18
50 #define AIF1_RXD_CTRL 0x19
51 #define ADC_DIG_CTRL 0x40
52 #define ADC_VOL_CTRL 0x41
53 #define ADC_DBG_CTRL 0x42
55 #define HMIC_CTRL1 0x44
56 #define HMIC_CTRL2 0x45
59 #define DAC_DIG_CTRL 0x48
60 #define DAC_VOL_CTRL 0x49
61 #define DAC_DBG_CTRL 0x4a
62 #define DAC_MXR_SRC 0x4c
63 #define DAC_MXR_GAIN 0x4d
65 #define ADC_APC_CTRL 0x50
67 #define ADC_SRCBST_CTRL 0x52
68 #define OMIXER_DACA_CTRL 0x53
69 #define OMIXER_SR 0x54
70 #define OMIXER_BST1_CTRL 0x55
71 #define HPOUT_CTRL 0x56
72 #define ESPKOUT_CTRL 0x57
73 #define SPKOUT_CTRL 0x58
74 #define LOUT_CTRL 0x59
75 #define ADDA_TUNE1 0x5a
76 #define ADDA_TUNE2 0x5b
77 #define ADDA_TUNE3 0x5c
78 #define HPOUT_STR 0x5d
81 #define AC101_CHIP_ID 0x0101
84 #define DPLL_DAC_BIAS 14
85 #define PLL_POSTDIV_M 8
91 #define PLL_LOCK_STATUS 14
92 #define PLL_PREDIV_NI 4
93 #define PLL_POSTDIV_NF 0
98 #define AIF1CLK_ENA 11
100 #define AIF2CLK_ENA 7
101 #define AIF2CLK_SRC 4
106 #define MOD_CLK_AIF1 15
107 #define MOD_CLK_AIF2 14
108 #define MOD_CLK_AIF3 13
109 #define MOD_CLK_SRC1 11
110 #define MOD_CLK_SRC2 10
111 #define MOD_CLK_HPF_AGC 7
112 #define MOD_CLK_HPF_DRC 6
113 #define MOD_CLK_ADC_DIG 3
114 #define MOD_CLK_DAC_DIG 2
117 #define MOD_RESET_CTL 0
118 #define MOD_RESET_AIF1 15
119 #define MOD_RESET_AIF2 14
120 #define MOD_RESET_AIF3 13
121 #define MOD_RESET_SRC1 11
122 #define MOD_RESET_SRC2 10
123 #define MOD_RESET_HPF_AGC 7
124 #define MOD_RESET_HPF_DRC 6
125 #define MOD_RESET_ADC_DIG 3
126 #define MOD_RESET_DAC_DIG 2
129 #define AIF1_FS 12 //AIF1 Sample Rate
130 #define AIF2_FS 8 //AIF2 Sample Rate
137 #define AIF1_MSTR_MOD 15
138 #define AIF1_BCLK_INV 14
139 #define AIF1_LRCK_INV 13
140 #define AIF1_BCLK_DIV 9
141 #define AIF1_LRCK_DIV 6
142 #define AIF1_WORK_SIZ 4
143 #define AIF1_DATA_FMT 2
144 #define DSP_MONO_PCM 1
145 #define AIF1_TDMM_ENA 0
148 #define AIF1_AD0L_ENA 15
149 #define AIF1_AD0R_ENA 14
150 #define AIF1_AD1L_ENA 13
151 #define AIF1_AD1R_ENA 12
152 #define AIF1_AD0L_SRC 10
153 #define AIF1_AD0R_SRC 8
154 #define AIF1_AD1L_SRC 6
155 #define AIF1_AD1R_SRC 4
156 #define AIF1_ADCP_ENA 3
157 #define AIF1_ADUL_ENA 2
158 #define AIF1_SLOT_SIZ 0
161 #define AIF1_DA0L_ENA 15
162 #define AIF1_DA0R_ENA 14
163 #define AIF1_DA1L_ENA 13
164 #define AIF1_DA1R_ENA 12
165 #define AIF1_DA0L_SRC 10
166 #define AIF1_DA0R_SRC 8
167 #define AIF1_DA1L_SRC 6
168 #define AIF1_DA1R_SRC 4
169 #define AIF1_DACP_ENA 3
170 #define AIF1_DAUL_ENA 2
171 #define AIF1_SLOT_SIZ 0
174 #define AIF1_AD0L_AIF1_DA0L_MXR 15
175 #define AIF1_AD0L_AIF2_DACL_MXR 14
176 #define AIF1_AD0L_ADCL_MXR 13
177 #define AIF1_AD0L_AIF2_DACR_MXR 12
178 #define AIF1_AD0R_AIF1_DA0R_MXR 11
179 #define AIF1_AD0R_AIF2_DACR_MXR 10
180 #define AIF1_AD0R_ADCR_MXR 9
181 #define AIF1_AD0R_AIF2_DACL_MXR 8
182 #define AIF1_AD1L_AIF2_DACL_MXR 7
183 #define AIF1_AD1L_ADCL_MXR 6
184 #define AIF1_AD1L_MXR_SRC 6
185 #define AIF1_AD1R_AIF2_DACR_MXR 3
186 #define AIF1_AD1R_ADCR_MXR 2
187 #define AIF1_AD1R_MXR_SRC 2
190 #define AIF1_AD0L_VOL 8
191 #define AIF1_AD0R_VOL 0
194 #define AIF1_AD1L_VOL 8
195 #define AIF1_AD1R_VOL 0
198 #define AIF1_DA0L_VOL 8
199 #define AIF1_DA0R_VOL 0
202 #define AIF1_DA1L_VOL 8
203 #define AIF1_DA1R_VOL 0
206 #define AIF1_AD0L_MXR_GAIN 12
207 #define AIF1_AD0R_MXR_GAIN 8
208 #define AIF1_AD1L_MXR_GAIN 6
209 #define AIF1_AD1R_MXR_GAIN 2
212 #define AIF1_N_DATA_DISCARD 8
227 #define DMIC_CLK_PIN_CTRL 12
232 #define HMIC_DATA_IRQ_MODE 7
233 #define HMIC_TH1_HYSTERESIS 5
234 #define HMIC_PULLOUT_IRQ 4
235 #define HMIC_PLUGIN_IRQ 3
236 #define HMIC_KEYUP_IRQ 2
237 #define HMIC_KEYDOWN_IRQ 1
238 #define HMIC_DATA_IRQ_EN 0
241 #define HMIC_SAMPLE_SELECT 14
242 #define HMIC_TH2_HYSTERESIS 13
245 #define KEYUP_CLEAR 5
250 #define GET_HMIC_DATA(r) (((r) >> HMIC_DATA) & 0x1F)
251 #define HMIC_PULLOUT_PEND 4
252 #define HMIC_PLUGIN_PEND 3
253 #define HMIC_KEYUP_PEND 2
254 #define HMKC_KEYDOWN_PEND 1
255 #define HMIC_DATA_PEND 0
256 #define HMIC_PEND_ALL (0x1F)
271 #define DAC_MOD_DBG 13
272 #define DAC_PTN_SEL 6
276 #define DACL_MXR_AIF1_DA0L 15
277 #define DACL_MXR_AIF1_DA1L 14
278 #define DACL_MXR_AIF2_DACL 13
279 #define DACL_MXR_ADCL 12
280 #define DACL_MXR_SRC 12
281 #define DACR_MXR_AIF1_DA0R 11
282 #define DACR_MXR_AIF1_DA1R 10
283 #define DACR_MXR_AIF2_DACR 9
284 #define DACR_MXR_ADCR 8
285 #define DACR_MXR_SRC 8
288 #define DACL_MXR_GAIN 12
289 #define DACR_MXR_GAIN 8
297 #define MMIC_BIAS_CHOP_EN 6
298 #define MMIC_BIAS_CHOP_CKS 4
304 #define RADCMIXMUTEMIC1BOOST (13)
305 #define RADCMIXMUTEMIC2BOOST (12)
306 #define RADCMIXMUTELINEINLR (11)
307 #define RADCMIXMUTELINEINR (10)
308 #define RADCMIXMUTEAUXINR (9)
309 #define RADCMIXMUTEROUTPUT (8)
310 #define RADCMIXMUTELOUTPUT (7)
311 #define LADCMIXMUTEMIC1BOOST (6)
312 #define LADCMIXMUTEMIC2BOOST (5)
313 #define LADCMIXMUTELINEINLR (4)
314 #define LADCMIXMUTELINEINL (3)
315 #define LADCMIXMUTEAUXINL (2)
316 #define LADCMIXMUTELOUTPUT (1)
317 #define LADCMIXMUTEROUTPUT (0)
326 #define LINEIN_PREG 4
334 #define HPOUTPUTENABLE 8
337 #define RMIXMUTEMIC1BOOST (13)
338 #define RMIXMUTEMIC2BOOST (12)
339 #define RMIXMUTELINEINLR (11)
340 #define RMIXMUTELINEINR (10)
341 #define RMIXMUTEAUXINR (9)
342 #define RMIXMUTEDACR (8)
343 #define RMIXMUTEDACL (7)
344 #define LMIXMUTEMIC1BOOST (6)
345 #define LMIXMUTEMIC2BOOST (5)
346 #define LMIXMUTELINEINLR (4)
347 #define LMIXMUTELINEINL (3)
348 #define LMIXMUTEAUXINL (2)
349 #define LMIXMUTEDACL (1)
350 #define LMIXMUTEDACR (0)
353 #define BIASVOLTAGE 12
355 #define OMIXER_MIC1G 6
356 #define OMIXER_MIC2G 3
362 #define RHPPA_MUTE 13
363 #define LHPPA_MUTE 12
370 #define EAR_RAMP_TIME 11
371 #define ESPA_OUT_CURRENT 9
396 #define CURRENT_TEST_SELECT 14
400 #define ZERO_CROSSOVER_EN 8
401 #define ZERO_CROSSOVER_TIME 7
402 #define EAR_SPEED_SELECT 6
403 #define REF_CHOPPEN_CKS 4
404 #define OPMIC_BIAS_CUR 0
407 #define OPDAC_BIAS_CUR 14
408 #define OPDRV_BIAS_CUR 12
409 #define OPMIX_BIAS_CUR 10
410 #define OPEAR_BIAS_CUR 8
411 #define OPVR_BIAS_CUR 6
412 #define OPAAF_BIAS_CUR 4
413 #define OPADC1_BIAS_CUR 2
414 #define OPADC2_BIAS_CUR 0
419 #define BIASCALIVERIFY 11
421 #define BIASCALIDATA 9
426 #define HPVL_SOFT_MOD 14
427 #define HPVL_STEP_CTRL 8
428 #define DACA_CHND_ENA 7
429 #define HPPA_MXRD_ENA 6
430 #define HPVL_CTRL_OUT 0
432 #endif//__AC101_REGS_H__