sound/soc/amd/acp-pcm-dma.c

   1 /*
   2  * AMD ALSA SoC PCM Driver for ACP 2.x
   3  *
   4  * Copyright 2014-2015 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/sizes.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include <sound/soc.h>
  23 #include <drm/amd_asic_type.h>
  24 #include "acp.h"
  25
  26 #define DRV_NAME "acp_audio_dma"
  27
  28 #define PLAYBACK_MIN_NUM_PERIODS    2
  29 #define PLAYBACK_MAX_NUM_PERIODS    2
  30 #define PLAYBACK_MAX_PERIOD_SIZE    16384
  31 #define PLAYBACK_MIN_PERIOD_SIZE    1024
  32 #define CAPTURE_MIN_NUM_PERIODS     2
  33 #define CAPTURE_MAX_NUM_PERIODS     2
  34 #define CAPTURE_MAX_PERIOD_SIZE     16384
  35 #define CAPTURE_MIN_PERIOD_SIZE     1024
  36
  37 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
  38 #define MIN_BUFFER MAX_BUFFER
  39
  40 #define ST_PLAYBACK_MAX_PERIOD_SIZE 8192
  41 #define ST_CAPTURE_MAX_PERIOD_SIZE  ST_PLAYBACK_MAX_PERIOD_SIZE
  42 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
  43 #define ST_MIN_BUFFER ST_MAX_BUFFER
  44
  45 #define DRV_NAME "acp_audio_dma"
  46
  47 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
  48         .info = SNDRV_PCM_INFO_INTERLEAVED |
  49                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
  50                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
  51                 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
  52         .formats = SNDRV_PCM_FMTBIT_S16_LE |
  53                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
  54         .channels_min = 1,
  55         .channels_max = 8,
  56         .rates = SNDRV_PCM_RATE_8000_96000,
  57         .rate_min = 8000,
  58         .rate_max = 96000,
  59         .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
  60         .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
  61         .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
  62         .periods_min = PLAYBACK_MIN_NUM_PERIODS,
  63         .periods_max = PLAYBACK_MAX_NUM_PERIODS,
  64 };
  65
  66 static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
  67         .info = SNDRV_PCM_INFO_INTERLEAVED |
  68                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
  69                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
  70             SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
  71         .formats = SNDRV_PCM_FMTBIT_S16_LE |
  72                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
  73         .channels_min = 1,
  74         .channels_max = 2,
  75         .rates = SNDRV_PCM_RATE_8000_48000,
  76         .rate_min = 8000,
  77         .rate_max = 48000,
  78         .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
  79         .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
  80         .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
  81         .periods_min = CAPTURE_MIN_NUM_PERIODS,
  82         .periods_max = CAPTURE_MAX_NUM_PERIODS,
  83 };
  84
  85 static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
  86         .info = SNDRV_PCM_INFO_INTERLEAVED |
  87                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
  88                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
  89                 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
  90         .formats = SNDRV_PCM_FMTBIT_S16_LE |
  91                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
  92         .channels_min = 1,
  93         .channels_max = 8,
  94         .rates = SNDRV_PCM_RATE_8000_96000,
  95         .rate_min = 8000,
  96         .rate_max = 96000,
  97         .buffer_bytes_max = ST_MAX_BUFFER,
  98         .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
  99         .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
 100         .periods_min = PLAYBACK_MIN_NUM_PERIODS,
 101         .periods_max = PLAYBACK_MAX_NUM_PERIODS,
 102 };
 103
 104 static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
 105         .info = SNDRV_PCM_INFO_INTERLEAVED |
 106                 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
 107                 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
 108                 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
 109         .formats = SNDRV_PCM_FMTBIT_S16_LE |
 110                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 111         .channels_min = 1,
 112         .channels_max = 2,
 113         .rates = SNDRV_PCM_RATE_8000_48000,
 114         .rate_min = 8000,
 115         .rate_max = 48000,
 116         .buffer_bytes_max = ST_MAX_BUFFER,
 117         .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
 118         .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
 119         .periods_min = CAPTURE_MIN_NUM_PERIODS,
 120         .periods_max = CAPTURE_MAX_NUM_PERIODS,
 121 };
 122
 123 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
 124 {
 125         return readl(acp_mmio + (reg * 4));
 126 }
 127
 128 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
 129 {
 130         writel(val, acp_mmio + (reg * 4));
 131 }
 132
 133 /*
 134  * Configure a given dma channel parameters - enable/disable,
 135  * number of descriptors, priority
 136  */
 137 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
 138                                    u16 dscr_strt_idx, u16 num_dscrs,
 139                                    enum acp_dma_priority_level priority_level)
 140 {
 141         u32 dma_ctrl;
 142
 143         /* disable the channel run field */
 144         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 145         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
 146         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 147
 148         /* program a DMA channel with first descriptor to be processed. */
 149         acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
 150                         & dscr_strt_idx),
 151                         acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
 152
 153         /*
 154          * program a DMA channel with the number of descriptors to be
 155          * processed in the transfer
 156          */
 157         acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
 158                       acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
 159
 160         /* set DMA channel priority */
 161         acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
 162 }
 163
 164 /* Initialize a dma descriptor in SRAM based on descritor information passed */
 165 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
 166                                           u16 descr_idx,
 167                                           acp_dma_dscr_transfer_t *descr_info)
 168 {
 169         u32 sram_offset;
 170
 171         sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
 172
 173         /* program the source base address. */
 174         acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 175         acp_reg_write(descr_info->src,  acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 176         /* program the destination base address. */
 177         acp_reg_write(sram_offset + 4,  acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 178         acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 179
 180         /* program the number of bytes to be transferred for this descriptor. */
 181         acp_reg_write(sram_offset + 8,  acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 182         acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 183 }
 184
 185 /*
 186  * Initialize the DMA descriptor information for transfer between
 187  * system memory <-> ACP SRAM
 188  */
 189 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
 190                                            u32 size, int direction,
 191                                            u32 pte_offset, u16 ch,
 192                                            u32 sram_bank, u16 dma_dscr_idx,
 193                                            u32 asic_type)
 194 {
 195         u16 i;
 196         acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
 197
 198         for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
 199                 dmadscr[i].xfer_val = 0;
 200                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
 201                         dma_dscr_idx = dma_dscr_idx + i;
 202                         dmadscr[i].dest = sram_bank + (i * (size / 2));
 203                         dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
 204                                 + (pte_offset * SZ_4K) + (i * (size / 2));
 205                         switch (asic_type) {
 206                         case CHIP_STONEY:
 207                                 dmadscr[i].xfer_val |=
 208                                 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM  << 16) |
 209                                 (size / 2);
 210                                 break;
 211                         default:
 212                                 dmadscr[i].xfer_val |=
 213                                 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM  << 16) |
 214                                 (size / 2);
 215                         }
 216                 } else {
 217                         dma_dscr_idx = dma_dscr_idx + i;
 218                         dmadscr[i].src = sram_bank + (i * (size / 2));
 219                         dmadscr[i].dest =
 220                         ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
 221                         (pte_offset * SZ_4K) + (i * (size / 2));
 222                         switch (asic_type) {
 223                         case CHIP_STONEY:
 224                                 dmadscr[i].xfer_val |=
 225                                 BIT(22) |
 226                                 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
 227                                 (size / 2);
 228                                 break;
 229                         default:
 230                                 dmadscr[i].xfer_val |=
 231                                 BIT(22) |
 232                                 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
 233                                 (size / 2);
 234                         }
 235                 }
 236                 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
 237                                               &dmadscr[i]);
 238         }
 239         config_acp_dma_channel(acp_mmio, ch,
 240                                dma_dscr_idx - 1,
 241                                NUM_DSCRS_PER_CHANNEL,
 242                                ACP_DMA_PRIORITY_LEVEL_NORMAL);
 243 }
 244
 245 /*
 246  * Initialize the DMA descriptor information for transfer between
 247  * ACP SRAM <-> I2S
 248  */
 249 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
 250                                            int direction, u32 sram_bank,
 251                                            u16 destination, u16 ch,
 252                                            u16 dma_dscr_idx, u32 asic_type)
 253 {
 254         u16 i;
 255         acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
 256
 257         for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
 258                 dmadscr[i].xfer_val = 0;
 259                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
 260                         dma_dscr_idx = dma_dscr_idx + i;
 261                         dmadscr[i].src = sram_bank  + (i * (size / 2));
 262                         /* dmadscr[i].dest is unused by hardware. */
 263                         dmadscr[i].dest = 0;
 264                         dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
 265                                                 (size / 2);
 266                 } else {
 267                         dma_dscr_idx = dma_dscr_idx + i;
 268                         /* dmadscr[i].src is unused by hardware. */
 269                         dmadscr[i].src = 0;
 270                         dmadscr[i].dest =
 271                                  sram_bank + (i * (size / 2));
 272                         dmadscr[i].xfer_val |= BIT(22) |
 273                                 (destination << 16) | (size / 2);
 274                 }
 275                 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
 276                                               &dmadscr[i]);
 277         }
 278         /* Configure the DMA channel with the above descriptore */
 279         config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
 280                                NUM_DSCRS_PER_CHANNEL,
 281                                ACP_DMA_PRIORITY_LEVEL_NORMAL);
 282 }
 283
 284 /* Create page table entries in ACP SRAM for the allocated memory */
 285 static void acp_pte_config(void __iomem *acp_mmio, struct page *pg,
 286                            u16 num_of_pages, u32 pte_offset)
 287 {
 288         u16 page_idx;
 289         u64 addr;
 290         u32 low;
 291         u32 high;
 292         u32 offset;
 293
 294         offset  = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
 295         for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
 296                 /* Load the low address of page int ACP SRAM through SRBM */
 297                 acp_reg_write((offset + (page_idx * 8)),
 298                               acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 299                 addr = page_to_phys(pg);
 300
 301                 low = lower_32_bits(addr);
 302                 high = upper_32_bits(addr);
 303
 304                 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 305
 306                 /* Load the High address of page int ACP SRAM through SRBM */
 307                 acp_reg_write((offset + (page_idx * 8) + 4),
 308                               acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
 309
 310                 /* page enable in ACP */
 311                 high |= BIT(31);
 312                 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
 313
 314                 /* Move to next physically contiguos page */
 315                 pg++;
 316         }
 317 }
 318
 319 static void config_acp_dma(void __iomem *acp_mmio,
 320                            struct audio_substream_data *rtd,
 321                            u32 asic_type)
 322 {
 323         acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages,
 324                        rtd->pte_offset);
 325         /* Configure System memory <-> ACP SRAM DMA descriptors */
 326         set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
 327                                        rtd->direction, rtd->pte_offset,
 328                                        rtd->ch1, rtd->sram_bank,
 329                                        rtd->dma_dscr_idx_1, asic_type);
 330         /* Configure ACP SRAM <-> I2S DMA descriptors */
 331         set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
 332                                        rtd->direction, rtd->sram_bank,
 333                                        rtd->destination, rtd->ch2,
 334                                        rtd->dma_dscr_idx_2, asic_type);
 335 }
 336
 337 /* Start a given DMA channel transfer */
 338 static void acp_dma_start(void __iomem *acp_mmio,
 339                           u16 ch_num, bool is_circular)
 340 {
 341         u32 dma_ctrl;
 342
 343         /* read the dma control register and disable the channel run field */
 344         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 345
 346         /* Invalidating the DAGB cache */
 347         acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
 348
 349         /*
 350          * configure the DMA channel and start the DMA transfer
 351          * set dmachrun bit to start the transfer and enable the
 352          * interrupt on completion of the dma transfer
 353          */
 354         dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
 355
 356         switch (ch_num) {
 357         case ACP_TO_I2S_DMA_CH_NUM:
 358         case ACP_TO_SYSRAM_CH_NUM:
 359         case I2S_TO_ACP_DMA_CH_NUM:
 360                 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
 361                 break;
 362         default:
 363                 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
 364                 break;
 365         }
 366
 367         /* enable  for ACP SRAM to/from I2S DMA channel */
 368         if (is_circular == true)
 369                 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
 370         else
 371                 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
 372
 373         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 374 }
 375
 376 /* Stop a given DMA channel transfer */
 377 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
 378 {
 379         u32 dma_ctrl;
 380         u32 dma_ch_sts;
 381         u32 count = ACP_DMA_RESET_TIME;
 382
 383         dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 384
 385         /*
 386          * clear the dma control register fields before writing zero
 387          * in reset bit
 388          */
 389         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
 390         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
 391
 392         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 393         dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
 394
 395         if (dma_ch_sts & BIT(ch_num)) {
 396                 /*
 397                  * set the reset bit for this channel to stop the dma
 398                  *  transfer
 399                  */
 400                 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
 401                 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
 402         }
 403
 404         /* check the channel status bit for some time and return the status */
 405         while (true) {
 406                 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
 407                 if (!(dma_ch_sts & BIT(ch_num))) {
 408                         /*
 409                          * clear the reset flag after successfully stopping
 410                          * the dma transfer and break from the loop
 411                          */
 412                         dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
 413
 414                         acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
 415                                       + ch_num);
 416                         break;
 417                 }
 418                 if (--count == 0) {
 419                         pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
 420                         return -ETIMEDOUT;
 421                 }
 422                 udelay(100);
 423         }
 424         return 0;
 425 }
 426
 427 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
 428                                     bool power_on)
 429 {
 430         u32 val, req_reg, sts_reg, sts_reg_mask;
 431         u32 loops = 1000;
 432
 433         if (bank < 32) {
 434                 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
 435                 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
 436                 sts_reg_mask = 0xFFFFFFFF;
 437
 438         } else {
 439                 bank -= 32;
 440                 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
 441                 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
 442                 sts_reg_mask = 0x0000FFFF;
 443         }
 444
 445         val = acp_reg_read(acp_mmio, req_reg);
 446         if (val & (1 << bank)) {
 447                 /* bank is in off state */
 448                 if (power_on == true)
 449                         /* request to on */
 450                         val &= ~(1 << bank);
 451                 else
 452                         /* request to off */
 453                         return;
 454         } else {
 455                 /* bank is in on state */
 456                 if (power_on == false)
 457                         /* request to off */
 458                         val |= 1 << bank;
 459                 else
 460                         /* request to on */
 461                         return;
 462         }
 463         acp_reg_write(val, acp_mmio, req_reg);
 464
 465         while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
 466                 if (!loops--) {
 467                         pr_err("ACP SRAM bank %d state change failed\n", bank);
 468                         break;
 469                 }
 470                 cpu_relax();
 471         }
 472 }
 473
 474 /* Initialize and bring ACP hardware to default state. */
 475 static int acp_init(void __iomem *acp_mmio, u32 asic_type)
 476 {
 477         u16 bank;
 478         u32 val, count, sram_pte_offset;
 479
 480         /* Assert Soft reset of ACP */
 481         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 482
 483         val |= ACP_SOFT_RESET__SoftResetAud_MASK;
 484         acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
 485
 486         count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
 487         while (true) {
 488                 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 489                 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
 490                     (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
 491                         break;
 492                 if (--count == 0) {
 493                         pr_err("Failed to reset ACP\n");
 494                         return -ETIMEDOUT;
 495                 }
 496                 udelay(100);
 497         }
 498
 499         /* Enable clock to ACP and wait until the clock is enabled */
 500         val = acp_reg_read(acp_mmio, mmACP_CONTROL);
 501         val = val | ACP_CONTROL__ClkEn_MASK;
 502         acp_reg_write(val, acp_mmio, mmACP_CONTROL);
 503
 504         count = ACP_CLOCK_EN_TIME_OUT_VALUE;
 505
 506         while (true) {
 507                 val = acp_reg_read(acp_mmio, mmACP_STATUS);
 508                 if (val & (u32)0x1)
 509                         break;
 510                 if (--count == 0) {
 511                         pr_err("Failed to reset ACP\n");
 512                         return -ETIMEDOUT;
 513                 }
 514                 udelay(100);
 515         }
 516
 517         /* Deassert the SOFT RESET flags */
 518         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 519         val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
 520         acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
 521
 522         /* initiailize Onion control DAGB register */
 523         acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
 524                       mmACP_AXI2DAGB_ONION_CNTL);
 525
 526         /* initiailize Garlic control DAGB registers */
 527         acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
 528                       mmACP_AXI2DAGB_GARLIC_CNTL);
 529
 530         sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
 531                         ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
 532                         ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
 533                         ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
 534         acp_reg_write(sram_pte_offset,  acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
 535         acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
 536                       mmACP_DAGB_PAGE_SIZE_GRP_1);
 537
 538         acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
 539                       mmACP_DMA_DESC_BASE_ADDR);
 540
 541         /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
 542         acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
 543         acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
 544                       acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
 545
 546        /*
 547         * When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
 548         * Now, turn off all of them. This can't be done in 'poweron' of
 549         * ACP pm domain, as this requires ACP to be initialized.
 550         * For Stoney, Memory gating is disabled,i.e SRAM Banks
 551         * won't be turned off. The default state for SRAM banks is ON.
 552         * Setting SRAM bank state code skipped for STONEY platform.
 553         */
 554         if (asic_type != CHIP_STONEY) {
 555                 for (bank = 1; bank < 48; bank++)
 556                         acp_set_sram_bank_state(acp_mmio, bank, false);
 557         }
 558         return 0;
 559 }
 560
 561 /* Deinitialize ACP */
 562 static int acp_deinit(void __iomem *acp_mmio)
 563 {
 564         u32 val;
 565         u32 count;
 566
 567         /* Assert Soft reset of ACP */
 568         val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 569
 570         val |= ACP_SOFT_RESET__SoftResetAud_MASK;
 571         acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
 572
 573         count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
 574         while (true) {
 575                 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
 576                 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
 577                     (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
 578                         break;
 579                 if (--count == 0) {
 580                         pr_err("Failed to reset ACP\n");
 581                         return -ETIMEDOUT;
 582                 }
 583                 udelay(100);
 584         }
 585         /* Disable ACP clock */
 586         val = acp_reg_read(acp_mmio, mmACP_CONTROL);
 587         val &= ~ACP_CONTROL__ClkEn_MASK;
 588         acp_reg_write(val, acp_mmio, mmACP_CONTROL);
 589
 590         count = ACP_CLOCK_EN_TIME_OUT_VALUE;
 591
 592         while (true) {
 593                 val = acp_reg_read(acp_mmio, mmACP_STATUS);
 594                 if (!(val & (u32)0x1))
 595                         break;
 596                 if (--count == 0) {
 597                         pr_err("Failed to reset ACP\n");
 598                         return -ETIMEDOUT;
 599                 }
 600                 udelay(100);
 601         }
 602         return 0;
 603 }
 604
 605 /* ACP DMA irq handler routine for playback, capture usecases */
 606 static irqreturn_t dma_irq_handler(int irq, void *arg)
 607 {
 608         u16 dscr_idx;
 609         u32 intr_flag, ext_intr_status;
 610         struct audio_drv_data *irq_data;
 611         void __iomem *acp_mmio;
 612         struct device *dev = arg;
 613         bool valid_irq = false;
 614
 615         irq_data = dev_get_drvdata(dev);
 616         acp_mmio = irq_data->acp_mmio;
 617
 618         ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 619         intr_flag = (((ext_intr_status &
 620                       ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
 621                      ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
 622
 623         if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
 624                 valid_irq = true;
 625                 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) ==
 626                                 PLAYBACK_START_DMA_DESCR_CH13)
 627                         dscr_idx = PLAYBACK_END_DMA_DESCR_CH12;
 628                 else
 629                         dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
 630                 config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx,
 631                                        1, 0);
 632                 acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
 633
 634                 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
 635
 636                 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
 637                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 638         }
 639
 640         if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
 641                 valid_irq = true;
 642                 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) ==
 643                                 CAPTURE_START_DMA_DESCR_CH15)
 644                         dscr_idx = CAPTURE_END_DMA_DESCR_CH14;
 645                 else
 646                         dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
 647                 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
 648                                        1, 0);
 649                 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);
 650
 651                 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
 652                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 653         }
 654
 655         if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
 656                 valid_irq = true;
 657                 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
 658                 acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
 659                               acp_mmio, mmACP_EXTERNAL_INTR_STAT);
 660         }
 661
 662         if (valid_irq)
 663                 return IRQ_HANDLED;
 664         else
 665                 return IRQ_NONE;
 666 }
 667
 668 static int acp_dma_open(struct snd_pcm_substream *substream)
 669 {
 670         u16 bank;
 671         int ret = 0;
 672         struct snd_pcm_runtime *runtime = substream->runtime;
 673         struct snd_soc_pcm_runtime *prtd = substream->private_data;
 674         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
 675                                                                     DRV_NAME);
 676         struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
 677         struct audio_substream_data *adata =
 678                 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
 679         if (!adata)
 680                 return -ENOMEM;
 681
 682         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 683                 switch (intr_data->asic_type) {
 684                 case CHIP_STONEY:
 685                         runtime->hw = acp_st_pcm_hardware_playback;
 686                         break;
 687                 default:
 688                         runtime->hw = acp_pcm_hardware_playback;
 689                 }
 690         } else {
 691                 switch (intr_data->asic_type) {
 692                 case CHIP_STONEY:
 693                         runtime->hw = acp_st_pcm_hardware_capture;
 694                         break;
 695                 default:
 696                         runtime->hw = acp_pcm_hardware_capture;
 697                 }
 698         }
 699
 700         ret = snd_pcm_hw_constraint_integer(runtime,
 701                                             SNDRV_PCM_HW_PARAM_PERIODS);
 702         if (ret < 0) {
 703                 dev_err(component->dev, "set integer constraint failed\n");
 704                 kfree(adata);
 705                 return ret;
 706         }
 707
 708         adata->acp_mmio = intr_data->acp_mmio;
 709         runtime->private_data = adata;
 710
 711         /*
 712          * Enable ACP irq, when neither playback or capture streams are
 713          * active by the time when a new stream is being opened.
 714          * This enablement is not required for another stream, if current
 715          * stream is not closed
 716          */
 717         if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream)
 718                 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
 719
 720         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 721                 intr_data->play_i2ssp_stream = substream;
 722                 /*
 723                  * For Stoney, Memory gating is disabled,i.e SRAM Banks
 724                  * won't be turned off. The default state for SRAM banks is ON.
 725                  * Setting SRAM bank state code skipped for STONEY platform.
 726                  */
 727                 if (intr_data->asic_type != CHIP_STONEY) {
 728                         for (bank = 1; bank <= 4; bank++)
 729                                 acp_set_sram_bank_state(intr_data->acp_mmio,
 730                                                         bank, true);
 731                 }
 732         } else {
 733                 intr_data->capture_i2ssp_stream = substream;
 734                 if (intr_data->asic_type != CHIP_STONEY) {
 735                         for (bank = 5; bank <= 8; bank++)
 736                                 acp_set_sram_bank_state(intr_data->acp_mmio,
 737                                                         bank, true);
 738                 }
 739         }
 740
 741         return 0;
 742 }
 743
 744 static int acp_dma_hw_params(struct snd_pcm_substream *substream,
 745                              struct snd_pcm_hw_params *params)
 746 {
 747         int status;
 748         uint64_t size;
 749         u32 val = 0;
 750         struct page *pg;
 751         struct snd_pcm_runtime *runtime;
 752         struct audio_substream_data *rtd;
 753         struct snd_soc_pcm_runtime *prtd = substream->private_data;
 754         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
 755                                                                     DRV_NAME);
 756         struct audio_drv_data *adata = dev_get_drvdata(component->dev);
 757
 758         runtime = substream->runtime;
 759         rtd = runtime->private_data;
 760
 761         if (WARN_ON(!rtd))
 762                 return -EINVAL;
 763
 764         if (adata->asic_type == CHIP_STONEY) {
 765                 val = acp_reg_read(adata->acp_mmio,
 766                                    mmACP_I2S_16BIT_RESOLUTION_EN);
 767                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 768                         val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
 769                 else
 770                         val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
 771                 acp_reg_write(val, adata->acp_mmio,
 772                               mmACP_I2S_16BIT_RESOLUTION_EN);
 773         }
 774
 775         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 776                 switch (adata->asic_type) {
 777                 case CHIP_STONEY:
 778                         rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
 779                         break;
 780                 default:
 781                         rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
 782                 }
 783                 rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
 784                 rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
 785                 rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
 786                 rtd->destination = TO_ACP_I2S_1;
 787                 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
 788                 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
 789                 rtd->byte_cnt_high_reg_offset =
 790                                 mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
 791                 rtd->byte_cnt_low_reg_offset = mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
 792         } else {
 793                 switch (adata->asic_type) {
 794                 case CHIP_STONEY:
 795                         rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
 796                         rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
 797                         break;
 798                 default:
 799                         rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
 800                         rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
 801                 }
 802                 rtd->ch1 = ACP_TO_SYSRAM_CH_NUM;
 803                 rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM;
 804                 rtd->destination = FROM_ACP_I2S_1;
 805                 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
 806                 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
 807                 rtd->byte_cnt_high_reg_offset =
 808                                 mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
 809                 rtd->byte_cnt_low_reg_offset = mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
 810         }
 811
 812         size = params_buffer_bytes(params);
 813         status = snd_pcm_lib_malloc_pages(substream, size);
 814         if (status < 0)
 815                 return status;
 816
 817         memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
 818         pg = virt_to_page(substream->dma_buffer.area);
 819
 820         if (pg) {
 821                 acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
 822                 /* Save for runtime private data */
 823                 rtd->pg = pg;
 824                 rtd->order = get_order(size);
 825
 826                 /* Fill the page table entries in ACP SRAM */
 827                 rtd->pg = pg;
 828                 rtd->size = size;
 829                 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
 830                 rtd->direction = substream->stream;
 831
 832                 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
 833                 status = 0;
 834         } else {
 835                 status = -ENOMEM;
 836         }
 837         return status;
 838 }
 839
 840 static int acp_dma_hw_free(struct snd_pcm_substream *substream)
 841 {
 842         return snd_pcm_lib_free_pages(substream);
 843 }
 844
 845 static u64 acp_get_byte_count(struct audio_substream_data *rtd)
 846 {
 847         union acp_dma_count byte_count;
 848
 849         byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,
 850                                               rtd->byte_cnt_high_reg_offset);
 851         byte_count.bcount.low  = acp_reg_read(rtd->acp_mmio,
 852                                               rtd->byte_cnt_low_reg_offset);
 853         return byte_count.bytescount;
 854 }
 855
 856 static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
 857 {
 858         u32 buffersize;
 859         u32 pos = 0;
 860         u64 bytescount = 0;
 861
 862         struct snd_pcm_runtime *runtime = substream->runtime;
 863         struct audio_substream_data *rtd = runtime->private_data;
 864
 865         if (!rtd)
 866                 return -EINVAL;
 867
 868         buffersize = frames_to_bytes(runtime, runtime->buffer_size);
 869         bytescount = acp_get_byte_count(rtd);
 870
 871         if (bytescount > rtd->bytescount)
 872                 bytescount -= rtd->bytescount;
 873         pos = do_div(bytescount, buffersize);
 874         return bytes_to_frames(runtime, pos);
 875 }
 876
 877 static int acp_dma_mmap(struct snd_pcm_substream *substream,
 878                         struct vm_area_struct *vma)
 879 {
 880         return snd_pcm_lib_default_mmap(substream, vma);
 881 }
 882
 883 static int acp_dma_prepare(struct snd_pcm_substream *substream)
 884 {
 885         struct snd_pcm_runtime *runtime = substream->runtime;
 886         struct audio_substream_data *rtd = runtime->private_data;
 887
 888         if (!rtd)
 889                 return -EINVAL;
 890
 891         config_acp_dma_channel(rtd->acp_mmio,
 892                                rtd->ch1,
 893                                rtd->dma_dscr_idx_1,
 894                                NUM_DSCRS_PER_CHANNEL, 0);
 895         config_acp_dma_channel(rtd->acp_mmio,
 896                                rtd->ch2,
 897                                rtd->dma_dscr_idx_2,
 898                                NUM_DSCRS_PER_CHANNEL, 0);
 899         return 0;
 900 }
 901
 902 static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
 903 {
 904         int ret;
 905         u32 loops = 4000;
 906         u64 bytescount = 0;
 907
 908         struct snd_pcm_runtime *runtime = substream->runtime;
 909         struct snd_soc_pcm_runtime *prtd = substream->private_data;
 910         struct audio_substream_data *rtd = runtime->private_data;
 911         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
 912                                                                     DRV_NAME);
 913
 914         if (!rtd)
 915                 return -EINVAL;
 916         switch (cmd) {
 917         case SNDRV_PCM_TRIGGER_START:
 918         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 919         case SNDRV_PCM_TRIGGER_RESUME:
 920                 bytescount = acp_get_byte_count(rtd);
 921                 if (rtd->bytescount == 0)
 922                         rtd->bytescount = bytescount;
 923                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 924                         acp_dma_start(rtd->acp_mmio, rtd->ch1, false);
 925                         while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) &
 926                                 BIT(rtd->ch1)) {
 927                                 if (!loops--) {
 928                                         dev_err(component->dev,
 929                                                 "acp dma start timeout\n");
 930                                         return -ETIMEDOUT;
 931                                 }
 932                                 cpu_relax();
 933                         }
 934                 }
 935                 acp_dma_start(rtd->acp_mmio, rtd->ch2, true);
 936                 ret = 0;
 937                 break;
 938         case SNDRV_PCM_TRIGGER_STOP:
 939         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 940         case SNDRV_PCM_TRIGGER_SUSPEND:
 941                 /* For playback, non circular dma should be stopped first
 942                  * i.e Sysram to acp dma transfer channel(rtd->ch1) should be
 943                  * stopped before stopping cirular dma which is acp sram to i2s
 944                  * fifo dma transfer channel(rtd->ch2). Where as in Capture
 945                  * scenario, i2s fifo to acp sram dma channel(rtd->ch2) stopped
 946                  * first before stopping acp sram to sysram which is circular
 947                  * dma(rtd->ch1).
 948                  */
 949                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 950                         acp_dma_stop(rtd->acp_mmio, rtd->ch1);
 951                         ret =  acp_dma_stop(rtd->acp_mmio, rtd->ch2);
 952                 } else {
 953                         acp_dma_stop(rtd->acp_mmio, rtd->ch2);
 954                         ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
 955                 }
 956                 rtd->bytescount = 0;
 957                 break;
 958         default:
 959                 ret = -EINVAL;
 960         }
 961         return ret;
 962 }
 963
 964 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
 965 {
 966         int ret;
 967         struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd,
 968                                                                     DRV_NAME);
 969         struct audio_drv_data *adata = dev_get_drvdata(component->dev);
 970
 971         switch (adata->asic_type) {
 972         case CHIP_STONEY:
 973                 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
 974                                                             SNDRV_DMA_TYPE_DEV,
 975                                                             NULL, ST_MIN_BUFFER,
 976                                                             ST_MAX_BUFFER);
 977                 break;
 978         default:
 979                 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
 980                                                             SNDRV_DMA_TYPE_DEV,
 981                                                             NULL, MIN_BUFFER,
 982                                                             MAX_BUFFER);
 983                 break;
 984         }
 985         if (ret < 0)
 986                 dev_err(component->dev,
 987                         "buffer preallocation failure error:%d\n", ret);
 988         return ret;
 989 }
 990
 991 static int acp_dma_close(struct snd_pcm_substream *substream)
 992 {
 993         u16 bank;
 994         struct snd_pcm_runtime *runtime = substream->runtime;
 995         struct audio_substream_data *rtd = runtime->private_data;
 996         struct snd_soc_pcm_runtime *prtd = substream->private_data;
 997         struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
 998                                                                     DRV_NAME);
 999         struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1000
1001         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1002                 adata->play_i2ssp_stream = NULL;
1003                 /*
1004                  * For Stoney, Memory gating is disabled,i.e SRAM Banks
1005                  * won't be turned off. The default state for SRAM banks is ON.
1006                  * Setting SRAM bank state code skipped for STONEY platform.
1007                  * added condition checks for Carrizo platform only
1008                  */
1009                 if (adata->asic_type != CHIP_STONEY) {
1010                         for (bank = 1; bank <= 4; bank++)
1011                                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1012                                                         false);
1013                 }
1014         } else  {
1015                 adata->capture_i2ssp_stream = NULL;
1016                 if (adata->asic_type != CHIP_STONEY) {
1017                         for (bank = 5; bank <= 8; bank++)
1018                                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1019                                                         false);
1020                 }
1021         }
1022
1023         /*
1024          * Disable ACP irq, when the current stream is being closed and
1025          * another stream is also not active.
1026          */
1027         if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream)
1028                 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1029         kfree(rtd);
1030         return 0;
1031 }
1032
1033 static const struct snd_pcm_ops acp_dma_ops = {
1034         .open = acp_dma_open,
1035         .close = acp_dma_close,
1036         .ioctl = snd_pcm_lib_ioctl,
1037         .hw_params = acp_dma_hw_params,
1038         .hw_free = acp_dma_hw_free,
1039         .trigger = acp_dma_trigger,
1040         .pointer = acp_dma_pointer,
1041         .mmap = acp_dma_mmap,
1042         .prepare = acp_dma_prepare,
1043 };
1044
1045 static const struct snd_soc_component_driver acp_asoc_platform = {
1046         .name = DRV_NAME,
1047         .ops = &acp_dma_ops,
1048         .pcm_new = acp_dma_new,
1049 };
1050
1051 static int acp_audio_probe(struct platform_device *pdev)
1052 {
1053         int status;
1054         struct audio_drv_data *audio_drv_data;
1055         struct resource *res;
1056         const u32 *pdata = pdev->dev.platform_data;
1057
1058         if (!pdata) {
1059                 dev_err(&pdev->dev, "Missing platform data\n");
1060                 return -ENODEV;
1061         }
1062
1063         audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
1064                                       GFP_KERNEL);
1065         if (!audio_drv_data)
1066                 return -ENOMEM;
1067
1068         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1069         audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res);
1070         if (IS_ERR(audio_drv_data->acp_mmio))
1071                 return PTR_ERR(audio_drv_data->acp_mmio);
1072
1073         /*
1074          * The following members gets populated in device 'open'
1075          * function. Till then interrupts are disabled in 'acp_init'
1076          * and device doesn't generate any interrupts.
1077          */
1078
1079         audio_drv_data->play_i2ssp_stream = NULL;
1080         audio_drv_data->capture_i2ssp_stream = NULL;
1081
1082         audio_drv_data->asic_type =  *pdata;
1083
1084         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1085         if (!res) {
1086                 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
1087                 return -ENODEV;
1088         }
1089
1090         status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler,
1091                                   0, "ACP_IRQ", &pdev->dev);
1092         if (status) {
1093                 dev_err(&pdev->dev, "ACP IRQ request failed\n");
1094                 return status;
1095         }
1096
1097         dev_set_drvdata(&pdev->dev, audio_drv_data);
1098
1099         /* Initialize the ACP */
1100         status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
1101         if (status) {
1102                 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
1103                 return status;
1104         }
1105
1106         status = devm_snd_soc_register_component(&pdev->dev,
1107                                                  &acp_asoc_platform, NULL, 0);
1108         if (status != 0) {
1109                 dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
1110                 return status;
1111         }
1112
1113         pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
1114         pm_runtime_use_autosuspend(&pdev->dev);
1115         pm_runtime_enable(&pdev->dev);
1116
1117         return status;
1118 }
1119
1120 static int acp_audio_remove(struct platform_device *pdev)
1121 {
1122         int status;
1123         struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
1124
1125         status = acp_deinit(adata->acp_mmio);
1126         if (status)
1127                 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
1128         pm_runtime_disable(&pdev->dev);
1129
1130         return 0;
1131 }
1132
1133 static int acp_pcm_resume(struct device *dev)
1134 {
1135         u16 bank;
1136         int status;
1137         struct audio_drv_data *adata = dev_get_drvdata(dev);
1138
1139         status = acp_init(adata->acp_mmio, adata->asic_type);
1140         if (status) {
1141                 dev_err(dev, "ACP Init failed status:%d\n", status);
1142                 return status;
1143         }
1144
1145         if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
1146                 /*
1147                  * For Stoney, Memory gating is disabled,i.e SRAM Banks
1148                  * won't be turned off. The default state for SRAM banks is ON.
1149                  * Setting SRAM bank state code skipped for STONEY platform.
1150                  */
1151                 if (adata->asic_type != CHIP_STONEY) {
1152                         for (bank = 1; bank <= 4; bank++)
1153                                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1154                                                         true);
1155                 }
1156                 config_acp_dma(adata->acp_mmio,
1157                                adata->play_i2ssp_stream->runtime->private_data,
1158                                adata->asic_type);
1159         }
1160         if (adata->capture_i2ssp_stream &&
1161             adata->capture_i2ssp_stream->runtime) {
1162                 if (adata->asic_type != CHIP_STONEY) {
1163                         for (bank = 5; bank <= 8; bank++)
1164                                 acp_set_sram_bank_state(adata->acp_mmio, bank,
1165                                                         true);
1166                 }
1167                 config_acp_dma(adata->acp_mmio,
1168                                adata->capture_i2ssp_stream->runtime->private_data,
1169                                adata->asic_type);
1170         }
1171         acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1172         return 0;
1173 }
1174
1175 static int acp_pcm_runtime_suspend(struct device *dev)
1176 {
1177         int status;
1178         struct audio_drv_data *adata = dev_get_drvdata(dev);
1179
1180         status = acp_deinit(adata->acp_mmio);
1181         if (status)
1182                 dev_err(dev, "ACP Deinit failed status:%d\n", status);
1183         acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1184         return 0;
1185 }
1186
1187 static int acp_pcm_runtime_resume(struct device *dev)
1188 {
1189         int status;
1190         struct audio_drv_data *adata = dev_get_drvdata(dev);
1191
1192         status = acp_init(adata->acp_mmio, adata->asic_type);
1193         if (status) {
1194                 dev_err(dev, "ACP Init failed status:%d\n", status);
1195                 return status;
1196         }
1197         acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1198         return 0;
1199 }
1200
1201 static const struct dev_pm_ops acp_pm_ops = {
1202         .resume = acp_pcm_resume,
1203         .runtime_suspend = acp_pcm_runtime_suspend,
1204         .runtime_resume = acp_pcm_runtime_resume,
1205 };
1206
1207 static struct platform_driver acp_dma_driver = {
1208         .probe = acp_audio_probe,
1209         .remove = acp_audio_remove,
1210         .driver = {
1211                 .name = DRV_NAME,
1212                 .pm = &acp_pm_ops,
1213         },
1214 };
1215
1216 module_platform_driver(acp_dma_driver);
1217
1218 MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
1219 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
1220 MODULE_DESCRIPTION("AMD ACP PCM Driver");
1221 MODULE_LICENSE("GPL v2");
1222 MODULE_ALIAS("platform:"DRV_NAME);