1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Digigram VXpocket soundcards
5 * lowlevel routines for VXpocket soundcards
7 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/firmware.h>
14 #include <sound/core.h>
18 static const int vxp_reg_offset[VX_REG_MAX] = {
19 [VX_ICR] = 0x00, // ICR
20 [VX_CVR] = 0x01, // CVR
21 [VX_ISR] = 0x02, // ISR
22 [VX_IVR] = 0x03, // IVR
23 [VX_RXH] = 0x05, // RXH
24 [VX_RXM] = 0x06, // RXM
25 [VX_RXL] = 0x07, // RXL
26 [VX_DMA] = 0x04, // DMA
27 [VX_CDSP] = 0x08, // CDSP
28 [VX_LOFREQ] = 0x09, // LFREQ
29 [VX_HIFREQ] = 0x0a, // HFREQ
30 [VX_DATA] = 0x0b, // DATA
31 [VX_MICRO] = 0x0c, // MICRO
32 [VX_DIALOG] = 0x0d, // DIALOG
33 [VX_CSUER] = 0x0e, // CSUER
34 [VX_RUER] = 0x0f, // RUER
38 static inline unsigned long vxp_reg_addr(struct vx_core *_chip, int reg)
40 struct snd_vxpocket *chip = to_vxpocket(_chip);
41 return chip->port + vxp_reg_offset[reg];
45 * snd_vx_inb - read a byte from the register
46 * @offset: register offset
48 static unsigned char vxp_inb(struct vx_core *chip, int offset)
50 return inb(vxp_reg_addr(chip, offset));
54 * snd_vx_outb - write a byte on the register
55 * @offset: the register offset
56 * @val: the value to write
58 static void vxp_outb(struct vx_core *chip, int offset, unsigned char val)
60 outb(val, vxp_reg_addr(chip, offset));
64 * redefine macros to call directly
67 #define vx_inb(chip,reg) vxp_inb((struct vx_core *)(chip), VX_##reg)
69 #define vx_outb(chip,reg,val) vxp_outb((struct vx_core *)(chip), VX_##reg,val)
73 * vx_check_magic - check the magic word on xilinx
75 * returns zero if a magic word is detected, or a negative error code.
77 static int vx_check_magic(struct vx_core *chip)
79 unsigned long end_time = jiffies + HZ / 5;
82 c = vx_inb(chip, CDSP);
86 } while (time_after_eq(end_time, jiffies));
87 snd_printk(KERN_ERR "cannot find xilinx magic word (%x)\n", c);
93 * vx_reset_dsp - reset the DSP
96 #define XX_DSP_RESET_WAIT_TIME 2 /* ms */
98 static void vxp_reset_dsp(struct vx_core *_chip)
100 struct snd_vxpocket *chip = to_vxpocket(_chip);
102 /* set the reset dsp bit to 1 */
103 vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_DSP_RESET_MASK);
105 mdelay(XX_DSP_RESET_WAIT_TIME);
107 chip->regCDSP &= ~VXP_CDSP_DSP_RESET_MASK;
108 vx_outb(chip, CDSP, chip->regCDSP);
110 mdelay(XX_DSP_RESET_WAIT_TIME);
116 static void vxp_reset_codec(struct vx_core *_chip)
118 struct snd_vxpocket *chip = to_vxpocket(_chip);
120 /* Set the reset CODEC bit to 1. */
121 vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK);
124 /* Set the reset CODEC bit to 0. */
125 chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK;
126 vx_outb(chip, CDSP, chip->regCDSP);
132 * vx_load_xilinx_binary - load the xilinx binary image
133 * the binary image is the binary array converted from the bitstream file.
135 static int vxp_load_xilinx_binary(struct vx_core *_chip, const struct firmware *fw)
137 struct snd_vxpocket *chip = to_vxpocket(_chip);
140 int regCSUER, regRUER;
141 const unsigned char *image;
144 /* Switch to programmation mode */
145 chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
146 vx_outb(chip, DIALOG, chip->regDIALOG);
148 /* Save register CSUER and RUER */
149 regCSUER = vx_inb(chip, CSUER);
150 regRUER = vx_inb(chip, RUER);
152 /* reset HF0 and HF1 */
153 vx_outb(chip, ICR, 0);
155 /* Wait for answer HF2 equal to 1 */
156 snd_printdd(KERN_DEBUG "check ISR_HF2\n");
157 if (vx_check_isr(_chip, ISR_HF2, ISR_HF2, 20) < 0)
160 /* set HF1 for loading xilinx binary */
161 vx_outb(chip, ICR, ICR_HF1);
163 for (i = 0; i < fw->size; i++, image++) {
165 if (vx_wait_isr_bit(_chip, ISR_TX_EMPTY) < 0)
167 vx_outb(chip, TXL, data);
168 /* wait for reading */
169 if (vx_wait_for_rx_full(_chip) < 0)
171 c = vx_inb(chip, RXL);
173 snd_printk(KERN_ERR "vxpocket: load xilinx mismatch at %d: 0x%x != 0x%x\n", i, c, (int)data);
177 vx_outb(chip, ICR, 0);
180 if (vx_check_isr(_chip, ISR_HF3, ISR_HF3, 20) < 0)
183 /* read the number of bytes received */
184 if (vx_wait_for_rx_full(_chip) < 0)
187 c = (int)vx_inb(chip, RXH) << 16;
188 c |= (int)vx_inb(chip, RXM) << 8;
189 c |= vx_inb(chip, RXL);
191 snd_printdd(KERN_DEBUG "xilinx: dsp size received 0x%x, orig 0x%zx\n", c, fw->size);
193 vx_outb(chip, ICR, ICR_HF0);
195 /* TEMPO 250ms : wait until Xilinx is downloaded */
198 /* test magical word */
199 if (vx_check_magic(_chip) < 0)
202 /* Restore register 0x0E and 0x0F (thus replacing COR and FCSR) */
203 vx_outb(chip, CSUER, regCSUER);
204 vx_outb(chip, RUER, regRUER);
206 /* Reset the Xilinx's signal enabling IO access */
207 chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK;
208 vx_outb(chip, DIALOG, chip->regDIALOG);
209 vx_inb(chip, DIALOG);
211 chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
212 vx_outb(chip, DIALOG, chip->regDIALOG);
213 vx_inb(chip, DIALOG);
215 /* Reset of the Codec */
216 vxp_reset_codec(_chip);
222 vx_outb(chip, CSUER, regCSUER);
223 vx_outb(chip, RUER, regRUER);
224 chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK;
225 vx_outb(chip, DIALOG, chip->regDIALOG);
231 * vxp_load_dsp - load_dsp callback
233 static int vxp_load_dsp(struct vx_core *vx, int index, const struct firmware *fw)
240 err = vx_check_magic(vx);
243 err = snd_vx_load_boot_image(vx, fw);
249 return vxp_load_xilinx_binary(vx, fw);
252 return snd_vx_dsp_boot(vx, fw);
255 return snd_vx_dsp_load(vx, fw);
264 * vx_test_and_ack - test and acknowledge interrupt
266 * called from irq hander, too
270 static int vxp_test_and_ack(struct vx_core *_chip)
272 struct snd_vxpocket *chip = to_vxpocket(_chip);
274 /* not booted yet? */
275 if (! (_chip->chip_status & VX_STAT_XILINX_LOADED))
278 if (! (vx_inb(chip, DIALOG) & VXP_DLG_MEMIRQ_MASK))
281 /* ok, interrupts generated, now ack it */
282 /* set ACQUIT bit up and down */
283 vx_outb(chip, DIALOG, chip->regDIALOG | VXP_DLG_ACK_MEMIRQ_MASK);
284 /* useless read just to spend some time and maintain
285 * the ACQUIT signal up for a while ( a bus cycle )
287 vx_inb(chip, DIALOG);
288 vx_outb(chip, DIALOG, chip->regDIALOG & ~VXP_DLG_ACK_MEMIRQ_MASK);
295 * vx_validate_irq - enable/disable IRQ
297 static void vxp_validate_irq(struct vx_core *_chip, int enable)
299 struct snd_vxpocket *chip = to_vxpocket(_chip);
301 /* Set the interrupt enable bit to 1 in CDSP register */
303 chip->regCDSP |= VXP_CDSP_VALID_IRQ_MASK;
305 chip->regCDSP &= ~VXP_CDSP_VALID_IRQ_MASK;
306 vx_outb(chip, CDSP, chip->regCDSP);
310 * vx_setup_pseudo_dma - set up the pseudo dma read/write mode.
311 * @do_write: 0 = read, 1 = set up for DMA write
313 static void vx_setup_pseudo_dma(struct vx_core *_chip, int do_write)
315 struct snd_vxpocket *chip = to_vxpocket(_chip);
317 /* Interrupt mode and HREQ pin enabled for host transmit / receive data transfers */
318 vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ);
319 /* Reset the pseudo-dma register */
321 vx_outb(chip, ISR, 0);
323 /* Select DMA in read/write transfer mode and in 16-bit accesses */
324 chip->regDIALOG |= VXP_DLG_DMA16_SEL_MASK;
325 chip->regDIALOG |= do_write ? VXP_DLG_DMAWRITE_SEL_MASK : VXP_DLG_DMAREAD_SEL_MASK;
326 vx_outb(chip, DIALOG, chip->regDIALOG);
331 * vx_release_pseudo_dma - disable the pseudo-DMA mode
333 static void vx_release_pseudo_dma(struct vx_core *_chip)
335 struct snd_vxpocket *chip = to_vxpocket(_chip);
337 /* Disable DMA and 16-bit accesses */
338 chip->regDIALOG &= ~(VXP_DLG_DMAWRITE_SEL_MASK|
339 VXP_DLG_DMAREAD_SEL_MASK|
340 VXP_DLG_DMA16_SEL_MASK);
341 vx_outb(chip, DIALOG, chip->regDIALOG);
342 /* HREQ pin disabled. */
343 vx_outb(chip, ICR, 0);
347 * vx_pseudo_dma_write - write bulk data on pseudo-DMA mode
348 * @count: data length to transfer in bytes
350 * data size must be aligned to 6 bytes to ensure the 24bit alignment on DSP.
351 * NB: call with a certain lock!
353 static void vxp_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
354 struct vx_pipe *pipe, int count)
356 long port = vxp_reg_addr(chip, VX_DMA);
357 int offset = pipe->hw_ptr;
358 unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
360 vx_setup_pseudo_dma(chip, 1);
361 if (offset + count >= pipe->buffer_bytes) {
362 int length = pipe->buffer_bytes - offset;
364 length >>= 1; /* in 16bit words */
365 /* Transfer using pseudo-dma. */
366 for (; length > 0; length--) {
370 addr = (unsigned short *)runtime->dma_area;
373 pipe->hw_ptr += count;
374 count >>= 1; /* in 16bit words */
375 /* Transfer using pseudo-dma. */
376 for (; count > 0; count--) {
380 vx_release_pseudo_dma(chip);
385 * vx_pseudo_dma_read - read bulk data on pseudo DMA mode
386 * @offset: buffer offset in bytes
387 * @count: data length to transfer in bytes
389 * the read length must be aligned to 6 bytes, as well as write.
390 * NB: call with a certain lock!
392 static void vxp_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
393 struct vx_pipe *pipe, int count)
395 struct snd_vxpocket *pchip = to_vxpocket(chip);
396 long port = vxp_reg_addr(chip, VX_DMA);
397 int offset = pipe->hw_ptr;
398 unsigned short *addr = (unsigned short *)(runtime->dma_area + offset);
400 if (snd_BUG_ON(count % 2))
402 vx_setup_pseudo_dma(chip, 0);
403 if (offset + count >= pipe->buffer_bytes) {
404 int length = pipe->buffer_bytes - offset;
406 length >>= 1; /* in 16bit words */
407 /* Transfer using pseudo-dma. */
408 for (; length > 0; length--)
410 addr = (unsigned short *)runtime->dma_area;
413 pipe->hw_ptr += count;
414 count >>= 1; /* in 16bit words */
415 /* Transfer using pseudo-dma. */
416 for (; count > 1; count--)
419 pchip->regDIALOG &= ~VXP_DLG_DMAREAD_SEL_MASK;
420 vx_outb(chip, DIALOG, pchip->regDIALOG);
421 /* Read the last word (16 bits) */
423 /* Disable 16-bit accesses */
424 pchip->regDIALOG &= ~VXP_DLG_DMA16_SEL_MASK;
425 vx_outb(chip, DIALOG, pchip->regDIALOG);
426 /* HREQ pin disabled. */
427 vx_outb(chip, ICR, 0);
432 * write a codec data (24bit)
434 static void vxp_write_codec_reg(struct vx_core *chip, int codec, unsigned int data)
438 /* Activate access to the corresponding codec register */
440 vx_inb(chip, LOFREQ);
442 vx_inb(chip, CODEC2);
444 /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */
445 for (i = 0; i < 24; i++, data <<= 1)
446 vx_outb(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0));
448 /* Terminate access to codec registers */
449 vx_inb(chip, HIFREQ);
454 * vx_set_mic_boost - set mic boost level (on vxp440 only)
455 * @boost: 0 = 20dB, 1 = +38dB
457 void vx_set_mic_boost(struct vx_core *chip, int boost)
459 struct snd_vxpocket *pchip = to_vxpocket(chip);
461 if (chip->chip_status & VX_STAT_IS_STALE)
464 mutex_lock(&chip->lock);
465 if (pchip->regCDSP & P24_CDSP_MICS_SEL_MASK) {
468 pchip->regCDSP &= ~P24_CDSP_MIC20_SEL_MASK;
469 pchip->regCDSP |= P24_CDSP_MIC38_SEL_MASK;
471 /* minimum value: 20 dB */
472 pchip->regCDSP |= P24_CDSP_MIC20_SEL_MASK;
473 pchip->regCDSP &= ~P24_CDSP_MIC38_SEL_MASK;
475 vx_outb(chip, CDSP, pchip->regCDSP);
477 mutex_unlock(&chip->lock);
481 * remap the linear value (0-8) to the actual value (0-15)
483 static int vx_compute_mic_level(int level)
486 case 5: level = 6 ; break;
487 case 6: level = 8 ; break;
488 case 7: level = 11; break;
489 case 8: level = 15; break;
496 * vx_set_mic_level - set mic level (on vxpocket only)
497 * @level: the mic level = 0 - 8 (max)
499 void vx_set_mic_level(struct vx_core *chip, int level)
501 struct snd_vxpocket *pchip = to_vxpocket(chip);
503 if (chip->chip_status & VX_STAT_IS_STALE)
506 mutex_lock(&chip->lock);
507 if (pchip->regCDSP & VXP_CDSP_MIC_SEL_MASK) {
508 level = vx_compute_mic_level(level);
509 vx_outb(chip, MICRO, level);
511 mutex_unlock(&chip->lock);
516 * change the input audio source
518 static void vxp_change_audio_source(struct vx_core *_chip, int src)
520 struct snd_vxpocket *chip = to_vxpocket(_chip);
523 case VX_AUDIO_SRC_DIGITAL:
524 chip->regCDSP |= VXP_CDSP_DATAIN_SEL_MASK;
525 vx_outb(chip, CDSP, chip->regCDSP);
527 case VX_AUDIO_SRC_LINE:
528 chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
529 if (_chip->type == VX_TYPE_VXP440)
530 chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
532 chip->regCDSP &= ~VXP_CDSP_MIC_SEL_MASK;
533 vx_outb(chip, CDSP, chip->regCDSP);
535 case VX_AUDIO_SRC_MIC:
536 chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK;
537 /* reset mic levels */
538 if (_chip->type == VX_TYPE_VXP440) {
539 chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK;
541 chip->regCDSP |= P24_CDSP_MIC38_SEL_MASK;
543 chip->regCDSP |= P24_CDSP_MIC20_SEL_MASK;
544 vx_outb(chip, CDSP, chip->regCDSP);
546 chip->regCDSP |= VXP_CDSP_MIC_SEL_MASK;
547 vx_outb(chip, CDSP, chip->regCDSP);
548 vx_outb(chip, MICRO, vx_compute_mic_level(chip->mic_level));
555 * change the clock source
556 * source = INTERNAL_QUARTZ or UER_SYNC
558 static void vxp_set_clock_source(struct vx_core *_chip, int source)
560 struct snd_vxpocket *chip = to_vxpocket(_chip);
562 if (source == INTERNAL_QUARTZ)
563 chip->regCDSP &= ~VXP_CDSP_CLOCKIN_SEL_MASK;
565 chip->regCDSP |= VXP_CDSP_CLOCKIN_SEL_MASK;
566 vx_outb(chip, CDSP, chip->regCDSP);
573 static void vxp_reset_board(struct vx_core *_chip, int cold_reset)
575 struct snd_vxpocket *chip = to_vxpocket(_chip);
586 const struct snd_vx_ops snd_vxpocket_ops = {
589 .test_and_ack = vxp_test_and_ack,
590 .validate_irq = vxp_validate_irq,
591 .write_codec = vxp_write_codec_reg,
592 .reset_codec = vxp_reset_codec,
593 .change_audio_source = vxp_change_audio_source,
594 .set_clock_source = vxp_set_clock_source,
595 .load_dsp = vxp_load_dsp,
596 .add_controls = vxp_add_mic_controls,
597 .reset_dsp = vxp_reset_dsp,
598 .reset_board = vxp_reset_board,
599 .dma_write = vxp_dma_write,
600 .dma_read = vxp_dma_read,