1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ALSA driver for RME Hammerfall DSP audio interface(s)
5 * Copyright (c) 2002 Paul Davis
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/pci.h>
14 #include <linux/firmware.h>
15 #include <linux/module.h>
16 #include <linux/math64.h>
17 #include <linux/vmalloc.h>
19 #include <linux/nospec.h>
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/info.h>
25 #include <sound/asoundef.h>
26 #include <sound/rawmidi.h>
27 #include <sound/hwdep.h>
28 #include <sound/initval.h>
29 #include <sound/hdsp.h>
31 #include <asm/byteorder.h>
32 #include <asm/current.h>
34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
38 module_param_array(index, int, NULL, 0444);
39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40 module_param_array(id, charp, NULL, 0444);
41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42 module_param_array(enable, bool, NULL, 0444);
43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45 MODULE_DESCRIPTION("RME Hammerfall DSP");
46 MODULE_LICENSE("GPL");
47 MODULE_FIRMWARE("rpm_firmware.bin");
48 MODULE_FIRMWARE("multiface_firmware.bin");
49 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
50 MODULE_FIRMWARE("digiface_firmware.bin");
51 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
53 #define HDSP_MAX_CHANNELS 26
54 #define HDSP_MAX_DS_CHANNELS 14
55 #define HDSP_MAX_QS_CHANNELS 8
56 #define DIGIFACE_SS_CHANNELS 26
57 #define DIGIFACE_DS_CHANNELS 14
58 #define MULTIFACE_SS_CHANNELS 18
59 #define MULTIFACE_DS_CHANNELS 14
60 #define H9652_SS_CHANNELS 26
61 #define H9652_DS_CHANNELS 14
62 /* This does not include possible Analog Extension Boards
63 AEBs are detected at card initialization
65 #define H9632_SS_CHANNELS 12
66 #define H9632_DS_CHANNELS 8
67 #define H9632_QS_CHANNELS 4
68 #define RPM_CHANNELS 6
70 /* Write registers. These are defined as byte-offsets from the iobase value.
72 #define HDSP_resetPointer 0
73 #define HDSP_freqReg 0
74 #define HDSP_outputBufferAddress 32
75 #define HDSP_inputBufferAddress 36
76 #define HDSP_controlRegister 64
77 #define HDSP_interruptConfirmation 96
78 #define HDSP_outputEnable 128
79 #define HDSP_control2Reg 256
80 #define HDSP_midiDataOut0 352
81 #define HDSP_midiDataOut1 356
82 #define HDSP_fifoData 368
83 #define HDSP_inputEnable 384
85 /* Read registers. These are defined as byte-offsets from the iobase value
88 #define HDSP_statusRegister 0
89 #define HDSP_timecode 128
90 #define HDSP_status2Register 192
91 #define HDSP_midiDataIn0 360
92 #define HDSP_midiDataIn1 364
93 #define HDSP_midiStatusOut0 384
94 #define HDSP_midiStatusOut1 388
95 #define HDSP_midiStatusIn0 392
96 #define HDSP_midiStatusIn1 396
97 #define HDSP_fifoStatus 400
99 /* the meters are regular i/o-mapped registers, but offset
100 considerably from the rest. the peak registers are reset
101 when read; the least-significant 4 bits are full-scale counters;
102 the actual peak value is in the most-significant 24 bits.
105 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
106 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
107 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
108 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
109 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
112 /* This is for H9652 cards
113 Peak values are read downward from the base
114 Rms values are read upward
115 There are rms values for the outputs too
116 26*3 values are read in ss mode
117 14*3 in ds mode, with no gap between values
119 #define HDSP_9652_peakBase 7164
120 #define HDSP_9652_rmsBase 4096
122 /* c.f. the hdsp_9632_meters_t struct */
123 #define HDSP_9632_metersBase 4096
125 #define HDSP_IO_EXTENT 7168
127 /* control2 register bits */
129 #define HDSP_TMS 0x01
130 #define HDSP_TCK 0x02
131 #define HDSP_TDI 0x04
132 #define HDSP_JTAG 0x08
133 #define HDSP_PWDN 0x10
134 #define HDSP_PROGRAM 0x020
135 #define HDSP_CONFIG_MODE_0 0x040
136 #define HDSP_CONFIG_MODE_1 0x080
137 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
138 #define HDSP_BIGENDIAN_MODE 0x200
139 #define HDSP_RD_MULTIPLE 0x400
140 #define HDSP_9652_ENABLE_MIXER 0x800
141 #define HDSP_S200 0x800
142 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
143 #define HDSP_CYCLIC_MODE 0x1000
144 #define HDSP_TDO 0x10000000
146 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
147 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
149 /* Control Register bits */
151 #define HDSP_Start (1<<0) /* start engine */
152 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
153 #define HDSP_Latency1 (1<<2) /* [ see above ] */
154 #define HDSP_Latency2 (1<<3) /* [ see above ] */
155 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
156 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
157 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
158 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
159 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
160 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
161 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
162 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
163 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
164 #define HDSP_SyncRef2 (1<<13)
165 #define HDSP_SPDIFInputSelect0 (1<<14)
166 #define HDSP_SPDIFInputSelect1 (1<<15)
167 #define HDSP_SyncRef0 (1<<16)
168 #define HDSP_SyncRef1 (1<<17)
169 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
170 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
171 #define HDSP_Midi0InterruptEnable (1<<22)
172 #define HDSP_Midi1InterruptEnable (1<<23)
173 #define HDSP_LineOut (1<<24)
174 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
175 #define HDSP_ADGain1 (1<<26)
176 #define HDSP_DAGain0 (1<<27)
177 #define HDSP_DAGain1 (1<<28)
178 #define HDSP_PhoneGain0 (1<<29)
179 #define HDSP_PhoneGain1 (1<<30)
180 #define HDSP_QuadSpeed (1<<31)
182 /* RPM uses some of the registers for special purposes */
183 #define HDSP_RPM_Inp12 0x04A00
184 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
185 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
186 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
187 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
188 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
190 #define HDSP_RPM_Inp34 0x32000
191 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
192 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
193 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
194 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
195 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
197 #define HDSP_RPM_Bypass 0x01000
199 #define HDSP_RPM_Disconnect 0x00001
201 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
202 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
203 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
204 #define HDSP_ADGainLowGain 0
206 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
207 #define HDSP_DAGainHighGain HDSP_DAGainMask
208 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
209 #define HDSP_DAGainMinus10dBV 0
211 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
212 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
213 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
214 #define HDSP_PhoneGainMinus12dB 0
216 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
217 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
219 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
220 #define HDSP_SPDIFInputADAT1 0
221 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
222 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
223 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
225 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
226 #define HDSP_SyncRef_ADAT1 0
227 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
228 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
229 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
230 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
231 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
233 /* Sample Clock Sources */
235 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
236 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
237 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
238 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
239 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
240 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
241 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
242 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
243 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
244 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
246 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
248 #define HDSP_SYNC_FROM_WORD 0
249 #define HDSP_SYNC_FROM_SPDIF 1
250 #define HDSP_SYNC_FROM_ADAT1 2
251 #define HDSP_SYNC_FROM_ADAT_SYNC 3
252 #define HDSP_SYNC_FROM_ADAT2 4
253 #define HDSP_SYNC_FROM_ADAT3 5
255 /* SyncCheck status */
257 #define HDSP_SYNC_CHECK_NO_LOCK 0
258 #define HDSP_SYNC_CHECK_LOCK 1
259 #define HDSP_SYNC_CHECK_SYNC 2
261 /* AutoSync references - used by "autosync_ref" control switch */
263 #define HDSP_AUTOSYNC_FROM_WORD 0
264 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
265 #define HDSP_AUTOSYNC_FROM_SPDIF 2
266 #define HDSP_AUTOSYNC_FROM_NONE 3
267 #define HDSP_AUTOSYNC_FROM_ADAT1 4
268 #define HDSP_AUTOSYNC_FROM_ADAT2 5
269 #define HDSP_AUTOSYNC_FROM_ADAT3 6
271 /* Possible sources of S/PDIF input */
273 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
274 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
275 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
276 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
278 #define HDSP_Frequency32KHz HDSP_Frequency0
279 #define HDSP_Frequency44_1KHz HDSP_Frequency1
280 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
281 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
282 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
283 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
284 /* For H9632 cards */
285 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
286 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
287 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
288 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
289 return 104857600000000 / rate; // 100 MHz
290 return 110100480000000 / rate; // 105 MHz
292 #define DDS_NUMERATOR 104857600000000ULL /* = 2^20 * 10^8 */
294 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
295 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
297 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
298 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
300 /* Status Register bits */
302 #define HDSP_audioIRQPending (1<<0)
303 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
304 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
305 #define HDSP_Lock1 (1<<2)
306 #define HDSP_Lock0 (1<<3)
307 #define HDSP_SPDIFSync (1<<4)
308 #define HDSP_TimecodeLock (1<<5)
309 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
310 #define HDSP_Sync2 (1<<16)
311 #define HDSP_Sync1 (1<<17)
312 #define HDSP_Sync0 (1<<18)
313 #define HDSP_DoubleSpeedStatus (1<<19)
314 #define HDSP_ConfigError (1<<20)
315 #define HDSP_DllError (1<<21)
316 #define HDSP_spdifFrequency0 (1<<22)
317 #define HDSP_spdifFrequency1 (1<<23)
318 #define HDSP_spdifFrequency2 (1<<24)
319 #define HDSP_SPDIFErrorFlag (1<<25)
320 #define HDSP_BufferID (1<<26)
321 #define HDSP_TimecodeSync (1<<27)
322 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
323 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
324 #define HDSP_midi0IRQPending (1<<30)
325 #define HDSP_midi1IRQPending (1<<31)
327 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
328 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
329 HDSP_spdifFrequency1|\
330 HDSP_spdifFrequency2|\
331 HDSP_spdifFrequency3)
333 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
334 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
335 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
337 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
338 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
339 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
341 /* This is for H9632 cards */
342 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
343 HDSP_spdifFrequency1|\
344 HDSP_spdifFrequency2)
345 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
346 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
348 /* Status2 Register bits */
350 #define HDSP_version0 (1<<0)
351 #define HDSP_version1 (1<<1)
352 #define HDSP_version2 (1<<2)
353 #define HDSP_wc_lock (1<<3)
354 #define HDSP_wc_sync (1<<4)
355 #define HDSP_inp_freq0 (1<<5)
356 #define HDSP_inp_freq1 (1<<6)
357 #define HDSP_inp_freq2 (1<<7)
358 #define HDSP_SelSyncRef0 (1<<8)
359 #define HDSP_SelSyncRef1 (1<<9)
360 #define HDSP_SelSyncRef2 (1<<10)
362 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
364 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
365 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
366 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
367 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
368 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
369 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
370 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
371 /* FIXME : more values for 9632 cards ? */
373 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
374 #define HDSP_SelSyncRef_ADAT1 0
375 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
376 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
377 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
378 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
379 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
381 /* Card state flags */
383 #define HDSP_InitializationComplete (1<<0)
384 #define HDSP_FirmwareLoaded (1<<1)
385 #define HDSP_FirmwareCached (1<<2)
387 /* FIFO wait times, defined in terms of 1/10ths of msecs */
389 #define HDSP_LONG_WAIT 5000
390 #define HDSP_SHORT_WAIT 30
392 #define UNITY_GAIN 32768
393 #define MINUS_INFINITY_GAIN 0
395 /* the size of a substream (1 mono data stream) */
397 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
398 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
400 /* the size of the area we need to allocate for DMA transfers. the
401 size is the same regardless of the number of channels - the
402 Multiface still uses the same memory area.
404 Note that we allocate 1 more channel than is apparently needed
405 because the h/w seems to write 1 byte beyond the end of the last
409 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
410 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
412 #define HDSP_FIRMWARE_SIZE (24413 * 4)
414 struct hdsp_9632_meters {
416 u32 playback_peak[16];
420 u32 input_rms_low[16];
421 u32 playback_rms_low[16];
422 u32 output_rms_low[16];
424 u32 input_rms_high[16];
425 u32 playback_rms_high[16];
426 u32 output_rms_high[16];
427 u32 xxx_rms_high[16];
433 struct snd_rawmidi *rmidi;
434 struct snd_rawmidi_substream *input;
435 struct snd_rawmidi_substream *output;
436 signed char istimer; /* timer in use */
437 struct timer_list timer;
444 struct snd_pcm_substream *capture_substream;
445 struct snd_pcm_substream *playback_substream;
446 struct hdsp_midi midi[2];
447 struct work_struct midi_work;
450 u32 control_register; /* cached value */
451 u32 control2_register; /* cached value */
453 u32 creg_spdif_stream;
454 int clock_source_locked;
455 char *card_name; /* digiface/multiface/rpm */
456 enum HDSP_IO_Type io_type; /* ditto, but for code use */
457 unsigned short firmware_rev;
458 unsigned short state; /* stores state bits */
459 const struct firmware *firmware;
461 size_t period_bytes; /* guess what this is */
462 unsigned char max_channels;
463 unsigned char qs_in_channels; /* quad speed mode for H9632 */
464 unsigned char ds_in_channels;
465 unsigned char ss_in_channels; /* different for multiface/digiface */
466 unsigned char qs_out_channels;
467 unsigned char ds_out_channels;
468 unsigned char ss_out_channels;
469 u32 io_loopback; /* output loopback channel states*/
471 /* DMA buffers; those are copied instances from the original snd_dma_buf
472 * objects (which are managed via devres) for the address alignments
474 struct snd_dma_buffer capture_dma_buf;
475 struct snd_dma_buffer playback_dma_buf;
476 unsigned char *capture_buffer; /* suitably aligned address */
477 unsigned char *playback_buffer; /* suitably aligned address */
482 int system_sample_rate;
483 const signed char *channel_map;
487 void __iomem *iobase;
488 struct snd_card *card;
490 struct snd_hwdep *hwdep;
492 struct snd_kcontrol *spdif_ctl;
493 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
494 unsigned int dds_value; /* last value written to freq register */
497 /* These tables map the ALSA channels 1..N to the channels that we
498 need to use in order to find the relevant channel buffer. RME
499 refer to this kind of mapping as between "the ADAT channel and
500 the DMA channel." We index it using the logical audio channel,
501 and the value is the DMA channel (i.e. channel buffer number)
502 where the data for that channel can be read/written from/to.
505 static const signed char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
506 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
507 18, 19, 20, 21, 22, 23, 24, 25
510 static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
512 0, 1, 2, 3, 4, 5, 6, 7,
514 16, 17, 18, 19, 20, 21, 22, 23,
517 -1, -1, -1, -1, -1, -1, -1, -1
520 static const signed char channel_map_ds[HDSP_MAX_CHANNELS] = {
521 /* ADAT channels are remapped */
522 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
523 /* channels 12 and 13 are S/PDIF */
525 /* others don't exist */
526 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
529 static const signed char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
531 0, 1, 2, 3, 4, 5, 6, 7,
536 /* AO4S-192 and AI4S-192 extension boards */
538 /* others don't exist */
539 -1, -1, -1, -1, -1, -1, -1, -1,
543 static const signed char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
550 /* AO4S-192 and AI4S-192 extension boards */
552 /* others don't exist */
553 -1, -1, -1, -1, -1, -1, -1, -1,
554 -1, -1, -1, -1, -1, -1
557 static const signed char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
558 /* ADAT is disabled in this mode */
563 /* AO4S-192 and AI4S-192 extension boards */
565 /* others don't exist */
566 -1, -1, -1, -1, -1, -1, -1, -1,
567 -1, -1, -1, -1, -1, -1, -1, -1,
571 static struct snd_dma_buffer *
572 snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size)
574 return snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, size);
577 static const struct pci_device_id snd_hdsp_ids[] = {
579 .vendor = PCI_VENDOR_ID_XILINX,
580 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
581 .subvendor = PCI_ANY_ID,
582 .subdevice = PCI_ANY_ID,
583 }, /* RME Hammerfall-DSP */
587 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
590 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
591 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
592 static int snd_hdsp_enable_io (struct hdsp *hdsp);
593 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
594 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
595 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
596 static int hdsp_autosync_ref(struct hdsp *hdsp);
597 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
598 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
600 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
602 switch (hdsp->io_type) {
607 if (hdsp->firmware_rev == 0xa)
608 return (64 * out) + (32 + (in));
610 return (52 * out) + (26 + (in));
612 return (32 * out) + (16 + (in));
614 return (52 * out) + (26 + (in));
618 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
620 switch (hdsp->io_type) {
625 if (hdsp->firmware_rev == 0xa)
626 return (64 * out) + in;
628 return (52 * out) + in;
630 return (32 * out) + in;
632 return (52 * out) + in;
636 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
638 writel(val, hdsp->iobase + reg);
641 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
643 return readl (hdsp->iobase + reg);
646 static int hdsp_check_for_iobox (struct hdsp *hdsp)
650 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
651 for (i = 0; i < 500; i++) {
652 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
655 dev_dbg(hdsp->card->dev,
656 "IO box found after %d ms\n",
663 dev_err(hdsp->card->dev, "no IO box connected!\n");
664 hdsp->state &= ~HDSP_FirmwareLoaded;
668 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
673 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
676 for (i = 0; i != loops; ++i) {
677 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
680 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
686 dev_info(hdsp->card->dev, "no IO box connected!\n");
687 hdsp->state &= ~HDSP_FirmwareLoaded;
691 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
697 if (hdsp->fw_uploaded)
698 cache = hdsp->fw_uploaded;
702 cache = (u32 *)hdsp->firmware->data;
707 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
709 dev_info(hdsp->card->dev, "loading firmware\n");
711 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
712 hdsp_write (hdsp, HDSP_fifoData, 0);
714 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
715 dev_info(hdsp->card->dev,
716 "timeout waiting for download preparation\n");
717 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
721 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
723 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
724 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
725 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
726 dev_info(hdsp->card->dev,
727 "timeout during firmware loading\n");
728 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
733 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
734 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
737 #ifdef SNDRV_BIG_ENDIAN
738 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
740 hdsp->control2_register = 0;
742 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
743 dev_info(hdsp->card->dev, "finished firmware loading\n");
746 if (hdsp->state & HDSP_InitializationComplete) {
747 dev_info(hdsp->card->dev,
748 "firmware loaded from cache, restoring defaults\n");
749 spin_lock_irqsave(&hdsp->lock, flags);
750 snd_hdsp_set_defaults(hdsp);
751 spin_unlock_irqrestore(&hdsp->lock, flags);
754 hdsp->state |= HDSP_FirmwareLoaded;
759 static int hdsp_get_iobox_version (struct hdsp *hdsp)
761 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
763 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
764 hdsp_write(hdsp, HDSP_fifoData, 0);
766 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
767 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
768 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
771 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
772 hdsp_write (hdsp, HDSP_fifoData, 0);
773 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
776 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
777 hdsp_write(hdsp, HDSP_fifoData, 0);
778 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
779 hdsp->io_type = Digiface;
780 dev_info(hdsp->card->dev, "Digiface found\n");
784 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
785 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
786 hdsp_write(hdsp, HDSP_fifoData, 0);
787 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
790 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
791 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
792 hdsp_write(hdsp, HDSP_fifoData, 0);
793 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
797 dev_info(hdsp->card->dev, "RPM found\n");
800 /* firmware was already loaded, get iobox type */
801 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
803 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
804 hdsp->io_type = Multiface;
806 hdsp->io_type = Digiface;
811 hdsp->io_type = Multiface;
812 dev_info(hdsp->card->dev, "Multiface found\n");
817 static int hdsp_request_fw_loader(struct hdsp *hdsp);
819 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
821 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
823 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
824 hdsp->state &= ~HDSP_FirmwareLoaded;
825 if (! load_on_demand)
827 dev_err(hdsp->card->dev, "firmware not present.\n");
828 /* try to load firmware */
829 if (! (hdsp->state & HDSP_FirmwareCached)) {
830 if (! hdsp_request_fw_loader(hdsp))
832 dev_err(hdsp->card->dev,
833 "No firmware loaded nor cached, please upload firmware.\n");
836 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
837 dev_err(hdsp->card->dev,
838 "Firmware loading from cache failed, please upload manually.\n");
846 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
850 /* the fifoStatus registers reports on how many words
851 are available in the command FIFO.
854 for (i = 0; i < timeout; i++) {
856 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
859 /* not very friendly, but we only do this during a firmware
860 load and changing the mixer, so we just put up with it.
866 dev_warn(hdsp->card->dev,
867 "wait for FIFO status <= %d failed after %d iterations\n",
872 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
874 if (addr >= HDSP_MATRIX_MIXER_SIZE)
877 return hdsp->mixer_matrix[addr];
880 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
884 if (addr >= HDSP_MATRIX_MIXER_SIZE)
887 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
889 /* from martin bjornsen:
891 "You can only write dwords to the
892 mixer memory which contain two
893 mixer values in the low and high
894 word. So if you want to change
895 value 0 you have to read value 1
896 from the cache and write both to
897 the first dword in the mixer
901 if (hdsp->io_type == H9632 && addr >= 512)
904 if (hdsp->io_type == H9652 && addr >= 1352)
907 hdsp->mixer_matrix[addr] = data;
910 /* `addr' addresses a 16-bit wide address, but
911 the address space accessed via hdsp_write
912 uses byte offsets. put another way, addr
913 varies from 0 to 1351, but to access the
914 corresponding memory location, we need
915 to access 0 to 2703 ...
919 hdsp_write (hdsp, 4096 + (ad*4),
920 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
921 hdsp->mixer_matrix[addr&0x7fe]);
927 ad = (addr << 16) + data;
929 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
932 hdsp_write (hdsp, HDSP_fifoData, ad);
933 hdsp->mixer_matrix[addr] = data;
940 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
945 spin_lock_irqsave(&hdsp->lock, flags);
946 if ((hdsp->playback_pid != hdsp->capture_pid) &&
947 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
949 spin_unlock_irqrestore(&hdsp->lock, flags);
953 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
955 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
956 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
958 /* For the 9632, the mask is different */
959 if (hdsp->io_type == H9632)
960 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
962 if (status & HDSP_SPDIFErrorFlag)
966 case HDSP_spdifFrequency32KHz: return 32000;
967 case HDSP_spdifFrequency44_1KHz: return 44100;
968 case HDSP_spdifFrequency48KHz: return 48000;
969 case HDSP_spdifFrequency64KHz: return 64000;
970 case HDSP_spdifFrequency88_2KHz: return 88200;
971 case HDSP_spdifFrequency96KHz: return 96000;
972 case HDSP_spdifFrequency128KHz:
973 if (hdsp->io_type == H9632) return 128000;
975 case HDSP_spdifFrequency176_4KHz:
976 if (hdsp->io_type == H9632) return 176400;
978 case HDSP_spdifFrequency192KHz:
979 if (hdsp->io_type == H9632) return 192000;
984 dev_warn(hdsp->card->dev,
985 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
990 static int hdsp_external_sample_rate(struct hdsp *hdsp)
992 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
993 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
995 /* For the 9632 card, there seems to be no bit for indicating external
996 * sample rate greater than 96kHz. The card reports the corresponding
997 * single speed. So the best means seems to get spdif rate when
998 * autosync reference is spdif */
999 if (hdsp->io_type == H9632 &&
1000 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1001 return hdsp_spdif_sample_rate(hdsp);
1003 switch (rate_bits) {
1004 case HDSP_systemFrequency32: return 32000;
1005 case HDSP_systemFrequency44_1: return 44100;
1006 case HDSP_systemFrequency48: return 48000;
1007 case HDSP_systemFrequency64: return 64000;
1008 case HDSP_systemFrequency88_2: return 88200;
1009 case HDSP_systemFrequency96: return 96000;
1015 static void hdsp_compute_period_size(struct hdsp *hdsp)
1017 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1020 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1024 position = hdsp_read(hdsp, HDSP_statusRegister);
1026 if (!hdsp->precise_ptr)
1027 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1029 position &= HDSP_BufferPositionMask;
1031 position &= (hdsp->period_bytes/2) - 1;
1035 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1037 hdsp_write (hdsp, HDSP_resetPointer, 0);
1038 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1039 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1040 * requires (?) to write again DDS value after a reset pointer
1041 * (at least, it works like this) */
1042 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1045 static void hdsp_start_audio(struct hdsp *s)
1047 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1048 hdsp_write(s, HDSP_controlRegister, s->control_register);
1051 static void hdsp_stop_audio(struct hdsp *s)
1053 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1054 hdsp_write(s, HDSP_controlRegister, s->control_register);
1057 static void hdsp_silence_playback(struct hdsp *hdsp)
1059 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1062 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1066 spin_lock_irq(&s->lock);
1075 s->control_register &= ~HDSP_LatencyMask;
1076 s->control_register |= hdsp_encode_latency(n);
1078 hdsp_write(s, HDSP_controlRegister, s->control_register);
1080 hdsp_compute_period_size(s);
1082 spin_unlock_irq(&s->lock);
1087 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1093 else if (rate >= 56000)
1097 n = div_u64(n, rate);
1098 /* n should be less than 2^32 for being written to FREQ register */
1099 snd_BUG_ON(n >> 32);
1100 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1101 value to write it after a reset */
1102 hdsp->dds_value = n;
1103 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1106 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1108 int reject_if_open = 0;
1112 /* ASSUMPTION: hdsp->lock is either held, or
1113 there is no need for it (e.g. during module
1117 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1118 if (called_internally) {
1119 /* request from ctl or card initialization */
1120 dev_err(hdsp->card->dev,
1121 "device is not running as a clock master: cannot set sample rate.\n");
1124 /* hw_param request while in AutoSync mode */
1125 int external_freq = hdsp_external_sample_rate(hdsp);
1126 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1128 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1129 dev_info(hdsp->card->dev,
1130 "Detected ADAT in double speed mode\n");
1131 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1132 dev_info(hdsp->card->dev,
1133 "Detected ADAT in quad speed mode\n");
1134 else if (rate != external_freq) {
1135 dev_info(hdsp->card->dev,
1136 "No AutoSync source for requested rate\n");
1142 current_rate = hdsp->system_sample_rate;
1144 /* Changing from a "single speed" to a "double speed" rate is
1145 not allowed if any substreams are open. This is because
1146 such a change causes a shift in the location of
1147 the DMA buffers and a reduction in the number of available
1150 Note that a similar but essentially insoluble problem
1151 exists for externally-driven rate changes. All we can do
1152 is to flag rate changes in the read/write routines. */
1154 if (rate > 96000 && hdsp->io_type != H9632)
1159 if (current_rate > 48000)
1161 rate_bits = HDSP_Frequency32KHz;
1164 if (current_rate > 48000)
1166 rate_bits = HDSP_Frequency44_1KHz;
1169 if (current_rate > 48000)
1171 rate_bits = HDSP_Frequency48KHz;
1174 if (current_rate <= 48000 || current_rate > 96000)
1176 rate_bits = HDSP_Frequency64KHz;
1179 if (current_rate <= 48000 || current_rate > 96000)
1181 rate_bits = HDSP_Frequency88_2KHz;
1184 if (current_rate <= 48000 || current_rate > 96000)
1186 rate_bits = HDSP_Frequency96KHz;
1189 if (current_rate < 128000)
1191 rate_bits = HDSP_Frequency128KHz;
1194 if (current_rate < 128000)
1196 rate_bits = HDSP_Frequency176_4KHz;
1199 if (current_rate < 128000)
1201 rate_bits = HDSP_Frequency192KHz;
1207 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1208 dev_warn(hdsp->card->dev,
1209 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1211 hdsp->playback_pid);
1215 hdsp->control_register &= ~HDSP_FrequencyMask;
1216 hdsp->control_register |= rate_bits;
1217 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1219 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1220 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1221 hdsp_set_dds_value(hdsp, rate);
1223 if (rate >= 128000) {
1224 hdsp->channel_map = channel_map_H9632_qs;
1225 } else if (rate > 48000) {
1226 if (hdsp->io_type == H9632)
1227 hdsp->channel_map = channel_map_H9632_ds;
1229 hdsp->channel_map = channel_map_ds;
1231 switch (hdsp->io_type) {
1234 hdsp->channel_map = channel_map_mf_ss;
1238 hdsp->channel_map = channel_map_df_ss;
1241 hdsp->channel_map = channel_map_H9632_ss;
1244 /* should never happen */
1249 hdsp->system_sample_rate = rate;
1254 /*----------------------------------------------------------------------------
1256 ----------------------------------------------------------------------------*/
1258 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1260 /* the hardware already does the relevant bit-mask with 0xff */
1262 return hdsp_read(hdsp, HDSP_midiDataIn1);
1264 return hdsp_read(hdsp, HDSP_midiDataIn0);
1267 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1269 /* the hardware already does the relevant bit-mask with 0xff */
1271 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1273 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1276 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1279 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1281 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1284 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1286 int fifo_bytes_used;
1289 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1291 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1293 if (fifo_bytes_used < 128)
1294 return 128 - fifo_bytes_used;
1299 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1301 while (snd_hdsp_midi_input_available (hdsp, id))
1302 snd_hdsp_midi_read_byte (hdsp, id);
1305 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1307 unsigned long flags;
1311 unsigned char buf[128];
1313 /* Output is not interrupt driven */
1315 spin_lock_irqsave (&hmidi->lock, flags);
1316 if (hmidi->output) {
1317 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1318 n_pending = snd_hdsp_midi_output_possible(hmidi->hdsp, hmidi->id);
1319 if (n_pending > 0) {
1320 if (n_pending > (int)sizeof (buf))
1321 n_pending = sizeof (buf);
1323 to_write = snd_rawmidi_transmit(hmidi->output, buf, n_pending);
1325 for (i = 0; i < to_write; ++i)
1326 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1331 spin_unlock_irqrestore (&hmidi->lock, flags);
1335 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1337 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1338 unsigned long flags;
1342 spin_lock_irqsave (&hmidi->lock, flags);
1343 n_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id);
1344 if (n_pending > 0) {
1346 if (n_pending > (int)sizeof (buf))
1347 n_pending = sizeof (buf);
1348 for (i = 0; i < n_pending; ++i)
1349 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1351 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1353 /* flush the MIDI input FIFO */
1355 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1360 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1362 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1363 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1364 spin_unlock_irqrestore (&hmidi->lock, flags);
1365 return snd_hdsp_midi_output_write (hmidi);
1368 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1371 struct hdsp_midi *hmidi;
1372 unsigned long flags;
1375 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1377 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1378 spin_lock_irqsave (&hdsp->lock, flags);
1380 if (!(hdsp->control_register & ie)) {
1381 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1382 hdsp->control_register |= ie;
1385 hdsp->control_register &= ~ie;
1388 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1389 spin_unlock_irqrestore (&hdsp->lock, flags);
1392 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1394 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1395 unsigned long flags;
1397 snd_hdsp_midi_output_write(hmidi);
1398 spin_lock_irqsave (&hmidi->lock, flags);
1400 /* this does not bump hmidi->istimer, because the
1401 kernel automatically removed the timer when it
1402 expired, and we are now adding it back, thus
1403 leaving istimer wherever it was set before.
1407 mod_timer(&hmidi->timer, 1 + jiffies);
1409 spin_unlock_irqrestore (&hmidi->lock, flags);
1412 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1414 struct hdsp_midi *hmidi;
1415 unsigned long flags;
1417 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1418 spin_lock_irqsave (&hmidi->lock, flags);
1420 if (!hmidi->istimer) {
1421 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1423 mod_timer(&hmidi->timer, 1 + jiffies);
1427 if (hmidi->istimer && --hmidi->istimer <= 0)
1428 del_timer (&hmidi->timer);
1430 spin_unlock_irqrestore (&hmidi->lock, flags);
1432 snd_hdsp_midi_output_write(hmidi);
1435 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1437 struct hdsp_midi *hmidi;
1439 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1440 spin_lock_irq (&hmidi->lock);
1441 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1442 hmidi->input = substream;
1443 spin_unlock_irq (&hmidi->lock);
1448 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1450 struct hdsp_midi *hmidi;
1452 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1453 spin_lock_irq (&hmidi->lock);
1454 hmidi->output = substream;
1455 spin_unlock_irq (&hmidi->lock);
1460 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1462 struct hdsp_midi *hmidi;
1464 snd_hdsp_midi_input_trigger (substream, 0);
1466 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1467 spin_lock_irq (&hmidi->lock);
1468 hmidi->input = NULL;
1469 spin_unlock_irq (&hmidi->lock);
1474 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1476 struct hdsp_midi *hmidi;
1478 snd_hdsp_midi_output_trigger (substream, 0);
1480 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1481 spin_lock_irq (&hmidi->lock);
1482 hmidi->output = NULL;
1483 spin_unlock_irq (&hmidi->lock);
1488 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1490 .open = snd_hdsp_midi_output_open,
1491 .close = snd_hdsp_midi_output_close,
1492 .trigger = snd_hdsp_midi_output_trigger,
1495 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1497 .open = snd_hdsp_midi_input_open,
1498 .close = snd_hdsp_midi_input_close,
1499 .trigger = snd_hdsp_midi_input_trigger,
1502 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1506 hdsp->midi[id].id = id;
1507 hdsp->midi[id].rmidi = NULL;
1508 hdsp->midi[id].input = NULL;
1509 hdsp->midi[id].output = NULL;
1510 hdsp->midi[id].hdsp = hdsp;
1511 hdsp->midi[id].istimer = 0;
1512 hdsp->midi[id].pending = 0;
1513 spin_lock_init (&hdsp->midi[id].lock);
1515 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1516 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1519 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1520 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1522 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1523 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1525 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1526 SNDRV_RAWMIDI_INFO_INPUT |
1527 SNDRV_RAWMIDI_INFO_DUPLEX;
1532 /*-----------------------------------------------------------------------------
1534 ----------------------------------------------------------------------------*/
1536 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1539 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1540 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1541 if (val & HDSP_SPDIFProfessional)
1542 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1544 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1548 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1550 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1551 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1552 if (val & HDSP_SPDIFProfessional)
1553 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1555 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1558 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1560 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1565 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1567 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1569 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1573 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1575 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1579 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1580 spin_lock_irq(&hdsp->lock);
1581 change = val != hdsp->creg_spdif;
1582 hdsp->creg_spdif = val;
1583 spin_unlock_irq(&hdsp->lock);
1587 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1589 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1594 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1596 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1598 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1602 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1604 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1608 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1609 spin_lock_irq(&hdsp->lock);
1610 change = val != hdsp->creg_spdif_stream;
1611 hdsp->creg_spdif_stream = val;
1612 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1613 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1614 spin_unlock_irq(&hdsp->lock);
1618 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1620 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1625 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1627 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1631 #define HDSP_SPDIF_IN(xname, xindex) \
1632 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1635 .info = snd_hdsp_info_spdif_in, \
1636 .get = snd_hdsp_get_spdif_in, \
1637 .put = snd_hdsp_put_spdif_in }
1639 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1641 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1644 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1646 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1647 hdsp->control_register |= hdsp_encode_spdif_in(in);
1648 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1652 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1654 static const char * const texts[4] = {
1655 "Optical", "Coaxial", "Internal", "AES"
1657 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1659 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1663 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1665 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1667 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1671 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1673 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1677 if (!snd_hdsp_use_is_exclusive(hdsp))
1679 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1680 spin_lock_irq(&hdsp->lock);
1681 change = val != hdsp_spdif_in(hdsp);
1683 hdsp_set_spdif_input(hdsp, val);
1684 spin_unlock_irq(&hdsp->lock);
1688 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1689 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1691 .private_value = xindex, \
1692 .info = snd_hdsp_info_toggle_setting, \
1693 .get = snd_hdsp_get_toggle_setting, \
1694 .put = snd_hdsp_put_toggle_setting \
1697 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1699 return (hdsp->control_register & regmask) ? 1 : 0;
1702 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1705 hdsp->control_register |= regmask;
1707 hdsp->control_register &= ~regmask;
1708 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1713 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1715 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1716 struct snd_ctl_elem_value *ucontrol)
1718 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1719 u32 regmask = kcontrol->private_value;
1721 spin_lock_irq(&hdsp->lock);
1722 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1723 spin_unlock_irq(&hdsp->lock);
1727 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1728 struct snd_ctl_elem_value *ucontrol)
1730 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1731 u32 regmask = kcontrol->private_value;
1735 if (!snd_hdsp_use_is_exclusive(hdsp))
1737 val = ucontrol->value.integer.value[0] & 1;
1738 spin_lock_irq(&hdsp->lock);
1739 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1741 hdsp_set_toggle_setting(hdsp, regmask, val);
1742 spin_unlock_irq(&hdsp->lock);
1746 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1747 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1750 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1751 .info = snd_hdsp_info_spdif_sample_rate, \
1752 .get = snd_hdsp_get_spdif_sample_rate \
1755 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1757 static const char * const texts[] = {
1758 "32000", "44100", "48000", "64000", "88200", "96000",
1759 "None", "128000", "176400", "192000"
1761 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1763 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1767 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1769 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1771 switch (hdsp_spdif_sample_rate(hdsp)) {
1773 ucontrol->value.enumerated.item[0] = 0;
1776 ucontrol->value.enumerated.item[0] = 1;
1779 ucontrol->value.enumerated.item[0] = 2;
1782 ucontrol->value.enumerated.item[0] = 3;
1785 ucontrol->value.enumerated.item[0] = 4;
1788 ucontrol->value.enumerated.item[0] = 5;
1791 ucontrol->value.enumerated.item[0] = 7;
1794 ucontrol->value.enumerated.item[0] = 8;
1797 ucontrol->value.enumerated.item[0] = 9;
1800 ucontrol->value.enumerated.item[0] = 6;
1805 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1806 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1809 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1810 .info = snd_hdsp_info_system_sample_rate, \
1811 .get = snd_hdsp_get_system_sample_rate \
1814 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1816 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1821 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1823 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1825 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1829 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1830 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1833 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1834 .info = snd_hdsp_info_autosync_sample_rate, \
1835 .get = snd_hdsp_get_autosync_sample_rate \
1838 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1840 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1841 static const char * const texts[] = {
1842 "32000", "44100", "48000", "64000", "88200", "96000",
1843 "None", "128000", "176400", "192000"
1846 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1850 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1852 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1854 switch (hdsp_external_sample_rate(hdsp)) {
1856 ucontrol->value.enumerated.item[0] = 0;
1859 ucontrol->value.enumerated.item[0] = 1;
1862 ucontrol->value.enumerated.item[0] = 2;
1865 ucontrol->value.enumerated.item[0] = 3;
1868 ucontrol->value.enumerated.item[0] = 4;
1871 ucontrol->value.enumerated.item[0] = 5;
1874 ucontrol->value.enumerated.item[0] = 7;
1877 ucontrol->value.enumerated.item[0] = 8;
1880 ucontrol->value.enumerated.item[0] = 9;
1883 ucontrol->value.enumerated.item[0] = 6;
1888 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1889 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1892 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1893 .info = snd_hdsp_info_system_clock_mode, \
1894 .get = snd_hdsp_get_system_clock_mode \
1897 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1899 if (hdsp->control_register & HDSP_ClockModeMaster)
1901 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1906 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1908 static const char * const texts[] = {"Master", "Slave" };
1910 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1913 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1915 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1917 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1921 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1922 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1925 .info = snd_hdsp_info_clock_source, \
1926 .get = snd_hdsp_get_clock_source, \
1927 .put = snd_hdsp_put_clock_source \
1930 static int hdsp_clock_source(struct hdsp *hdsp)
1932 if (hdsp->control_register & HDSP_ClockModeMaster) {
1933 switch (hdsp->system_sample_rate) {
1960 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1964 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1965 if (hdsp_external_sample_rate(hdsp) != 0) {
1966 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1967 hdsp->control_register &= ~HDSP_ClockModeMaster;
1968 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1973 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1976 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1979 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1982 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1985 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1988 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1991 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1994 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1997 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2003 hdsp->control_register |= HDSP_ClockModeMaster;
2004 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2005 hdsp_set_rate(hdsp, rate, 1);
2009 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2011 static const char * const texts[] = {
2012 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2013 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2014 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2015 "Internal 192.0 KHz"
2017 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2019 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2023 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2025 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2027 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2031 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2033 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2037 if (!snd_hdsp_use_is_exclusive(hdsp))
2039 val = ucontrol->value.enumerated.item[0];
2040 if (val < 0) val = 0;
2041 if (hdsp->io_type == H9632) {
2048 spin_lock_irq(&hdsp->lock);
2049 if (val != hdsp_clock_source(hdsp))
2050 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2053 spin_unlock_irq(&hdsp->lock);
2057 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2059 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2061 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2063 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2067 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2069 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2072 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2074 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2078 #define HDSP_DA_GAIN(xname, xindex) \
2079 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2082 .info = snd_hdsp_info_da_gain, \
2083 .get = snd_hdsp_get_da_gain, \
2084 .put = snd_hdsp_put_da_gain \
2087 static int hdsp_da_gain(struct hdsp *hdsp)
2089 switch (hdsp->control_register & HDSP_DAGainMask) {
2090 case HDSP_DAGainHighGain:
2092 case HDSP_DAGainPlus4dBu:
2094 case HDSP_DAGainMinus10dBV:
2101 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2103 hdsp->control_register &= ~HDSP_DAGainMask;
2106 hdsp->control_register |= HDSP_DAGainHighGain;
2109 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2112 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2118 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2122 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2124 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2126 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2129 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2131 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2133 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2137 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2139 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2143 if (!snd_hdsp_use_is_exclusive(hdsp))
2145 val = ucontrol->value.enumerated.item[0];
2146 if (val < 0) val = 0;
2147 if (val > 2) val = 2;
2148 spin_lock_irq(&hdsp->lock);
2149 if (val != hdsp_da_gain(hdsp))
2150 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2153 spin_unlock_irq(&hdsp->lock);
2157 #define HDSP_AD_GAIN(xname, xindex) \
2158 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2161 .info = snd_hdsp_info_ad_gain, \
2162 .get = snd_hdsp_get_ad_gain, \
2163 .put = snd_hdsp_put_ad_gain \
2166 static int hdsp_ad_gain(struct hdsp *hdsp)
2168 switch (hdsp->control_register & HDSP_ADGainMask) {
2169 case HDSP_ADGainMinus10dBV:
2171 case HDSP_ADGainPlus4dBu:
2173 case HDSP_ADGainLowGain:
2180 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2182 hdsp->control_register &= ~HDSP_ADGainMask;
2185 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2188 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2191 hdsp->control_register |= HDSP_ADGainLowGain;
2197 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2201 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2203 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2205 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2208 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2210 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2212 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2216 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2218 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2222 if (!snd_hdsp_use_is_exclusive(hdsp))
2224 val = ucontrol->value.enumerated.item[0];
2225 if (val < 0) val = 0;
2226 if (val > 2) val = 2;
2227 spin_lock_irq(&hdsp->lock);
2228 if (val != hdsp_ad_gain(hdsp))
2229 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2232 spin_unlock_irq(&hdsp->lock);
2236 #define HDSP_PHONE_GAIN(xname, xindex) \
2237 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2240 .info = snd_hdsp_info_phone_gain, \
2241 .get = snd_hdsp_get_phone_gain, \
2242 .put = snd_hdsp_put_phone_gain \
2245 static int hdsp_phone_gain(struct hdsp *hdsp)
2247 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2248 case HDSP_PhoneGain0dB:
2250 case HDSP_PhoneGainMinus6dB:
2252 case HDSP_PhoneGainMinus12dB:
2259 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2261 hdsp->control_register &= ~HDSP_PhoneGainMask;
2264 hdsp->control_register |= HDSP_PhoneGain0dB;
2267 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2270 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2276 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2280 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2282 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2284 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2287 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2289 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2291 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2295 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2297 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2301 if (!snd_hdsp_use_is_exclusive(hdsp))
2303 val = ucontrol->value.enumerated.item[0];
2304 if (val < 0) val = 0;
2305 if (val > 2) val = 2;
2306 spin_lock_irq(&hdsp->lock);
2307 if (val != hdsp_phone_gain(hdsp))
2308 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2311 spin_unlock_irq(&hdsp->lock);
2315 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2316 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2319 .info = snd_hdsp_info_pref_sync_ref, \
2320 .get = snd_hdsp_get_pref_sync_ref, \
2321 .put = snd_hdsp_put_pref_sync_ref \
2324 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2326 /* Notice that this looks at the requested sync source,
2327 not the one actually in use.
2330 switch (hdsp->control_register & HDSP_SyncRefMask) {
2331 case HDSP_SyncRef_ADAT1:
2332 return HDSP_SYNC_FROM_ADAT1;
2333 case HDSP_SyncRef_ADAT2:
2334 return HDSP_SYNC_FROM_ADAT2;
2335 case HDSP_SyncRef_ADAT3:
2336 return HDSP_SYNC_FROM_ADAT3;
2337 case HDSP_SyncRef_SPDIF:
2338 return HDSP_SYNC_FROM_SPDIF;
2339 case HDSP_SyncRef_WORD:
2340 return HDSP_SYNC_FROM_WORD;
2341 case HDSP_SyncRef_ADAT_SYNC:
2342 return HDSP_SYNC_FROM_ADAT_SYNC;
2344 return HDSP_SYNC_FROM_WORD;
2349 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2351 hdsp->control_register &= ~HDSP_SyncRefMask;
2353 case HDSP_SYNC_FROM_ADAT1:
2354 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2356 case HDSP_SYNC_FROM_ADAT2:
2357 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2359 case HDSP_SYNC_FROM_ADAT3:
2360 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2362 case HDSP_SYNC_FROM_SPDIF:
2363 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2365 case HDSP_SYNC_FROM_WORD:
2366 hdsp->control_register |= HDSP_SyncRef_WORD;
2368 case HDSP_SYNC_FROM_ADAT_SYNC:
2369 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2374 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2378 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2380 static const char * const texts[] = {
2381 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2383 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2386 switch (hdsp->io_type) {
2401 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2404 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2406 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2408 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2412 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2414 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2418 if (!snd_hdsp_use_is_exclusive(hdsp))
2421 switch (hdsp->io_type) {
2436 val = ucontrol->value.enumerated.item[0] % max;
2437 spin_lock_irq(&hdsp->lock);
2438 change = (int)val != hdsp_pref_sync_ref(hdsp);
2439 hdsp_set_pref_sync_ref(hdsp, val);
2440 spin_unlock_irq(&hdsp->lock);
2444 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2445 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2448 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2449 .info = snd_hdsp_info_autosync_ref, \
2450 .get = snd_hdsp_get_autosync_ref, \
2453 static int hdsp_autosync_ref(struct hdsp *hdsp)
2455 /* This looks at the autosync selected sync reference */
2456 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2458 switch (status2 & HDSP_SelSyncRefMask) {
2459 case HDSP_SelSyncRef_WORD:
2460 return HDSP_AUTOSYNC_FROM_WORD;
2461 case HDSP_SelSyncRef_ADAT_SYNC:
2462 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2463 case HDSP_SelSyncRef_SPDIF:
2464 return HDSP_AUTOSYNC_FROM_SPDIF;
2465 case HDSP_SelSyncRefMask:
2466 return HDSP_AUTOSYNC_FROM_NONE;
2467 case HDSP_SelSyncRef_ADAT1:
2468 return HDSP_AUTOSYNC_FROM_ADAT1;
2469 case HDSP_SelSyncRef_ADAT2:
2470 return HDSP_AUTOSYNC_FROM_ADAT2;
2471 case HDSP_SelSyncRef_ADAT3:
2472 return HDSP_AUTOSYNC_FROM_ADAT3;
2474 return HDSP_AUTOSYNC_FROM_WORD;
2479 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2481 static const char * const texts[] = {
2482 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2485 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2488 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2490 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2492 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2496 #define HDSP_PRECISE_POINTER(xname, xindex) \
2497 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2500 .info = snd_hdsp_info_precise_pointer, \
2501 .get = snd_hdsp_get_precise_pointer, \
2502 .put = snd_hdsp_put_precise_pointer \
2505 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2508 hdsp->precise_ptr = 1;
2510 hdsp->precise_ptr = 0;
2514 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2516 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2518 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2520 spin_lock_irq(&hdsp->lock);
2521 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2522 spin_unlock_irq(&hdsp->lock);
2526 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2528 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2532 if (!snd_hdsp_use_is_exclusive(hdsp))
2534 val = ucontrol->value.integer.value[0] & 1;
2535 spin_lock_irq(&hdsp->lock);
2536 change = (int)val != hdsp->precise_ptr;
2537 hdsp_set_precise_pointer(hdsp, val);
2538 spin_unlock_irq(&hdsp->lock);
2542 #define HDSP_USE_MIDI_WORK(xname, xindex) \
2543 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2546 .info = snd_hdsp_info_use_midi_work, \
2547 .get = snd_hdsp_get_use_midi_work, \
2548 .put = snd_hdsp_put_use_midi_work \
2551 static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work)
2554 hdsp->use_midi_work = 1;
2556 hdsp->use_midi_work = 0;
2560 #define snd_hdsp_info_use_midi_work snd_ctl_boolean_mono_info
2562 static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2564 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2566 spin_lock_irq(&hdsp->lock);
2567 ucontrol->value.integer.value[0] = hdsp->use_midi_work;
2568 spin_unlock_irq(&hdsp->lock);
2572 static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2574 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2578 if (!snd_hdsp_use_is_exclusive(hdsp))
2580 val = ucontrol->value.integer.value[0] & 1;
2581 spin_lock_irq(&hdsp->lock);
2582 change = (int)val != hdsp->use_midi_work;
2583 hdsp_set_use_midi_work(hdsp, val);
2584 spin_unlock_irq(&hdsp->lock);
2588 #define HDSP_MIXER(xname, xindex) \
2589 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2593 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2594 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2595 .info = snd_hdsp_info_mixer, \
2596 .get = snd_hdsp_get_mixer, \
2597 .put = snd_hdsp_put_mixer \
2600 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2602 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2604 uinfo->value.integer.min = 0;
2605 uinfo->value.integer.max = 65536;
2606 uinfo->value.integer.step = 1;
2610 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2612 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2617 source = ucontrol->value.integer.value[0];
2618 destination = ucontrol->value.integer.value[1];
2620 if (source >= hdsp->max_channels)
2621 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2623 addr = hdsp_input_to_output_key(hdsp,source, destination);
2625 spin_lock_irq(&hdsp->lock);
2626 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2627 spin_unlock_irq(&hdsp->lock);
2631 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2633 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2640 if (!snd_hdsp_use_is_exclusive(hdsp))
2643 source = ucontrol->value.integer.value[0];
2644 destination = ucontrol->value.integer.value[1];
2646 if (source >= hdsp->max_channels)
2647 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2649 addr = hdsp_input_to_output_key(hdsp,source, destination);
2651 gain = ucontrol->value.integer.value[2];
2653 spin_lock_irq(&hdsp->lock);
2654 change = gain != hdsp_read_gain(hdsp, addr);
2656 hdsp_write_gain(hdsp, addr, gain);
2657 spin_unlock_irq(&hdsp->lock);
2661 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2662 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2665 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2666 .info = snd_hdsp_info_sync_check, \
2667 .get = snd_hdsp_get_wc_sync_check \
2670 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2672 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2674 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2677 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2679 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2680 if (status2 & HDSP_wc_lock) {
2681 if (status2 & HDSP_wc_sync)
2690 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2692 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2694 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2698 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2699 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2702 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2703 .info = snd_hdsp_info_sync_check, \
2704 .get = snd_hdsp_get_spdif_sync_check \
2707 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2709 int status = hdsp_read(hdsp, HDSP_statusRegister);
2710 if (status & HDSP_SPDIFErrorFlag)
2713 if (status & HDSP_SPDIFSync)
2721 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2723 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2725 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2729 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2730 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2733 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2734 .info = snd_hdsp_info_sync_check, \
2735 .get = snd_hdsp_get_adatsync_sync_check \
2738 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2740 int status = hdsp_read(hdsp, HDSP_statusRegister);
2741 if (status & HDSP_TimecodeLock) {
2742 if (status & HDSP_TimecodeSync)
2750 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2752 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2754 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2758 #define HDSP_ADAT_SYNC_CHECK \
2759 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2760 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2761 .info = snd_hdsp_info_sync_check, \
2762 .get = snd_hdsp_get_adat_sync_check \
2765 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2767 int status = hdsp_read(hdsp, HDSP_statusRegister);
2769 if (status & (HDSP_Lock0>>idx)) {
2770 if (status & (HDSP_Sync0>>idx))
2778 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2781 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2783 offset = ucontrol->id.index - 1;
2784 if (snd_BUG_ON(offset < 0))
2787 switch (hdsp->io_type) {
2802 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2806 #define HDSP_DDS_OFFSET(xname, xindex) \
2807 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2810 .info = snd_hdsp_info_dds_offset, \
2811 .get = snd_hdsp_get_dds_offset, \
2812 .put = snd_hdsp_put_dds_offset \
2815 static int hdsp_dds_offset(struct hdsp *hdsp)
2818 unsigned int dds_value = hdsp->dds_value;
2819 int system_sample_rate = hdsp->system_sample_rate;
2826 * dds_value = n / rate
2827 * rate = n / dds_value
2829 n = div_u64(n, dds_value);
2830 if (system_sample_rate >= 112000)
2832 else if (system_sample_rate >= 56000)
2834 return ((int)n) - system_sample_rate;
2837 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2839 int rate = hdsp->system_sample_rate + offset_hz;
2840 hdsp_set_dds_value(hdsp, rate);
2844 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2846 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2848 uinfo->value.integer.min = -5000;
2849 uinfo->value.integer.max = 5000;
2853 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2855 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2857 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2861 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2863 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2867 if (!snd_hdsp_use_is_exclusive(hdsp))
2869 val = ucontrol->value.integer.value[0];
2870 spin_lock_irq(&hdsp->lock);
2871 if (val != hdsp_dds_offset(hdsp))
2872 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2875 spin_unlock_irq(&hdsp->lock);
2879 static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2880 HDSP_DA_GAIN("DA Gain", 0),
2881 HDSP_AD_GAIN("AD Gain", 0),
2882 HDSP_PHONE_GAIN("Phones Gain", 0),
2883 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2884 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2887 static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2889 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2890 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2891 .info = snd_hdsp_control_spdif_info,
2892 .get = snd_hdsp_control_spdif_get,
2893 .put = snd_hdsp_control_spdif_put,
2896 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2897 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2898 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2899 .info = snd_hdsp_control_spdif_stream_info,
2900 .get = snd_hdsp_control_spdif_stream_get,
2901 .put = snd_hdsp_control_spdif_stream_put,
2904 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2905 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2906 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2907 .info = snd_hdsp_control_spdif_mask_info,
2908 .get = snd_hdsp_control_spdif_mask_get,
2909 .private_value = IEC958_AES0_NONAUDIO |
2910 IEC958_AES0_PROFESSIONAL |
2911 IEC958_AES0_CON_EMPHASIS,
2914 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2915 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2916 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2917 .info = snd_hdsp_control_spdif_mask_info,
2918 .get = snd_hdsp_control_spdif_mask_get,
2919 .private_value = IEC958_AES0_NONAUDIO |
2920 IEC958_AES0_PROFESSIONAL |
2921 IEC958_AES0_PRO_EMPHASIS,
2923 HDSP_MIXER("Mixer", 0),
2924 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2925 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2926 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2927 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2928 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2929 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2930 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2932 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2933 .name = "Sample Clock Source Locking",
2934 .info = snd_hdsp_info_clock_source_lock,
2935 .get = snd_hdsp_get_clock_source_lock,
2936 .put = snd_hdsp_put_clock_source_lock,
2938 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2939 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2940 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2941 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2942 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2943 /* 'External Rate' complies with the alsa control naming scheme */
2944 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2945 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2946 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2947 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2948 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2949 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2950 HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),
2954 static int hdsp_rpm_input12(struct hdsp *hdsp)
2956 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2957 case HDSP_RPM_Inp12_Phon_6dB:
2959 case HDSP_RPM_Inp12_Phon_n6dB:
2961 case HDSP_RPM_Inp12_Line_0dB:
2963 case HDSP_RPM_Inp12_Line_n6dB:
2970 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2972 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2974 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2979 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2981 hdsp->control_register &= ~HDSP_RPM_Inp12;
2984 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2989 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2992 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2995 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3001 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3006 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3008 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3012 if (!snd_hdsp_use_is_exclusive(hdsp))
3014 val = ucontrol->value.enumerated.item[0];
3019 spin_lock_irq(&hdsp->lock);
3020 if (val != hdsp_rpm_input12(hdsp))
3021 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3024 spin_unlock_irq(&hdsp->lock);
3029 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3031 static const char * const texts[] = {
3032 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3035 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3039 static int hdsp_rpm_input34(struct hdsp *hdsp)
3041 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3042 case HDSP_RPM_Inp34_Phon_6dB:
3044 case HDSP_RPM_Inp34_Phon_n6dB:
3046 case HDSP_RPM_Inp34_Line_0dB:
3048 case HDSP_RPM_Inp34_Line_n6dB:
3055 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3057 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3059 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3064 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3066 hdsp->control_register &= ~HDSP_RPM_Inp34;
3069 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3074 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3077 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3080 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3086 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3091 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3093 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3097 if (!snd_hdsp_use_is_exclusive(hdsp))
3099 val = ucontrol->value.enumerated.item[0];
3104 spin_lock_irq(&hdsp->lock);
3105 if (val != hdsp_rpm_input34(hdsp))
3106 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3109 spin_unlock_irq(&hdsp->lock);
3114 /* RPM Bypass switch */
3115 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3117 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3121 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3123 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3125 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3130 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3133 hdsp->control_register |= HDSP_RPM_Bypass;
3135 hdsp->control_register &= ~HDSP_RPM_Bypass;
3136 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3141 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3143 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3147 if (!snd_hdsp_use_is_exclusive(hdsp))
3149 val = ucontrol->value.integer.value[0] & 1;
3150 spin_lock_irq(&hdsp->lock);
3151 change = (int)val != hdsp_rpm_bypass(hdsp);
3152 hdsp_set_rpm_bypass(hdsp, val);
3153 spin_unlock_irq(&hdsp->lock);
3158 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3160 static const char * const texts[] = {"On", "Off"};
3162 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3166 /* RPM Disconnect switch */
3167 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3169 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3173 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3175 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3177 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3182 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3185 hdsp->control_register |= HDSP_RPM_Disconnect;
3187 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3188 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3193 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3195 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3199 if (!snd_hdsp_use_is_exclusive(hdsp))
3201 val = ucontrol->value.integer.value[0] & 1;
3202 spin_lock_irq(&hdsp->lock);
3203 change = (int)val != hdsp_rpm_disconnect(hdsp);
3204 hdsp_set_rpm_disconnect(hdsp, val);
3205 spin_unlock_irq(&hdsp->lock);
3209 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3211 static const char * const texts[] = {"On", "Off"};
3213 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3216 static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3218 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3219 .name = "RPM Bypass",
3220 .get = snd_hdsp_get_rpm_bypass,
3221 .put = snd_hdsp_put_rpm_bypass,
3222 .info = snd_hdsp_info_rpm_bypass
3225 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3226 .name = "RPM Disconnect",
3227 .get = snd_hdsp_get_rpm_disconnect,
3228 .put = snd_hdsp_put_rpm_disconnect,
3229 .info = snd_hdsp_info_rpm_disconnect
3232 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3233 .name = "Input 1/2",
3234 .get = snd_hdsp_get_rpm_input12,
3235 .put = snd_hdsp_put_rpm_input12,
3236 .info = snd_hdsp_info_rpm_input
3239 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3240 .name = "Input 3/4",
3241 .get = snd_hdsp_get_rpm_input34,
3242 .put = snd_hdsp_put_rpm_input34,
3243 .info = snd_hdsp_info_rpm_input
3245 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3246 HDSP_MIXER("Mixer", 0)
3249 static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3250 HDSP_TOGGLE_SETTING("Analog Extension Board",
3251 HDSP_AnalogExtensionBoard);
3252 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3255 static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel)
3257 return hdsp->io_loopback & (1 << channel);
3260 static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable)
3262 if (hdsp_loopback_get(hdsp, channel) == enable)
3265 hdsp->io_loopback ^= (1 << channel);
3267 hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable);
3272 static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol,
3273 struct snd_ctl_elem_value *const ucontrol)
3275 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3276 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3278 if (channel >= hdsp->max_channels)
3281 ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel);
3286 static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol,
3287 struct snd_ctl_elem_value *const ucontrol)
3289 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3290 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3291 const bool enable = ucontrol->value.integer.value[0] & 1;
3293 if (channel >= hdsp->max_channels)
3296 return hdsp_loopback_set(hdsp, channel, enable);
3299 static struct snd_kcontrol_new snd_hdsp_loopback_control = {
3300 .iface = SNDRV_CTL_ELEM_IFACE_HWDEP,
3301 .name = "Output Loopback",
3302 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
3303 .info = snd_ctl_boolean_mono_info,
3304 .get = snd_hdsp_loopback_get,
3305 .put = snd_hdsp_loopback_put
3308 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3312 struct snd_kcontrol *kctl;
3314 if (hdsp->io_type == RPM) {
3315 /* RPM Bypass, Disconnect and Input switches */
3316 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3317 err = snd_ctl_add(card, snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3324 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3325 kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp);
3326 err = snd_ctl_add(card, kctl);
3329 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3330 hdsp->spdif_ctl = kctl;
3333 /* ADAT SyncCheck status */
3334 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3335 snd_hdsp_adat_sync_check.index = 1;
3336 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3337 err = snd_ctl_add(card, kctl);
3340 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3341 for (idx = 1; idx < 3; ++idx) {
3342 snd_hdsp_adat_sync_check.index = idx+1;
3343 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);
3344 err = snd_ctl_add(card, kctl);
3350 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3351 if (hdsp->io_type == H9632) {
3352 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3353 kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp);
3354 err = snd_ctl_add(card, kctl);
3360 /* Output loopback controls for H9632 cards */
3361 if (hdsp->io_type == H9632) {
3362 snd_hdsp_loopback_control.count = hdsp->max_channels;
3363 kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp);
3366 err = snd_ctl_add(card, kctl);
3371 /* AEB control for H96xx card */
3372 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3373 kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp);
3374 err = snd_ctl_add(card, kctl);
3382 /*------------------------------------------------------------
3384 ------------------------------------------------------------*/
3387 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3389 struct hdsp *hdsp = entry->private_data;
3390 unsigned int status;
3391 unsigned int status2;
3392 char *pref_sync_ref;
3394 char *system_clock_mode;
3398 status = hdsp_read(hdsp, HDSP_statusRegister);
3399 status2 = hdsp_read(hdsp, HDSP_status2Register);
3401 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3402 hdsp->card->number + 1);
3403 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3404 hdsp->capture_buffer, hdsp->playback_buffer);
3405 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3406 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3407 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3408 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3409 hdsp->control2_register);
3410 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3411 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3413 if (hdsp_check_for_iobox(hdsp)) {
3414 snd_iprintf(buffer, "No I/O box connected.\n"
3415 "Please connect one and upload firmware.\n");
3419 if (hdsp_check_for_firmware(hdsp, 0)) {
3420 if (hdsp->state & HDSP_FirmwareCached) {
3421 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3422 snd_iprintf(buffer, "Firmware loading from "
3424 "please upload manually.\n");
3430 err = hdsp_request_fw_loader(hdsp);
3433 "No firmware loaded nor cached, "
3434 "please upload firmware.\n");
3440 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3441 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3442 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3443 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3444 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3445 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off");
3447 snd_iprintf(buffer, "\n");
3449 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3451 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3452 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3453 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3454 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3456 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3458 snd_iprintf(buffer, "\n");
3460 switch (hdsp_clock_source(hdsp)) {
3461 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3462 clock_source = "AutoSync";
3464 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3465 clock_source = "Internal 32 kHz";
3467 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3468 clock_source = "Internal 44.1 kHz";
3470 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3471 clock_source = "Internal 48 kHz";
3473 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3474 clock_source = "Internal 64 kHz";
3476 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3477 clock_source = "Internal 88.2 kHz";
3479 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3480 clock_source = "Internal 96 kHz";
3482 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3483 clock_source = "Internal 128 kHz";
3485 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3486 clock_source = "Internal 176.4 kHz";
3488 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3489 clock_source = "Internal 192 kHz";
3492 clock_source = "Error";
3494 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3496 if (hdsp_system_clock_mode(hdsp))
3497 system_clock_mode = "Slave";
3499 system_clock_mode = "Master";
3501 switch (hdsp_pref_sync_ref (hdsp)) {
3502 case HDSP_SYNC_FROM_WORD:
3503 pref_sync_ref = "Word Clock";
3505 case HDSP_SYNC_FROM_ADAT_SYNC:
3506 pref_sync_ref = "ADAT Sync";
3508 case HDSP_SYNC_FROM_SPDIF:
3509 pref_sync_ref = "SPDIF";
3511 case HDSP_SYNC_FROM_ADAT1:
3512 pref_sync_ref = "ADAT1";
3514 case HDSP_SYNC_FROM_ADAT2:
3515 pref_sync_ref = "ADAT2";
3517 case HDSP_SYNC_FROM_ADAT3:
3518 pref_sync_ref = "ADAT3";
3521 pref_sync_ref = "Word Clock";
3524 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3526 switch (hdsp_autosync_ref (hdsp)) {
3527 case HDSP_AUTOSYNC_FROM_WORD:
3528 autosync_ref = "Word Clock";
3530 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3531 autosync_ref = "ADAT Sync";
3533 case HDSP_AUTOSYNC_FROM_SPDIF:
3534 autosync_ref = "SPDIF";
3536 case HDSP_AUTOSYNC_FROM_NONE:
3537 autosync_ref = "None";
3539 case HDSP_AUTOSYNC_FROM_ADAT1:
3540 autosync_ref = "ADAT1";
3542 case HDSP_AUTOSYNC_FROM_ADAT2:
3543 autosync_ref = "ADAT2";
3545 case HDSP_AUTOSYNC_FROM_ADAT3:
3546 autosync_ref = "ADAT3";
3549 autosync_ref = "---";
3552 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3554 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3556 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3558 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3559 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3561 snd_iprintf(buffer, "\n");
3563 if (hdsp->io_type != RPM) {
3564 switch (hdsp_spdif_in(hdsp)) {
3565 case HDSP_SPDIFIN_OPTICAL:
3566 snd_iprintf(buffer, "IEC958 input: Optical\n");
3568 case HDSP_SPDIFIN_COAXIAL:
3569 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3571 case HDSP_SPDIFIN_INTERNAL:
3572 snd_iprintf(buffer, "IEC958 input: Internal\n");
3574 case HDSP_SPDIFIN_AES:
3575 snd_iprintf(buffer, "IEC958 input: AES\n");
3578 snd_iprintf(buffer, "IEC958 input: ???\n");
3583 if (RPM == hdsp->io_type) {
3584 if (hdsp->control_register & HDSP_RPM_Bypass)
3585 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3587 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3588 if (hdsp->control_register & HDSP_RPM_Disconnect)
3589 snd_iprintf(buffer, "RPM disconnected\n");
3591 snd_iprintf(buffer, "RPM connected\n");
3593 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3594 case HDSP_RPM_Inp12_Phon_6dB:
3595 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3597 case HDSP_RPM_Inp12_Phon_0dB:
3598 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3600 case HDSP_RPM_Inp12_Phon_n6dB:
3601 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3603 case HDSP_RPM_Inp12_Line_0dB:
3604 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3606 case HDSP_RPM_Inp12_Line_n6dB:
3607 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3610 snd_iprintf(buffer, "Input 1/2: ???\n");
3613 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3614 case HDSP_RPM_Inp34_Phon_6dB:
3615 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3617 case HDSP_RPM_Inp34_Phon_0dB:
3618 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3620 case HDSP_RPM_Inp34_Phon_n6dB:
3621 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3623 case HDSP_RPM_Inp34_Line_0dB:
3624 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3626 case HDSP_RPM_Inp34_Line_n6dB:
3627 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3630 snd_iprintf(buffer, "Input 3/4: ???\n");
3634 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3635 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3637 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3639 if (hdsp->control_register & HDSP_SPDIFProfessional)
3640 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3642 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3644 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3645 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3647 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3649 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3650 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3652 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3653 x = hdsp_spdif_sample_rate(hdsp);
3655 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3657 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3659 snd_iprintf(buffer, "\n");
3662 x = status & HDSP_Sync0;
3663 if (status & HDSP_Lock0)
3664 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3666 snd_iprintf(buffer, "ADAT1: No Lock\n");
3668 switch (hdsp->io_type) {
3671 x = status & HDSP_Sync1;
3672 if (status & HDSP_Lock1)
3673 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3675 snd_iprintf(buffer, "ADAT2: No Lock\n");
3676 x = status & HDSP_Sync2;
3677 if (status & HDSP_Lock2)
3678 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3680 snd_iprintf(buffer, "ADAT3: No Lock\n");
3687 x = status & HDSP_SPDIFSync;
3688 if (status & HDSP_SPDIFErrorFlag)
3689 snd_iprintf (buffer, "SPDIF: No Lock\n");
3691 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3693 x = status2 & HDSP_wc_sync;
3694 if (status2 & HDSP_wc_lock)
3695 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3697 snd_iprintf (buffer, "Word Clock: No Lock\n");
3699 x = status & HDSP_TimecodeSync;
3700 if (status & HDSP_TimecodeLock)
3701 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3703 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3705 snd_iprintf(buffer, "\n");
3707 /* Informations about H9632 specific controls */
3708 if (hdsp->io_type == H9632) {
3711 switch (hdsp_ad_gain(hdsp)) {
3722 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3724 switch (hdsp_da_gain(hdsp)) {
3735 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3737 switch (hdsp_phone_gain(hdsp)) {
3748 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3750 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3751 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3754 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3755 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3757 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3758 snd_iprintf(buffer, "\n");
3763 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3765 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3768 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3770 struct snd_dma_buffer *capture_dma, *playback_dma;
3772 capture_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3773 playback_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);
3774 if (!capture_dma || !playback_dma) {
3775 dev_err(hdsp->card->dev,
3776 "%s: no buffers available\n", hdsp->card_name);
3780 /* copy to the own data for alignment */
3781 hdsp->capture_dma_buf = *capture_dma;
3782 hdsp->playback_dma_buf = *playback_dma;
3784 /* Align to bus-space 64K boundary */
3785 hdsp->capture_dma_buf.addr = ALIGN(capture_dma->addr, 0x10000ul);
3786 hdsp->playback_dma_buf.addr = ALIGN(playback_dma->addr, 0x10000ul);
3788 /* Tell the card where it is */
3789 hdsp_write(hdsp, HDSP_inputBufferAddress, hdsp->capture_dma_buf.addr);
3790 hdsp_write(hdsp, HDSP_outputBufferAddress, hdsp->playback_dma_buf.addr);
3792 hdsp->capture_dma_buf.area += hdsp->capture_dma_buf.addr - capture_dma->addr;
3793 hdsp->playback_dma_buf.area += hdsp->playback_dma_buf.addr - playback_dma->addr;
3794 hdsp->capture_buffer = hdsp->capture_dma_buf.area;
3795 hdsp->playback_buffer = hdsp->playback_dma_buf.area;
3800 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3804 /* ASSUMPTION: hdsp->lock is either held, or
3805 there is no need to hold it (e.g. during module
3811 SPDIF Input via Coax
3813 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3814 which implies 2 4096 sample, 32Kbyte periods).
3818 hdsp->control_register = HDSP_ClockModeMaster |
3819 HDSP_SPDIFInputCoaxial |
3820 hdsp_encode_latency(7) |
3824 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3826 #ifdef SNDRV_BIG_ENDIAN
3827 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3829 hdsp->control2_register = 0;
3831 if (hdsp->io_type == H9652)
3832 snd_hdsp_9652_enable_mixer (hdsp);
3834 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3836 hdsp_reset_hw_pointer(hdsp);
3837 hdsp_compute_period_size(hdsp);
3839 /* silence everything */
3841 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3842 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3844 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3845 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3849 /* H9632 specific defaults */
3850 if (hdsp->io_type == H9632) {
3851 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3852 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3855 /* set a default rate so that the channel map is set up.
3858 hdsp_set_rate(hdsp, 48000, 1);
3863 static void hdsp_midi_work(struct work_struct *work)
3865 struct hdsp *hdsp = container_of(work, struct hdsp, midi_work);
3867 if (hdsp->midi[0].pending)
3868 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3869 if (hdsp->midi[1].pending)
3870 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3873 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3875 struct hdsp *hdsp = (struct hdsp *) dev_id;
3876 unsigned int status;
3880 unsigned int midi0status;
3881 unsigned int midi1status;
3884 status = hdsp_read(hdsp, HDSP_statusRegister);
3886 audio = status & HDSP_audioIRQPending;
3887 midi0 = status & HDSP_midi0IRQPending;
3888 midi1 = status & HDSP_midi1IRQPending;
3890 if (!audio && !midi0 && !midi1)
3893 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3895 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3896 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3898 if (!(hdsp->state & HDSP_InitializationComplete))
3902 if (hdsp->capture_substream)
3903 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3905 if (hdsp->playback_substream)
3906 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3909 if (midi0 && midi0status) {
3910 if (hdsp->use_midi_work) {
3911 /* we disable interrupts for this input until processing is done */
3912 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3913 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3914 hdsp->midi[0].pending = 1;
3917 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3920 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3921 if (hdsp->use_midi_work) {
3922 /* we disable interrupts for this input until processing is done */
3923 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3924 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3925 hdsp->midi[1].pending = 1;
3928 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3931 if (hdsp->use_midi_work && schedule)
3932 queue_work(system_highpri_wq, &hdsp->midi_work);
3936 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3938 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3939 return hdsp_hw_pointer(hdsp);
3942 static signed char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3949 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3952 mapped_channel = hdsp->channel_map[channel];
3953 if (mapped_channel < 0)
3956 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3957 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3959 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3962 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3963 int channel, unsigned long pos,
3964 void __user *src, unsigned long count)
3966 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3967 signed char *channel_buf;
3969 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3972 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3973 if (snd_BUG_ON(!channel_buf))
3975 if (copy_from_user(channel_buf + pos, src, count))
3980 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3981 int channel, unsigned long pos,
3982 void *src, unsigned long count)
3984 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3985 signed char *channel_buf;
3987 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3988 if (snd_BUG_ON(!channel_buf))
3990 memcpy(channel_buf + pos, src, count);
3994 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3995 int channel, unsigned long pos,
3996 void __user *dst, unsigned long count)
3998 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3999 signed char *channel_buf;
4001 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
4004 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4005 if (snd_BUG_ON(!channel_buf))
4007 if (copy_to_user(dst, channel_buf + pos, count))
4012 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
4013 int channel, unsigned long pos,
4014 void *dst, unsigned long count)
4016 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4017 signed char *channel_buf;
4019 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
4020 if (snd_BUG_ON(!channel_buf))
4022 memcpy(dst, channel_buf + pos, count);
4026 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
4027 int channel, unsigned long pos,
4028 unsigned long count)
4030 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4031 signed char *channel_buf;
4033 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4034 if (snd_BUG_ON(!channel_buf))
4036 memset(channel_buf + pos, 0, count);
4040 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4042 struct snd_pcm_runtime *runtime = substream->runtime;
4043 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4044 struct snd_pcm_substream *other;
4045 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4046 other = hdsp->capture_substream;
4048 other = hdsp->playback_substream;
4050 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4052 runtime->status->hw_ptr = 0;
4054 struct snd_pcm_substream *s;
4055 struct snd_pcm_runtime *oruntime = other->runtime;
4056 snd_pcm_group_for_each_entry(s, substream) {
4058 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4066 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4067 struct snd_pcm_hw_params *params)
4069 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4074 if (hdsp_check_for_iobox (hdsp))
4077 if (hdsp_check_for_firmware(hdsp, 1))
4080 spin_lock_irq(&hdsp->lock);
4082 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4083 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4084 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4085 this_pid = hdsp->playback_pid;
4086 other_pid = hdsp->capture_pid;
4088 this_pid = hdsp->capture_pid;
4089 other_pid = hdsp->playback_pid;
4092 if ((other_pid > 0) && (this_pid != other_pid)) {
4094 /* The other stream is open, and not by the same
4095 task as this one. Make sure that the parameters
4096 that matter are the same.
4099 if (params_rate(params) != hdsp->system_sample_rate) {
4100 spin_unlock_irq(&hdsp->lock);
4101 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4105 if (params_period_size(params) != hdsp->period_bytes / 4) {
4106 spin_unlock_irq(&hdsp->lock);
4107 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4113 spin_unlock_irq(&hdsp->lock);
4117 spin_unlock_irq(&hdsp->lock);
4120 /* how to make sure that the rate matches an externally-set one ?
4123 spin_lock_irq(&hdsp->lock);
4124 if (! hdsp->clock_source_locked) {
4125 err = hdsp_set_rate(hdsp, params_rate(params), 0);
4127 spin_unlock_irq(&hdsp->lock);
4128 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4132 spin_unlock_irq(&hdsp->lock);
4134 err = hdsp_set_interrupt_interval(hdsp, params_period_size(params));
4136 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4143 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4144 struct snd_pcm_channel_info *info)
4146 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4147 unsigned int channel = info->channel;
4149 if (snd_BUG_ON(channel >= hdsp->max_channels))
4151 channel = array_index_nospec(channel, hdsp->max_channels);
4153 if (hdsp->channel_map[channel] < 0)
4156 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4162 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4163 unsigned int cmd, void *arg)
4166 case SNDRV_PCM_IOCTL1_RESET:
4167 return snd_hdsp_reset(substream);
4168 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4169 return snd_hdsp_channel_info(substream, arg);
4174 return snd_pcm_lib_ioctl(substream, cmd, arg);
4177 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4179 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4180 struct snd_pcm_substream *other;
4183 if (hdsp_check_for_iobox (hdsp))
4186 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4189 spin_lock(&hdsp->lock);
4190 running = hdsp->running;
4192 case SNDRV_PCM_TRIGGER_START:
4193 running |= 1 << substream->stream;
4195 case SNDRV_PCM_TRIGGER_STOP:
4196 running &= ~(1 << substream->stream);
4200 spin_unlock(&hdsp->lock);
4203 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4204 other = hdsp->capture_substream;
4206 other = hdsp->playback_substream;
4209 struct snd_pcm_substream *s;
4210 snd_pcm_group_for_each_entry(s, substream) {
4212 snd_pcm_trigger_done(s, substream);
4213 if (cmd == SNDRV_PCM_TRIGGER_START)
4214 running |= 1 << s->stream;
4216 running &= ~(1 << s->stream);
4220 if (cmd == SNDRV_PCM_TRIGGER_START) {
4221 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4222 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4223 hdsp_silence_playback(hdsp);
4226 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4227 hdsp_silence_playback(hdsp);
4230 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4231 hdsp_silence_playback(hdsp);
4234 snd_pcm_trigger_done(substream, substream);
4235 if (!hdsp->running && running)
4236 hdsp_start_audio(hdsp);
4237 else if (hdsp->running && !running)
4238 hdsp_stop_audio(hdsp);
4239 hdsp->running = running;
4240 spin_unlock(&hdsp->lock);
4245 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4247 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4250 if (hdsp_check_for_iobox (hdsp))
4253 if (hdsp_check_for_firmware(hdsp, 1))
4256 spin_lock_irq(&hdsp->lock);
4258 hdsp_reset_hw_pointer(hdsp);
4259 spin_unlock_irq(&hdsp->lock);
4263 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4265 .info = (SNDRV_PCM_INFO_MMAP |
4266 SNDRV_PCM_INFO_MMAP_VALID |
4267 SNDRV_PCM_INFO_NONINTERLEAVED |
4268 SNDRV_PCM_INFO_SYNC_START |
4269 SNDRV_PCM_INFO_DOUBLE),
4270 #ifdef SNDRV_BIG_ENDIAN
4271 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4273 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4275 .rates = (SNDRV_PCM_RATE_32000 |
4276 SNDRV_PCM_RATE_44100 |
4277 SNDRV_PCM_RATE_48000 |
4278 SNDRV_PCM_RATE_64000 |
4279 SNDRV_PCM_RATE_88200 |
4280 SNDRV_PCM_RATE_96000),
4284 .channels_max = HDSP_MAX_CHANNELS,
4285 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4286 .period_bytes_min = (64 * 4) * 10,
4287 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4293 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4295 .info = (SNDRV_PCM_INFO_MMAP |
4296 SNDRV_PCM_INFO_MMAP_VALID |
4297 SNDRV_PCM_INFO_NONINTERLEAVED |
4298 SNDRV_PCM_INFO_SYNC_START),
4299 #ifdef SNDRV_BIG_ENDIAN
4300 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4302 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4304 .rates = (SNDRV_PCM_RATE_32000 |
4305 SNDRV_PCM_RATE_44100 |
4306 SNDRV_PCM_RATE_48000 |
4307 SNDRV_PCM_RATE_64000 |
4308 SNDRV_PCM_RATE_88200 |
4309 SNDRV_PCM_RATE_96000),
4313 .channels_max = HDSP_MAX_CHANNELS,
4314 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4315 .period_bytes_min = (64 * 4) * 10,
4316 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4322 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4324 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4325 .count = ARRAY_SIZE(hdsp_period_sizes),
4326 .list = hdsp_period_sizes,
4330 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4332 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4333 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4334 .list = hdsp_9632_sample_rates,
4338 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4339 struct snd_pcm_hw_rule *rule)
4341 struct hdsp *hdsp = rule->private;
4342 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4343 if (hdsp->io_type == H9632) {
4344 unsigned int list[3];
4345 list[0] = hdsp->qs_in_channels;
4346 list[1] = hdsp->ds_in_channels;
4347 list[2] = hdsp->ss_in_channels;
4348 return snd_interval_list(c, 3, list, 0);
4350 unsigned int list[2];
4351 list[0] = hdsp->ds_in_channels;
4352 list[1] = hdsp->ss_in_channels;
4353 return snd_interval_list(c, 2, list, 0);
4357 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4358 struct snd_pcm_hw_rule *rule)
4360 unsigned int list[3];
4361 struct hdsp *hdsp = rule->private;
4362 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4363 if (hdsp->io_type == H9632) {
4364 list[0] = hdsp->qs_out_channels;
4365 list[1] = hdsp->ds_out_channels;
4366 list[2] = hdsp->ss_out_channels;
4367 return snd_interval_list(c, 3, list, 0);
4369 list[0] = hdsp->ds_out_channels;
4370 list[1] = hdsp->ss_out_channels;
4372 return snd_interval_list(c, 2, list, 0);
4375 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4376 struct snd_pcm_hw_rule *rule)
4378 struct hdsp *hdsp = rule->private;
4379 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4380 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4381 if (r->min > 96000 && hdsp->io_type == H9632) {
4382 struct snd_interval t = {
4383 .min = hdsp->qs_in_channels,
4384 .max = hdsp->qs_in_channels,
4387 return snd_interval_refine(c, &t);
4388 } else if (r->min > 48000 && r->max <= 96000) {
4389 struct snd_interval t = {
4390 .min = hdsp->ds_in_channels,
4391 .max = hdsp->ds_in_channels,
4394 return snd_interval_refine(c, &t);
4395 } else if (r->max < 64000) {
4396 struct snd_interval t = {
4397 .min = hdsp->ss_in_channels,
4398 .max = hdsp->ss_in_channels,
4401 return snd_interval_refine(c, &t);
4406 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4407 struct snd_pcm_hw_rule *rule)
4409 struct hdsp *hdsp = rule->private;
4410 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4411 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4412 if (r->min > 96000 && hdsp->io_type == H9632) {
4413 struct snd_interval t = {
4414 .min = hdsp->qs_out_channels,
4415 .max = hdsp->qs_out_channels,
4418 return snd_interval_refine(c, &t);
4419 } else if (r->min > 48000 && r->max <= 96000) {
4420 struct snd_interval t = {
4421 .min = hdsp->ds_out_channels,
4422 .max = hdsp->ds_out_channels,
4425 return snd_interval_refine(c, &t);
4426 } else if (r->max < 64000) {
4427 struct snd_interval t = {
4428 .min = hdsp->ss_out_channels,
4429 .max = hdsp->ss_out_channels,
4432 return snd_interval_refine(c, &t);
4437 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4438 struct snd_pcm_hw_rule *rule)
4440 struct hdsp *hdsp = rule->private;
4441 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4442 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4443 if (c->min >= hdsp->ss_out_channels) {
4444 struct snd_interval t = {
4449 return snd_interval_refine(r, &t);
4450 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4451 struct snd_interval t = {
4456 return snd_interval_refine(r, &t);
4457 } else if (c->max <= hdsp->ds_out_channels) {
4458 struct snd_interval t = {
4463 return snd_interval_refine(r, &t);
4468 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4469 struct snd_pcm_hw_rule *rule)
4471 struct hdsp *hdsp = rule->private;
4472 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4473 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4474 if (c->min >= hdsp->ss_in_channels) {
4475 struct snd_interval t = {
4480 return snd_interval_refine(r, &t);
4481 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4482 struct snd_interval t = {
4487 return snd_interval_refine(r, &t);
4488 } else if (c->max <= hdsp->ds_in_channels) {
4489 struct snd_interval t = {
4494 return snd_interval_refine(r, &t);
4499 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4501 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4502 struct snd_pcm_runtime *runtime = substream->runtime;
4504 if (hdsp_check_for_iobox (hdsp))
4507 if (hdsp_check_for_firmware(hdsp, 1))
4510 spin_lock_irq(&hdsp->lock);
4512 snd_pcm_set_sync(substream);
4514 runtime->hw = snd_hdsp_playback_subinfo;
4515 snd_pcm_set_runtime_buffer(substream, &hdsp->playback_dma_buf);
4517 hdsp->playback_pid = current->pid;
4518 hdsp->playback_substream = substream;
4520 spin_unlock_irq(&hdsp->lock);
4522 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4523 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4524 if (hdsp->clock_source_locked) {
4525 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4526 } else if (hdsp->io_type == H9632) {
4527 runtime->hw.rate_max = 192000;
4528 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4529 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4531 if (hdsp->io_type == H9632) {
4532 runtime->hw.channels_min = hdsp->qs_out_channels;
4533 runtime->hw.channels_max = hdsp->ss_out_channels;
4536 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4537 snd_hdsp_hw_rule_out_channels, hdsp,
4538 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4539 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4540 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4541 SNDRV_PCM_HW_PARAM_RATE, -1);
4542 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4543 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4544 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4546 if (RPM != hdsp->io_type) {
4547 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4548 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4549 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4550 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4555 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4557 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4559 spin_lock_irq(&hdsp->lock);
4561 hdsp->playback_pid = -1;
4562 hdsp->playback_substream = NULL;
4564 spin_unlock_irq(&hdsp->lock);
4566 if (RPM != hdsp->io_type) {
4567 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4568 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4569 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4575 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4577 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4578 struct snd_pcm_runtime *runtime = substream->runtime;
4580 if (hdsp_check_for_iobox (hdsp))
4583 if (hdsp_check_for_firmware(hdsp, 1))
4586 spin_lock_irq(&hdsp->lock);
4588 snd_pcm_set_sync(substream);
4590 runtime->hw = snd_hdsp_capture_subinfo;
4591 snd_pcm_set_runtime_buffer(substream, &hdsp->capture_dma_buf);
4593 hdsp->capture_pid = current->pid;
4594 hdsp->capture_substream = substream;
4596 spin_unlock_irq(&hdsp->lock);
4598 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4599 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4600 if (hdsp->io_type == H9632) {
4601 runtime->hw.channels_min = hdsp->qs_in_channels;
4602 runtime->hw.channels_max = hdsp->ss_in_channels;
4603 runtime->hw.rate_max = 192000;
4604 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4605 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4607 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4608 snd_hdsp_hw_rule_in_channels, hdsp,
4609 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4610 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4611 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4612 SNDRV_PCM_HW_PARAM_RATE, -1);
4613 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4614 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4615 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4619 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4621 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4623 spin_lock_irq(&hdsp->lock);
4625 hdsp->capture_pid = -1;
4626 hdsp->capture_substream = NULL;
4628 spin_unlock_irq(&hdsp->lock);
4632 /* helper functions for copying meter values */
4633 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4635 u32 val = readl(src);
4636 return copy_to_user(dest, &val, 4);
4639 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4641 u32 rms_low, rms_high;
4643 rms_low = readl(src_low);
4644 rms_high = readl(src_high);
4645 rms = ((u64)rms_high << 32) | rms_low;
4646 return copy_to_user(dest, &rms, 8);
4649 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4651 u32 rms_low, rms_high;
4653 rms_low = readl(src_low) & 0xffffff00;
4654 rms_high = readl(src_high) & 0xffffff00;
4655 rms = ((u64)rms_high << 32) | rms_low;
4656 return copy_to_user(dest, &rms, 8);
4659 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4661 int doublespeed = 0;
4662 int i, j, channels, ofs;
4664 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4666 channels = doublespeed ? 14 : 26;
4667 for (i = 0, j = 0; i < 26; ++i) {
4668 if (doublespeed && (i & 4))
4670 ofs = HDSP_9652_peakBase - j * 4;
4671 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4673 ofs -= channels * 4;
4674 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4676 ofs -= channels * 4;
4677 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4679 ofs = HDSP_9652_rmsBase + j * 8;
4680 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4681 hdsp->iobase + ofs + 4))
4683 ofs += channels * 8;
4684 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4685 hdsp->iobase + ofs + 4))
4687 ofs += channels * 8;
4688 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4689 hdsp->iobase + ofs + 4))
4696 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4699 struct hdsp_9632_meters __iomem *m;
4700 int doublespeed = 0;
4702 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4704 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4705 for (i = 0, j = 0; i < 16; ++i, ++j) {
4706 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4708 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4710 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4712 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4713 &m->input_rms_high[j]))
4715 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4716 &m->playback_rms_high[j]))
4718 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4719 &m->output_rms_high[j]))
4721 if (doublespeed && i == 3) i += 4;
4726 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4730 for (i = 0; i < 26; i++) {
4731 if (copy_u32_le(&peak_rms->playback_peaks[i],
4732 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4734 if (copy_u32_le(&peak_rms->input_peaks[i],
4735 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4738 for (i = 0; i < 28; i++) {
4739 if (copy_u32_le(&peak_rms->output_peaks[i],
4740 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4743 for (i = 0; i < 26; ++i) {
4744 if (copy_u64_le(&peak_rms->playback_rms[i],
4745 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4746 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4748 if (copy_u64_le(&peak_rms->input_rms[i],
4749 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4750 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4756 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4758 struct hdsp *hdsp = hw->private_data;
4759 void __user *argp = (void __user *)arg;
4763 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4764 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4766 err = hdsp_check_for_iobox(hdsp);
4770 err = hdsp_check_for_firmware(hdsp, 1);
4774 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4775 dev_err(hdsp->card->dev,
4776 "firmware needs to be uploaded to the card.\n");
4780 switch (hdsp->io_type) {
4782 return hdsp_9652_get_peak(hdsp, peak_rms);
4784 return hdsp_9632_get_peak(hdsp, peak_rms);
4786 return hdsp_get_peak(hdsp, peak_rms);
4789 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4790 struct hdsp_config_info info;
4791 unsigned long flags;
4794 err = hdsp_check_for_iobox(hdsp);
4798 err = hdsp_check_for_firmware(hdsp, 1);
4802 memset(&info, 0, sizeof(info));
4803 spin_lock_irqsave(&hdsp->lock, flags);
4804 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4805 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4806 if (hdsp->io_type != H9632)
4807 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4808 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4809 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4810 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4811 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4812 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4813 HDSP_SPDIFOpticalOut);
4814 info.spdif_professional = (unsigned char)
4815 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4816 info.spdif_emphasis = (unsigned char)
4817 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4818 info.spdif_nonaudio = (unsigned char)
4819 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4820 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4821 info.system_sample_rate = hdsp->system_sample_rate;
4822 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4823 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4824 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4825 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4826 info.line_out = (unsigned char)
4827 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4828 if (hdsp->io_type == H9632) {
4829 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4830 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4831 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4832 info.xlr_breakout_cable =
4833 (unsigned char)hdsp_toggle_setting(hdsp,
4834 HDSP_XLRBreakoutCable);
4836 } else if (hdsp->io_type == RPM) {
4837 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4838 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4840 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4841 info.analog_extension_board =
4842 (unsigned char)hdsp_toggle_setting(hdsp,
4843 HDSP_AnalogExtensionBoard);
4844 spin_unlock_irqrestore(&hdsp->lock, flags);
4845 if (copy_to_user(argp, &info, sizeof(info)))
4849 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4850 struct hdsp_9632_aeb h9632_aeb;
4852 if (hdsp->io_type != H9632) return -EINVAL;
4853 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4854 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4855 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4859 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4860 struct hdsp_version hdsp_version;
4863 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4864 if (hdsp->io_type == Undefined) {
4865 err = hdsp_get_iobox_version(hdsp);
4869 memset(&hdsp_version, 0, sizeof(hdsp_version));
4870 hdsp_version.io_type = hdsp->io_type;
4871 hdsp_version.firmware_rev = hdsp->firmware_rev;
4872 if (copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))
4876 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4877 struct hdsp_firmware firmware;
4878 u32 __user *firmware_data;
4881 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4882 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4883 if (hdsp->io_type == Undefined) return -EINVAL;
4885 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4888 dev_info(hdsp->card->dev,
4889 "initializing firmware upload\n");
4890 if (copy_from_user(&firmware, argp, sizeof(firmware)))
4892 firmware_data = (u32 __user *)firmware.firmware_data;
4894 if (hdsp_check_for_iobox (hdsp))
4897 if (!hdsp->fw_uploaded) {
4898 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4899 if (!hdsp->fw_uploaded)
4903 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4904 HDSP_FIRMWARE_SIZE)) {
4905 vfree(hdsp->fw_uploaded);
4906 hdsp->fw_uploaded = NULL;
4910 hdsp->state |= HDSP_FirmwareCached;
4912 err = snd_hdsp_load_firmware_from_cache(hdsp);
4916 if (!(hdsp->state & HDSP_InitializationComplete)) {
4917 err = snd_hdsp_enable_io(hdsp);
4921 snd_hdsp_initialize_channels(hdsp);
4922 snd_hdsp_initialize_midi_flush(hdsp);
4924 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
4926 dev_err(hdsp->card->dev,
4927 "error creating alsa devices\n");
4933 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4934 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4935 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4945 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4946 .open = snd_hdsp_playback_open,
4947 .close = snd_hdsp_playback_release,
4948 .ioctl = snd_hdsp_ioctl,
4949 .hw_params = snd_hdsp_hw_params,
4950 .prepare = snd_hdsp_prepare,
4951 .trigger = snd_hdsp_trigger,
4952 .pointer = snd_hdsp_hw_pointer,
4953 .copy_user = snd_hdsp_playback_copy,
4954 .copy_kernel = snd_hdsp_playback_copy_kernel,
4955 .fill_silence = snd_hdsp_hw_silence,
4958 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4959 .open = snd_hdsp_capture_open,
4960 .close = snd_hdsp_capture_release,
4961 .ioctl = snd_hdsp_ioctl,
4962 .hw_params = snd_hdsp_hw_params,
4963 .prepare = snd_hdsp_prepare,
4964 .trigger = snd_hdsp_trigger,
4965 .pointer = snd_hdsp_hw_pointer,
4966 .copy_user = snd_hdsp_capture_copy,
4967 .copy_kernel = snd_hdsp_capture_copy_kernel,
4970 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4972 struct snd_hwdep *hw;
4975 err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw);
4980 hw->private_data = hdsp;
4981 strcpy(hw->name, "HDSP hwdep interface");
4983 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4984 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4989 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4991 struct snd_pcm *pcm;
4994 err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm);
4999 pcm->private_data = hdsp;
5000 strcpy(pcm->name, hdsp->card_name);
5002 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
5003 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
5005 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
5010 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
5012 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
5013 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
5016 static int snd_hdsp_enable_io (struct hdsp *hdsp)
5020 if (hdsp_fifo_wait (hdsp, 0, 100)) {
5021 dev_err(hdsp->card->dev,
5022 "enable_io fifo_wait failed\n");
5026 for (i = 0; i < hdsp->max_channels; ++i) {
5027 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
5028 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
5034 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
5036 int status, aebi_channels, aebo_channels, i;
5038 switch (hdsp->io_type) {
5040 hdsp->card_name = "RME Hammerfall DSP + Digiface";
5041 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5042 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5046 hdsp->card_name = "RME Hammerfall HDSP 9652";
5047 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5048 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5052 status = hdsp_read(hdsp, HDSP_statusRegister);
5053 /* HDSP_AEBx bits are low when AEB are connected */
5054 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5055 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5056 hdsp->card_name = "RME Hammerfall HDSP 9632";
5057 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5058 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5059 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5060 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5061 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5062 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5063 /* Disable loopback of output channels, as the set function
5064 * only sets on a change we fake all bits (channels) as enabled.
5066 hdsp->io_loopback = 0xffffffff;
5067 for (i = 0; i < hdsp->max_channels; ++i)
5068 hdsp_loopback_set(hdsp, i, false);
5072 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5073 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5074 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5078 hdsp->card_name = "RME Hammerfall DSP + RPM";
5079 hdsp->ss_in_channels = RPM_CHANNELS-1;
5080 hdsp->ss_out_channels = RPM_CHANNELS;
5081 hdsp->ds_in_channels = RPM_CHANNELS-1;
5082 hdsp->ds_out_channels = RPM_CHANNELS;
5086 /* should never get here */
5091 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5093 snd_hdsp_flush_midi_input (hdsp, 0);
5094 snd_hdsp_flush_midi_input (hdsp, 1);
5097 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5101 err = snd_hdsp_create_pcm(card, hdsp);
5104 "Error creating pcm interface\n");
5109 err = snd_hdsp_create_midi(card, hdsp, 0);
5112 "Error creating first midi interface\n");
5116 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5117 err = snd_hdsp_create_midi(card, hdsp, 1);
5120 "Error creating second midi interface\n");
5125 err = snd_hdsp_create_controls(card, hdsp);
5128 "Error creating ctl interface\n");
5132 snd_hdsp_proc_init(hdsp);
5134 hdsp->system_sample_rate = -1;
5135 hdsp->playback_pid = -1;
5136 hdsp->capture_pid = -1;
5137 hdsp->capture_substream = NULL;
5138 hdsp->playback_substream = NULL;
5140 err = snd_hdsp_set_defaults(hdsp);
5143 "Error setting default values\n");
5147 if (!(hdsp->state & HDSP_InitializationComplete)) {
5148 strcpy(card->shortname, "Hammerfall DSP");
5149 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5150 hdsp->port, hdsp->irq);
5152 err = snd_card_register(card);
5155 "error registering card\n");
5158 hdsp->state |= HDSP_InitializationComplete;
5164 /* load firmware via hotplug fw loader */
5165 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5168 const struct firmware *fw;
5171 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5173 if (hdsp->io_type == Undefined) {
5174 err = hdsp_get_iobox_version(hdsp);
5177 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5181 /* caution: max length of firmware filename is 30! */
5182 switch (hdsp->io_type) {
5184 fwfile = "rpm_firmware.bin";
5187 if (hdsp->firmware_rev == 0xa)
5188 fwfile = "multiface_firmware.bin";
5190 fwfile = "multiface_firmware_rev11.bin";
5193 if (hdsp->firmware_rev == 0xa)
5194 fwfile = "digiface_firmware.bin";
5196 fwfile = "digiface_firmware_rev11.bin";
5199 dev_err(hdsp->card->dev,
5200 "invalid io_type %d\n", hdsp->io_type);
5204 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5205 dev_err(hdsp->card->dev,
5206 "cannot load firmware %s\n", fwfile);
5209 if (fw->size < HDSP_FIRMWARE_SIZE) {
5210 dev_err(hdsp->card->dev,
5211 "too short firmware size %d (expected %d)\n",
5212 (int)fw->size, HDSP_FIRMWARE_SIZE);
5213 release_firmware(fw);
5217 hdsp->firmware = fw;
5219 hdsp->state |= HDSP_FirmwareCached;
5221 err = snd_hdsp_load_firmware_from_cache(hdsp);
5225 if (!(hdsp->state & HDSP_InitializationComplete)) {
5226 err = snd_hdsp_enable_io(hdsp);
5230 err = snd_hdsp_create_hwdep(hdsp->card, hdsp);
5232 dev_err(hdsp->card->dev,
5233 "error creating hwdep device\n");
5236 snd_hdsp_initialize_channels(hdsp);
5237 snd_hdsp_initialize_midi_flush(hdsp);
5238 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);
5240 dev_err(hdsp->card->dev,
5241 "error creating alsa devices\n");
5248 static int snd_hdsp_create(struct snd_card *card,
5251 struct pci_dev *pci = hdsp->pci;
5258 hdsp->midi[0].rmidi = NULL;
5259 hdsp->midi[1].rmidi = NULL;
5260 hdsp->midi[0].input = NULL;
5261 hdsp->midi[1].input = NULL;
5262 hdsp->midi[0].output = NULL;
5263 hdsp->midi[1].output = NULL;
5264 hdsp->midi[0].pending = 0;
5265 hdsp->midi[1].pending = 0;
5266 spin_lock_init(&hdsp->midi[0].lock);
5267 spin_lock_init(&hdsp->midi[1].lock);
5268 hdsp->iobase = NULL;
5269 hdsp->control_register = 0;
5270 hdsp->control2_register = 0;
5271 hdsp->io_type = Undefined;
5272 hdsp->max_channels = 26;
5276 spin_lock_init(&hdsp->lock);
5278 INIT_WORK(&hdsp->midi_work, hdsp_midi_work);
5280 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5281 hdsp->firmware_rev &= 0xff;
5283 /* From Martin Bjoernsen :
5284 "It is important that the card's latency timer register in
5285 the PCI configuration space is set to a value much larger
5286 than 0 by the computer's BIOS or the driver.
5287 The windows driver always sets this 8 bit register [...]
5288 to its maximum 255 to avoid problems with some computers."
5290 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5292 strcpy(card->driver, "H-DSP");
5293 strcpy(card->mixername, "Xilinx FPGA");
5295 if (hdsp->firmware_rev < 0xa)
5297 else if (hdsp->firmware_rev < 0x64)
5298 hdsp->card_name = "RME Hammerfall DSP";
5299 else if (hdsp->firmware_rev < 0x96) {
5300 hdsp->card_name = "RME HDSP 9652";
5303 hdsp->card_name = "RME HDSP 9632";
5304 hdsp->max_channels = 16;
5308 err = pcim_enable_device(pci);
5312 pci_set_master(hdsp->pci);
5314 err = pci_request_regions(pci, "hdsp");
5317 hdsp->port = pci_resource_start(pci, 0);
5318 hdsp->iobase = devm_ioremap(&pci->dev, hdsp->port, HDSP_IO_EXTENT);
5319 if (!hdsp->iobase) {
5320 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5321 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5325 if (devm_request_irq(&pci->dev, pci->irq, snd_hdsp_interrupt,
5326 IRQF_SHARED, KBUILD_MODNAME, hdsp)) {
5327 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5331 hdsp->irq = pci->irq;
5332 card->sync_irq = hdsp->irq;
5333 hdsp->precise_ptr = 0;
5334 hdsp->use_midi_work = 1;
5335 hdsp->dds_value = 0;
5337 err = snd_hdsp_initialize_memory(hdsp);
5341 if (!is_9652 && !is_9632) {
5342 /* we wait a maximum of 10 seconds to let freshly
5343 * inserted cardbus cards do their hardware init */
5344 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5349 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5350 err = hdsp_request_fw_loader(hdsp);
5352 /* we don't fail as this can happen
5353 if userspace is not ready for
5356 dev_err(hdsp->card->dev,
5357 "couldn't get firmware from userspace. try using hdsploader\n");
5359 /* init is complete, we return */
5361 /* we defer initialization */
5362 dev_info(hdsp->card->dev,
5363 "card initialization pending : waiting for firmware\n");
5364 err = snd_hdsp_create_hwdep(card, hdsp);
5369 dev_info(hdsp->card->dev,
5370 "Firmware already present, initializing card.\n");
5371 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5372 hdsp->io_type = RPM;
5373 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5374 hdsp->io_type = Multiface;
5376 hdsp->io_type = Digiface;
5380 err = snd_hdsp_enable_io(hdsp);
5385 hdsp->io_type = H9652;
5388 hdsp->io_type = H9632;
5390 err = snd_hdsp_create_hwdep(card, hdsp);
5394 snd_hdsp_initialize_channels(hdsp);
5395 snd_hdsp_initialize_midi_flush(hdsp);
5397 hdsp->state |= HDSP_FirmwareLoaded;
5399 err = snd_hdsp_create_alsa_devices(card, hdsp);
5406 static void snd_hdsp_card_free(struct snd_card *card)
5408 struct hdsp *hdsp = card->private_data;
5411 /* stop the audio, and cancel all interrupts */
5412 cancel_work_sync(&hdsp->midi_work);
5413 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5414 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5417 release_firmware(hdsp->firmware);
5418 vfree(hdsp->fw_uploaded);
5421 static int snd_hdsp_probe(struct pci_dev *pci,
5422 const struct pci_device_id *pci_id)
5426 struct snd_card *card;
5429 if (dev >= SNDRV_CARDS)
5436 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5437 sizeof(struct hdsp), &card);
5441 hdsp = card->private_data;
5442 card->private_free = snd_hdsp_card_free;
5445 err = snd_hdsp_create(card, hdsp);
5449 strcpy(card->shortname, "Hammerfall DSP");
5450 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5451 hdsp->port, hdsp->irq);
5452 err = snd_card_register(card);
5455 pci_set_drvdata(pci, card);
5460 snd_card_free(card);
5464 static struct pci_driver hdsp_driver = {
5465 .name = KBUILD_MODNAME,
5466 .id_table = snd_hdsp_ids,
5467 .probe = snd_hdsp_probe,
5470 module_pci_driver(hdsp_driver);