sound/pci/rme96.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
   4  *   interfaces
   5  *
   6  *      Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
   7  *
   8  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
   9  *      code.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/pci.h>
  16 #include <linux/module.h>
  17 #include <linux/vmalloc.h>
  18 #include <linux/io.h>
  19
  20 #include <sound/core.h>
  21 #include <sound/info.h>
  22 #include <sound/control.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/asoundef.h>
  26 #include <sound/initval.h>
  27
  28 /* note, two last pcis should be equal, it is not a bug */
  29
  30 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
  31 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
  32                    "Digi96/8 PAD");
  33 MODULE_LICENSE("GPL");
  34 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
  35                 "{RME,Digi96/8},"
  36                 "{RME,Digi96/8 PRO},"
  37                 "{RME,Digi96/8 PST},"
  38                 "{RME,Digi96/8 PAD}}");
  39
  40 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  41 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  42 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  43
  44 module_param_array(index, int, NULL, 0444);
  45 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
  46 module_param_array(id, charp, NULL, 0444);
  47 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
  48 module_param_array(enable, bool, NULL, 0444);
  49 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
  50
  51 /*
  52  * Defines for RME Digi96 series, from internal RME reference documents
  53  * dated 12.01.00
  54  */
  55
  56 #define RME96_SPDIF_NCHANNELS 2
  57
  58 /* Playback and capture buffer size */
  59 #define RME96_BUFFER_SIZE 0x10000
  60
  61 /* IO area size */
  62 #define RME96_IO_SIZE 0x60000
  63
  64 /* IO area offsets */
  65 #define RME96_IO_PLAY_BUFFER      0x0
  66 #define RME96_IO_REC_BUFFER       0x10000
  67 #define RME96_IO_CONTROL_REGISTER 0x20000
  68 #define RME96_IO_ADDITIONAL_REG   0x20004
  69 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
  70 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
  71 #define RME96_IO_SET_PLAY_POS     0x40000
  72 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
  73 #define RME96_IO_SET_REC_POS      0x50000
  74 #define RME96_IO_RESET_REC_POS    0x5FFFC
  75 #define RME96_IO_GET_PLAY_POS     0x20000
  76 #define RME96_IO_GET_REC_POS      0x30000
  77
  78 /* Write control register bits */
  79 #define RME96_WCR_START     (1 << 0)
  80 #define RME96_WCR_START_2   (1 << 1)
  81 #define RME96_WCR_GAIN_0    (1 << 2)
  82 #define RME96_WCR_GAIN_1    (1 << 3)
  83 #define RME96_WCR_MODE24    (1 << 4)
  84 #define RME96_WCR_MODE24_2  (1 << 5)
  85 #define RME96_WCR_BM        (1 << 6)
  86 #define RME96_WCR_BM_2      (1 << 7)
  87 #define RME96_WCR_ADAT      (1 << 8)
  88 #define RME96_WCR_FREQ_0    (1 << 9)
  89 #define RME96_WCR_FREQ_1    (1 << 10)
  90 #define RME96_WCR_DS        (1 << 11)
  91 #define RME96_WCR_PRO       (1 << 12)
  92 #define RME96_WCR_EMP       (1 << 13)
  93 #define RME96_WCR_SEL       (1 << 14)
  94 #define RME96_WCR_MASTER    (1 << 15)
  95 #define RME96_WCR_PD        (1 << 16)
  96 #define RME96_WCR_INP_0     (1 << 17)
  97 #define RME96_WCR_INP_1     (1 << 18)
  98 #define RME96_WCR_THRU_0    (1 << 19)
  99 #define RME96_WCR_THRU_1    (1 << 20)
 100 #define RME96_WCR_THRU_2    (1 << 21)
 101 #define RME96_WCR_THRU_3    (1 << 22)
 102 #define RME96_WCR_THRU_4    (1 << 23)
 103 #define RME96_WCR_THRU_5    (1 << 24)
 104 #define RME96_WCR_THRU_6    (1 << 25)
 105 #define RME96_WCR_THRU_7    (1 << 26)
 106 #define RME96_WCR_DOLBY     (1 << 27)
 107 #define RME96_WCR_MONITOR_0 (1 << 28)
 108 #define RME96_WCR_MONITOR_1 (1 << 29)
 109 #define RME96_WCR_ISEL      (1 << 30)
 110 #define RME96_WCR_IDIS      (1 << 31)
 111
 112 #define RME96_WCR_BITPOS_GAIN_0 2
 113 #define RME96_WCR_BITPOS_GAIN_1 3
 114 #define RME96_WCR_BITPOS_FREQ_0 9
 115 #define RME96_WCR_BITPOS_FREQ_1 10
 116 #define RME96_WCR_BITPOS_INP_0 17
 117 #define RME96_WCR_BITPOS_INP_1 18
 118 #define RME96_WCR_BITPOS_MONITOR_0 28
 119 #define RME96_WCR_BITPOS_MONITOR_1 29
 120
 121 /* Read control register bits */
 122 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
 123 #define RME96_RCR_IRQ_2     (1 << 16)
 124 #define RME96_RCR_T_OUT     (1 << 17)
 125 #define RME96_RCR_DEV_ID_0  (1 << 21)
 126 #define RME96_RCR_DEV_ID_1  (1 << 22)
 127 #define RME96_RCR_LOCK      (1 << 23)
 128 #define RME96_RCR_VERF      (1 << 26)
 129 #define RME96_RCR_F0        (1 << 27)
 130 #define RME96_RCR_F1        (1 << 28)
 131 #define RME96_RCR_F2        (1 << 29)
 132 #define RME96_RCR_AUTOSYNC  (1 << 30)
 133 #define RME96_RCR_IRQ       (1 << 31)
 134
 135 #define RME96_RCR_BITPOS_F0 27
 136 #define RME96_RCR_BITPOS_F1 28
 137 #define RME96_RCR_BITPOS_F2 29
 138
 139 /* Additional register bits */
 140 #define RME96_AR_WSEL       (1 << 0)
 141 #define RME96_AR_ANALOG     (1 << 1)
 142 #define RME96_AR_FREQPAD_0  (1 << 2)
 143 #define RME96_AR_FREQPAD_1  (1 << 3)
 144 #define RME96_AR_FREQPAD_2  (1 << 4)
 145 #define RME96_AR_PD2        (1 << 5)
 146 #define RME96_AR_DAC_EN     (1 << 6)
 147 #define RME96_AR_CLATCH     (1 << 7)
 148 #define RME96_AR_CCLK       (1 << 8)
 149 #define RME96_AR_CDATA      (1 << 9)
 150
 151 #define RME96_AR_BITPOS_F0 2
 152 #define RME96_AR_BITPOS_F1 3
 153 #define RME96_AR_BITPOS_F2 4
 154
 155 /* Monitor tracks */
 156 #define RME96_MONITOR_TRACKS_1_2 0
 157 #define RME96_MONITOR_TRACKS_3_4 1
 158 #define RME96_MONITOR_TRACKS_5_6 2
 159 #define RME96_MONITOR_TRACKS_7_8 3
 160
 161 /* Attenuation */
 162 #define RME96_ATTENUATION_0 0
 163 #define RME96_ATTENUATION_6 1
 164 #define RME96_ATTENUATION_12 2
 165 #define RME96_ATTENUATION_18 3
 166
 167 /* Input types */
 168 #define RME96_INPUT_OPTICAL 0
 169 #define RME96_INPUT_COAXIAL 1
 170 #define RME96_INPUT_INTERNAL 2
 171 #define RME96_INPUT_XLR 3
 172 #define RME96_INPUT_ANALOG 4
 173
 174 /* Clock modes */
 175 #define RME96_CLOCKMODE_SLAVE 0
 176 #define RME96_CLOCKMODE_MASTER 1
 177 #define RME96_CLOCKMODE_WORDCLOCK 2
 178
 179 /* Block sizes in bytes */
 180 #define RME96_SMALL_BLOCK_SIZE 2048
 181 #define RME96_LARGE_BLOCK_SIZE 8192
 182
 183 /* Volume control */
 184 #define RME96_AD1852_VOL_BITS 14
 185 #define RME96_AD1855_VOL_BITS 10
 186
 187 /* Defines for snd_rme96_trigger */
 188 #define RME96_TB_START_PLAYBACK 1
 189 #define RME96_TB_START_CAPTURE 2
 190 #define RME96_TB_STOP_PLAYBACK 4
 191 #define RME96_TB_STOP_CAPTURE 8
 192 #define RME96_TB_RESET_PLAYPOS 16
 193 #define RME96_TB_RESET_CAPTUREPOS 32
 194 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64
 195 #define RME96_TB_CLEAR_CAPTURE_IRQ 128
 196 #define RME96_RESUME_PLAYBACK   (RME96_TB_START_PLAYBACK)
 197 #define RME96_RESUME_CAPTURE    (RME96_TB_START_CAPTURE)
 198 #define RME96_RESUME_BOTH       (RME96_RESUME_PLAYBACK \
 199                                 | RME96_RESUME_CAPTURE)
 200 #define RME96_START_PLAYBACK    (RME96_TB_START_PLAYBACK \
 201                                 | RME96_TB_RESET_PLAYPOS)
 202 #define RME96_START_CAPTURE     (RME96_TB_START_CAPTURE \
 203                                 | RME96_TB_RESET_CAPTUREPOS)
 204 #define RME96_START_BOTH        (RME96_START_PLAYBACK \
 205                                 | RME96_START_CAPTURE)
 206 #define RME96_STOP_PLAYBACK     (RME96_TB_STOP_PLAYBACK \
 207                                 | RME96_TB_CLEAR_PLAYBACK_IRQ)
 208 #define RME96_STOP_CAPTURE      (RME96_TB_STOP_CAPTURE \
 209                                 | RME96_TB_CLEAR_CAPTURE_IRQ)
 210 #define RME96_STOP_BOTH         (RME96_STOP_PLAYBACK \
 211                                 | RME96_STOP_CAPTURE)
 212
 213 struct rme96 {
 214         spinlock_t    lock;
 215         int irq;
 216         unsigned long port;
 217         void __iomem *iobase;
 218
 219         u32 wcreg;    /* cached write control register value */
 220         u32 wcreg_spdif;                /* S/PDIF setup */
 221         u32 wcreg_spdif_stream;         /* S/PDIF setup (temporary) */
 222         u32 rcreg;    /* cached read control register value */
 223         u32 areg;     /* cached additional register value */
 224         u16 vol[2]; /* cached volume of analog output */
 225
 226         u8 rev; /* card revision number */
 227
 228 #ifdef CONFIG_PM_SLEEP
 229         u32 playback_pointer;
 230         u32 capture_pointer;
 231         void *playback_suspend_buffer;
 232         void *capture_suspend_buffer;
 233 #endif
 234
 235         struct snd_pcm_substream *playback_substream;
 236         struct snd_pcm_substream *capture_substream;
 237
 238         int playback_frlog; /* log2 of framesize */
 239         int capture_frlog;
 240
 241         size_t playback_periodsize; /* in bytes, zero if not used */
 242         size_t capture_periodsize; /* in bytes, zero if not used */
 243
 244         struct snd_card *card;
 245         struct snd_pcm *spdif_pcm;
 246         struct snd_pcm *adat_pcm;
 247         struct pci_dev     *pci;
 248         struct snd_kcontrol   *spdif_ctl;
 249 };
 250
 251 static const struct pci_device_id snd_rme96_ids[] = {
 252         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
 253         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
 254         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
 255         { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
 256         { 0, }
 257 };
 258
 259 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
 260
 261 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
 262 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
 263 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 264 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
 265                                      (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
 266 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
 267 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
 268                                   ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
 269 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
 270
 271 static int
 272 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
 273
 274 static int
 275 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
 276
 277 static int
 278 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
 279                            int cmd);
 280
 281 static int
 282 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
 283                           int cmd);
 284
 285 static snd_pcm_uframes_t
 286 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
 287
 288 static snd_pcm_uframes_t
 289 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
 290
 291 static void snd_rme96_proc_init(struct rme96 *rme96);
 292
 293 static int
 294 snd_rme96_create_switches(struct snd_card *card,
 295                           struct rme96 *rme96);
 296
 297 static int
 298 snd_rme96_getinputtype(struct rme96 *rme96);
 299
 300 static inline unsigned int
 301 snd_rme96_playback_ptr(struct rme96 *rme96)
 302 {
 303         return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
 304                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
 305 }
 306
 307 static inline unsigned int
 308 snd_rme96_capture_ptr(struct rme96 *rme96)
 309 {
 310         return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
 311                 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
 312 }
 313
 314 static int
 315 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
 316                            int channel, unsigned long pos, unsigned long count)
 317 {
 318         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 319
 320         memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
 321                   0, count);
 322         return 0;
 323 }
 324
 325 static int
 326 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
 327                         int channel, unsigned long pos,
 328                         void __user *src, unsigned long count)
 329 {
 330         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 331
 332         return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
 333                                    src, count);
 334 }
 335
 336 static int
 337 snd_rme96_playback_copy_kernel(struct snd_pcm_substream *substream,
 338                                int channel, unsigned long pos,
 339                                void *src, unsigned long count)
 340 {
 341         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 342
 343         memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, count);
 344         return 0;
 345 }
 346
 347 static int
 348 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
 349                        int channel, unsigned long pos,
 350                        void __user *dst, unsigned long count)
 351 {
 352         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 353
 354         return copy_to_user_fromio(dst,
 355                                    rme96->iobase + RME96_IO_REC_BUFFER + pos,
 356                                    count);
 357 }
 358
 359 static int
 360 snd_rme96_capture_copy_kernel(struct snd_pcm_substream *substream,
 361                               int channel, unsigned long pos,
 362                               void *dst, unsigned long count)
 363 {
 364         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 365
 366         memcpy_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, count);
 367         return 0;
 368 }
 369
 370 /*
 371  * Digital output capabilities (S/PDIF)
 372  */
 373 static const struct snd_pcm_hardware snd_rme96_playback_spdif_info =
 374 {
 375         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 376                               SNDRV_PCM_INFO_MMAP_VALID |
 377                               SNDRV_PCM_INFO_SYNC_START |
 378                               SNDRV_PCM_INFO_RESUME |
 379                               SNDRV_PCM_INFO_INTERLEAVED |
 380                               SNDRV_PCM_INFO_PAUSE),
 381         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 382                               SNDRV_PCM_FMTBIT_S32_LE),
 383         .rates =             (SNDRV_PCM_RATE_32000 |
 384                               SNDRV_PCM_RATE_44100 |
 385                               SNDRV_PCM_RATE_48000 |
 386                               SNDRV_PCM_RATE_64000 |
 387                               SNDRV_PCM_RATE_88200 |
 388                               SNDRV_PCM_RATE_96000),
 389         .rate_min =          32000,
 390         .rate_max =          96000,
 391         .channels_min =      2,
 392         .channels_max =      2,
 393         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 394         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 395         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 396         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 397         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 398         .fifo_size =         0,
 399 };
 400
 401 /*
 402  * Digital input capabilities (S/PDIF)
 403  */
 404 static const struct snd_pcm_hardware snd_rme96_capture_spdif_info =
 405 {
 406         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 407                               SNDRV_PCM_INFO_MMAP_VALID |
 408                               SNDRV_PCM_INFO_SYNC_START |
 409                               SNDRV_PCM_INFO_RESUME |
 410                               SNDRV_PCM_INFO_INTERLEAVED |
 411                               SNDRV_PCM_INFO_PAUSE),
 412         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 413                               SNDRV_PCM_FMTBIT_S32_LE),
 414         .rates =             (SNDRV_PCM_RATE_32000 |
 415                               SNDRV_PCM_RATE_44100 |
 416                               SNDRV_PCM_RATE_48000 |
 417                               SNDRV_PCM_RATE_64000 |
 418                               SNDRV_PCM_RATE_88200 |
 419                               SNDRV_PCM_RATE_96000),
 420         .rate_min =          32000,
 421         .rate_max =          96000,
 422         .channels_min =      2,
 423         .channels_max =      2,
 424         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 425         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 426         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 427         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 428         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 429         .fifo_size =         0,
 430 };
 431
 432 /*
 433  * Digital output capabilities (ADAT)
 434  */
 435 static const struct snd_pcm_hardware snd_rme96_playback_adat_info =
 436 {
 437         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 438                               SNDRV_PCM_INFO_MMAP_VALID |
 439                               SNDRV_PCM_INFO_SYNC_START |
 440                               SNDRV_PCM_INFO_RESUME |
 441                               SNDRV_PCM_INFO_INTERLEAVED |
 442                               SNDRV_PCM_INFO_PAUSE),
 443         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 444                               SNDRV_PCM_FMTBIT_S32_LE),
 445         .rates =             (SNDRV_PCM_RATE_44100 |
 446                               SNDRV_PCM_RATE_48000),
 447         .rate_min =          44100,
 448         .rate_max =          48000,
 449         .channels_min =      8,
 450         .channels_max =      8,
 451         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 452         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 453         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 454         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 455         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 456         .fifo_size =         0,
 457 };
 458
 459 /*
 460  * Digital input capabilities (ADAT)
 461  */
 462 static const struct snd_pcm_hardware snd_rme96_capture_adat_info =
 463 {
 464         .info =              (SNDRV_PCM_INFO_MMAP_IOMEM |
 465                               SNDRV_PCM_INFO_MMAP_VALID |
 466                               SNDRV_PCM_INFO_SYNC_START |
 467                               SNDRV_PCM_INFO_RESUME |
 468                               SNDRV_PCM_INFO_INTERLEAVED |
 469                               SNDRV_PCM_INFO_PAUSE),
 470         .formats =           (SNDRV_PCM_FMTBIT_S16_LE |
 471                               SNDRV_PCM_FMTBIT_S32_LE),
 472         .rates =             (SNDRV_PCM_RATE_44100 |
 473                               SNDRV_PCM_RATE_48000),
 474         .rate_min =          44100,
 475         .rate_max =          48000,
 476         .channels_min =      8,
 477         .channels_max =      8,
 478         .buffer_bytes_max =  RME96_BUFFER_SIZE,
 479         .period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
 480         .period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
 481         .periods_min =       RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
 482         .periods_max =       RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
 483         .fifo_size =         0,
 484 };
 485
 486 /*
 487  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
 488  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
 489  * on the falling edge of CCLK and be stable on the rising edge.  The rising
 490  * edge of CLATCH after the last data bit clocks in the whole data word.
 491  * A fast processor could probably drive the SPI interface faster than the
 492  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
 493  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
 494  *
 495  * NOTE: increased delay from 1 to 10, since there where problems setting
 496  * the volume.
 497  */
 498 static void
 499 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
 500 {
 501         int i;
 502
 503         for (i = 0; i < 16; i++) {
 504                 if (val & 0x8000) {
 505                         rme96->areg |= RME96_AR_CDATA;
 506                 } else {
 507                         rme96->areg &= ~RME96_AR_CDATA;
 508                 }
 509                 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
 510                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 511                 udelay(10);
 512                 rme96->areg |= RME96_AR_CCLK;
 513                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 514                 udelay(10);
 515                 val <<= 1;
 516         }
 517         rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
 518         rme96->areg |= RME96_AR_CLATCH;
 519         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 520         udelay(10);
 521         rme96->areg &= ~RME96_AR_CLATCH;
 522         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 523 }
 524
 525 static void
 526 snd_rme96_apply_dac_volume(struct rme96 *rme96)
 527 {
 528         if (RME96_DAC_IS_1852(rme96)) {
 529                 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
 530                 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
 531         } else if (RME96_DAC_IS_1855(rme96)) {
 532                 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
 533                 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
 534         }
 535 }
 536
 537 static void
 538 snd_rme96_reset_dac(struct rme96 *rme96)
 539 {
 540         writel(rme96->wcreg | RME96_WCR_PD,
 541                rme96->iobase + RME96_IO_CONTROL_REGISTER);
 542         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 543 }
 544
 545 static int
 546 snd_rme96_getmontracks(struct rme96 *rme96)
 547 {
 548         return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
 549                 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
 550 }
 551
 552 static int
 553 snd_rme96_setmontracks(struct rme96 *rme96,
 554                        int montracks)
 555 {
 556         if (montracks & 1) {
 557                 rme96->wcreg |= RME96_WCR_MONITOR_0;
 558         } else {
 559                 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
 560         }
 561         if (montracks & 2) {
 562                 rme96->wcreg |= RME96_WCR_MONITOR_1;
 563         } else {
 564                 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
 565         }
 566         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 567         return 0;
 568 }
 569
 570 static int
 571 snd_rme96_getattenuation(struct rme96 *rme96)
 572 {
 573         return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
 574                 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
 575 }
 576
 577 static int
 578 snd_rme96_setattenuation(struct rme96 *rme96,
 579                          int attenuation)
 580 {
 581         switch (attenuation) {
 582         case 0:
 583                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
 584                         ~RME96_WCR_GAIN_1;
 585                 break;
 586         case 1:
 587                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
 588                         ~RME96_WCR_GAIN_1;
 589                 break;
 590         case 2:
 591                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
 592                         RME96_WCR_GAIN_1;
 593                 break;
 594         case 3:
 595                 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
 596                         RME96_WCR_GAIN_1;
 597                 break;
 598         default:
 599                 return -EINVAL;
 600         }
 601         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 602         return 0;
 603 }
 604
 605 static int
 606 snd_rme96_capture_getrate(struct rme96 *rme96,
 607                           int *is_adat)
 608 {
 609         int n, rate;
 610
 611         *is_adat = 0;
 612         if (rme96->areg & RME96_AR_ANALOG) {
 613                 /* Analog input, overrides S/PDIF setting */
 614                 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
 615                         (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
 616                 switch (n) {
 617                 case 1:
 618                         rate = 32000;
 619                         break;
 620                 case 2:
 621                         rate = 44100;
 622                         break;
 623                 case 3:
 624                         rate = 48000;
 625                         break;
 626                 default:
 627                         return -1;
 628                 }
 629                 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
 630         }
 631
 632         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
 633         if (rme96->rcreg & RME96_RCR_LOCK) {
 634                 /* ADAT rate */
 635                 *is_adat = 1;
 636                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 637                         return 48000;
 638                 }
 639                 return 44100;
 640         }
 641
 642         if (rme96->rcreg & RME96_RCR_VERF) {
 643                 return -1;
 644         }
 645
 646         /* S/PDIF rate */
 647         n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
 648                 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
 649                 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
 650
 651         switch (n) {
 652         case 0:
 653                 if (rme96->rcreg & RME96_RCR_T_OUT) {
 654                         return 64000;
 655                 }
 656                 return -1;
 657         case 3: return 96000;
 658         case 4: return 88200;
 659         case 5: return 48000;
 660         case 6: return 44100;
 661         case 7: return 32000;
 662         default:
 663                 break;
 664         }
 665         return -1;
 666 }
 667
 668 static int
 669 snd_rme96_playback_getrate(struct rme96 *rme96)
 670 {
 671         int rate, dummy;
 672
 673         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 674             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 675             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 676         {
 677                 /* slave clock */
 678                 return rate;
 679         }
 680         rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
 681                 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
 682         switch (rate) {
 683         case 1:
 684                 rate = 32000;
 685                 break;
 686         case 2:
 687                 rate = 44100;
 688                 break;
 689         case 3:
 690                 rate = 48000;
 691                 break;
 692         default:
 693                 return -1;
 694         }
 695         return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
 696 }
 697
 698 static int
 699 snd_rme96_playback_setrate(struct rme96 *rme96,
 700                            int rate)
 701 {
 702         int ds;
 703
 704         ds = rme96->wcreg & RME96_WCR_DS;
 705         switch (rate) {
 706         case 32000:
 707                 rme96->wcreg &= ~RME96_WCR_DS;
 708                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 709                         ~RME96_WCR_FREQ_1;
 710                 break;
 711         case 44100:
 712                 rme96->wcreg &= ~RME96_WCR_DS;
 713                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 714                         ~RME96_WCR_FREQ_0;
 715                 break;
 716         case 48000:
 717                 rme96->wcreg &= ~RME96_WCR_DS;
 718                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 719                         RME96_WCR_FREQ_1;
 720                 break;
 721         case 64000:
 722                 rme96->wcreg |= RME96_WCR_DS;
 723                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
 724                         ~RME96_WCR_FREQ_1;
 725                 break;
 726         case 88200:
 727                 rme96->wcreg |= RME96_WCR_DS;
 728                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
 729                         ~RME96_WCR_FREQ_0;
 730                 break;
 731         case 96000:
 732                 rme96->wcreg |= RME96_WCR_DS;
 733                 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
 734                         RME96_WCR_FREQ_1;
 735                 break;
 736         default:
 737                 return -EINVAL;
 738         }
 739         if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
 740             (ds && !(rme96->wcreg & RME96_WCR_DS)))
 741         {
 742                 /* change to/from double-speed: reset the DAC (if available) */
 743                 snd_rme96_reset_dac(rme96);
 744                 return 1; /* need to restore volume */
 745         } else {
 746                 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 747                 return 0;
 748         }
 749 }
 750
 751 static int
 752 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
 753                                  int rate)
 754 {
 755         switch (rate) {
 756         case 32000:
 757                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 758                                ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 759                 break;
 760         case 44100:
 761                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 762                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 763                 break;
 764         case 48000:
 765                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 766                                RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
 767                 break;
 768         case 64000:
 769                 if (rme96->rev < 4) {
 770                         return -EINVAL;
 771                 }
 772                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
 773                                ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 774                 break;
 775         case 88200:
 776                 if (rme96->rev < 4) {
 777                         return -EINVAL;
 778                 }
 779                 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
 780                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 781                 break;
 782         case 96000:
 783                 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
 784                                RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
 785                 break;
 786         default:
 787                 return -EINVAL;
 788         }
 789         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 790         return 0;
 791 }
 792
 793 static int
 794 snd_rme96_setclockmode(struct rme96 *rme96,
 795                        int mode)
 796 {
 797         switch (mode) {
 798         case RME96_CLOCKMODE_SLAVE:
 799                 /* AutoSync */
 800                 rme96->wcreg &= ~RME96_WCR_MASTER;
 801                 rme96->areg &= ~RME96_AR_WSEL;
 802                 break;
 803         case RME96_CLOCKMODE_MASTER:
 804                 /* Internal */
 805                 rme96->wcreg |= RME96_WCR_MASTER;
 806                 rme96->areg &= ~RME96_AR_WSEL;
 807                 break;
 808         case RME96_CLOCKMODE_WORDCLOCK:
 809                 /* Word clock is a master mode */
 810                 rme96->wcreg |= RME96_WCR_MASTER;
 811                 rme96->areg |= RME96_AR_WSEL;
 812                 break;
 813         default:
 814                 return -EINVAL;
 815         }
 816         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 817         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 818         return 0;
 819 }
 820
 821 static int
 822 snd_rme96_getclockmode(struct rme96 *rme96)
 823 {
 824         if (rme96->areg & RME96_AR_WSEL) {
 825                 return RME96_CLOCKMODE_WORDCLOCK;
 826         }
 827         return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
 828                 RME96_CLOCKMODE_SLAVE;
 829 }
 830
 831 static int
 832 snd_rme96_setinputtype(struct rme96 *rme96,
 833                        int type)
 834 {
 835         int n;
 836
 837         switch (type) {
 838         case RME96_INPUT_OPTICAL:
 839                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
 840                         ~RME96_WCR_INP_1;
 841                 break;
 842         case RME96_INPUT_COAXIAL:
 843                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
 844                         ~RME96_WCR_INP_1;
 845                 break;
 846         case RME96_INPUT_INTERNAL:
 847                 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
 848                         RME96_WCR_INP_1;
 849                 break;
 850         case RME96_INPUT_XLR:
 851                 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 852                      rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
 853                     (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
 854                      rme96->rev > 4))
 855                 {
 856                         /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
 857                         return -EINVAL;
 858                 }
 859                 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
 860                         RME96_WCR_INP_1;
 861                 break;
 862         case RME96_INPUT_ANALOG:
 863                 if (!RME96_HAS_ANALOG_IN(rme96)) {
 864                         return -EINVAL;
 865                 }
 866                 rme96->areg |= RME96_AR_ANALOG;
 867                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 868                 if (rme96->rev < 4) {
 869                         /*
 870                          * Revision less than 004 does not support 64 and
 871                          * 88.2 kHz
 872                          */
 873                         if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
 874                                 snd_rme96_capture_analog_setrate(rme96, 44100);
 875                         }
 876                         if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
 877                                 snd_rme96_capture_analog_setrate(rme96, 32000);
 878                         }
 879                 }
 880                 return 0;
 881         default:
 882                 return -EINVAL;
 883         }
 884         if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
 885                 rme96->areg &= ~RME96_AR_ANALOG;
 886                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
 887         }
 888         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 889         return 0;
 890 }
 891
 892 static int
 893 snd_rme96_getinputtype(struct rme96 *rme96)
 894 {
 895         if (rme96->areg & RME96_AR_ANALOG) {
 896                 return RME96_INPUT_ANALOG;
 897         }
 898         return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
 899                 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
 900 }
 901
 902 static void
 903 snd_rme96_setframelog(struct rme96 *rme96,
 904                       int n_channels,
 905                       int is_playback)
 906 {
 907         int frlog;
 908
 909         if (n_channels == 2) {
 910                 frlog = 1;
 911         } else {
 912                 /* assume 8 channels */
 913                 frlog = 3;
 914         }
 915         if (is_playback) {
 916                 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
 917                 rme96->playback_frlog = frlog;
 918         } else {
 919                 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
 920                 rme96->capture_frlog = frlog;
 921         }
 922 }
 923
 924 static int
 925 snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format)
 926 {
 927         switch (format) {
 928         case SNDRV_PCM_FORMAT_S16_LE:
 929                 rme96->wcreg &= ~RME96_WCR_MODE24;
 930                 break;
 931         case SNDRV_PCM_FORMAT_S32_LE:
 932                 rme96->wcreg |= RME96_WCR_MODE24;
 933                 break;
 934         default:
 935                 return -EINVAL;
 936         }
 937         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 938         return 0;
 939 }
 940
 941 static int
 942 snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format)
 943 {
 944         switch (format) {
 945         case SNDRV_PCM_FORMAT_S16_LE:
 946                 rme96->wcreg &= ~RME96_WCR_MODE24_2;
 947                 break;
 948         case SNDRV_PCM_FORMAT_S32_LE:
 949                 rme96->wcreg |= RME96_WCR_MODE24_2;
 950                 break;
 951         default:
 952                 return -EINVAL;
 953         }
 954         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 955         return 0;
 956 }
 957
 958 static void
 959 snd_rme96_set_period_properties(struct rme96 *rme96,
 960                                 size_t period_bytes)
 961 {
 962         switch (period_bytes) {
 963         case RME96_LARGE_BLOCK_SIZE:
 964                 rme96->wcreg &= ~RME96_WCR_ISEL;
 965                 break;
 966         case RME96_SMALL_BLOCK_SIZE:
 967                 rme96->wcreg |= RME96_WCR_ISEL;
 968                 break;
 969         default:
 970                 snd_BUG();
 971                 break;
 972         }
 973         rme96->wcreg &= ~RME96_WCR_IDIS;
 974         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
 975 }
 976
 977 static int
 978 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
 979                              struct snd_pcm_hw_params *params)
 980 {
 981         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
 982         struct snd_pcm_runtime *runtime = substream->runtime;
 983         int err, rate, dummy;
 984         bool apply_dac_volume = false;
 985
 986         runtime->dma_area = (void __force *)(rme96->iobase +
 987                                              RME96_IO_PLAY_BUFFER);
 988         runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
 989         runtime->dma_bytes = RME96_BUFFER_SIZE;
 990
 991         spin_lock_irq(&rme96->lock);
 992         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
 993             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
 994             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
 995         {
 996                 /* slave clock */
 997                 if ((int)params_rate(params) != rate) {
 998                         err = -EIO;
 999                         goto error;
1000                 }
1001         } else {
1002                 err = snd_rme96_playback_setrate(rme96, params_rate(params));
1003                 if (err < 0)
1004                         goto error;
1005                 apply_dac_volume = err > 0; /* need to restore volume later? */
1006         }
1007
1008         err = snd_rme96_playback_setformat(rme96, params_format(params));
1009         if (err < 0)
1010                 goto error;
1011         snd_rme96_setframelog(rme96, params_channels(params), 1);
1012         if (rme96->capture_periodsize != 0) {
1013                 if (params_period_size(params) << rme96->playback_frlog !=
1014                     rme96->capture_periodsize)
1015                 {
1016                         err = -EBUSY;
1017                         goto error;
1018                 }
1019         }
1020         rme96->playback_periodsize =
1021                 params_period_size(params) << rme96->playback_frlog;
1022         snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1023         /* S/PDIF setup */
1024         if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1025                 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1026                 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1027         }
1028
1029         err = 0;
1030  error:
1031         spin_unlock_irq(&rme96->lock);
1032         if (apply_dac_volume) {
1033                 usleep_range(3000, 10000);
1034                 snd_rme96_apply_dac_volume(rme96);
1035         }
1036
1037         return err;
1038 }
1039
1040 static int
1041 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1042                             struct snd_pcm_hw_params *params)
1043 {
1044         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1045         struct snd_pcm_runtime *runtime = substream->runtime;
1046         int err, isadat, rate;
1047
1048         runtime->dma_area = (void __force *)(rme96->iobase +
1049                                              RME96_IO_REC_BUFFER);
1050         runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1051         runtime->dma_bytes = RME96_BUFFER_SIZE;
1052
1053         spin_lock_irq(&rme96->lock);
1054         if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1055                 spin_unlock_irq(&rme96->lock);
1056                 return err;
1057         }
1058         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1059                 if ((err = snd_rme96_capture_analog_setrate(rme96,
1060                                                             params_rate(params))) < 0)
1061                 {
1062                         spin_unlock_irq(&rme96->lock);
1063                         return err;
1064                 }
1065         } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1066                 if ((int)params_rate(params) != rate) {
1067                         spin_unlock_irq(&rme96->lock);
1068                         return -EIO;
1069                 }
1070                 if ((isadat && runtime->hw.channels_min == 2) ||
1071                     (!isadat && runtime->hw.channels_min == 8))
1072                 {
1073                         spin_unlock_irq(&rme96->lock);
1074                         return -EIO;
1075                 }
1076         }
1077         snd_rme96_setframelog(rme96, params_channels(params), 0);
1078         if (rme96->playback_periodsize != 0) {
1079                 if (params_period_size(params) << rme96->capture_frlog !=
1080                     rme96->playback_periodsize)
1081                 {
1082                         spin_unlock_irq(&rme96->lock);
1083                         return -EBUSY;
1084                 }
1085         }
1086         rme96->capture_periodsize =
1087                 params_period_size(params) << rme96->capture_frlog;
1088         snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1089         spin_unlock_irq(&rme96->lock);
1090
1091         return 0;
1092 }
1093
1094 static void
1095 snd_rme96_trigger(struct rme96 *rme96,
1096                   int op)
1097 {
1098         if (op & RME96_TB_RESET_PLAYPOS)
1099                 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1100         if (op & RME96_TB_RESET_CAPTUREPOS)
1101                 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1102         if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) {
1103                 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1104                 if (rme96->rcreg & RME96_RCR_IRQ)
1105                         writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1106         }
1107         if (op & RME96_TB_CLEAR_CAPTURE_IRQ) {
1108                 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1109                 if (rme96->rcreg & RME96_RCR_IRQ_2)
1110                         writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1111         }
1112         if (op & RME96_TB_START_PLAYBACK)
1113                 rme96->wcreg |= RME96_WCR_START;
1114         if (op & RME96_TB_STOP_PLAYBACK)
1115                 rme96->wcreg &= ~RME96_WCR_START;
1116         if (op & RME96_TB_START_CAPTURE)
1117                 rme96->wcreg |= RME96_WCR_START_2;
1118         if (op & RME96_TB_STOP_CAPTURE)
1119                 rme96->wcreg &= ~RME96_WCR_START_2;
1120         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1121 }
1122
1123
1124
1125 static irqreturn_t
1126 snd_rme96_interrupt(int irq,
1127                     void *dev_id)
1128 {
1129         struct rme96 *rme96 = (struct rme96 *)dev_id;
1130
1131         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1132         /* fastpath out, to ease interrupt sharing */
1133         if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1134               (rme96->rcreg & RME96_RCR_IRQ_2)))
1135         {
1136                 return IRQ_NONE;
1137         }
1138
1139         if (rme96->rcreg & RME96_RCR_IRQ) {
1140                 /* playback */
1141                 snd_pcm_period_elapsed(rme96->playback_substream);
1142                 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1143         }
1144         if (rme96->rcreg & RME96_RCR_IRQ_2) {
1145                 /* capture */
1146                 snd_pcm_period_elapsed(rme96->capture_substream);
1147                 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1148         }
1149         return IRQ_HANDLED;
1150 }
1151
1152 static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1153
1154 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1155         .count = ARRAY_SIZE(period_bytes),
1156         .list = period_bytes,
1157         .mask = 0
1158 };
1159
1160 static void
1161 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1162                                  struct snd_pcm_runtime *runtime)
1163 {
1164         unsigned int size;
1165
1166         snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1167                                      RME96_BUFFER_SIZE);
1168         if ((size = rme96->playback_periodsize) != 0 ||
1169             (size = rme96->capture_periodsize) != 0)
1170                 snd_pcm_hw_constraint_single(runtime,
1171                                              SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1172                                              size);
1173         else
1174                 snd_pcm_hw_constraint_list(runtime, 0,
1175                                            SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1176                                            &hw_constraints_period_bytes);
1177 }
1178
1179 static int
1180 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1181 {
1182         int rate, dummy;
1183         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1184         struct snd_pcm_runtime *runtime = substream->runtime;
1185
1186         snd_pcm_set_sync(substream);
1187         spin_lock_irq(&rme96->lock);
1188         if (rme96->playback_substream) {
1189                 spin_unlock_irq(&rme96->lock);
1190                 return -EBUSY;
1191         }
1192         rme96->wcreg &= ~RME96_WCR_ADAT;
1193         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1194         rme96->playback_substream = substream;
1195         spin_unlock_irq(&rme96->lock);
1196
1197         runtime->hw = snd_rme96_playback_spdif_info;
1198         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1199             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1200             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1201         {
1202                 /* slave clock */
1203                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1204                 runtime->hw.rate_min = rate;
1205                 runtime->hw.rate_max = rate;
1206         }
1207         rme96_set_buffer_size_constraint(rme96, runtime);
1208
1209         rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1210         rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1211         snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1212                        SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1213         return 0;
1214 }
1215
1216 static int
1217 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1218 {
1219         int isadat, rate;
1220         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1221         struct snd_pcm_runtime *runtime = substream->runtime;
1222
1223         snd_pcm_set_sync(substream);
1224         runtime->hw = snd_rme96_capture_spdif_info;
1225         if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1226             (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1227         {
1228                 if (isadat) {
1229                         return -EIO;
1230                 }
1231                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1232                 runtime->hw.rate_min = rate;
1233                 runtime->hw.rate_max = rate;
1234         }
1235
1236         spin_lock_irq(&rme96->lock);
1237         if (rme96->capture_substream) {
1238                 spin_unlock_irq(&rme96->lock);
1239                 return -EBUSY;
1240         }
1241         rme96->capture_substream = substream;
1242         spin_unlock_irq(&rme96->lock);
1243
1244         rme96_set_buffer_size_constraint(rme96, runtime);
1245         return 0;
1246 }
1247
1248 static int
1249 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1250 {
1251         int rate, dummy;
1252         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1253         struct snd_pcm_runtime *runtime = substream->runtime;
1254
1255         snd_pcm_set_sync(substream);
1256         spin_lock_irq(&rme96->lock);
1257         if (rme96->playback_substream) {
1258                 spin_unlock_irq(&rme96->lock);
1259                 return -EBUSY;
1260         }
1261         rme96->wcreg |= RME96_WCR_ADAT;
1262         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1263         rme96->playback_substream = substream;
1264         spin_unlock_irq(&rme96->lock);
1265
1266         runtime->hw = snd_rme96_playback_adat_info;
1267         if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1268             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1269             (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1270         {
1271                 /* slave clock */
1272                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1273                 runtime->hw.rate_min = rate;
1274                 runtime->hw.rate_max = rate;
1275         }
1276         rme96_set_buffer_size_constraint(rme96, runtime);
1277         return 0;
1278 }
1279
1280 static int
1281 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1282 {
1283         int isadat, rate;
1284         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1285         struct snd_pcm_runtime *runtime = substream->runtime;
1286
1287         snd_pcm_set_sync(substream);
1288         runtime->hw = snd_rme96_capture_adat_info;
1289         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1290                 /* makes no sense to use analog input. Note that analog
1291                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1292                 return -EIO;
1293         }
1294         if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1295                 if (!isadat) {
1296                         return -EIO;
1297                 }
1298                 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1299                 runtime->hw.rate_min = rate;
1300                 runtime->hw.rate_max = rate;
1301         }
1302
1303         spin_lock_irq(&rme96->lock);
1304         if (rme96->capture_substream) {
1305                 spin_unlock_irq(&rme96->lock);
1306                 return -EBUSY;
1307         }
1308         rme96->capture_substream = substream;
1309         spin_unlock_irq(&rme96->lock);
1310
1311         rme96_set_buffer_size_constraint(rme96, runtime);
1312         return 0;
1313 }
1314
1315 static int
1316 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1317 {
1318         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1319         int spdif = 0;
1320
1321         spin_lock_irq(&rme96->lock);
1322         if (RME96_ISPLAYING(rme96)) {
1323                 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1324         }
1325         rme96->playback_substream = NULL;
1326         rme96->playback_periodsize = 0;
1327         spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1328         spin_unlock_irq(&rme96->lock);
1329         if (spdif) {
1330                 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1331                 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1332                                SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1333         }
1334         return 0;
1335 }
1336
1337 static int
1338 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1339 {
1340         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1341
1342         spin_lock_irq(&rme96->lock);
1343         if (RME96_ISRECORDING(rme96)) {
1344                 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1345         }
1346         rme96->capture_substream = NULL;
1347         rme96->capture_periodsize = 0;
1348         spin_unlock_irq(&rme96->lock);
1349         return 0;
1350 }
1351
1352 static int
1353 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1354 {
1355         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1356
1357         spin_lock_irq(&rme96->lock);
1358         if (RME96_ISPLAYING(rme96)) {
1359                 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK);
1360         }
1361         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1362         spin_unlock_irq(&rme96->lock);
1363         return 0;
1364 }
1365
1366 static int
1367 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1368 {
1369         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1370
1371         spin_lock_irq(&rme96->lock);
1372         if (RME96_ISRECORDING(rme96)) {
1373                 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE);
1374         }
1375         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1376         spin_unlock_irq(&rme96->lock);
1377         return 0;
1378 }
1379
1380 static int
1381 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1382                            int cmd)
1383 {
1384         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1385         struct snd_pcm_substream *s;
1386         bool sync;
1387
1388         snd_pcm_group_for_each_entry(s, substream) {
1389                 if (snd_pcm_substream_chip(s) == rme96)
1390                         snd_pcm_trigger_done(s, substream);
1391         }
1392
1393         sync = (rme96->playback_substream && rme96->capture_substream) &&
1394                (rme96->playback_substream->group ==
1395                 rme96->capture_substream->group);
1396
1397         switch (cmd) {
1398         case SNDRV_PCM_TRIGGER_START:
1399                 if (!RME96_ISPLAYING(rme96)) {
1400                         if (substream != rme96->playback_substream)
1401                                 return -EBUSY;
1402                         snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1403                                                  : RME96_START_PLAYBACK);
1404                 }
1405                 break;
1406
1407         case SNDRV_PCM_TRIGGER_SUSPEND:
1408         case SNDRV_PCM_TRIGGER_STOP:
1409                 if (RME96_ISPLAYING(rme96)) {
1410                         if (substream != rme96->playback_substream)
1411                                 return -EBUSY;
1412                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1413                                                  :  RME96_STOP_PLAYBACK);
1414                 }
1415                 break;
1416
1417         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1418                 if (RME96_ISPLAYING(rme96))
1419                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1420                                                  : RME96_STOP_PLAYBACK);
1421                 break;
1422
1423         case SNDRV_PCM_TRIGGER_RESUME:
1424         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1425                 if (!RME96_ISPLAYING(rme96))
1426                         snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1427                                                  : RME96_RESUME_PLAYBACK);
1428                 break;
1429
1430         default:
1431                 return -EINVAL;
1432         }
1433
1434         return 0;
1435 }
1436
1437 static int
1438 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1439                           int cmd)
1440 {
1441         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1442         struct snd_pcm_substream *s;
1443         bool sync;
1444
1445         snd_pcm_group_for_each_entry(s, substream) {
1446                 if (snd_pcm_substream_chip(s) == rme96)
1447                         snd_pcm_trigger_done(s, substream);
1448         }
1449
1450         sync = (rme96->playback_substream && rme96->capture_substream) &&
1451                (rme96->playback_substream->group ==
1452                 rme96->capture_substream->group);
1453
1454         switch (cmd) {
1455         case SNDRV_PCM_TRIGGER_START:
1456                 if (!RME96_ISRECORDING(rme96)) {
1457                         if (substream != rme96->capture_substream)
1458                                 return -EBUSY;
1459                         snd_rme96_trigger(rme96, sync ? RME96_START_BOTH
1460                                                  : RME96_START_CAPTURE);
1461                 }
1462                 break;
1463
1464         case SNDRV_PCM_TRIGGER_SUSPEND:
1465         case SNDRV_PCM_TRIGGER_STOP:
1466                 if (RME96_ISRECORDING(rme96)) {
1467                         if (substream != rme96->capture_substream)
1468                                 return -EBUSY;
1469                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1470                                                  : RME96_STOP_CAPTURE);
1471                 }
1472                 break;
1473
1474         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1475                 if (RME96_ISRECORDING(rme96))
1476                         snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH
1477                                                  : RME96_STOP_CAPTURE);
1478                 break;
1479
1480         case SNDRV_PCM_TRIGGER_RESUME:
1481         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1482                 if (!RME96_ISRECORDING(rme96))
1483                         snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH
1484                                                  : RME96_RESUME_CAPTURE);
1485                 break;
1486
1487         default:
1488                 return -EINVAL;
1489         }
1490
1491         return 0;
1492 }
1493
1494 static snd_pcm_uframes_t
1495 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1496 {
1497         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1498         return snd_rme96_playback_ptr(rme96);
1499 }
1500
1501 static snd_pcm_uframes_t
1502 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1503 {
1504         struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1505         return snd_rme96_capture_ptr(rme96);
1506 }
1507
1508 static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1509         .open =         snd_rme96_playback_spdif_open,
1510         .close =        snd_rme96_playback_close,
1511         .ioctl =        snd_pcm_lib_ioctl,
1512         .hw_params =    snd_rme96_playback_hw_params,
1513         .prepare =      snd_rme96_playback_prepare,
1514         .trigger =      snd_rme96_playback_trigger,
1515         .pointer =      snd_rme96_playback_pointer,
1516         .copy_user =    snd_rme96_playback_copy,
1517         .copy_kernel =  snd_rme96_playback_copy_kernel,
1518         .fill_silence = snd_rme96_playback_silence,
1519         .mmap =         snd_pcm_lib_mmap_iomem,
1520 };
1521
1522 static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1523         .open =         snd_rme96_capture_spdif_open,
1524         .close =        snd_rme96_capture_close,
1525         .ioctl =        snd_pcm_lib_ioctl,
1526         .hw_params =    snd_rme96_capture_hw_params,
1527         .prepare =      snd_rme96_capture_prepare,
1528         .trigger =      snd_rme96_capture_trigger,
1529         .pointer =      snd_rme96_capture_pointer,
1530         .copy_user =    snd_rme96_capture_copy,
1531         .copy_kernel =  snd_rme96_capture_copy_kernel,
1532         .mmap =         snd_pcm_lib_mmap_iomem,
1533 };
1534
1535 static const struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1536         .open =         snd_rme96_playback_adat_open,
1537         .close =        snd_rme96_playback_close,
1538         .ioctl =        snd_pcm_lib_ioctl,
1539         .hw_params =    snd_rme96_playback_hw_params,
1540         .prepare =      snd_rme96_playback_prepare,
1541         .trigger =      snd_rme96_playback_trigger,
1542         .pointer =      snd_rme96_playback_pointer,
1543         .copy_user =    snd_rme96_playback_copy,
1544         .copy_kernel =  snd_rme96_playback_copy_kernel,
1545         .fill_silence = snd_rme96_playback_silence,
1546         .mmap =         snd_pcm_lib_mmap_iomem,
1547 };
1548
1549 static const struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1550         .open =         snd_rme96_capture_adat_open,
1551         .close =        snd_rme96_capture_close,
1552         .ioctl =        snd_pcm_lib_ioctl,
1553         .hw_params =    snd_rme96_capture_hw_params,
1554         .prepare =      snd_rme96_capture_prepare,
1555         .trigger =      snd_rme96_capture_trigger,
1556         .pointer =      snd_rme96_capture_pointer,
1557         .copy_user =    snd_rme96_capture_copy,
1558         .copy_kernel =  snd_rme96_capture_copy_kernel,
1559         .mmap =         snd_pcm_lib_mmap_iomem,
1560 };
1561
1562 static void
1563 snd_rme96_free(void *private_data)
1564 {
1565         struct rme96 *rme96 = (struct rme96 *)private_data;
1566
1567         if (!rme96)
1568                 return;
1569
1570         if (rme96->irq >= 0) {
1571                 snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1572                 rme96->areg &= ~RME96_AR_DAC_EN;
1573                 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1574                 free_irq(rme96->irq, (void *)rme96);
1575                 rme96->irq = -1;
1576         }
1577         if (rme96->iobase) {
1578                 iounmap(rme96->iobase);
1579                 rme96->iobase = NULL;
1580         }
1581         if (rme96->port) {
1582                 pci_release_regions(rme96->pci);
1583                 rme96->port = 0;
1584         }
1585 #ifdef CONFIG_PM_SLEEP
1586         vfree(rme96->playback_suspend_buffer);
1587         vfree(rme96->capture_suspend_buffer);
1588 #endif
1589         pci_disable_device(rme96->pci);
1590 }
1591
1592 static void
1593 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1594 {
1595         struct rme96 *rme96 = pcm->private_data;
1596         rme96->spdif_pcm = NULL;
1597 }
1598
1599 static void
1600 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1601 {
1602         struct rme96 *rme96 = pcm->private_data;
1603         rme96->adat_pcm = NULL;
1604 }
1605
1606 static int
1607 snd_rme96_create(struct rme96 *rme96)
1608 {
1609         struct pci_dev *pci = rme96->pci;
1610         int err;
1611
1612         rme96->irq = -1;
1613         spin_lock_init(&rme96->lock);
1614
1615         if ((err = pci_enable_device(pci)) < 0)
1616                 return err;
1617
1618         if ((err = pci_request_regions(pci, "RME96")) < 0)
1619                 return err;
1620         rme96->port = pci_resource_start(rme96->pci, 0);
1621
1622         rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1623         if (!rme96->iobase) {
1624                 dev_err(rme96->card->dev,
1625                         "unable to remap memory region 0x%lx-0x%lx\n",
1626                         rme96->port, rme96->port + RME96_IO_SIZE - 1);
1627                 return -ENOMEM;
1628         }
1629
1630         if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1631                         KBUILD_MODNAME, rme96)) {
1632                 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq);
1633                 return -EBUSY;
1634         }
1635         rme96->irq = pci->irq;
1636
1637         /* read the card's revision number */
1638         pci_read_config_byte(pci, 8, &rme96->rev);
1639
1640         /* set up ALSA pcm device for S/PDIF */
1641         if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1642                                1, 1, &rme96->spdif_pcm)) < 0)
1643         {
1644                 return err;
1645         }
1646         rme96->spdif_pcm->private_data = rme96;
1647         rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1648         strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1649         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1650         snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1651
1652         rme96->spdif_pcm->info_flags = 0;
1653
1654         /* set up ALSA pcm device for ADAT */
1655         if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1656                 /* ADAT is not available on the base model */
1657                 rme96->adat_pcm = NULL;
1658         } else {
1659                 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1660                                        1, 1, &rme96->adat_pcm)) < 0)
1661                 {
1662                         return err;
1663                 }
1664                 rme96->adat_pcm->private_data = rme96;
1665                 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1666                 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1667                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1668                 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1669
1670                 rme96->adat_pcm->info_flags = 0;
1671         }
1672
1673         rme96->playback_periodsize = 0;
1674         rme96->capture_periodsize = 0;
1675
1676         /* make sure playback/capture is stopped, if by some reason active */
1677         snd_rme96_trigger(rme96, RME96_STOP_BOTH);
1678
1679         /* set default values in registers */
1680         rme96->wcreg =
1681                 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1682                 RME96_WCR_SEL |    /* normal playback */
1683                 RME96_WCR_MASTER | /* set to master clock mode */
1684                 RME96_WCR_INP_0;   /* set coaxial input */
1685
1686         rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1687
1688         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1689         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1690
1691         /* reset the ADC */
1692         writel(rme96->areg | RME96_AR_PD2,
1693                rme96->iobase + RME96_IO_ADDITIONAL_REG);
1694         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1695
1696         /* reset and enable the DAC (order is important). */
1697         snd_rme96_reset_dac(rme96);
1698         rme96->areg |= RME96_AR_DAC_EN;
1699         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1700
1701         /* reset playback and record buffer pointers */
1702         writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1703         writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1704
1705         /* reset volume */
1706         rme96->vol[0] = rme96->vol[1] = 0;
1707         if (RME96_HAS_ANALOG_OUT(rme96)) {
1708                 snd_rme96_apply_dac_volume(rme96);
1709         }
1710
1711         /* init switch interface */
1712         if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1713                 return err;
1714         }
1715
1716         /* init proc interface */
1717         snd_rme96_proc_init(rme96);
1718
1719         return 0;
1720 }
1721
1722 /*
1723  * proc interface
1724  */
1725
1726 static void
1727 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1728 {
1729         int n;
1730         struct rme96 *rme96 = entry->private_data;
1731
1732         rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1733
1734         snd_iprintf(buffer, rme96->card->longname);
1735         snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1736
1737         snd_iprintf(buffer, "\nGeneral settings\n");
1738         if (rme96->wcreg & RME96_WCR_IDIS) {
1739                 snd_iprintf(buffer, "  period size: N/A (interrupts "
1740                             "disabled)\n");
1741         } else if (rme96->wcreg & RME96_WCR_ISEL) {
1742                 snd_iprintf(buffer, "  period size: 2048 bytes\n");
1743         } else {
1744                 snd_iprintf(buffer, "  period size: 8192 bytes\n");
1745         }
1746         snd_iprintf(buffer, "\nInput settings\n");
1747         switch (snd_rme96_getinputtype(rme96)) {
1748         case RME96_INPUT_OPTICAL:
1749                 snd_iprintf(buffer, "  input: optical");
1750                 break;
1751         case RME96_INPUT_COAXIAL:
1752                 snd_iprintf(buffer, "  input: coaxial");
1753                 break;
1754         case RME96_INPUT_INTERNAL:
1755                 snd_iprintf(buffer, "  input: internal");
1756                 break;
1757         case RME96_INPUT_XLR:
1758                 snd_iprintf(buffer, "  input: XLR");
1759                 break;
1760         case RME96_INPUT_ANALOG:
1761                 snd_iprintf(buffer, "  input: analog");
1762                 break;
1763         }
1764         if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1765                 snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1766         } else {
1767                 if (n) {
1768                         snd_iprintf(buffer, " (8 channels)\n");
1769                 } else {
1770                         snd_iprintf(buffer, " (2 channels)\n");
1771                 }
1772                 snd_iprintf(buffer, "  sample rate: %d Hz\n",
1773                             snd_rme96_capture_getrate(rme96, &n));
1774         }
1775         if (rme96->wcreg & RME96_WCR_MODE24_2) {
1776                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1777         } else {
1778                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1779         }
1780
1781         snd_iprintf(buffer, "\nOutput settings\n");
1782         if (rme96->wcreg & RME96_WCR_SEL) {
1783                 snd_iprintf(buffer, "  output signal: normal playback\n");
1784         } else {
1785                 snd_iprintf(buffer, "  output signal: same as input\n");
1786         }
1787         snd_iprintf(buffer, "  sample rate: %d Hz\n",
1788                     snd_rme96_playback_getrate(rme96));
1789         if (rme96->wcreg & RME96_WCR_MODE24) {
1790                 snd_iprintf(buffer, "  sample format: 24 bit\n");
1791         } else {
1792                 snd_iprintf(buffer, "  sample format: 16 bit\n");
1793         }
1794         if (rme96->areg & RME96_AR_WSEL) {
1795                 snd_iprintf(buffer, "  sample clock source: word clock\n");
1796         } else if (rme96->wcreg & RME96_WCR_MASTER) {
1797                 snd_iprintf(buffer, "  sample clock source: internal\n");
1798         } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1799                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1800         } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1801                 snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1802         } else {
1803                 snd_iprintf(buffer, "  sample clock source: autosync\n");
1804         }
1805         if (rme96->wcreg & RME96_WCR_PRO) {
1806                 snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1807         } else {
1808                 snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1809         }
1810         if (rme96->wcreg & RME96_WCR_EMP) {
1811                 snd_iprintf(buffer, "  emphasis: on\n");
1812         } else {
1813                 snd_iprintf(buffer, "  emphasis: off\n");
1814         }
1815         if (rme96->wcreg & RME96_WCR_DOLBY) {
1816                 snd_iprintf(buffer, "  non-audio (dolby): on\n");
1817         } else {
1818                 snd_iprintf(buffer, "  non-audio (dolby): off\n");
1819         }
1820         if (RME96_HAS_ANALOG_IN(rme96)) {
1821                 snd_iprintf(buffer, "\nAnalog output settings\n");
1822                 switch (snd_rme96_getmontracks(rme96)) {
1823                 case RME96_MONITOR_TRACKS_1_2:
1824                         snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1825                         break;
1826                 case RME96_MONITOR_TRACKS_3_4:
1827                         snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1828                         break;
1829                 case RME96_MONITOR_TRACKS_5_6:
1830                         snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1831                         break;
1832                 case RME96_MONITOR_TRACKS_7_8:
1833                         snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1834                         break;
1835                 }
1836                 switch (snd_rme96_getattenuation(rme96)) {
1837                 case RME96_ATTENUATION_0:
1838                         snd_iprintf(buffer, "  attenuation: 0 dB\n");
1839                         break;
1840                 case RME96_ATTENUATION_6:
1841                         snd_iprintf(buffer, "  attenuation: -6 dB\n");
1842                         break;
1843                 case RME96_ATTENUATION_12:
1844                         snd_iprintf(buffer, "  attenuation: -12 dB\n");
1845                         break;
1846                 case RME96_ATTENUATION_18:
1847                         snd_iprintf(buffer, "  attenuation: -18 dB\n");
1848                         break;
1849                 }
1850                 snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1851                 snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1852         }
1853 }
1854
1855 static void snd_rme96_proc_init(struct rme96 *rme96)
1856 {
1857         snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read);
1858 }
1859
1860 /*
1861  * control interface
1862  */
1863
1864 #define snd_rme96_info_loopback_control         snd_ctl_boolean_mono_info
1865
1866 static int
1867 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1868 {
1869         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1870
1871         spin_lock_irq(&rme96->lock);
1872         ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1873         spin_unlock_irq(&rme96->lock);
1874         return 0;
1875 }
1876 static int
1877 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1878 {
1879         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1880         unsigned int val;
1881         int change;
1882
1883         val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1884         spin_lock_irq(&rme96->lock);
1885         val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1886         change = val != rme96->wcreg;
1887         rme96->wcreg = val;
1888         writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1889         spin_unlock_irq(&rme96->lock);
1890         return change;
1891 }
1892
1893 static int
1894 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1895 {
1896         static const char * const _texts[5] = {
1897                 "Optical", "Coaxial", "Internal", "XLR", "Analog"
1898         };
1899         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1900         const char *texts[5] = {
1901                 _texts[0], _texts[1], _texts[2], _texts[3], _texts[4]
1902         };
1903         int num_items;
1904
1905         switch (rme96->pci->device) {
1906         case PCI_DEVICE_ID_RME_DIGI96:
1907         case PCI_DEVICE_ID_RME_DIGI96_8:
1908                 num_items = 3;
1909                 break;
1910         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1911                 num_items = 4;
1912                 break;
1913         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1914                 if (rme96->rev > 4) {
1915                         /* PST */
1916                         num_items = 4;
1917                         texts[3] = _texts[4]; /* Analog instead of XLR */
1918                 } else {
1919                         /* PAD */
1920                         num_items = 5;
1921                 }
1922                 break;
1923         default:
1924                 snd_BUG();
1925                 return -EINVAL;
1926         }
1927         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1928 }
1929 static int
1930 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1931 {
1932         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1933         unsigned int items = 3;
1934
1935         spin_lock_irq(&rme96->lock);
1936         ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1937
1938         switch (rme96->pci->device) {
1939         case PCI_DEVICE_ID_RME_DIGI96:
1940         case PCI_DEVICE_ID_RME_DIGI96_8:
1941                 items = 3;
1942                 break;
1943         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1944                 items = 4;
1945                 break;
1946         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1947                 if (rme96->rev > 4) {
1948                         /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1949                         if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1950                                 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1951                         }
1952                         items = 4;
1953                 } else {
1954                         items = 5;
1955                 }
1956                 break;
1957         default:
1958                 snd_BUG();
1959                 break;
1960         }
1961         if (ucontrol->value.enumerated.item[0] >= items) {
1962                 ucontrol->value.enumerated.item[0] = items - 1;
1963         }
1964
1965         spin_unlock_irq(&rme96->lock);
1966         return 0;
1967 }
1968 static int
1969 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1970 {
1971         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1972         unsigned int val;
1973         int change, items = 3;
1974
1975         switch (rme96->pci->device) {
1976         case PCI_DEVICE_ID_RME_DIGI96:
1977         case PCI_DEVICE_ID_RME_DIGI96_8:
1978                 items = 3;
1979                 break;
1980         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1981                 items = 4;
1982                 break;
1983         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1984                 if (rme96->rev > 4) {
1985                         items = 4;
1986                 } else {
1987                         items = 5;
1988                 }
1989                 break;
1990         default:
1991                 snd_BUG();
1992                 break;
1993         }
1994         val = ucontrol->value.enumerated.item[0] % items;
1995
1996         /* special case for PST */
1997         if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1998                 if (val == RME96_INPUT_XLR) {
1999                         val = RME96_INPUT_ANALOG;
2000                 }
2001         }
2002
2003         spin_lock_irq(&rme96->lock);
2004         change = (int)val != snd_rme96_getinputtype(rme96);
2005         snd_rme96_setinputtype(rme96, val);
2006         spin_unlock_irq(&rme96->lock);
2007         return change;
2008 }
2009
2010 static int
2011 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2012 {
2013         static const char * const texts[3] = { "AutoSync", "Internal", "Word" };
2014
2015         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2016 }
2017 static int
2018 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2019 {
2020         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2021
2022         spin_lock_irq(&rme96->lock);
2023         ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2024         spin_unlock_irq(&rme96->lock);
2025         return 0;
2026 }
2027 static int
2028 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2029 {
2030         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2031         unsigned int val;
2032         int change;
2033
2034         val = ucontrol->value.enumerated.item[0] % 3;
2035         spin_lock_irq(&rme96->lock);
2036         change = (int)val != snd_rme96_getclockmode(rme96);
2037         snd_rme96_setclockmode(rme96, val);
2038         spin_unlock_irq(&rme96->lock);
2039         return change;
2040 }
2041
2042 static int
2043 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2044 {
2045         static const char * const texts[4] = {
2046                 "0 dB", "-6 dB", "-12 dB", "-18 dB"
2047         };
2048
2049         return snd_ctl_enum_info(uinfo, 1, 4, texts);
2050 }
2051 static int
2052 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2053 {
2054         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2055
2056         spin_lock_irq(&rme96->lock);
2057         ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2058         spin_unlock_irq(&rme96->lock);
2059         return 0;
2060 }
2061 static int
2062 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2063 {
2064         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2065         unsigned int val;
2066         int change;
2067
2068         val = ucontrol->value.enumerated.item[0] % 4;
2069         spin_lock_irq(&rme96->lock);
2070
2071         change = (int)val != snd_rme96_getattenuation(rme96);
2072         snd_rme96_setattenuation(rme96, val);
2073         spin_unlock_irq(&rme96->lock);
2074         return change;
2075 }
2076
2077 static int
2078 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2079 {
2080         static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2081
2082         return snd_ctl_enum_info(uinfo, 1, 4, texts);
2083 }
2084 static int
2085 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2086 {
2087         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2088
2089         spin_lock_irq(&rme96->lock);
2090         ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2091         spin_unlock_irq(&rme96->lock);
2092         return 0;
2093 }
2094 static int
2095 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2096 {
2097         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2098         unsigned int val;
2099         int change;
2100
2101         val = ucontrol->value.enumerated.item[0] % 4;
2102         spin_lock_irq(&rme96->lock);
2103         change = (int)val != snd_rme96_getmontracks(rme96);
2104         snd_rme96_setmontracks(rme96, val);
2105         spin_unlock_irq(&rme96->lock);
2106         return change;
2107 }
2108
2109 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2110 {
2111         u32 val = 0;
2112         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2113         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2114         if (val & RME96_WCR_PRO)
2115                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2116         else
2117                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2118         return val;
2119 }
2120
2121 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2122 {
2123         aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2124                          ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2125         if (val & RME96_WCR_PRO)
2126                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2127         else
2128                 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2129 }
2130
2131 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2132 {
2133         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2134         uinfo->count = 1;
2135         return 0;
2136 }
2137
2138 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2139 {
2140         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2141
2142         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2143         return 0;
2144 }
2145
2146 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2147 {
2148         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2149         int change;
2150         u32 val;
2151
2152         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2153         spin_lock_irq(&rme96->lock);
2154         change = val != rme96->wcreg_spdif;
2155         rme96->wcreg_spdif = val;
2156         spin_unlock_irq(&rme96->lock);
2157         return change;
2158 }
2159
2160 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2161 {
2162         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2163         uinfo->count = 1;
2164         return 0;
2165 }
2166
2167 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2168 {
2169         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2170
2171         snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2172         return 0;
2173 }
2174
2175 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2176 {
2177         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2178         int change;
2179         u32 val;
2180
2181         val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2182         spin_lock_irq(&rme96->lock);
2183         change = val != rme96->wcreg_spdif_stream;
2184         rme96->wcreg_spdif_stream = val;
2185         rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2186         rme96->wcreg |= val;
2187         writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2188         spin_unlock_irq(&rme96->lock);
2189         return change;
2190 }
2191
2192 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2193 {
2194         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2195         uinfo->count = 1;
2196         return 0;
2197 }
2198
2199 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2200 {
2201         ucontrol->value.iec958.status[0] = kcontrol->private_value;
2202         return 0;
2203 }
2204
2205 static int
2206 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2207 {
2208         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2209
2210         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2211         uinfo->count = 2;
2212         uinfo->value.integer.min = 0;
2213         uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2214         return 0;
2215 }
2216
2217 static int
2218 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2219 {
2220         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2221
2222         spin_lock_irq(&rme96->lock);
2223         u->value.integer.value[0] = rme96->vol[0];
2224         u->value.integer.value[1] = rme96->vol[1];
2225         spin_unlock_irq(&rme96->lock);
2226
2227         return 0;
2228 }
2229
2230 static int
2231 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2232 {
2233         struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2234         int change = 0;
2235         unsigned int vol, maxvol;
2236
2237
2238         if (!RME96_HAS_ANALOG_OUT(rme96))
2239                 return -EINVAL;
2240         maxvol = RME96_185X_MAX_OUT(rme96);
2241         spin_lock_irq(&rme96->lock);
2242         vol = u->value.integer.value[0];
2243         if (vol != rme96->vol[0] && vol <= maxvol) {
2244                 rme96->vol[0] = vol;
2245                 change = 1;
2246         }
2247         vol = u->value.integer.value[1];
2248         if (vol != rme96->vol[1] && vol <= maxvol) {
2249                 rme96->vol[1] = vol;
2250                 change = 1;
2251         }
2252         if (change)
2253                 snd_rme96_apply_dac_volume(rme96);
2254         spin_unlock_irq(&rme96->lock);
2255
2256         return change;
2257 }
2258
2259 static struct snd_kcontrol_new snd_rme96_controls[] = {
2260 {
2261         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2262         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2263         .info =         snd_rme96_control_spdif_info,
2264         .get =          snd_rme96_control_spdif_get,
2265         .put =          snd_rme96_control_spdif_put
2266 },
2267 {
2268         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2269         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2270         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2271         .info =         snd_rme96_control_spdif_stream_info,
2272         .get =          snd_rme96_control_spdif_stream_get,
2273         .put =          snd_rme96_control_spdif_stream_put
2274 },
2275 {
2276         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2277         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2278         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2279         .info =         snd_rme96_control_spdif_mask_info,
2280         .get =          snd_rme96_control_spdif_mask_get,
2281         .private_value = IEC958_AES0_NONAUDIO |
2282                         IEC958_AES0_PROFESSIONAL |
2283                         IEC958_AES0_CON_EMPHASIS
2284 },
2285 {
2286         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2287         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2288         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2289         .info =         snd_rme96_control_spdif_mask_info,
2290         .get =          snd_rme96_control_spdif_mask_get,
2291         .private_value = IEC958_AES0_NONAUDIO |
2292                         IEC958_AES0_PROFESSIONAL |
2293                         IEC958_AES0_PRO_EMPHASIS
2294 },
2295 {
2296         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2297         .name =         "Input Connector",
2298         .info =         snd_rme96_info_inputtype_control,
2299         .get =          snd_rme96_get_inputtype_control,
2300         .put =          snd_rme96_put_inputtype_control
2301 },
2302 {
2303         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2304         .name =         "Loopback Input",
2305         .info =         snd_rme96_info_loopback_control,
2306         .get =          snd_rme96_get_loopback_control,
2307         .put =          snd_rme96_put_loopback_control
2308 },
2309 {
2310         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2311         .name =         "Sample Clock Source",
2312         .info =         snd_rme96_info_clockmode_control,
2313         .get =          snd_rme96_get_clockmode_control,
2314         .put =          snd_rme96_put_clockmode_control
2315 },
2316 {
2317         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2318         .name =         "Monitor Tracks",
2319         .info =         snd_rme96_info_montracks_control,
2320         .get =          snd_rme96_get_montracks_control,
2321         .put =          snd_rme96_put_montracks_control
2322 },
2323 {
2324         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2325         .name =         "Attenuation",
2326         .info =         snd_rme96_info_attenuation_control,
2327         .get =          snd_rme96_get_attenuation_control,
2328         .put =          snd_rme96_put_attenuation_control
2329 },
2330 {
2331         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2332         .name =         "DAC Playback Volume",
2333         .info =         snd_rme96_dac_volume_info,
2334         .get =          snd_rme96_dac_volume_get,
2335         .put =          snd_rme96_dac_volume_put
2336 }
2337 };
2338
2339 static int
2340 snd_rme96_create_switches(struct snd_card *card,
2341                           struct rme96 *rme96)
2342 {
2343         int idx, err;
2344         struct snd_kcontrol *kctl;
2345
2346         for (idx = 0; idx < 7; idx++) {
2347                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2348                         return err;
2349                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
2350                         rme96->spdif_ctl = kctl;
2351         }
2352
2353         if (RME96_HAS_ANALOG_OUT(rme96)) {
2354                 for (idx = 7; idx < 10; idx++)
2355                         if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2356                                 return err;
2357         }
2358
2359         return 0;
2360 }
2361
2362 /*
2363  * Card initialisation
2364  */
2365
2366 #ifdef CONFIG_PM_SLEEP
2367
2368 static int rme96_suspend(struct device *dev)
2369 {
2370         struct snd_card *card = dev_get_drvdata(dev);
2371         struct rme96 *rme96 = card->private_data;
2372
2373         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2374
2375         /* save capture & playback pointers */
2376         rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2377                                   & RME96_RCR_AUDIO_ADDR_MASK;
2378         rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2379                                  & RME96_RCR_AUDIO_ADDR_MASK;
2380
2381         /* save playback and capture buffers */
2382         memcpy_fromio(rme96->playback_suspend_buffer,
2383                       rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2384         memcpy_fromio(rme96->capture_suspend_buffer,
2385                       rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2386
2387         /* disable the DAC  */
2388         rme96->areg &= ~RME96_AR_DAC_EN;
2389         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2390         return 0;
2391 }
2392
2393 static int rme96_resume(struct device *dev)
2394 {
2395         struct snd_card *card = dev_get_drvdata(dev);
2396         struct rme96 *rme96 = card->private_data;
2397
2398         /* reset playback and record buffer pointers */
2399         writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2400                   + rme96->playback_pointer);
2401         writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2402                   + rme96->capture_pointer);
2403
2404         /* restore playback and capture buffers */
2405         memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2406                     rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2407         memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2408                     rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2409
2410         /* reset the ADC */
2411         writel(rme96->areg | RME96_AR_PD2,
2412                rme96->iobase + RME96_IO_ADDITIONAL_REG);
2413         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2414
2415         /* reset and enable DAC, restore analog volume */
2416         snd_rme96_reset_dac(rme96);
2417         rme96->areg |= RME96_AR_DAC_EN;
2418         writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2419         if (RME96_HAS_ANALOG_OUT(rme96)) {
2420                 usleep_range(3000, 10000);
2421                 snd_rme96_apply_dac_volume(rme96);
2422         }
2423
2424         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2425
2426         return 0;
2427 }
2428
2429 static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume);
2430 #define RME96_PM_OPS    &rme96_pm
2431 #else
2432 #define RME96_PM_OPS    NULL
2433 #endif /* CONFIG_PM_SLEEP */
2434
2435 static void snd_rme96_card_free(struct snd_card *card)
2436 {
2437         snd_rme96_free(card->private_data);
2438 }
2439
2440 static int
2441 snd_rme96_probe(struct pci_dev *pci,
2442                 const struct pci_device_id *pci_id)
2443 {
2444         static int dev;
2445         struct rme96 *rme96;
2446         struct snd_card *card;
2447         int err;
2448         u8 val;
2449
2450         if (dev >= SNDRV_CARDS) {
2451                 return -ENODEV;
2452         }
2453         if (!enable[dev]) {
2454                 dev++;
2455                 return -ENOENT;
2456         }
2457         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2458                            sizeof(struct rme96), &card);
2459         if (err < 0)
2460                 return err;
2461         card->private_free = snd_rme96_card_free;
2462         rme96 = card->private_data;
2463         rme96->card = card;
2464         rme96->pci = pci;
2465         err = snd_rme96_create(rme96);
2466         if (err)
2467                 goto free_card;
2468
2469 #ifdef CONFIG_PM_SLEEP
2470         rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2471         if (!rme96->playback_suspend_buffer) {
2472                 err = -ENOMEM;
2473                 goto free_card;
2474         }
2475         rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2476         if (!rme96->capture_suspend_buffer) {
2477                 err = -ENOMEM;
2478                 goto free_card;
2479         }
2480 #endif
2481
2482         strcpy(card->driver, "Digi96");
2483         switch (rme96->pci->device) {
2484         case PCI_DEVICE_ID_RME_DIGI96:
2485                 strcpy(card->shortname, "RME Digi96");
2486                 break;
2487         case PCI_DEVICE_ID_RME_DIGI96_8:
2488                 strcpy(card->shortname, "RME Digi96/8");
2489                 break;
2490         case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2491                 strcpy(card->shortname, "RME Digi96/8 PRO");
2492                 break;
2493         case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2494                 pci_read_config_byte(rme96->pci, 8, &val);
2495                 if (val < 5) {
2496                         strcpy(card->shortname, "RME Digi96/8 PAD");
2497                 } else {
2498                         strcpy(card->shortname, "RME Digi96/8 PST");
2499                 }
2500                 break;
2501         }
2502         sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2503                 rme96->port, rme96->irq);
2504         err = snd_card_register(card);
2505         if (err)
2506                 goto free_card;
2507
2508         pci_set_drvdata(pci, card);
2509         dev++;
2510         return 0;
2511 free_card:
2512         snd_card_free(card);
2513         return err;
2514 }
2515
2516 static void snd_rme96_remove(struct pci_dev *pci)
2517 {
2518         snd_card_free(pci_get_drvdata(pci));
2519 }
2520
2521 static struct pci_driver rme96_driver = {
2522         .name = KBUILD_MODNAME,
2523         .id_table = snd_rme96_ids,
2524         .probe = snd_rme96_probe,
2525         .remove = snd_rme96_remove,
2526         .driver = {
2527                 .pm = RME96_PM_OPS,
2528         },
2529 };
2530
2531 module_pci_driver(rme96_driver);