1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
13 * Wu Fengguang <wfg@linux.intel.com>
16 * Wu Fengguang <wfg@linux.intel.com>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/asoundef.h>
28 #include <sound/tlv.h>
29 #include <sound/hdaudio.h>
30 #include <sound/hda_i915.h>
31 #include <sound/hda_chmap.h>
32 #include <sound/hda_codec.h>
33 #include "hda_local.h"
35 #include "hda_controller.h"
37 static bool static_hdmi_pcm;
38 module_param(static_hdmi_pcm, bool, 0644);
39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
41 static bool enable_acomp = true;
42 module_param(enable_acomp, bool, 0444);
43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
45 static bool enable_silent_stream =
46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47 module_param(enable_silent_stream, bool, 0644);
48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
50 static bool enable_all_pins;
51 module_param(enable_all_pins, bool, 0444);
52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins");
54 struct hdmi_spec_per_cvt {
57 unsigned int channels_min;
58 unsigned int channels_max;
64 /* max. connections to a widget */
65 #define HDA_MAX_CONNECTIONS 32
67 struct hdmi_spec_per_pin {
70 /* pin idx, different device entries on the same pin use the same idx */
73 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
77 struct hda_codec *codec;
78 struct hdmi_eld sink_eld;
80 struct delayed_work work;
81 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
82 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
84 bool setup; /* the stream has been set up by prepare callback */
86 int channels; /* current number of channels */
88 bool chmap_set; /* channel-map override by ALSA API? */
89 unsigned char chmap[8]; /* ALSA API channel-map */
90 #ifdef CONFIG_SND_PROC_FS
91 struct snd_info_entry *proc_entry;
95 /* operations used by generic code that can be overridden by patches */
97 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
98 int dev_id, unsigned char *buf, int *eld_size);
100 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int ca, int active_channels, int conn_type);
104 /* enable/disable HBR (HD passthrough) */
105 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
106 int dev_id, bool hbr);
108 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
109 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
112 void (*pin_cvt_fixup)(struct hda_codec *codec,
113 struct hdmi_spec_per_pin *per_pin,
119 struct snd_jack *jack;
120 struct snd_kcontrol *eld_ctl;
124 SILENT_STREAM_OFF = 0,
125 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
126 SILENT_STREAM_I915, /* Intel i915 extension */
130 struct hda_codec *codec;
132 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
133 hda_nid_t cvt_nids[4]; /* only for haswell fix */
136 * num_pins is the number of virtual pins
137 * for example, there are 3 pins, and each pin
138 * has 4 device entries, then the num_pins is 12
142 * num_nids is the number of real pins
143 * In the above example, num_nids is 3
147 * dev_num is the number of device entries
149 * In the above example, dev_num is 4
152 struct snd_array pins; /* struct hdmi_spec_per_pin */
153 struct hdmi_pcm pcm_rec[16];
154 struct mutex pcm_lock;
155 struct mutex bind_lock; /* for audio component binding */
156 /* pcm_bitmap means which pcms have been assigned to pins*/
157 unsigned long pcm_bitmap;
158 int pcm_used; /* counter of pcm_rec[] */
159 /* bitmap shows whether the pcm is opened in user space
160 * bit 0 means the first playback PCM (PCM3);
161 * bit 1 means the second playback PCM, and so on.
163 unsigned long pcm_in_use;
165 struct hdmi_eld temp_eld;
170 bool dyn_pcm_no_legacy;
171 /* hdmi interrupt trigger control flag for Nvidia codec */
172 bool hdmi_intr_trig_ctrl;
173 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
175 * Non-generic VIA/NVIDIA specific
177 struct hda_multi_out multiout;
178 struct hda_pcm_stream pcm_playback;
180 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
181 bool acomp_registered; /* audio component registered in this driver */
182 bool force_connect; /* force connectivity */
183 struct drm_audio_component_audio_ops drm_audio_ops;
184 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
186 struct hdac_chmap chmap;
187 hda_nid_t vendor_nid;
190 int silent_stream_type;
193 #ifdef CONFIG_SND_HDA_COMPONENT
194 static inline bool codec_has_acomp(struct hda_codec *codec)
196 struct hdmi_spec *spec = codec->spec;
197 return spec->use_acomp_notifier;
200 #define codec_has_acomp(codec) false
203 struct hdmi_audio_infoframe {
210 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
214 u8 LFEPBL01_LSV36_DM_INH7;
217 struct dp_audio_infoframe {
220 u8 ver; /* 0x11 << 2 */
222 u8 CC02_CT47; /* match with HDMI infoframe from this on */
226 u8 LFEPBL01_LSV36_DM_INH7;
229 union audio_infoframe {
230 struct hdmi_audio_infoframe hdmi;
231 struct dp_audio_infoframe dp;
239 #define get_pin(spec, idx) \
240 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
241 #define get_cvt(spec, idx) \
242 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
243 /* obtain hdmi_pcm object assigned to idx */
244 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
245 /* obtain hda_pcm object assigned to idx */
246 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
248 static int pin_id_to_pin_index(struct hda_codec *codec,
249 hda_nid_t pin_nid, int dev_id)
251 struct hdmi_spec *spec = codec->spec;
253 struct hdmi_spec_per_pin *per_pin;
256 * (dev_id == -1) means it is NON-MST pin
257 * return the first virtual pin on this port
262 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
263 per_pin = get_pin(spec, pin_idx);
264 if ((per_pin->pin_nid == pin_nid) &&
265 (per_pin->dev_id == dev_id))
269 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid);
273 static int hinfo_to_pcm_index(struct hda_codec *codec,
274 struct hda_pcm_stream *hinfo)
276 struct hdmi_spec *spec = codec->spec;
279 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
280 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
283 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
287 static int hinfo_to_pin_index(struct hda_codec *codec,
288 struct hda_pcm_stream *hinfo)
290 struct hdmi_spec *spec = codec->spec;
291 struct hdmi_spec_per_pin *per_pin;
294 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
295 per_pin = get_pin(spec, pin_idx);
297 per_pin->pcm->pcm->stream == hinfo)
301 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
302 hinfo_to_pcm_index(codec, hinfo));
306 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
310 struct hdmi_spec_per_pin *per_pin;
312 for (i = 0; i < spec->num_pins; i++) {
313 per_pin = get_pin(spec, i);
314 if (per_pin->pcm_idx == pcm_idx)
320 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
322 struct hdmi_spec *spec = codec->spec;
325 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
326 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
329 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid);
333 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
334 struct snd_ctl_elem_info *uinfo)
336 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
337 struct hdmi_spec *spec = codec->spec;
338 struct hdmi_spec_per_pin *per_pin;
339 struct hdmi_eld *eld;
342 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
344 pcm_idx = kcontrol->private_value;
345 mutex_lock(&spec->pcm_lock);
346 per_pin = pcm_idx_to_pin(spec, pcm_idx);
348 /* no pin is bound to the pcm */
352 eld = &per_pin->sink_eld;
353 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
356 mutex_unlock(&spec->pcm_lock);
360 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
361 struct snd_ctl_elem_value *ucontrol)
363 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
364 struct hdmi_spec *spec = codec->spec;
365 struct hdmi_spec_per_pin *per_pin;
366 struct hdmi_eld *eld;
370 pcm_idx = kcontrol->private_value;
371 mutex_lock(&spec->pcm_lock);
372 per_pin = pcm_idx_to_pin(spec, pcm_idx);
374 /* no pin is bound to the pcm */
375 memset(ucontrol->value.bytes.data, 0,
376 ARRAY_SIZE(ucontrol->value.bytes.data));
380 eld = &per_pin->sink_eld;
381 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
382 eld->eld_size > ELD_MAX_SIZE) {
388 memset(ucontrol->value.bytes.data, 0,
389 ARRAY_SIZE(ucontrol->value.bytes.data));
391 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
395 mutex_unlock(&spec->pcm_lock);
399 static const struct snd_kcontrol_new eld_bytes_ctl = {
400 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
401 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
402 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
404 .info = hdmi_eld_ctl_info,
405 .get = hdmi_eld_ctl_get,
408 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
411 struct snd_kcontrol *kctl;
412 struct hdmi_spec *spec = codec->spec;
415 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
418 kctl->private_value = pcm_idx;
419 kctl->id.device = device;
421 /* no pin nid is associated with the kctl now
422 * tbd: associate pin nid to eld ctl later
424 err = snd_hda_ctl_add(codec, 0, kctl);
428 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
433 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
434 int *packet_index, int *byte_index)
438 val = snd_hda_codec_read(codec, pin_nid, 0,
439 AC_VERB_GET_HDMI_DIP_INDEX, 0);
441 *packet_index = val >> 5;
442 *byte_index = val & 0x1f;
446 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
447 int packet_index, int byte_index)
451 val = (packet_index << 5) | (byte_index & 0x1f);
453 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
456 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
459 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
462 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
464 struct hdmi_spec *spec = codec->spec;
468 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
469 snd_hda_codec_write(codec, pin_nid, 0,
470 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
472 if (spec->dyn_pin_out)
473 /* Disable pin out until stream is active */
476 /* Enable pin out: some machines with GM965 gets broken output
477 * when the pin is disabled or changed while using with HDMI
481 snd_hda_codec_write(codec, pin_nid, 0,
482 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
489 #ifdef CONFIG_SND_PROC_FS
490 static void print_eld_info(struct snd_info_entry *entry,
491 struct snd_info_buffer *buffer)
493 struct hdmi_spec_per_pin *per_pin = entry->private_data;
495 mutex_lock(&per_pin->lock);
496 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
497 mutex_unlock(&per_pin->lock);
500 static void write_eld_info(struct snd_info_entry *entry,
501 struct snd_info_buffer *buffer)
503 struct hdmi_spec_per_pin *per_pin = entry->private_data;
505 mutex_lock(&per_pin->lock);
506 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
507 mutex_unlock(&per_pin->lock);
510 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
513 struct hda_codec *codec = per_pin->codec;
514 struct snd_info_entry *entry;
517 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
518 err = snd_card_proc_new(codec->card, name, &entry);
522 snd_info_set_text_ops(entry, per_pin, print_eld_info);
523 entry->c.text.write = write_eld_info;
525 per_pin->proc_entry = entry;
530 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
532 if (!per_pin->codec->bus->shutdown) {
533 snd_info_free_entry(per_pin->proc_entry);
534 per_pin->proc_entry = NULL;
538 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
543 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
549 * Audio InfoFrame routines
553 * Enable Audio InfoFrame Transmission
555 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
558 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
559 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
564 * Disable Audio InfoFrame Transmission
566 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
569 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
570 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
574 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
576 #ifdef CONFIG_SND_DEBUG_VERBOSE
580 size = snd_hdmi_get_eld_size(codec, pin_nid);
581 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
583 for (i = 0; i < 8; i++) {
584 size = snd_hda_codec_read(codec, pin_nid, 0,
585 AC_VERB_GET_HDMI_DIP_SIZE, i);
586 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
591 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
597 for (i = 0; i < 8; i++) {
598 size = snd_hda_codec_read(codec, pin_nid, 0,
599 AC_VERB_GET_HDMI_DIP_SIZE, i);
603 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
604 for (j = 1; j < 1000; j++) {
605 hdmi_write_dip_byte(codec, pin_nid, 0x0);
606 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
608 codec_dbg(codec, "dip index %d: %d != %d\n",
610 if (bi == 0) /* byte index wrapped around */
614 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
620 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
622 u8 *bytes = (u8 *)hdmi_ai;
626 hdmi_ai->checksum = 0;
628 for (i = 0; i < sizeof(*hdmi_ai); i++)
631 hdmi_ai->checksum = -sum;
634 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
640 hdmi_debug_dip_size(codec, pin_nid);
641 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
643 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
644 for (i = 0; i < size; i++)
645 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
648 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
654 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
655 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
659 for (i = 0; i < size; i++) {
660 val = snd_hda_codec_read(codec, pin_nid, 0,
661 AC_VERB_GET_HDMI_DIP_DATA, 0);
669 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
670 int dev_id, unsigned char *buf, int *eld_size)
672 snd_hda_set_dev_select(codec, nid, dev_id);
674 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
677 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
678 hda_nid_t pin_nid, int dev_id,
679 int ca, int active_channels,
682 union audio_infoframe ai;
684 memset(&ai, 0, sizeof(ai));
685 if (conn_type == 0) { /* HDMI */
686 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
688 hdmi_ai->type = 0x84;
691 hdmi_ai->CC02_CT47 = active_channels - 1;
693 hdmi_checksum_audio_infoframe(hdmi_ai);
694 } else if (conn_type == 1) { /* DisplayPort */
695 struct dp_audio_infoframe *dp_ai = &ai.dp;
699 dp_ai->ver = 0x11 << 2;
700 dp_ai->CC02_CT47 = active_channels - 1;
703 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid);
707 snd_hda_set_dev_select(codec, pin_nid, dev_id);
710 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
711 * sizeof(*dp_ai) to avoid partial match/update problems when
712 * the user switches between HDMI/DP monitors.
714 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
716 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n",
717 __func__, pin_nid, active_channels, ca);
718 hdmi_stop_infoframe_trans(codec, pin_nid);
719 hdmi_fill_audio_infoframe(codec, pin_nid,
720 ai.bytes, sizeof(ai));
721 hdmi_start_infoframe_trans(codec, pin_nid);
725 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
726 struct hdmi_spec_per_pin *per_pin,
729 struct hdmi_spec *spec = codec->spec;
730 struct hdac_chmap *chmap = &spec->chmap;
731 hda_nid_t pin_nid = per_pin->pin_nid;
732 int dev_id = per_pin->dev_id;
733 int channels = per_pin->channels;
735 struct hdmi_eld *eld;
741 snd_hda_set_dev_select(codec, pin_nid, dev_id);
743 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
744 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
745 snd_hda_codec_write(codec, pin_nid, 0,
746 AC_VERB_SET_AMP_GAIN_MUTE,
749 eld = &per_pin->sink_eld;
751 ca = snd_hdac_channel_allocation(&codec->core,
752 eld->info.spk_alloc, channels,
753 per_pin->chmap_set, non_pcm, per_pin->chmap);
755 active_channels = snd_hdac_get_active_channels(ca);
757 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
761 * always configure channel mapping, it may have been changed by the
762 * user in the meantime
764 snd_hdac_setup_channel_mapping(&spec->chmap,
765 pin_nid, non_pcm, ca, channels,
766 per_pin->chmap, per_pin->chmap_set);
768 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
769 ca, active_channels, eld->info.conn_type);
771 per_pin->non_pcm = non_pcm;
778 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
780 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
783 struct hdmi_spec *spec = codec->spec;
784 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
788 mutex_lock(&spec->pcm_lock);
789 hdmi_present_sense(get_pin(spec, pin_idx), 1);
790 mutex_unlock(&spec->pcm_lock);
793 static void jack_callback(struct hda_codec *codec,
794 struct hda_jack_callback *jack)
796 /* stop polling when notification is enabled */
797 if (codec_has_acomp(codec))
800 check_presence_and_report(codec, jack->nid, jack->dev_id);
803 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
804 struct hda_jack_tbl *jack)
806 jack->jack_dirty = 1;
809 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
810 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
811 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
813 check_presence_and_report(codec, jack->nid, jack->dev_id);
816 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
818 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
819 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
820 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
821 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
824 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
841 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
843 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
844 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
845 struct hda_jack_tbl *jack;
847 if (codec_has_acomp(codec))
852 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
854 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
856 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
860 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
865 hdmi_intrinsic_event(codec, res, jack);
867 hdmi_non_intrinsic_event(codec, res);
870 static void haswell_verify_D0(struct hda_codec *codec,
871 hda_nid_t cvt_nid, hda_nid_t nid)
875 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
876 * thus pins could only choose converter 0 for use. Make sure the
877 * converters are in correct power state */
878 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
879 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
881 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
882 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
885 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
886 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
887 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
895 /* HBR should be Non-PCM, 8 channels */
896 #define is_hbr_format(format) \
897 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
899 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
900 int dev_id, bool hbr)
902 int pinctl, new_pinctl;
904 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
905 snd_hda_set_dev_select(codec, pin_nid, dev_id);
906 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
907 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
910 return hbr ? -EINVAL : 0;
912 new_pinctl = pinctl & ~AC_PINCTL_EPT;
914 new_pinctl |= AC_PINCTL_EPT_HBR;
916 new_pinctl |= AC_PINCTL_EPT_NATIVE;
919 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
921 pinctl == new_pinctl ? "" : "new-",
924 if (pinctl != new_pinctl)
925 snd_hda_codec_write(codec, pin_nid, 0,
926 AC_VERB_SET_PIN_WIDGET_CONTROL,
934 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
935 hda_nid_t pin_nid, int dev_id,
936 u32 stream_tag, int format)
938 struct hdmi_spec *spec = codec->spec;
942 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
943 is_hbr_format(format));
946 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
950 if (spec->intel_hsw_fixup) {
953 * on recent platforms IEC Coding Type is required for HBR
954 * support, read current Digital Converter settings and set
955 * ICT bitfield if needed.
957 param = snd_hda_codec_read(codec, cvt_nid, 0,
958 AC_VERB_GET_DIGI_CONVERT_1, 0);
960 param = (param >> 16) & ~(AC_DIG3_ICT);
962 /* on recent platforms ICT mode is required for HBR support */
963 if (is_hbr_format(format))
966 snd_hda_codec_write(codec, cvt_nid, 0,
967 AC_VERB_SET_DIGI_CONVERT_3, param);
970 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
974 /* Try to find an available converter
975 * If pin_idx is less then zero, just try to find an available converter.
976 * Otherwise, try to find an available converter and get the cvt mux index
979 static int hdmi_choose_cvt(struct hda_codec *codec,
980 int pin_idx, int *cvt_id)
982 struct hdmi_spec *spec = codec->spec;
983 struct hdmi_spec_per_pin *per_pin;
984 struct hdmi_spec_per_cvt *per_cvt = NULL;
985 int cvt_idx, mux_idx = 0;
987 /* pin_idx < 0 means no pin will be bound to the converter */
991 per_pin = get_pin(spec, pin_idx);
993 if (per_pin && per_pin->silent_stream) {
994 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1000 /* Dynamically assign converter to stream */
1001 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1002 per_cvt = get_cvt(spec, cvt_idx);
1004 /* Must not already be assigned */
1005 if (per_cvt->assigned)
1007 if (per_pin == NULL)
1009 /* Must be in pin's mux's list of converters */
1010 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1011 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1013 /* Not in mux list */
1014 if (mux_idx == per_pin->num_mux_nids)
1019 /* No free converters */
1020 if (cvt_idx == spec->num_cvts)
1023 if (per_pin != NULL)
1024 per_pin->mux_idx = mux_idx;
1032 /* Assure the pin select the right convetor */
1033 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1034 struct hdmi_spec_per_pin *per_pin)
1036 hda_nid_t pin_nid = per_pin->pin_nid;
1039 mux_idx = per_pin->mux_idx;
1040 curr = snd_hda_codec_read(codec, pin_nid, 0,
1041 AC_VERB_GET_CONNECT_SEL, 0);
1042 if (curr != mux_idx)
1043 snd_hda_codec_write_cache(codec, pin_nid, 0,
1044 AC_VERB_SET_CONNECT_SEL,
1048 /* get the mux index for the converter of the pins
1049 * converter's mux index is the same for all pins on Intel platform
1051 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1056 for (i = 0; i < spec->num_cvts; i++)
1057 if (spec->cvt_nids[i] == cvt_nid)
1062 /* Intel HDMI workaround to fix audio routing issue:
1063 * For some Intel display codecs, pins share the same connection list.
1064 * So a conveter can be selected by multiple pins and playback on any of these
1065 * pins will generate sound on the external display, because audio flows from
1066 * the same converter to the display pipeline. Also muting one pin may make
1067 * other pins have no sound output.
1068 * So this function assures that an assigned converter for a pin is not selected
1069 * by any other pins.
1071 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1073 int dev_id, int mux_idx)
1075 struct hdmi_spec *spec = codec->spec;
1078 struct hdmi_spec_per_cvt *per_cvt;
1079 struct hdmi_spec_per_pin *per_pin;
1082 /* configure the pins connections */
1083 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1087 per_pin = get_pin(spec, pin_idx);
1089 * pin not connected to monitor
1090 * no need to operate on it
1095 if ((per_pin->pin_nid == pin_nid) &&
1096 (per_pin->dev_id == dev_id))
1100 * if per_pin->dev_id >= dev_num,
1101 * snd_hda_get_dev_select() will fail,
1102 * and the following operation is unpredictable.
1103 * So skip this situation.
1105 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1106 if (per_pin->dev_id >= dev_num)
1109 nid = per_pin->pin_nid;
1112 * Calling this function should not impact
1113 * on the device entry selection
1114 * So let's save the dev id for each pin,
1115 * and restore it when return
1117 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1118 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1119 curr = snd_hda_codec_read(codec, nid, 0,
1120 AC_VERB_GET_CONNECT_SEL, 0);
1121 if (curr != mux_idx) {
1122 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1127 /* choose an unassigned converter. The conveters in the
1128 * connection list are in the same order as in the codec.
1130 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1131 per_cvt = get_cvt(spec, cvt_idx);
1132 if (!per_cvt->assigned) {
1134 "choose cvt %d for pin NID 0x%x\n",
1136 snd_hda_codec_write_cache(codec, nid, 0,
1137 AC_VERB_SET_CONNECT_SEL,
1142 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1146 /* A wrapper of intel_not_share_asigned_cvt() */
1147 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1148 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1151 struct hdmi_spec *spec = codec->spec;
1153 /* On Intel platform, the mapping of converter nid to
1154 * mux index of the pins are always the same.
1155 * The pin nid may be 0, this means all pins will not
1156 * share the converter.
1158 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1160 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1163 /* skeleton caller of pin_cvt_fixup ops */
1164 static void pin_cvt_fixup(struct hda_codec *codec,
1165 struct hdmi_spec_per_pin *per_pin,
1168 struct hdmi_spec *spec = codec->spec;
1170 if (spec->ops.pin_cvt_fixup)
1171 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1174 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1175 * in dyn_pcm_assign mode.
1177 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1178 struct hda_codec *codec,
1179 struct snd_pcm_substream *substream)
1181 struct hdmi_spec *spec = codec->spec;
1182 struct snd_pcm_runtime *runtime = substream->runtime;
1183 int cvt_idx, pcm_idx;
1184 struct hdmi_spec_per_cvt *per_cvt = NULL;
1187 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1191 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1195 per_cvt = get_cvt(spec, cvt_idx);
1196 per_cvt->assigned = 1;
1197 hinfo->nid = per_cvt->cvt_nid;
1199 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1201 set_bit(pcm_idx, &spec->pcm_in_use);
1202 /* todo: setup spdif ctls assign */
1204 /* Initially set the converter's capabilities */
1205 hinfo->channels_min = per_cvt->channels_min;
1206 hinfo->channels_max = per_cvt->channels_max;
1207 hinfo->rates = per_cvt->rates;
1208 hinfo->formats = per_cvt->formats;
1209 hinfo->maxbps = per_cvt->maxbps;
1211 /* Store the updated parameters */
1212 runtime->hw.channels_min = hinfo->channels_min;
1213 runtime->hw.channels_max = hinfo->channels_max;
1214 runtime->hw.formats = hinfo->formats;
1215 runtime->hw.rates = hinfo->rates;
1217 snd_pcm_hw_constraint_step(substream->runtime, 0,
1218 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1225 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1226 struct hda_codec *codec,
1227 struct snd_pcm_substream *substream)
1229 struct hdmi_spec *spec = codec->spec;
1230 struct snd_pcm_runtime *runtime = substream->runtime;
1231 int pin_idx, cvt_idx, pcm_idx;
1232 struct hdmi_spec_per_pin *per_pin;
1233 struct hdmi_eld *eld;
1234 struct hdmi_spec_per_cvt *per_cvt = NULL;
1237 /* Validate hinfo */
1238 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1242 mutex_lock(&spec->pcm_lock);
1243 pin_idx = hinfo_to_pin_index(codec, hinfo);
1244 if (!spec->dyn_pcm_assign) {
1245 if (snd_BUG_ON(pin_idx < 0)) {
1250 /* no pin is assigned to the PCM
1251 * PA need pcm open successfully when probe
1254 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1259 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1263 per_cvt = get_cvt(spec, cvt_idx);
1264 /* Claim converter */
1265 per_cvt->assigned = 1;
1267 set_bit(pcm_idx, &spec->pcm_in_use);
1268 per_pin = get_pin(spec, pin_idx);
1269 per_pin->cvt_nid = per_cvt->cvt_nid;
1270 hinfo->nid = per_cvt->cvt_nid;
1272 /* flip stripe flag for the assigned stream if supported */
1273 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1274 azx_stream(get_azx_dev(substream))->stripe = 1;
1276 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1277 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1278 AC_VERB_SET_CONNECT_SEL,
1281 /* configure unused pins to choose other converters */
1282 pin_cvt_fixup(codec, per_pin, 0);
1284 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1286 /* Initially set the converter's capabilities */
1287 hinfo->channels_min = per_cvt->channels_min;
1288 hinfo->channels_max = per_cvt->channels_max;
1289 hinfo->rates = per_cvt->rates;
1290 hinfo->formats = per_cvt->formats;
1291 hinfo->maxbps = per_cvt->maxbps;
1293 eld = &per_pin->sink_eld;
1294 /* Restrict capabilities by ELD if this isn't disabled */
1295 if (!static_hdmi_pcm && eld->eld_valid) {
1296 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1297 if (hinfo->channels_min > hinfo->channels_max ||
1298 !hinfo->rates || !hinfo->formats) {
1299 per_cvt->assigned = 0;
1301 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1307 /* Store the updated parameters */
1308 runtime->hw.channels_min = hinfo->channels_min;
1309 runtime->hw.channels_max = hinfo->channels_max;
1310 runtime->hw.formats = hinfo->formats;
1311 runtime->hw.rates = hinfo->rates;
1313 snd_pcm_hw_constraint_step(substream->runtime, 0,
1314 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1316 mutex_unlock(&spec->pcm_lock);
1321 * HDA/HDMI auto parsing
1323 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1325 struct hdmi_spec *spec = codec->spec;
1326 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1327 hda_nid_t pin_nid = per_pin->pin_nid;
1328 int dev_id = per_pin->dev_id;
1331 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1333 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n",
1334 pin_nid, get_wcaps(codec, pin_nid));
1338 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1340 if (spec->intel_hsw_fixup) {
1341 conns = spec->num_cvts;
1342 memcpy(per_pin->mux_nids, spec->cvt_nids,
1343 sizeof(hda_nid_t) * conns);
1345 conns = snd_hda_get_raw_connections(codec, pin_nid,
1347 HDA_MAX_CONNECTIONS);
1350 /* all the device entries on the same pin have the same conn list */
1351 per_pin->num_mux_nids = conns;
1356 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1357 struct hdmi_spec_per_pin *per_pin)
1361 /* on the new machines, try to assign the pcm slot dynamically,
1362 * not use the preferred fixed map (legacy way) anymore.
1364 if (spec->dyn_pcm_no_legacy)
1368 * generic_hdmi_build_pcms() may allocate extra PCMs on some
1369 * platforms (with maximum of 'num_nids + dev_num - 1')
1371 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
1372 * if m==0. This guarantees that dynamic pcm assignments are compatible
1373 * with the legacy static per_pin-pcm assignment that existed in the
1374 * days before DP-MST.
1376 * Intel DP-MST prefers this legacy behavior for compatibility, too.
1378 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
1381 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
1382 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1383 return per_pin->pin_nid_idx;
1385 i = spec->num_nids + (per_pin->dev_id - 1);
1386 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
1390 /* have a second try; check the area over num_nids */
1391 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1392 if (!test_bit(i, &spec->pcm_bitmap))
1397 /* the last try; check the empty slots in pins */
1398 for (i = 0; i < spec->num_nids; i++) {
1399 if (!test_bit(i, &spec->pcm_bitmap))
1405 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1406 struct hdmi_spec_per_pin *per_pin)
1410 /* pcm already be attached to the pin */
1413 idx = hdmi_find_pcm_slot(spec, per_pin);
1416 per_pin->pcm_idx = idx;
1417 per_pin->pcm = get_hdmi_pcm(spec, idx);
1418 set_bit(idx, &spec->pcm_bitmap);
1421 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1422 struct hdmi_spec_per_pin *per_pin)
1426 /* pcm already be detached from the pin */
1429 idx = per_pin->pcm_idx;
1430 per_pin->pcm_idx = -1;
1431 per_pin->pcm = NULL;
1432 if (idx >= 0 && idx < spec->pcm_used)
1433 clear_bit(idx, &spec->pcm_bitmap);
1436 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1437 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1441 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1442 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1447 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1449 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1450 struct hdmi_spec_per_pin *per_pin)
1452 struct hda_codec *codec = per_pin->codec;
1453 struct hda_pcm *pcm;
1454 struct hda_pcm_stream *hinfo;
1455 struct snd_pcm_substream *substream;
1459 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1460 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1465 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1468 /* hdmi audio only uses playback and one substream */
1469 hinfo = pcm->stream;
1470 substream = pcm->pcm->streams[0].substream;
1472 per_pin->cvt_nid = hinfo->nid;
1474 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1475 if (mux_idx < per_pin->num_mux_nids) {
1476 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1478 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1479 AC_VERB_SET_CONNECT_SEL,
1482 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1484 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1485 if (substream->runtime)
1486 per_pin->channels = substream->runtime->channels;
1487 per_pin->setup = true;
1488 per_pin->mux_idx = mux_idx;
1490 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1493 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1494 struct hdmi_spec_per_pin *per_pin)
1496 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1497 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1499 per_pin->chmap_set = false;
1500 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1502 per_pin->setup = false;
1503 per_pin->channels = 0;
1506 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1507 struct hdmi_spec_per_pin *per_pin)
1509 struct hdmi_spec *spec = codec->spec;
1511 if (per_pin->pcm_idx >= 0)
1512 return spec->pcm_rec[per_pin->pcm_idx].jack;
1517 /* update per_pin ELD from the given new ELD;
1518 * setup info frame and notification accordingly
1519 * also notify ELD kctl and report jack status changes
1521 static void update_eld(struct hda_codec *codec,
1522 struct hdmi_spec_per_pin *per_pin,
1523 struct hdmi_eld *eld,
1526 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1527 struct hdmi_spec *spec = codec->spec;
1528 struct snd_jack *pcm_jack;
1529 bool old_eld_valid = pin_eld->eld_valid;
1533 if (eld->eld_valid) {
1534 if (eld->eld_size <= 0 ||
1535 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1536 eld->eld_size) < 0) {
1537 eld->eld_valid = false;
1539 schedule_delayed_work(&per_pin->work,
1540 msecs_to_jiffies(300));
1546 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) {
1547 eld->eld_valid = false;
1551 /* for monitor disconnection, save pcm_idx firstly */
1552 pcm_idx = per_pin->pcm_idx;
1555 * pcm_idx >=0 before update_eld() means it is in monitor
1556 * disconnected event. Jack must be fetched before update_eld().
1558 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1560 if (spec->dyn_pcm_assign) {
1561 if (eld->eld_valid) {
1562 hdmi_attach_hda_pcm(spec, per_pin);
1563 hdmi_pcm_setup_pin(spec, per_pin);
1565 hdmi_pcm_reset_pin(spec, per_pin);
1566 hdmi_detach_hda_pcm(spec, per_pin);
1569 /* if pcm_idx == -1, it means this is in monitor connection event
1570 * we can get the correct pcm_idx now.
1573 pcm_idx = per_pin->pcm_idx;
1575 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1578 snd_hdmi_show_eld(codec, &eld->info);
1580 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1581 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1582 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1583 if (pin_eld->eld_size != eld->eld_size ||
1584 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1585 eld->eld_size) != 0)
1589 pin_eld->monitor_present = eld->monitor_present;
1590 pin_eld->eld_valid = eld->eld_valid;
1591 pin_eld->eld_size = eld->eld_size;
1593 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1595 pin_eld->info = eld->info;
1599 * Re-setup pin and infoframe. This is needed e.g. when
1600 * - sink is first plugged-in
1601 * - transcoder can change during stream playback on Haswell
1602 * and this can make HW reset converter selection on a pin.
1604 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1605 pin_cvt_fixup(codec, per_pin, 0);
1606 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1609 if (eld_changed && pcm_idx >= 0)
1610 snd_ctl_notify(codec->card,
1611 SNDRV_CTL_EVENT_MASK_VALUE |
1612 SNDRV_CTL_EVENT_MASK_INFO,
1613 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1615 if (eld_changed && pcm_jack)
1616 snd_jack_report(pcm_jack,
1617 (eld->monitor_present && eld->eld_valid) ?
1618 SND_JACK_AVOUT : 0);
1621 /* update ELD and jack state via HD-audio verbs */
1622 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1625 struct hda_codec *codec = per_pin->codec;
1626 struct hdmi_spec *spec = codec->spec;
1627 struct hdmi_eld *eld = &spec->temp_eld;
1628 hda_nid_t pin_nid = per_pin->pin_nid;
1629 int dev_id = per_pin->dev_id;
1631 * Always execute a GetPinSense verb here, even when called from
1632 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1633 * response's PD bit is not the real PD value, but indicates that
1634 * the real PD value changed. An older version of the HD-audio
1635 * specification worked this way. Hence, we just ignore the data in
1636 * the unsolicited response to avoid custom WARs.
1641 ret = snd_hda_power_up_pm(codec);
1642 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec)))
1645 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1647 mutex_lock(&per_pin->lock);
1648 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1649 if (eld->monitor_present)
1650 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1652 eld->eld_valid = false;
1655 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n",
1656 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1658 if (eld->eld_valid) {
1659 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1660 eld->eld_buffer, &eld->eld_size) < 0)
1661 eld->eld_valid = false;
1664 update_eld(codec, per_pin, eld, repoll);
1665 mutex_unlock(&per_pin->lock);
1667 snd_hda_power_down_pm(codec);
1670 #define I915_SILENT_RATE 48000
1671 #define I915_SILENT_CHANNELS 2
1672 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE
1673 #define I915_SILENT_FORMAT_BITS 16
1674 #define I915_SILENT_FMT_MASK 0xf
1676 static void silent_stream_enable_i915(struct hda_codec *codec,
1677 struct hdmi_spec_per_pin *per_pin)
1679 unsigned int format;
1681 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1682 per_pin->dev_id, I915_SILENT_RATE);
1684 /* trigger silent stream generation in hw */
1685 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS,
1686 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0);
1687 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
1688 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
1689 usleep_range(100, 200);
1690 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
1692 per_pin->channels = I915_SILENT_CHANNELS;
1693 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1696 static void silent_stream_set_kae(struct hda_codec *codec,
1697 struct hdmi_spec_per_pin *per_pin,
1702 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid);
1704 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0);
1705 param = (param >> 16) & 0xff;
1708 param |= AC_DIG3_KAE;
1710 param &= ~AC_DIG3_KAE;
1712 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param);
1715 static void silent_stream_enable(struct hda_codec *codec,
1716 struct hdmi_spec_per_pin *per_pin)
1718 struct hdmi_spec *spec = codec->spec;
1719 struct hdmi_spec_per_cvt *per_cvt;
1720 int cvt_idx, pin_idx, err;
1724 * Power-up will call hdmi_present_sense, so the PM calls
1725 * have to be done without mutex held.
1728 err = snd_hda_power_up_pm(codec);
1729 if (err < 0 && err != -EACCES) {
1731 "Failed to power up codec for silent stream enable ret=[%d]\n", err);
1732 snd_hda_power_down_pm(codec);
1736 mutex_lock(&per_pin->lock);
1738 if (per_pin->setup) {
1739 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
1744 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
1745 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1747 codec_err(codec, "hdmi: no free converter to enable silent mode\n");
1751 per_cvt = get_cvt(spec, cvt_idx);
1752 per_cvt->assigned = 1;
1753 per_pin->cvt_nid = per_cvt->cvt_nid;
1754 per_pin->silent_stream = true;
1756 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
1757 per_pin->pin_nid, per_cvt->cvt_nid);
1759 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1760 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1761 AC_VERB_SET_CONNECT_SEL,
1764 /* configure unused pins to choose other converters */
1765 pin_cvt_fixup(codec, per_pin, 0);
1767 switch (spec->silent_stream_type) {
1768 case SILENT_STREAM_KAE:
1769 silent_stream_set_kae(codec, per_pin, true);
1771 case SILENT_STREAM_I915:
1772 silent_stream_enable_i915(codec, per_pin);
1780 mutex_unlock(&per_pin->lock);
1782 if (err || !keep_power)
1783 snd_hda_power_down_pm(codec);
1786 static void silent_stream_disable(struct hda_codec *codec,
1787 struct hdmi_spec_per_pin *per_pin)
1789 struct hdmi_spec *spec = codec->spec;
1790 struct hdmi_spec_per_cvt *per_cvt;
1793 err = snd_hda_power_up_pm(codec);
1794 if (err < 0 && err != -EACCES) {
1796 "Failed to power up codec for silent stream disable ret=[%d]\n",
1798 snd_hda_power_down_pm(codec);
1802 mutex_lock(&per_pin->lock);
1803 if (!per_pin->silent_stream)
1806 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
1807 per_pin->pin_nid, per_pin->cvt_nid);
1809 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1810 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
1811 per_cvt = get_cvt(spec, cvt_idx);
1812 per_cvt->assigned = 0;
1815 if (spec->silent_stream_type == SILENT_STREAM_I915) {
1816 /* release ref taken in silent_stream_enable() */
1817 snd_hda_power_down_pm(codec);
1818 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) {
1819 silent_stream_set_kae(codec, per_pin, false);
1822 per_pin->cvt_nid = 0;
1823 per_pin->silent_stream = false;
1826 mutex_unlock(&per_pin->lock);
1828 snd_hda_power_down_pm(codec);
1831 /* update ELD and jack state via audio component */
1832 static void sync_eld_via_acomp(struct hda_codec *codec,
1833 struct hdmi_spec_per_pin *per_pin)
1835 struct hdmi_spec *spec = codec->spec;
1836 struct hdmi_eld *eld = &spec->temp_eld;
1837 bool monitor_prev, monitor_next;
1839 mutex_lock(&per_pin->lock);
1840 eld->monitor_present = false;
1841 monitor_prev = per_pin->sink_eld.monitor_present;
1842 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1843 per_pin->dev_id, &eld->monitor_present,
1844 eld->eld_buffer, ELD_MAX_SIZE);
1845 eld->eld_valid = (eld->eld_size > 0);
1846 update_eld(codec, per_pin, eld, 0);
1847 monitor_next = per_pin->sink_eld.monitor_present;
1848 mutex_unlock(&per_pin->lock);
1850 if (spec->silent_stream_type) {
1851 if (!monitor_prev && monitor_next)
1852 silent_stream_enable(codec, per_pin);
1853 else if (monitor_prev && !monitor_next)
1854 silent_stream_disable(codec, per_pin);
1858 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1860 struct hda_codec *codec = per_pin->codec;
1862 if (!codec_has_acomp(codec))
1863 hdmi_present_sense_via_verbs(per_pin, repoll);
1865 sync_eld_via_acomp(codec, per_pin);
1868 static void hdmi_repoll_eld(struct work_struct *work)
1870 struct hdmi_spec_per_pin *per_pin =
1871 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1872 struct hda_codec *codec = per_pin->codec;
1873 struct hdmi_spec *spec = codec->spec;
1874 struct hda_jack_tbl *jack;
1876 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1879 jack->jack_dirty = 1;
1881 if (per_pin->repoll_count++ > 6)
1882 per_pin->repoll_count = 0;
1884 mutex_lock(&spec->pcm_lock);
1885 hdmi_present_sense(per_pin, per_pin->repoll_count);
1886 mutex_unlock(&spec->pcm_lock);
1889 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1891 struct hdmi_spec *spec = codec->spec;
1892 unsigned int caps, config;
1894 struct hdmi_spec_per_pin *per_pin;
1898 caps = snd_hda_query_pin_caps(codec, pin_nid);
1899 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1903 * For DP MST audio, Configuration Default is the same for
1904 * all device entries on the same pin
1906 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1907 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1908 !spec->force_connect)
1912 * To simplify the implementation, malloc all
1913 * the virtual pins in the initialization statically
1915 if (spec->intel_hsw_fixup) {
1917 * On Intel platforms, device entries count returned
1918 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on
1919 * the type of receiver that is connected. Allocate pin
1920 * structures based on worst case.
1922 dev_num = spec->dev_num;
1923 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1924 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1926 * spec->dev_num is the maxinum number of device entries
1927 * among all the pins
1929 spec->dev_num = (spec->dev_num > dev_num) ?
1930 spec->dev_num : dev_num;
1933 * If the platform doesn't support DP MST,
1934 * manually set dev_num to 1. This means
1935 * the pin has only one device entry.
1941 for (i = 0; i < dev_num; i++) {
1942 pin_idx = spec->num_pins;
1943 per_pin = snd_array_new(&spec->pins);
1948 if (spec->dyn_pcm_assign) {
1949 per_pin->pcm = NULL;
1950 per_pin->pcm_idx = -1;
1952 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1953 per_pin->pcm_idx = pin_idx;
1955 per_pin->pin_nid = pin_nid;
1956 per_pin->pin_nid_idx = spec->num_nids;
1957 per_pin->dev_id = i;
1958 per_pin->non_pcm = false;
1959 snd_hda_set_dev_select(codec, pin_nid, i);
1960 err = hdmi_read_pin_conn(codec, pin_idx);
1970 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1972 struct hdmi_spec *spec = codec->spec;
1973 struct hdmi_spec_per_cvt *per_cvt;
1977 chans = get_wcaps(codec, cvt_nid);
1978 chans = get_wcaps_channels(chans);
1980 per_cvt = snd_array_new(&spec->cvts);
1984 per_cvt->cvt_nid = cvt_nid;
1985 per_cvt->channels_min = 2;
1987 per_cvt->channels_max = chans;
1988 if (chans > spec->chmap.channels_max)
1989 spec->chmap.channels_max = chans;
1992 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1999 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
2000 spec->cvt_nids[spec->num_cvts] = cvt_nid;
2006 static const struct snd_pci_quirk force_connect_list[] = {
2007 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
2008 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
2009 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
2010 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
2014 static int hdmi_parse_codec(struct hda_codec *codec)
2016 struct hdmi_spec *spec = codec->spec;
2017 hda_nid_t start_nid;
2020 const struct snd_pci_quirk *q;
2022 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
2023 if (!start_nid || nodes < 0) {
2024 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
2028 if (enable_all_pins)
2029 spec->force_connect = true;
2031 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
2034 spec->force_connect = true;
2037 * hdmi_add_pin() assumes total amount of converters to
2038 * be known, so first discover all converters
2040 for (i = 0; i < nodes; i++) {
2041 hda_nid_t nid = start_nid + i;
2043 caps = get_wcaps(codec, nid);
2045 if (!(caps & AC_WCAP_DIGITAL))
2048 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
2049 hdmi_add_cvt(codec, nid);
2052 /* discover audio pins */
2053 for (i = 0; i < nodes; i++) {
2054 hda_nid_t nid = start_nid + i;
2056 caps = get_wcaps(codec, nid);
2058 if (!(caps & AC_WCAP_DIGITAL))
2061 if (get_wcaps_type(caps) == AC_WID_PIN)
2062 hdmi_add_pin(codec, nid);
2070 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2072 struct hda_spdif_out *spdif;
2075 mutex_lock(&codec->spdif_mutex);
2076 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2077 /* Add sanity check to pass klockwork check.
2078 * This should never happen.
2080 if (WARN_ON(spdif == NULL)) {
2081 mutex_unlock(&codec->spdif_mutex);
2084 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2085 mutex_unlock(&codec->spdif_mutex);
2093 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2094 struct hda_codec *codec,
2095 unsigned int stream_tag,
2096 unsigned int format,
2097 struct snd_pcm_substream *substream)
2099 hda_nid_t cvt_nid = hinfo->nid;
2100 struct hdmi_spec *spec = codec->spec;
2102 struct hdmi_spec_per_pin *per_pin;
2103 struct snd_pcm_runtime *runtime = substream->runtime;
2108 mutex_lock(&spec->pcm_lock);
2109 pin_idx = hinfo_to_pin_index(codec, hinfo);
2110 if (spec->dyn_pcm_assign && pin_idx < 0) {
2111 /* when dyn_pcm_assign and pcm is not bound to a pin
2112 * skip pin setup and return 0 to make audio playback
2115 pin_cvt_fixup(codec, NULL, cvt_nid);
2116 snd_hda_codec_setup_stream(codec, cvt_nid,
2117 stream_tag, 0, format);
2121 if (snd_BUG_ON(pin_idx < 0)) {
2125 per_pin = get_pin(spec, pin_idx);
2127 /* Verify pin:cvt selections to avoid silent audio after S3.
2128 * After S3, the audio driver restores pin:cvt selections
2129 * but this can happen before gfx is ready and such selection
2130 * is overlooked by HW. Thus multiple pins can share a same
2131 * default convertor and mute control will affect each other,
2132 * which can cause a resumed audio playback become silent
2135 pin_cvt_fixup(codec, per_pin, 0);
2137 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2138 /* Todo: add DP1.2 MST audio support later */
2139 if (codec_has_acomp(codec))
2140 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
2141 per_pin->dev_id, runtime->rate);
2143 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
2144 mutex_lock(&per_pin->lock);
2145 per_pin->channels = substream->runtime->channels;
2146 per_pin->setup = true;
2148 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2149 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2151 snd_hda_codec_write(codec, cvt_nid, 0,
2152 AC_VERB_SET_STRIPE_CONTROL,
2156 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2157 mutex_unlock(&per_pin->lock);
2158 if (spec->dyn_pin_out) {
2159 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2161 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2162 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2163 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2164 AC_VERB_SET_PIN_WIDGET_CONTROL,
2168 /* snd_hda_set_dev_select() has been called before */
2169 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2170 per_pin->dev_id, stream_tag, format);
2172 mutex_unlock(&spec->pcm_lock);
2176 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2177 struct hda_codec *codec,
2178 struct snd_pcm_substream *substream)
2180 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2184 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2185 struct hda_codec *codec,
2186 struct snd_pcm_substream *substream)
2188 struct hdmi_spec *spec = codec->spec;
2189 int cvt_idx, pin_idx, pcm_idx;
2190 struct hdmi_spec_per_cvt *per_cvt;
2191 struct hdmi_spec_per_pin *per_pin;
2195 mutex_lock(&spec->pcm_lock);
2197 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2198 if (snd_BUG_ON(pcm_idx < 0)) {
2202 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2203 if (snd_BUG_ON(cvt_idx < 0)) {
2207 per_cvt = get_cvt(spec, cvt_idx);
2208 per_cvt->assigned = 0;
2211 azx_stream(get_azx_dev(substream))->stripe = 0;
2213 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2214 clear_bit(pcm_idx, &spec->pcm_in_use);
2215 pin_idx = hinfo_to_pin_index(codec, hinfo);
2216 if (spec->dyn_pcm_assign && pin_idx < 0)
2219 if (snd_BUG_ON(pin_idx < 0)) {
2223 per_pin = get_pin(spec, pin_idx);
2225 if (spec->dyn_pin_out) {
2226 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2228 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2229 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2230 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2231 AC_VERB_SET_PIN_WIDGET_CONTROL,
2235 mutex_lock(&per_pin->lock);
2236 per_pin->chmap_set = false;
2237 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2239 per_pin->setup = false;
2240 per_pin->channels = 0;
2241 mutex_unlock(&per_pin->lock);
2245 mutex_unlock(&spec->pcm_lock);
2250 static const struct hda_pcm_ops generic_ops = {
2251 .open = hdmi_pcm_open,
2252 .close = hdmi_pcm_close,
2253 .prepare = generic_hdmi_playback_pcm_prepare,
2254 .cleanup = generic_hdmi_playback_pcm_cleanup,
2257 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2259 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2260 struct hdmi_spec *spec = codec->spec;
2261 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2266 return per_pin->sink_eld.info.spk_alloc;
2269 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2270 unsigned char *chmap)
2272 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2273 struct hdmi_spec *spec = codec->spec;
2274 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2276 /* chmap is already set to 0 in caller */
2280 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2283 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2284 unsigned char *chmap, int prepared)
2286 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2287 struct hdmi_spec *spec = codec->spec;
2288 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2292 mutex_lock(&per_pin->lock);
2293 per_pin->chmap_set = true;
2294 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2296 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2297 mutex_unlock(&per_pin->lock);
2300 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2302 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2303 struct hdmi_spec *spec = codec->spec;
2304 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2306 return per_pin ? true:false;
2309 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2311 struct hdmi_spec *spec = codec->spec;
2315 * for non-mst mode, pcm number is the same as before
2316 * for DP MST mode without extra PCM, pcm number is same
2317 * for DP MST mode with extra PCMs, pcm number is
2318 * (nid number + dev_num - 1)
2319 * dev_num is the device entry number in a pin
2322 if (codec->mst_no_extra_pcms)
2323 pcm_num = spec->num_nids;
2325 pcm_num = spec->num_nids + spec->dev_num - 1;
2327 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2329 for (idx = 0; idx < pcm_num; idx++) {
2330 struct hda_pcm *info;
2331 struct hda_pcm_stream *pstr;
2333 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2337 spec->pcm_rec[idx].pcm = info;
2339 info->pcm_type = HDA_PCM_TYPE_HDMI;
2340 info->own_chmap = true;
2342 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2343 pstr->substreams = 1;
2344 pstr->ops = generic_ops;
2345 /* pcm number is less than 16 */
2346 if (spec->pcm_used >= 16)
2348 /* other pstr fields are set in open */
2354 static void free_hdmi_jack_priv(struct snd_jack *jack)
2356 struct hdmi_pcm *pcm = jack->private_data;
2361 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2363 char hdmi_str[32] = "HDMI/DP";
2364 struct hdmi_spec *spec = codec->spec;
2365 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
2366 struct snd_jack *jack;
2367 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2371 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2372 if (!spec->dyn_pcm_assign &&
2373 !is_jack_detectable(codec, per_pin->pin_nid))
2374 strncat(hdmi_str, " Phantom",
2375 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2377 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2382 spec->pcm_rec[pcm_idx].jack = jack;
2383 jack->private_data = &spec->pcm_rec[pcm_idx];
2384 jack->private_free = free_hdmi_jack_priv;
2388 static int generic_hdmi_build_controls(struct hda_codec *codec)
2390 struct hdmi_spec *spec = codec->spec;
2392 int pin_idx, pcm_idx;
2394 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2395 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2396 /* no PCM: mark this for skipping permanently */
2397 set_bit(pcm_idx, &spec->pcm_bitmap);
2401 err = generic_hdmi_build_jack(codec, pcm_idx);
2405 /* create the spdif for each pcm
2406 * pin will be bound when monitor is connected
2408 if (spec->dyn_pcm_assign)
2409 err = snd_hda_create_dig_out_ctls(codec,
2410 0, spec->cvt_nids[0],
2413 struct hdmi_spec_per_pin *per_pin =
2414 get_pin(spec, pcm_idx);
2415 err = snd_hda_create_dig_out_ctls(codec,
2417 per_pin->mux_nids[0],
2422 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2424 dev = get_pcm_rec(spec, pcm_idx)->device;
2425 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2426 /* add control for ELD Bytes */
2427 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2433 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2434 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2435 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2437 pin_eld->eld_valid = false;
2438 hdmi_present_sense(per_pin, 0);
2441 /* add channel maps */
2442 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2443 struct hda_pcm *pcm;
2445 pcm = get_pcm_rec(spec, pcm_idx);
2446 if (!pcm || !pcm->pcm)
2448 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2456 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2458 struct hdmi_spec *spec = codec->spec;
2461 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2462 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2464 per_pin->codec = codec;
2465 mutex_init(&per_pin->lock);
2466 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2467 eld_proc_new(per_pin, pin_idx);
2472 static int generic_hdmi_init(struct hda_codec *codec)
2474 struct hdmi_spec *spec = codec->spec;
2477 mutex_lock(&spec->bind_lock);
2478 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2479 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2480 hda_nid_t pin_nid = per_pin->pin_nid;
2481 int dev_id = per_pin->dev_id;
2483 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2484 hdmi_init_pin(codec, pin_nid);
2485 if (codec_has_acomp(codec))
2487 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2490 mutex_unlock(&spec->bind_lock);
2494 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2496 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2497 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2500 static void hdmi_array_free(struct hdmi_spec *spec)
2502 snd_array_free(&spec->pins);
2503 snd_array_free(&spec->cvts);
2506 static void generic_spec_free(struct hda_codec *codec)
2508 struct hdmi_spec *spec = codec->spec;
2511 hdmi_array_free(spec);
2515 codec->dp_mst = false;
2518 static void generic_hdmi_free(struct hda_codec *codec)
2520 struct hdmi_spec *spec = codec->spec;
2521 int pin_idx, pcm_idx;
2523 if (spec->acomp_registered) {
2524 snd_hdac_acomp_exit(&codec->bus->core);
2525 } else if (codec_has_acomp(codec)) {
2526 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2528 codec->relaxed_resume = 0;
2530 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2531 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2532 cancel_delayed_work_sync(&per_pin->work);
2533 eld_proc_free(per_pin);
2536 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2537 if (spec->pcm_rec[pcm_idx].jack == NULL)
2539 if (spec->dyn_pcm_assign)
2540 snd_device_free(codec->card,
2541 spec->pcm_rec[pcm_idx].jack);
2543 spec->pcm_rec[pcm_idx].jack = NULL;
2546 generic_spec_free(codec);
2550 static int generic_hdmi_suspend(struct hda_codec *codec)
2552 struct hdmi_spec *spec = codec->spec;
2555 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2556 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2557 cancel_delayed_work_sync(&per_pin->work);
2562 static int generic_hdmi_resume(struct hda_codec *codec)
2564 struct hdmi_spec *spec = codec->spec;
2567 codec->patch_ops.init(codec);
2568 snd_hda_regmap_sync(codec);
2570 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2571 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2572 hdmi_present_sense(per_pin, 1);
2578 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2579 .init = generic_hdmi_init,
2580 .free = generic_hdmi_free,
2581 .build_pcms = generic_hdmi_build_pcms,
2582 .build_controls = generic_hdmi_build_controls,
2583 .unsol_event = hdmi_unsol_event,
2585 .suspend = generic_hdmi_suspend,
2586 .resume = generic_hdmi_resume,
2590 static const struct hdmi_ops generic_standard_hdmi_ops = {
2591 .pin_get_eld = hdmi_pin_get_eld,
2592 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2593 .pin_hbr_setup = hdmi_pin_hbr_setup,
2594 .setup_stream = hdmi_setup_stream,
2597 /* allocate codec->spec and assign/initialize generic parser ops */
2598 static int alloc_generic_hdmi(struct hda_codec *codec)
2600 struct hdmi_spec *spec;
2602 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2606 spec->codec = codec;
2607 spec->ops = generic_standard_hdmi_ops;
2608 spec->dev_num = 1; /* initialize to 1 */
2609 mutex_init(&spec->pcm_lock);
2610 mutex_init(&spec->bind_lock);
2611 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2613 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2614 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2615 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2616 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
2619 hdmi_array_init(spec, 4);
2621 codec->patch_ops = generic_hdmi_patch_ops;
2626 /* generic HDMI parser */
2627 static int patch_generic_hdmi(struct hda_codec *codec)
2631 err = alloc_generic_hdmi(codec);
2635 err = hdmi_parse_codec(codec);
2637 generic_spec_free(codec);
2641 generic_hdmi_init_per_pins(codec);
2646 * generic audio component binding
2649 /* turn on / off the unsol event jack detection dynamically */
2650 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2651 int dev_id, bool use_acomp)
2653 struct hda_jack_tbl *tbl;
2655 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2657 /* clear unsol even if component notifier is used, or re-enable
2658 * if notifier is cleared
2660 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2661 snd_hda_codec_write_cache(codec, nid, 0,
2662 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2666 /* set up / clear component notifier dynamically */
2667 static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2670 struct hdmi_spec *spec;
2673 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2674 mutex_lock(&spec->bind_lock);
2675 spec->use_acomp_notifier = use_acomp;
2676 spec->codec->relaxed_resume = use_acomp;
2677 spec->codec->bus->keep_power = 0;
2678 /* reprogram each jack detection logic depending on the notifier */
2679 for (i = 0; i < spec->num_pins; i++)
2680 reprogram_jack_detect(spec->codec,
2681 get_pin(spec, i)->pin_nid,
2682 get_pin(spec, i)->dev_id,
2684 mutex_unlock(&spec->bind_lock);
2687 /* enable / disable the notifier via master bind / unbind */
2688 static int generic_acomp_master_bind(struct device *dev,
2689 struct drm_audio_component *acomp)
2691 generic_acomp_notifier_set(acomp, true);
2695 static void generic_acomp_master_unbind(struct device *dev,
2696 struct drm_audio_component *acomp)
2698 generic_acomp_notifier_set(acomp, false);
2701 /* check whether both HD-audio and DRM PCI devices belong to the same bus */
2702 static int match_bound_vga(struct device *dev, int subtype, void *data)
2704 struct hdac_bus *bus = data;
2705 struct pci_dev *pci, *master;
2707 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2709 master = to_pci_dev(bus->dev);
2710 pci = to_pci_dev(dev);
2711 return master->bus == pci->bus;
2714 /* audio component notifier for AMD/Nvidia HDMI codecs */
2715 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2717 struct hda_codec *codec = audio_ptr;
2718 struct hdmi_spec *spec = codec->spec;
2719 hda_nid_t pin_nid = spec->port2pin(codec, port);
2723 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2725 /* skip notification during system suspend (but not in runtime PM);
2726 * the state will be updated at resume
2728 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2730 /* ditto during suspend/resume process itself */
2731 if (snd_hdac_is_in_pm(&codec->core))
2734 check_presence_and_report(codec, pin_nid, dev_id);
2737 /* set up the private drm_audio_ops from the template */
2738 static void setup_drm_audio_ops(struct hda_codec *codec,
2739 const struct drm_audio_component_audio_ops *ops)
2741 struct hdmi_spec *spec = codec->spec;
2743 spec->drm_audio_ops.audio_ptr = codec;
2744 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2745 * will call pin_eld_notify with using audio_ptr pointer
2746 * We need make sure audio_ptr is really setup
2749 spec->drm_audio_ops.pin2port = ops->pin2port;
2750 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2751 spec->drm_audio_ops.master_bind = ops->master_bind;
2752 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2755 /* initialize the generic HDMI audio component */
2756 static void generic_acomp_init(struct hda_codec *codec,
2757 const struct drm_audio_component_audio_ops *ops,
2758 int (*port2pin)(struct hda_codec *, int))
2760 struct hdmi_spec *spec = codec->spec;
2762 if (!enable_acomp) {
2763 codec_info(codec, "audio component disabled by module option\n");
2767 spec->port2pin = port2pin;
2768 setup_drm_audio_ops(codec, ops);
2769 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2770 match_bound_vga, 0)) {
2771 spec->acomp_registered = true;
2776 * Intel codec parsers and helpers
2779 #define INTEL_GET_VENDOR_VERB 0xf81
2780 #define INTEL_SET_VENDOR_VERB 0x781
2781 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2782 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2784 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2787 unsigned int vendor_param;
2788 struct hdmi_spec *spec = codec->spec;
2790 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2791 INTEL_GET_VENDOR_VERB, 0);
2792 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2795 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2796 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2797 INTEL_SET_VENDOR_VERB, vendor_param);
2798 if (vendor_param == -1)
2802 snd_hda_codec_update_widgets(codec);
2805 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2807 unsigned int vendor_param;
2808 struct hdmi_spec *spec = codec->spec;
2810 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2811 INTEL_GET_VENDOR_VERB, 0);
2812 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2815 /* enable DP1.2 mode */
2816 vendor_param |= INTEL_EN_DP12;
2817 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2818 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2819 INTEL_SET_VENDOR_VERB, vendor_param);
2822 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2823 * Otherwise you may get severe h/w communication errors.
2825 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2826 unsigned int power_state)
2828 if (power_state == AC_PWRST_D0) {
2829 intel_haswell_enable_all_pins(codec, false);
2830 intel_haswell_fixup_enable_dp12(codec);
2833 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2834 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2837 /* There is a fixed mapping between audio pin node and display port.
2838 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2839 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2840 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2841 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2844 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2845 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2846 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2848 static int intel_base_nid(struct hda_codec *codec)
2850 switch (codec->core.vendor_id) {
2851 case 0x80860054: /* ILK */
2852 case 0x80862804: /* ILK */
2853 case 0x80862882: /* VLV */
2860 static int intel_pin2port(void *audio_ptr, int pin_nid)
2862 struct hda_codec *codec = audio_ptr;
2863 struct hdmi_spec *spec = codec->spec;
2866 if (!spec->port_num) {
2867 base_nid = intel_base_nid(codec);
2868 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2870 return pin_nid - base_nid + 1;
2874 * looking for the pin number in the mapping table and return
2875 * the index which indicate the port number
2877 for (i = 0; i < spec->port_num; i++) {
2878 if (pin_nid == spec->port_map[i])
2882 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
2886 static int intel_port2pin(struct hda_codec *codec, int port)
2888 struct hdmi_spec *spec = codec->spec;
2890 if (!spec->port_num) {
2891 /* we assume only from port-B to port-D */
2892 if (port < 1 || port > 3)
2894 return port + intel_base_nid(codec) - 1;
2897 if (port < 0 || port >= spec->port_num)
2899 return spec->port_map[port];
2902 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2904 struct hda_codec *codec = audio_ptr;
2908 pin_nid = intel_port2pin(codec, port);
2911 /* skip notification during system suspend (but not in runtime PM);
2912 * the state will be updated at resume
2914 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2916 /* ditto during suspend/resume process itself */
2917 if (snd_hdac_is_in_pm(&codec->core))
2920 snd_hdac_i915_set_bclk(&codec->bus->core);
2921 check_presence_and_report(codec, pin_nid, dev_id);
2924 static const struct drm_audio_component_audio_ops intel_audio_ops = {
2925 .pin2port = intel_pin2port,
2926 .pin_eld_notify = intel_pin_eld_notify,
2929 /* register i915 component pin_eld_notify callback */
2930 static void register_i915_notifier(struct hda_codec *codec)
2932 struct hdmi_spec *spec = codec->spec;
2934 spec->use_acomp_notifier = true;
2935 spec->port2pin = intel_port2pin;
2936 setup_drm_audio_ops(codec, &intel_audio_ops);
2937 snd_hdac_acomp_register_notifier(&codec->bus->core,
2938 &spec->drm_audio_ops);
2939 /* no need for forcible resume for jack check thanks to notifier */
2940 codec->relaxed_resume = 1;
2943 /* setup_stream ops override for HSW+ */
2944 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2945 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2948 haswell_verify_D0(codec, cvt_nid, pin_nid);
2949 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2950 stream_tag, format);
2953 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2954 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2955 struct hdmi_spec_per_pin *per_pin,
2959 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2960 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2962 intel_verify_pin_cvt_connect(codec, per_pin);
2963 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2964 per_pin->dev_id, per_pin->mux_idx);
2966 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2970 /* precondition and allocation for Intel codecs */
2971 static int alloc_intel_hdmi(struct hda_codec *codec)
2975 /* requires i915 binding */
2976 if (!codec->bus->core.audio_component) {
2977 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2978 /* set probe_id here to prevent generic fallback binding */
2979 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2983 err = alloc_generic_hdmi(codec);
2986 /* no need to handle unsol events */
2987 codec->patch_ops.unsol_event = NULL;
2991 /* parse and post-process for Intel codecs */
2992 static int parse_intel_hdmi(struct hda_codec *codec)
2994 int err, retries = 3;
2997 err = hdmi_parse_codec(codec);
2998 } while (err < 0 && retries--);
3001 generic_spec_free(codec);
3005 generic_hdmi_init_per_pins(codec);
3006 register_i915_notifier(codec);
3010 /* Intel Haswell and onwards; audio component with eld notifier */
3011 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
3012 const int *port_map, int port_num, int dev_num,
3013 bool send_silent_stream)
3015 struct hdmi_spec *spec;
3018 err = alloc_intel_hdmi(codec);
3022 codec->dp_mst = true;
3023 spec->dyn_pcm_assign = true;
3024 spec->vendor_nid = vendor_nid;
3025 spec->port_map = port_map;
3026 spec->port_num = port_num;
3027 spec->intel_hsw_fixup = true;
3028 spec->dev_num = dev_num;
3030 intel_haswell_enable_all_pins(codec, true);
3031 intel_haswell_fixup_enable_dp12(codec);
3033 codec->display_power_control = 1;
3035 codec->patch_ops.set_power_state = haswell_set_power_state;
3036 codec->depop_delay = 0;
3037 codec->auto_runtime_pm = 1;
3039 spec->ops.setup_stream = i915_hsw_setup_stream;
3040 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3043 * Enable silent stream feature, if it is enabled via
3044 * module param or Kconfig option
3046 if (send_silent_stream)
3047 spec->silent_stream_type = SILENT_STREAM_I915;
3049 return parse_intel_hdmi(codec);
3052 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
3054 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
3055 enable_silent_stream);
3058 static int patch_i915_glk_hdmi(struct hda_codec *codec)
3061 * Silent stream calls audio component .get_power() from
3062 * .pin_eld_notify(). On GLK this will deadlock in i915 due
3063 * to the audio vs. CDCLK workaround.
3065 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
3068 static int patch_i915_icl_hdmi(struct hda_codec *codec)
3071 * pin to port mapping table where the value indicate the pin number and
3072 * the index indicate the port number.
3074 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
3076 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
3077 enable_silent_stream);
3080 static int patch_i915_tgl_hdmi(struct hda_codec *codec)
3083 * pin to port mapping table where the value indicate the pin number and
3084 * the index indicate the port number.
3086 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
3089 ret = intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
3090 enable_silent_stream);
3092 struct hdmi_spec *spec = codec->spec;
3094 spec->dyn_pcm_no_legacy = true;
3100 static int patch_i915_adlp_hdmi(struct hda_codec *codec)
3102 struct hdmi_spec *spec;
3105 res = patch_i915_tgl_hdmi(codec);
3109 if (spec->silent_stream_type)
3110 spec->silent_stream_type = SILENT_STREAM_KAE;
3116 /* Intel Baytrail and Braswell; with eld notifier */
3117 static int patch_i915_byt_hdmi(struct hda_codec *codec)
3119 struct hdmi_spec *spec;
3122 err = alloc_intel_hdmi(codec);
3127 /* For Valleyview/Cherryview, only the display codec is in the display
3128 * power well and can use link_power ops to request/release the power.
3130 codec->display_power_control = 1;
3132 codec->depop_delay = 0;
3133 codec->auto_runtime_pm = 1;
3135 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3137 return parse_intel_hdmi(codec);
3140 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
3141 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
3145 err = alloc_intel_hdmi(codec);
3148 return parse_intel_hdmi(codec);
3152 * Shared non-generic implementations
3155 static int simple_playback_build_pcms(struct hda_codec *codec)
3157 struct hdmi_spec *spec = codec->spec;
3158 struct hda_pcm *info;
3160 struct hda_pcm_stream *pstr;
3161 struct hdmi_spec_per_cvt *per_cvt;
3163 per_cvt = get_cvt(spec, 0);
3164 chans = get_wcaps(codec, per_cvt->cvt_nid);
3165 chans = get_wcaps_channels(chans);
3167 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
3170 spec->pcm_rec[0].pcm = info;
3171 info->pcm_type = HDA_PCM_TYPE_HDMI;
3172 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
3173 *pstr = spec->pcm_playback;
3174 pstr->nid = per_cvt->cvt_nid;
3175 if (pstr->channels_max <= 2 && chans && chans <= 16)
3176 pstr->channels_max = chans;
3181 /* unsolicited event for jack sensing */
3182 static void simple_hdmi_unsol_event(struct hda_codec *codec,
3185 snd_hda_jack_set_dirty_all(codec);
3186 snd_hda_jack_report_sync(codec);
3189 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
3190 * as long as spec->pins[] is set correctly
3192 #define simple_hdmi_build_jack generic_hdmi_build_jack
3194 static int simple_playback_build_controls(struct hda_codec *codec)
3196 struct hdmi_spec *spec = codec->spec;
3197 struct hdmi_spec_per_cvt *per_cvt;
3200 per_cvt = get_cvt(spec, 0);
3201 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3206 return simple_hdmi_build_jack(codec, 0);
3209 static int simple_playback_init(struct hda_codec *codec)
3211 struct hdmi_spec *spec = codec->spec;
3212 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3213 hda_nid_t pin = per_pin->pin_nid;
3215 snd_hda_codec_write(codec, pin, 0,
3216 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3217 /* some codecs require to unmute the pin */
3218 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3219 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3221 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3225 static void simple_playback_free(struct hda_codec *codec)
3227 struct hdmi_spec *spec = codec->spec;
3229 hdmi_array_free(spec);
3234 * Nvidia specific implementations
3237 #define Nv_VERB_SET_Channel_Allocation 0xF79
3238 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3239 #define Nv_VERB_SET_Audio_Protection_On 0xF98
3240 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
3242 #define nvhdmi_master_con_nid_7x 0x04
3243 #define nvhdmi_master_pin_nid_7x 0x05
3245 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3246 /*front, rear, clfe, rear_surr */
3250 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3251 /* set audio protect on */
3252 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3253 /* enable digital output on pin widget */
3254 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3258 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3259 /* set audio protect on */
3260 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3261 /* enable digital output on pin widget */
3262 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3263 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3264 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3265 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3266 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3270 #ifdef LIMITED_RATE_FMT_SUPPORT
3271 /* support only the safe format and rate */
3272 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3273 #define SUPPORTED_MAXBPS 16
3274 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3276 /* support all rates and formats */
3277 #define SUPPORTED_RATES \
3278 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3279 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3280 SNDRV_PCM_RATE_192000)
3281 #define SUPPORTED_MAXBPS 24
3282 #define SUPPORTED_FORMATS \
3283 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3286 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3288 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3292 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3294 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3298 static const unsigned int channels_2_6_8[] = {
3302 static const unsigned int channels_2_8[] = {
3306 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3307 .count = ARRAY_SIZE(channels_2_6_8),
3308 .list = channels_2_6_8,
3312 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3313 .count = ARRAY_SIZE(channels_2_8),
3314 .list = channels_2_8,
3318 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3319 struct hda_codec *codec,
3320 struct snd_pcm_substream *substream)
3322 struct hdmi_spec *spec = codec->spec;
3323 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3325 switch (codec->preset->vendor_id) {
3330 hw_constraints_channels = &hw_constraints_2_8_channels;
3333 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3339 if (hw_constraints_channels != NULL) {
3340 snd_pcm_hw_constraint_list(substream->runtime, 0,
3341 SNDRV_PCM_HW_PARAM_CHANNELS,
3342 hw_constraints_channels);
3344 snd_pcm_hw_constraint_step(substream->runtime, 0,
3345 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3348 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3351 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3352 struct hda_codec *codec,
3353 struct snd_pcm_substream *substream)
3355 struct hdmi_spec *spec = codec->spec;
3356 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3359 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3360 struct hda_codec *codec,
3361 unsigned int stream_tag,
3362 unsigned int format,
3363 struct snd_pcm_substream *substream)
3365 struct hdmi_spec *spec = codec->spec;
3366 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3367 stream_tag, format, substream);
3370 static const struct hda_pcm_stream simple_pcm_playback = {
3375 .open = simple_playback_pcm_open,
3376 .close = simple_playback_pcm_close,
3377 .prepare = simple_playback_pcm_prepare
3381 static const struct hda_codec_ops simple_hdmi_patch_ops = {
3382 .build_controls = simple_playback_build_controls,
3383 .build_pcms = simple_playback_build_pcms,
3384 .init = simple_playback_init,
3385 .free = simple_playback_free,
3386 .unsol_event = simple_hdmi_unsol_event,
3389 static int patch_simple_hdmi(struct hda_codec *codec,
3390 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3392 struct hdmi_spec *spec;
3393 struct hdmi_spec_per_cvt *per_cvt;
3394 struct hdmi_spec_per_pin *per_pin;
3396 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3400 spec->codec = codec;
3402 hdmi_array_init(spec, 1);
3404 spec->multiout.num_dacs = 0; /* no analog */
3405 spec->multiout.max_channels = 2;
3406 spec->multiout.dig_out_nid = cvt_nid;
3409 per_pin = snd_array_new(&spec->pins);
3410 per_cvt = snd_array_new(&spec->cvts);
3411 if (!per_pin || !per_cvt) {
3412 simple_playback_free(codec);
3415 per_cvt->cvt_nid = cvt_nid;
3416 per_pin->pin_nid = pin_nid;
3417 spec->pcm_playback = simple_pcm_playback;
3419 codec->patch_ops = simple_hdmi_patch_ops;
3424 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3427 unsigned int chanmask;
3428 int chan = channels ? (channels - 1) : 1;
3447 /* Set the audio infoframe channel allocation and checksum fields. The
3448 * channel count is computed implicitly by the hardware. */
3449 snd_hda_codec_write(codec, 0x1, 0,
3450 Nv_VERB_SET_Channel_Allocation, chanmask);
3452 snd_hda_codec_write(codec, 0x1, 0,
3453 Nv_VERB_SET_Info_Frame_Checksum,
3454 (0x71 - chan - chanmask));
3457 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3458 struct hda_codec *codec,
3459 struct snd_pcm_substream *substream)
3461 struct hdmi_spec *spec = codec->spec;
3464 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3465 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3466 for (i = 0; i < 4; i++) {
3467 /* set the stream id */
3468 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3469 AC_VERB_SET_CHANNEL_STREAMID, 0);
3470 /* set the stream format */
3471 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3472 AC_VERB_SET_STREAM_FORMAT, 0);
3475 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3476 * streams are disabled. */
3477 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3479 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3482 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3483 struct hda_codec *codec,
3484 unsigned int stream_tag,
3485 unsigned int format,
3486 struct snd_pcm_substream *substream)
3489 unsigned int dataDCC2, channel_id;
3491 struct hdmi_spec *spec = codec->spec;
3492 struct hda_spdif_out *spdif;
3493 struct hdmi_spec_per_cvt *per_cvt;
3495 mutex_lock(&codec->spdif_mutex);
3496 per_cvt = get_cvt(spec, 0);
3497 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3499 chs = substream->runtime->channels;
3503 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3504 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3505 snd_hda_codec_write(codec,
3506 nvhdmi_master_con_nid_7x,
3508 AC_VERB_SET_DIGI_CONVERT_1,
3509 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3511 /* set the stream id */
3512 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3513 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3515 /* set the stream format */
3516 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3517 AC_VERB_SET_STREAM_FORMAT, format);
3519 /* turn on again (if needed) */
3520 /* enable and set the channel status audio/data flag */
3521 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3522 snd_hda_codec_write(codec,
3523 nvhdmi_master_con_nid_7x,
3525 AC_VERB_SET_DIGI_CONVERT_1,
3526 spdif->ctls & 0xff);
3527 snd_hda_codec_write(codec,
3528 nvhdmi_master_con_nid_7x,
3530 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3533 for (i = 0; i < 4; i++) {
3539 /* turn off SPDIF once;
3540 *otherwise the IEC958 bits won't be updated
3542 if (codec->spdif_status_reset &&
3543 (spdif->ctls & AC_DIG1_ENABLE))
3544 snd_hda_codec_write(codec,
3545 nvhdmi_con_nids_7x[i],
3547 AC_VERB_SET_DIGI_CONVERT_1,
3548 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3549 /* set the stream id */
3550 snd_hda_codec_write(codec,
3551 nvhdmi_con_nids_7x[i],
3553 AC_VERB_SET_CHANNEL_STREAMID,
3554 (stream_tag << 4) | channel_id);
3555 /* set the stream format */
3556 snd_hda_codec_write(codec,
3557 nvhdmi_con_nids_7x[i],
3559 AC_VERB_SET_STREAM_FORMAT,
3561 /* turn on again (if needed) */
3562 /* enable and set the channel status audio/data flag */
3563 if (codec->spdif_status_reset &&
3564 (spdif->ctls & AC_DIG1_ENABLE)) {
3565 snd_hda_codec_write(codec,
3566 nvhdmi_con_nids_7x[i],
3568 AC_VERB_SET_DIGI_CONVERT_1,
3569 spdif->ctls & 0xff);
3570 snd_hda_codec_write(codec,
3571 nvhdmi_con_nids_7x[i],
3573 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3577 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3579 mutex_unlock(&codec->spdif_mutex);
3583 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3587 .nid = nvhdmi_master_con_nid_7x,
3588 .rates = SUPPORTED_RATES,
3589 .maxbps = SUPPORTED_MAXBPS,
3590 .formats = SUPPORTED_FORMATS,
3592 .open = simple_playback_pcm_open,
3593 .close = nvhdmi_8ch_7x_pcm_close,
3594 .prepare = nvhdmi_8ch_7x_pcm_prepare
3598 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3600 struct hdmi_spec *spec;
3601 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3602 nvhdmi_master_pin_nid_7x);
3606 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3607 /* override the PCM rates, etc, as the codec doesn't give full list */
3609 spec->pcm_playback.rates = SUPPORTED_RATES;
3610 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3611 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3615 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3617 struct hdmi_spec *spec = codec->spec;
3618 int err = simple_playback_build_pcms(codec);
3620 struct hda_pcm *info = get_pcm_rec(spec, 0);
3621 info->own_chmap = true;
3626 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3628 struct hdmi_spec *spec = codec->spec;
3629 struct hda_pcm *info;
3630 struct snd_pcm_chmap *chmap;
3633 err = simple_playback_build_controls(codec);
3637 /* add channel maps */
3638 info = get_pcm_rec(spec, 0);
3639 err = snd_pcm_add_chmap_ctls(info->pcm,
3640 SNDRV_PCM_STREAM_PLAYBACK,
3641 snd_pcm_alt_chmaps, 8, 0, &chmap);
3644 switch (codec->preset->vendor_id) {
3649 chmap->channel_mask = (1U << 2) | (1U << 8);
3652 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3657 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3659 struct hdmi_spec *spec;
3660 int err = patch_nvhdmi_2ch(codec);
3664 spec->multiout.max_channels = 8;
3665 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3666 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3667 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3668 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3670 /* Initialize the audio infoframe channel mask and checksum to something
3672 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3678 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3682 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3683 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3685 if (cap->ca_index == 0x00 && channels == 2)
3686 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3688 /* If the speaker allocation matches the channel count, it is OK. */
3689 if (cap->channels != channels)
3692 /* all channels are remappable freely */
3693 return SNDRV_CTL_TLVT_CHMAP_VAR;
3696 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3697 int ca, int chs, unsigned char *map)
3699 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3705 /* map from pin NID to port; port is 0-based */
3706 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3707 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3712 /* reverse-map from port to pin NID: see above */
3713 static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3718 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3719 .pin2port = nvhdmi_pin2port,
3720 .pin_eld_notify = generic_acomp_pin_eld_notify,
3721 .master_bind = generic_acomp_master_bind,
3722 .master_unbind = generic_acomp_master_unbind,
3725 static int patch_nvhdmi(struct hda_codec *codec)
3727 struct hdmi_spec *spec;
3730 err = alloc_generic_hdmi(codec);
3733 codec->dp_mst = true;
3736 spec->dyn_pcm_assign = true;
3738 err = hdmi_parse_codec(codec);
3740 generic_spec_free(codec);
3744 generic_hdmi_init_per_pins(codec);
3746 spec->dyn_pin_out = true;
3748 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3749 nvhdmi_chmap_cea_alloc_validate_get_type;
3750 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3752 codec->link_down_at_suspend = 1;
3754 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3759 static int patch_nvhdmi_legacy(struct hda_codec *codec)
3761 struct hdmi_spec *spec;
3764 err = patch_generic_hdmi(codec);
3769 spec->dyn_pin_out = true;
3771 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3772 nvhdmi_chmap_cea_alloc_validate_get_type;
3773 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3775 codec->link_down_at_suspend = 1;
3781 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3782 * accessed using vendor-defined verbs. These registers can be used for
3783 * interoperability between the HDA and HDMI drivers.
3786 /* Audio Function Group node */
3787 #define NVIDIA_AFG_NID 0x01
3790 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3791 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3792 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3793 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3794 * additional bit (at position 30) to signal the validity of the format.
3796 * | 31 | 30 | 29 16 | 15 0 |
3797 * +---------+-------+--------+--------+
3798 * | TRIGGER | VALID | UNUSED | FORMAT |
3799 * +-----------------------------------|
3801 * Note that for the trigger bit to take effect it needs to change value
3802 * (i.e. it needs to be toggled). The trigger bit is not applicable from
3803 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt
3806 #define NVIDIA_SET_HOST_INTR 0xf80
3807 #define NVIDIA_GET_SCRATCH0 0xfa6
3808 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3809 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3810 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3811 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3812 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3813 #define NVIDIA_SCRATCH_VALID (1 << 6)
3815 #define NVIDIA_GET_SCRATCH1 0xfab
3816 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3817 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3818 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3819 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3822 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3823 * the format is invalidated so that the HDMI codec can be disabled.
3825 static void tegra_hdmi_set_format(struct hda_codec *codec,
3827 unsigned int format)
3830 unsigned int nid = NVIDIA_AFG_NID;
3831 struct hdmi_spec *spec = codec->spec;
3834 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST.
3835 * This resulted in moving scratch registers from audio function
3836 * group to converter widget context. So CVT NID should be used for
3837 * scratch register read/write for DP MST supported Tegra HDA codec.
3842 /* bits [31:30] contain the trigger and valid bits */
3843 value = snd_hda_codec_read(codec, nid, 0,
3844 NVIDIA_GET_SCRATCH0, 0);
3845 value = (value >> 24) & 0xff;
3847 /* bits [15:0] are used to store the HDA format */
3848 snd_hda_codec_write(codec, nid, 0,
3849 NVIDIA_SET_SCRATCH0_BYTE0,
3850 (format >> 0) & 0xff);
3851 snd_hda_codec_write(codec, nid, 0,
3852 NVIDIA_SET_SCRATCH0_BYTE1,
3853 (format >> 8) & 0xff);
3855 /* bits [16:24] are unused */
3856 snd_hda_codec_write(codec, nid, 0,
3857 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3860 * Bit 30 signals that the data is valid and hence that HDMI audio can
3864 value &= ~NVIDIA_SCRATCH_VALID;
3866 value |= NVIDIA_SCRATCH_VALID;
3868 if (spec->hdmi_intr_trig_ctrl) {
3870 * For Tegra HDA Codec design from TEGRA234 onwards, the
3871 * Interrupt to hdmi driver is triggered by writing
3872 * non-zero values to verb 0xF80 instead of 31st bit of
3875 snd_hda_codec_write(codec, nid, 0,
3876 NVIDIA_SET_SCRATCH0_BYTE3, value);
3877 snd_hda_codec_write(codec, nid, 0,
3878 NVIDIA_SET_HOST_INTR, 0x1);
3881 * Whenever the 31st trigger bit is toggled, an interrupt is raised
3882 * in the HDMI codec. The HDMI driver will use that as trigger
3883 * to update its configuration.
3885 value ^= NVIDIA_SCRATCH_TRIGGER;
3887 snd_hda_codec_write(codec, nid, 0,
3888 NVIDIA_SET_SCRATCH0_BYTE3, value);
3892 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3893 struct hda_codec *codec,
3894 unsigned int stream_tag,
3895 unsigned int format,
3896 struct snd_pcm_substream *substream)
3900 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3905 /* notify the HDMI codec of the format change */
3906 tegra_hdmi_set_format(codec, hinfo->nid, format);
3911 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3912 struct hda_codec *codec,
3913 struct snd_pcm_substream *substream)
3915 /* invalidate the format in the HDMI codec */
3916 tegra_hdmi_set_format(codec, hinfo->nid, 0);
3918 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3921 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3923 struct hdmi_spec *spec = codec->spec;
3926 for (i = 0; i < spec->num_pins; i++) {
3927 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3929 if (pcm->pcm_type == type)
3936 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3938 struct hda_pcm_stream *stream;
3939 struct hda_pcm *pcm;
3942 err = generic_hdmi_build_pcms(codec);
3946 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3951 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3952 * codec about format changes.
3954 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3955 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3956 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3961 static int tegra_hdmi_init(struct hda_codec *codec)
3963 struct hdmi_spec *spec = codec->spec;
3966 err = hdmi_parse_codec(codec);
3968 generic_spec_free(codec);
3972 for (i = 0; i < spec->num_cvts; i++)
3973 snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
3974 AC_VERB_SET_DIGI_CONVERT_1,
3977 generic_hdmi_init_per_pins(codec);
3979 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3980 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3981 nvhdmi_chmap_cea_alloc_validate_get_type;
3982 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3984 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3985 nvhdmi_chmap_cea_alloc_validate_get_type;
3986 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3991 static int patch_tegra_hdmi(struct hda_codec *codec)
3995 err = alloc_generic_hdmi(codec);
3999 return tegra_hdmi_init(codec);
4002 static int patch_tegra234_hdmi(struct hda_codec *codec)
4004 struct hdmi_spec *spec;
4007 err = alloc_generic_hdmi(codec);
4011 codec->dp_mst = true;
4012 codec->mst_no_extra_pcms = true;
4014 spec->dyn_pin_out = true;
4015 spec->dyn_pcm_assign = true;
4016 spec->hdmi_intr_trig_ctrl = true;
4018 return tegra_hdmi_init(codec);
4022 * ATI/AMD-specific implementations
4025 #define is_amdhdmi_rev3_or_later(codec) \
4026 ((codec)->core.vendor_id == 0x1002aa01 && \
4027 ((codec)->core.revision_id & 0xff00) >= 0x0300)
4028 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
4030 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
4031 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
4032 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
4033 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
4034 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
4035 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
4036 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
4037 #define ATI_VERB_SET_HBR_CONTROL 0x77c
4038 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
4039 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
4040 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
4041 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
4042 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
4043 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
4044 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
4045 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
4046 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
4047 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
4048 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
4049 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
4050 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
4051 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
4052 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
4053 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
4054 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
4056 /* AMD specific HDA cvt verbs */
4057 #define ATI_VERB_SET_RAMP_RATE 0x770
4058 #define ATI_VERB_GET_RAMP_RATE 0xf70
4060 #define ATI_OUT_ENABLE 0x1
4062 #define ATI_MULTICHANNEL_MODE_PAIRED 0
4063 #define ATI_MULTICHANNEL_MODE_SINGLE 1
4065 #define ATI_HBR_CAPABLE 0x01
4066 #define ATI_HBR_ENABLE 0x10
4068 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
4069 int dev_id, unsigned char *buf, int *eld_size)
4071 WARN_ON(dev_id != 0);
4072 /* call hda_eld.c ATI/AMD-specific function */
4073 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
4074 is_amdhdmi_rev3_or_later(codec));
4077 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
4078 hda_nid_t pin_nid, int dev_id, int ca,
4079 int active_channels, int conn_type)
4081 WARN_ON(dev_id != 0);
4082 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
4085 static int atihdmi_paired_swap_fc_lfe(int pos)
4088 * ATI/AMD have automatic FC/LFE swap built-in
4089 * when in pairwise mapping mode.
4093 /* see channel_allocations[].speakers[] */
4102 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
4103 int ca, int chs, unsigned char *map)
4105 struct hdac_cea_channel_speaker_allocation *cap;
4108 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
4110 cap = snd_hdac_get_ch_alloc_from_ca(ca);
4111 for (i = 0; i < chs; ++i) {
4112 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
4114 bool companion_ok = false;
4119 for (j = 0 + i % 2; j < 8; j += 2) {
4120 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
4121 if (cap->speakers[chan_idx] == mask) {
4122 /* channel is in a supported position */
4125 if (i % 2 == 0 && i + 1 < chs) {
4126 /* even channel, check the odd companion */
4127 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
4128 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
4129 int comp_mask_act = cap->speakers[comp_chan_idx];
4131 if (comp_mask_req == comp_mask_act)
4132 companion_ok = true;
4144 i++; /* companion channel already checked */
4150 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
4151 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
4153 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4155 int ati_channel_setup = 0;
4160 if (!has_amd_full_remap_support(codec)) {
4161 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
4163 /* In case this is an odd slot but without stream channel, do not
4164 * disable the slot since the corresponding even slot could have a
4165 * channel. In case neither have a channel, the slot pair will be
4166 * disabled when this function is called for the even slot. */
4167 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
4170 hdmi_slot -= hdmi_slot % 2;
4172 if (stream_channel != 0xf)
4173 stream_channel -= stream_channel % 2;
4176 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
4178 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
4180 if (stream_channel != 0xf)
4181 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
4183 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
4186 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
4187 hda_nid_t pin_nid, int asp_slot)
4189 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4190 bool was_odd = false;
4191 int ati_asp_slot = asp_slot;
4193 int ati_channel_setup;
4198 if (!has_amd_full_remap_support(codec)) {
4199 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
4200 if (ati_asp_slot % 2 != 0) {
4206 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
4208 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
4210 if (!(ati_channel_setup & ATI_OUT_ENABLE))
4213 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
4216 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
4217 struct hdac_chmap *chmap,
4218 struct hdac_cea_channel_speaker_allocation *cap,
4224 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
4225 * we need to take that into account (a single channel may take 2
4226 * channel slots if we need to carry a silent channel next to it).
4227 * On Rev3+ AMD codecs this function is not used.
4231 /* We only produce even-numbered channel count TLVs */
4232 if ((channels % 2) != 0)
4235 for (c = 0; c < 7; c += 2) {
4236 if (cap->speakers[c] || cap->speakers[c+1])
4240 if (chanpairs * 2 != channels)
4243 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
4246 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
4247 struct hdac_cea_channel_speaker_allocation *cap,
4248 unsigned int *chmap, int channels)
4250 /* produce paired maps for pre-rev3 ATI/AMD codecs */
4254 for (c = 7; c >= 0; c--) {
4255 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
4256 int spk = cap->speakers[chan];
4258 /* add N/A channel if the companion channel is occupied */
4259 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
4260 chmap[count++] = SNDRV_CHMAP_NA;
4265 chmap[count++] = snd_hdac_spk_to_chmap(spk);
4268 WARN_ON(count != channels);
4271 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4272 int dev_id, bool hbr)
4274 int hbr_ctl, hbr_ctl_new;
4276 WARN_ON(dev_id != 0);
4278 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4279 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4281 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4283 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4286 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4288 hbr_ctl == hbr_ctl_new ? "" : "new-",
4291 if (hbr_ctl != hbr_ctl_new)
4292 snd_hda_codec_write(codec, pin_nid, 0,
4293 ATI_VERB_SET_HBR_CONTROL,
4302 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4303 hda_nid_t pin_nid, int dev_id,
4304 u32 stream_tag, int format)
4306 if (is_amdhdmi_rev3_or_later(codec)) {
4307 int ramp_rate = 180; /* default as per AMD spec */
4308 /* disable ramp-up/down for non-pcm as per AMD spec */
4309 if (format & AC_FMT_TYPE_NON_PCM)
4312 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4315 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4316 stream_tag, format);
4320 static int atihdmi_init(struct hda_codec *codec)
4322 struct hdmi_spec *spec = codec->spec;
4325 err = generic_hdmi_init(codec);
4330 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4331 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4333 /* make sure downmix information in infoframe is zero */
4334 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4336 /* enable channel-wise remap mode if supported */
4337 if (has_amd_full_remap_support(codec))
4338 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4339 ATI_VERB_SET_MULTICHANNEL_MODE,
4340 ATI_MULTICHANNEL_MODE_SINGLE);
4342 codec->auto_runtime_pm = 1;
4347 /* map from pin NID to port; port is 0-based */
4348 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4349 static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4351 return pin_nid / 2 - 1;
4354 /* reverse-map from port to pin NID: see above */
4355 static int atihdmi_port2pin(struct hda_codec *codec, int port)
4357 return port * 2 + 3;
4360 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4361 .pin2port = atihdmi_pin2port,
4362 .pin_eld_notify = generic_acomp_pin_eld_notify,
4363 .master_bind = generic_acomp_master_bind,
4364 .master_unbind = generic_acomp_master_unbind,
4367 static int patch_atihdmi(struct hda_codec *codec)
4369 struct hdmi_spec *spec;
4370 struct hdmi_spec_per_cvt *per_cvt;
4373 err = patch_generic_hdmi(codec);
4378 codec->patch_ops.init = atihdmi_init;
4382 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4383 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4384 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4385 spec->ops.setup_stream = atihdmi_setup_stream;
4387 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4388 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4390 if (!has_amd_full_remap_support(codec)) {
4391 /* override to ATI/AMD-specific versions with pairwise mapping */
4392 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4393 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4394 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4395 atihdmi_paired_cea_alloc_to_tlv_chmap;
4396 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4399 /* ATI/AMD converters do not advertise all of their capabilities */
4400 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4401 per_cvt = get_cvt(spec, cvt_idx);
4402 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4403 per_cvt->rates |= SUPPORTED_RATES;
4404 per_cvt->formats |= SUPPORTED_FORMATS;
4405 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4408 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4410 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4411 * the link-down as is. Tell the core to allow it.
4413 codec->link_down_at_suspend = 1;
4415 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4420 /* VIA HDMI Implementation */
4421 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4422 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4424 static int patch_via_hdmi(struct hda_codec *codec)
4426 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4432 static const struct hda_device_id snd_hda_id_hdmi[] = {
4433 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4434 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4435 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4436 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4437 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4438 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4439 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4440 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4441 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4442 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4443 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4444 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4445 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4446 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4447 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4448 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4449 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4450 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4451 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4452 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4453 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4454 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4455 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4456 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4457 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4458 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4459 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4460 /* 17 is known to be absent */
4461 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4462 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4463 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4464 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4465 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4466 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4467 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4468 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4469 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4470 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4471 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4472 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4473 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4474 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi),
4475 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4476 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4477 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4478 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4479 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4480 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4481 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4482 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4483 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4484 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4485 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4486 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4487 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4488 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4489 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4490 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4491 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4492 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4493 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4494 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4495 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4496 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4497 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4498 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4499 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4500 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4501 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4502 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4503 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4504 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4505 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4506 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4507 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4508 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4509 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4510 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4511 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4512 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4513 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4514 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4515 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4516 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4517 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4518 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4519 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4520 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4521 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4522 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4523 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4524 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4525 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4526 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4527 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4528 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4529 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4530 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4531 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4532 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4533 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4534 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4535 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4536 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4537 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4538 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4539 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4540 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
4541 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
4542 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4543 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi),
4544 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_adlp_hdmi),
4545 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4546 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4547 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
4548 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4549 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4550 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4551 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4552 /* special ID for generic HDMI */
4553 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4556 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4558 MODULE_LICENSE("GPL");
4559 MODULE_DESCRIPTION("HDMI HD-audio codec");
4560 MODULE_ALIAS("snd-hda-codec-intelhdmi");
4561 MODULE_ALIAS("snd-hda-codec-nvhdmi");
4562 MODULE_ALIAS("snd-hda-codec-atihdmi");
4564 static struct hda_codec_driver hdmi_driver = {
4565 .id = snd_hda_id_hdmi,
4568 module_hda_codec_driver(hdmi_driver);