1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
13 * Wu Fengguang <wfg@linux.intel.com>
16 * Wu Fengguang <wfg@linux.intel.com>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/asoundef.h>
28 #include <sound/tlv.h>
29 #include <sound/hdaudio.h>
30 #include <sound/hda_i915.h>
31 #include <sound/hda_chmap.h>
32 #include <sound/hda_codec.h>
33 #include "hda_local.h"
35 #include "hda_controller.h"
37 static bool static_hdmi_pcm;
38 module_param(static_hdmi_pcm, bool, 0644);
39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
41 static bool enable_acomp = true;
42 module_param(enable_acomp, bool, 0444);
43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
45 static bool enable_silent_stream =
46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47 module_param(enable_silent_stream, bool, 0644);
48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
50 static bool enable_all_pins;
51 module_param(enable_all_pins, bool, 0444);
52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins");
54 struct hdmi_spec_per_cvt {
57 unsigned int channels_min;
58 unsigned int channels_max;
64 /* max. connections to a widget */
65 #define HDA_MAX_CONNECTIONS 32
67 struct hdmi_spec_per_pin {
70 /* pin idx, different device entries on the same pin use the same idx */
73 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
77 struct hda_codec *codec;
78 struct hdmi_eld sink_eld;
80 struct delayed_work work;
81 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
82 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
84 bool setup; /* the stream has been set up by prepare callback */
86 int channels; /* current number of channels */
88 bool chmap_set; /* channel-map override by ALSA API? */
89 unsigned char chmap[8]; /* ALSA API channel-map */
90 #ifdef CONFIG_SND_PROC_FS
91 struct snd_info_entry *proc_entry;
95 /* operations used by generic code that can be overridden by patches */
97 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
98 int dev_id, unsigned char *buf, int *eld_size);
100 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int ca, int active_channels, int conn_type);
104 /* enable/disable HBR (HD passthrough) */
105 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
106 int dev_id, bool hbr);
108 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
109 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
112 void (*pin_cvt_fixup)(struct hda_codec *codec,
113 struct hdmi_spec_per_pin *per_pin,
119 struct snd_jack *jack;
120 struct snd_kcontrol *eld_ctl;
124 struct hda_codec *codec;
126 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
127 hda_nid_t cvt_nids[4]; /* only for haswell fix */
130 * num_pins is the number of virtual pins
131 * for example, there are 3 pins, and each pin
132 * has 4 device entries, then the num_pins is 12
136 * num_nids is the number of real pins
137 * In the above example, num_nids is 3
141 * dev_num is the number of device entries
143 * In the above example, dev_num is 4
146 struct snd_array pins; /* struct hdmi_spec_per_pin */
147 struct hdmi_pcm pcm_rec[16];
148 struct mutex pcm_lock;
149 struct mutex bind_lock; /* for audio component binding */
150 /* pcm_bitmap means which pcms have been assigned to pins*/
151 unsigned long pcm_bitmap;
152 int pcm_used; /* counter of pcm_rec[] */
153 /* bitmap shows whether the pcm is opened in user space
154 * bit 0 means the first playback PCM (PCM3);
155 * bit 1 means the second playback PCM, and so on.
157 unsigned long pcm_in_use;
159 struct hdmi_eld temp_eld;
164 bool dyn_pcm_no_legacy;
165 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */
167 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
169 * Non-generic VIA/NVIDIA specific
171 struct hda_multi_out multiout;
172 struct hda_pcm_stream pcm_playback;
174 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
175 bool acomp_registered; /* audio component registered in this driver */
176 bool force_connect; /* force connectivity */
177 struct drm_audio_component_audio_ops drm_audio_ops;
178 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
180 struct hdac_chmap chmap;
181 hda_nid_t vendor_nid;
184 bool send_silent_stream; /* Flag to enable silent stream feature */
187 #ifdef CONFIG_SND_HDA_COMPONENT
188 static inline bool codec_has_acomp(struct hda_codec *codec)
190 struct hdmi_spec *spec = codec->spec;
191 return spec->use_acomp_notifier;
194 #define codec_has_acomp(codec) false
197 struct hdmi_audio_infoframe {
204 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
208 u8 LFEPBL01_LSV36_DM_INH7;
211 struct dp_audio_infoframe {
214 u8 ver; /* 0x11 << 2 */
216 u8 CC02_CT47; /* match with HDMI infoframe from this on */
220 u8 LFEPBL01_LSV36_DM_INH7;
223 union audio_infoframe {
224 struct hdmi_audio_infoframe hdmi;
225 struct dp_audio_infoframe dp;
233 #define get_pin(spec, idx) \
234 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
235 #define get_cvt(spec, idx) \
236 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
237 /* obtain hdmi_pcm object assigned to idx */
238 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
239 /* obtain hda_pcm object assigned to idx */
240 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
242 static int pin_id_to_pin_index(struct hda_codec *codec,
243 hda_nid_t pin_nid, int dev_id)
245 struct hdmi_spec *spec = codec->spec;
247 struct hdmi_spec_per_pin *per_pin;
250 * (dev_id == -1) means it is NON-MST pin
251 * return the first virtual pin on this port
256 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
257 per_pin = get_pin(spec, pin_idx);
258 if ((per_pin->pin_nid == pin_nid) &&
259 (per_pin->dev_id == dev_id))
263 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid);
267 static int hinfo_to_pcm_index(struct hda_codec *codec,
268 struct hda_pcm_stream *hinfo)
270 struct hdmi_spec *spec = codec->spec;
273 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
274 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
277 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
281 static int hinfo_to_pin_index(struct hda_codec *codec,
282 struct hda_pcm_stream *hinfo)
284 struct hdmi_spec *spec = codec->spec;
285 struct hdmi_spec_per_pin *per_pin;
288 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
289 per_pin = get_pin(spec, pin_idx);
291 per_pin->pcm->pcm->stream == hinfo)
295 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
296 hinfo_to_pcm_index(codec, hinfo));
300 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
304 struct hdmi_spec_per_pin *per_pin;
306 for (i = 0; i < spec->num_pins; i++) {
307 per_pin = get_pin(spec, i);
308 if (per_pin->pcm_idx == pcm_idx)
314 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
316 struct hdmi_spec *spec = codec->spec;
319 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
320 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
323 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid);
327 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
328 struct snd_ctl_elem_info *uinfo)
330 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
331 struct hdmi_spec *spec = codec->spec;
332 struct hdmi_spec_per_pin *per_pin;
333 struct hdmi_eld *eld;
336 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
338 pcm_idx = kcontrol->private_value;
339 mutex_lock(&spec->pcm_lock);
340 per_pin = pcm_idx_to_pin(spec, pcm_idx);
342 /* no pin is bound to the pcm */
346 eld = &per_pin->sink_eld;
347 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
350 mutex_unlock(&spec->pcm_lock);
354 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
357 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
358 struct hdmi_spec *spec = codec->spec;
359 struct hdmi_spec_per_pin *per_pin;
360 struct hdmi_eld *eld;
364 pcm_idx = kcontrol->private_value;
365 mutex_lock(&spec->pcm_lock);
366 per_pin = pcm_idx_to_pin(spec, pcm_idx);
368 /* no pin is bound to the pcm */
369 memset(ucontrol->value.bytes.data, 0,
370 ARRAY_SIZE(ucontrol->value.bytes.data));
374 eld = &per_pin->sink_eld;
375 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
376 eld->eld_size > ELD_MAX_SIZE) {
382 memset(ucontrol->value.bytes.data, 0,
383 ARRAY_SIZE(ucontrol->value.bytes.data));
385 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
389 mutex_unlock(&spec->pcm_lock);
393 static const struct snd_kcontrol_new eld_bytes_ctl = {
394 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
395 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
396 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
398 .info = hdmi_eld_ctl_info,
399 .get = hdmi_eld_ctl_get,
402 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
405 struct snd_kcontrol *kctl;
406 struct hdmi_spec *spec = codec->spec;
409 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
412 kctl->private_value = pcm_idx;
413 kctl->id.device = device;
415 /* no pin nid is associated with the kctl now
416 * tbd: associate pin nid to eld ctl later
418 err = snd_hda_ctl_add(codec, 0, kctl);
422 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
427 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
428 int *packet_index, int *byte_index)
432 val = snd_hda_codec_read(codec, pin_nid, 0,
433 AC_VERB_GET_HDMI_DIP_INDEX, 0);
435 *packet_index = val >> 5;
436 *byte_index = val & 0x1f;
440 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
441 int packet_index, int byte_index)
445 val = (packet_index << 5) | (byte_index & 0x1f);
447 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
450 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
453 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
456 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
458 struct hdmi_spec *spec = codec->spec;
462 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
463 snd_hda_codec_write(codec, pin_nid, 0,
464 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
466 if (spec->dyn_pin_out)
467 /* Disable pin out until stream is active */
470 /* Enable pin out: some machines with GM965 gets broken output
471 * when the pin is disabled or changed while using with HDMI
475 snd_hda_codec_write(codec, pin_nid, 0,
476 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
483 #ifdef CONFIG_SND_PROC_FS
484 static void print_eld_info(struct snd_info_entry *entry,
485 struct snd_info_buffer *buffer)
487 struct hdmi_spec_per_pin *per_pin = entry->private_data;
489 mutex_lock(&per_pin->lock);
490 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
491 mutex_unlock(&per_pin->lock);
494 static void write_eld_info(struct snd_info_entry *entry,
495 struct snd_info_buffer *buffer)
497 struct hdmi_spec_per_pin *per_pin = entry->private_data;
499 mutex_lock(&per_pin->lock);
500 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
501 mutex_unlock(&per_pin->lock);
504 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
507 struct hda_codec *codec = per_pin->codec;
508 struct snd_info_entry *entry;
511 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
512 err = snd_card_proc_new(codec->card, name, &entry);
516 snd_info_set_text_ops(entry, per_pin, print_eld_info);
517 entry->c.text.write = write_eld_info;
519 per_pin->proc_entry = entry;
524 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
526 if (!per_pin->codec->bus->shutdown) {
527 snd_info_free_entry(per_pin->proc_entry);
528 per_pin->proc_entry = NULL;
532 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
537 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
543 * Audio InfoFrame routines
547 * Enable Audio InfoFrame Transmission
549 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
552 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
553 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
558 * Disable Audio InfoFrame Transmission
560 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
563 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
564 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
568 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
570 #ifdef CONFIG_SND_DEBUG_VERBOSE
574 size = snd_hdmi_get_eld_size(codec, pin_nid);
575 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
577 for (i = 0; i < 8; i++) {
578 size = snd_hda_codec_read(codec, pin_nid, 0,
579 AC_VERB_GET_HDMI_DIP_SIZE, i);
580 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
585 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
591 for (i = 0; i < 8; i++) {
592 size = snd_hda_codec_read(codec, pin_nid, 0,
593 AC_VERB_GET_HDMI_DIP_SIZE, i);
597 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
598 for (j = 1; j < 1000; j++) {
599 hdmi_write_dip_byte(codec, pin_nid, 0x0);
600 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
602 codec_dbg(codec, "dip index %d: %d != %d\n",
604 if (bi == 0) /* byte index wrapped around */
608 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
614 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
616 u8 *bytes = (u8 *)hdmi_ai;
620 hdmi_ai->checksum = 0;
622 for (i = 0; i < sizeof(*hdmi_ai); i++)
625 hdmi_ai->checksum = -sum;
628 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
634 hdmi_debug_dip_size(codec, pin_nid);
635 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
637 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
638 for (i = 0; i < size; i++)
639 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
642 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
648 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
649 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
653 for (i = 0; i < size; i++) {
654 val = snd_hda_codec_read(codec, pin_nid, 0,
655 AC_VERB_GET_HDMI_DIP_DATA, 0);
663 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
664 int dev_id, unsigned char *buf, int *eld_size)
666 snd_hda_set_dev_select(codec, nid, dev_id);
668 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
671 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
672 hda_nid_t pin_nid, int dev_id,
673 int ca, int active_channels,
676 struct hdmi_spec *spec = codec->spec;
677 union audio_infoframe ai;
679 memset(&ai, 0, sizeof(ai));
680 if ((conn_type == 0) || /* HDMI */
681 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */
682 (conn_type == 1 && spec->nv_dp_workaround)) {
683 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
685 if (conn_type == 0) { /* HDMI */
686 hdmi_ai->type = 0x84;
689 } else {/* Nvidia DP */
690 hdmi_ai->type = 0x84;
692 hdmi_ai->len = 0x11 << 2;
694 hdmi_ai->CC02_CT47 = active_channels - 1;
696 hdmi_checksum_audio_infoframe(hdmi_ai);
697 } else if (conn_type == 1) { /* DisplayPort */
698 struct dp_audio_infoframe *dp_ai = &ai.dp;
702 dp_ai->ver = 0x11 << 2;
703 dp_ai->CC02_CT47 = active_channels - 1;
706 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid);
710 snd_hda_set_dev_select(codec, pin_nid, dev_id);
713 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
714 * sizeof(*dp_ai) to avoid partial match/update problems when
715 * the user switches between HDMI/DP monitors.
717 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
719 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n",
720 __func__, pin_nid, active_channels, ca);
721 hdmi_stop_infoframe_trans(codec, pin_nid);
722 hdmi_fill_audio_infoframe(codec, pin_nid,
723 ai.bytes, sizeof(ai));
724 hdmi_start_infoframe_trans(codec, pin_nid);
728 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
729 struct hdmi_spec_per_pin *per_pin,
732 struct hdmi_spec *spec = codec->spec;
733 struct hdac_chmap *chmap = &spec->chmap;
734 hda_nid_t pin_nid = per_pin->pin_nid;
735 int dev_id = per_pin->dev_id;
736 int channels = per_pin->channels;
738 struct hdmi_eld *eld;
744 snd_hda_set_dev_select(codec, pin_nid, dev_id);
746 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
747 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
748 snd_hda_codec_write(codec, pin_nid, 0,
749 AC_VERB_SET_AMP_GAIN_MUTE,
752 eld = &per_pin->sink_eld;
754 ca = snd_hdac_channel_allocation(&codec->core,
755 eld->info.spk_alloc, channels,
756 per_pin->chmap_set, non_pcm, per_pin->chmap);
758 active_channels = snd_hdac_get_active_channels(ca);
760 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
764 * always configure channel mapping, it may have been changed by the
765 * user in the meantime
767 snd_hdac_setup_channel_mapping(&spec->chmap,
768 pin_nid, non_pcm, ca, channels,
769 per_pin->chmap, per_pin->chmap_set);
771 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
772 ca, active_channels, eld->info.conn_type);
774 per_pin->non_pcm = non_pcm;
781 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
783 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
786 struct hdmi_spec *spec = codec->spec;
787 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
791 mutex_lock(&spec->pcm_lock);
792 hdmi_present_sense(get_pin(spec, pin_idx), 1);
793 mutex_unlock(&spec->pcm_lock);
796 static void jack_callback(struct hda_codec *codec,
797 struct hda_jack_callback *jack)
799 /* stop polling when notification is enabled */
800 if (codec_has_acomp(codec))
803 check_presence_and_report(codec, jack->nid, jack->dev_id);
806 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
807 struct hda_jack_tbl *jack)
809 jack->jack_dirty = 1;
812 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
813 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
814 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
816 check_presence_and_report(codec, jack->nid, jack->dev_id);
819 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
821 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
822 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
823 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
824 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
827 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
844 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
846 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
847 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
848 struct hda_jack_tbl *jack;
850 if (codec_has_acomp(codec))
855 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
857 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
859 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
863 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
868 hdmi_intrinsic_event(codec, res, jack);
870 hdmi_non_intrinsic_event(codec, res);
873 static void haswell_verify_D0(struct hda_codec *codec,
874 hda_nid_t cvt_nid, hda_nid_t nid)
878 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
879 * thus pins could only choose converter 0 for use. Make sure the
880 * converters are in correct power state */
881 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
882 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
884 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
885 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
888 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
889 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
890 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
898 /* HBR should be Non-PCM, 8 channels */
899 #define is_hbr_format(format) \
900 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
902 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
903 int dev_id, bool hbr)
905 int pinctl, new_pinctl;
907 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
908 snd_hda_set_dev_select(codec, pin_nid, dev_id);
909 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
910 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
913 return hbr ? -EINVAL : 0;
915 new_pinctl = pinctl & ~AC_PINCTL_EPT;
917 new_pinctl |= AC_PINCTL_EPT_HBR;
919 new_pinctl |= AC_PINCTL_EPT_NATIVE;
922 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
924 pinctl == new_pinctl ? "" : "new-",
927 if (pinctl != new_pinctl)
928 snd_hda_codec_write(codec, pin_nid, 0,
929 AC_VERB_SET_PIN_WIDGET_CONTROL,
937 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
938 hda_nid_t pin_nid, int dev_id,
939 u32 stream_tag, int format)
941 struct hdmi_spec *spec = codec->spec;
945 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
946 is_hbr_format(format));
949 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
953 if (spec->intel_hsw_fixup) {
956 * on recent platforms IEC Coding Type is required for HBR
957 * support, read current Digital Converter settings and set
958 * ICT bitfield if needed.
960 param = snd_hda_codec_read(codec, cvt_nid, 0,
961 AC_VERB_GET_DIGI_CONVERT_1, 0);
963 param = (param >> 16) & ~(AC_DIG3_ICT);
965 /* on recent platforms ICT mode is required for HBR support */
966 if (is_hbr_format(format))
969 snd_hda_codec_write(codec, cvt_nid, 0,
970 AC_VERB_SET_DIGI_CONVERT_3, param);
973 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
977 /* Try to find an available converter
978 * If pin_idx is less then zero, just try to find an available converter.
979 * Otherwise, try to find an available converter and get the cvt mux index
982 static int hdmi_choose_cvt(struct hda_codec *codec,
983 int pin_idx, int *cvt_id)
985 struct hdmi_spec *spec = codec->spec;
986 struct hdmi_spec_per_pin *per_pin;
987 struct hdmi_spec_per_cvt *per_cvt = NULL;
988 int cvt_idx, mux_idx = 0;
990 /* pin_idx < 0 means no pin will be bound to the converter */
994 per_pin = get_pin(spec, pin_idx);
996 if (per_pin && per_pin->silent_stream) {
997 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1003 /* Dynamically assign converter to stream */
1004 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1005 per_cvt = get_cvt(spec, cvt_idx);
1007 /* Must not already be assigned */
1008 if (per_cvt->assigned)
1010 if (per_pin == NULL)
1012 /* Must be in pin's mux's list of converters */
1013 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1014 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1016 /* Not in mux list */
1017 if (mux_idx == per_pin->num_mux_nids)
1022 /* No free converters */
1023 if (cvt_idx == spec->num_cvts)
1026 if (per_pin != NULL)
1027 per_pin->mux_idx = mux_idx;
1035 /* Assure the pin select the right convetor */
1036 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1037 struct hdmi_spec_per_pin *per_pin)
1039 hda_nid_t pin_nid = per_pin->pin_nid;
1042 mux_idx = per_pin->mux_idx;
1043 curr = snd_hda_codec_read(codec, pin_nid, 0,
1044 AC_VERB_GET_CONNECT_SEL, 0);
1045 if (curr != mux_idx)
1046 snd_hda_codec_write_cache(codec, pin_nid, 0,
1047 AC_VERB_SET_CONNECT_SEL,
1051 /* get the mux index for the converter of the pins
1052 * converter's mux index is the same for all pins on Intel platform
1054 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1059 for (i = 0; i < spec->num_cvts; i++)
1060 if (spec->cvt_nids[i] == cvt_nid)
1065 /* Intel HDMI workaround to fix audio routing issue:
1066 * For some Intel display codecs, pins share the same connection list.
1067 * So a conveter can be selected by multiple pins and playback on any of these
1068 * pins will generate sound on the external display, because audio flows from
1069 * the same converter to the display pipeline. Also muting one pin may make
1070 * other pins have no sound output.
1071 * So this function assures that an assigned converter for a pin is not selected
1072 * by any other pins.
1074 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1076 int dev_id, int mux_idx)
1078 struct hdmi_spec *spec = codec->spec;
1081 struct hdmi_spec_per_cvt *per_cvt;
1082 struct hdmi_spec_per_pin *per_pin;
1085 /* configure the pins connections */
1086 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1090 per_pin = get_pin(spec, pin_idx);
1092 * pin not connected to monitor
1093 * no need to operate on it
1098 if ((per_pin->pin_nid == pin_nid) &&
1099 (per_pin->dev_id == dev_id))
1103 * if per_pin->dev_id >= dev_num,
1104 * snd_hda_get_dev_select() will fail,
1105 * and the following operation is unpredictable.
1106 * So skip this situation.
1108 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1109 if (per_pin->dev_id >= dev_num)
1112 nid = per_pin->pin_nid;
1115 * Calling this function should not impact
1116 * on the device entry selection
1117 * So let's save the dev id for each pin,
1118 * and restore it when return
1120 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1121 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1122 curr = snd_hda_codec_read(codec, nid, 0,
1123 AC_VERB_GET_CONNECT_SEL, 0);
1124 if (curr != mux_idx) {
1125 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1130 /* choose an unassigned converter. The conveters in the
1131 * connection list are in the same order as in the codec.
1133 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1134 per_cvt = get_cvt(spec, cvt_idx);
1135 if (!per_cvt->assigned) {
1137 "choose cvt %d for pin NID 0x%x\n",
1139 snd_hda_codec_write_cache(codec, nid, 0,
1140 AC_VERB_SET_CONNECT_SEL,
1145 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1149 /* A wrapper of intel_not_share_asigned_cvt() */
1150 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1151 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1154 struct hdmi_spec *spec = codec->spec;
1156 /* On Intel platform, the mapping of converter nid to
1157 * mux index of the pins are always the same.
1158 * The pin nid may be 0, this means all pins will not
1159 * share the converter.
1161 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1163 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1166 /* skeleton caller of pin_cvt_fixup ops */
1167 static void pin_cvt_fixup(struct hda_codec *codec,
1168 struct hdmi_spec_per_pin *per_pin,
1171 struct hdmi_spec *spec = codec->spec;
1173 if (spec->ops.pin_cvt_fixup)
1174 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1177 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1178 * in dyn_pcm_assign mode.
1180 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1181 struct hda_codec *codec,
1182 struct snd_pcm_substream *substream)
1184 struct hdmi_spec *spec = codec->spec;
1185 struct snd_pcm_runtime *runtime = substream->runtime;
1186 int cvt_idx, pcm_idx;
1187 struct hdmi_spec_per_cvt *per_cvt = NULL;
1190 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1194 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1198 per_cvt = get_cvt(spec, cvt_idx);
1199 per_cvt->assigned = 1;
1200 hinfo->nid = per_cvt->cvt_nid;
1202 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1204 set_bit(pcm_idx, &spec->pcm_in_use);
1205 /* todo: setup spdif ctls assign */
1207 /* Initially set the converter's capabilities */
1208 hinfo->channels_min = per_cvt->channels_min;
1209 hinfo->channels_max = per_cvt->channels_max;
1210 hinfo->rates = per_cvt->rates;
1211 hinfo->formats = per_cvt->formats;
1212 hinfo->maxbps = per_cvt->maxbps;
1214 /* Store the updated parameters */
1215 runtime->hw.channels_min = hinfo->channels_min;
1216 runtime->hw.channels_max = hinfo->channels_max;
1217 runtime->hw.formats = hinfo->formats;
1218 runtime->hw.rates = hinfo->rates;
1220 snd_pcm_hw_constraint_step(substream->runtime, 0,
1221 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1228 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1229 struct hda_codec *codec,
1230 struct snd_pcm_substream *substream)
1232 struct hdmi_spec *spec = codec->spec;
1233 struct snd_pcm_runtime *runtime = substream->runtime;
1234 int pin_idx, cvt_idx, pcm_idx;
1235 struct hdmi_spec_per_pin *per_pin;
1236 struct hdmi_eld *eld;
1237 struct hdmi_spec_per_cvt *per_cvt = NULL;
1240 /* Validate hinfo */
1241 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1245 mutex_lock(&spec->pcm_lock);
1246 pin_idx = hinfo_to_pin_index(codec, hinfo);
1247 if (!spec->dyn_pcm_assign) {
1248 if (snd_BUG_ON(pin_idx < 0)) {
1253 /* no pin is assigned to the PCM
1254 * PA need pcm open successfully when probe
1257 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1262 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1266 per_cvt = get_cvt(spec, cvt_idx);
1267 /* Claim converter */
1268 per_cvt->assigned = 1;
1270 set_bit(pcm_idx, &spec->pcm_in_use);
1271 per_pin = get_pin(spec, pin_idx);
1272 per_pin->cvt_nid = per_cvt->cvt_nid;
1273 per_pin->silent_stream = false;
1274 hinfo->nid = per_cvt->cvt_nid;
1276 /* flip stripe flag for the assigned stream if supported */
1277 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1278 azx_stream(get_azx_dev(substream))->stripe = 1;
1280 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1281 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1282 AC_VERB_SET_CONNECT_SEL,
1285 /* configure unused pins to choose other converters */
1286 pin_cvt_fixup(codec, per_pin, 0);
1288 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1290 /* Initially set the converter's capabilities */
1291 hinfo->channels_min = per_cvt->channels_min;
1292 hinfo->channels_max = per_cvt->channels_max;
1293 hinfo->rates = per_cvt->rates;
1294 hinfo->formats = per_cvt->formats;
1295 hinfo->maxbps = per_cvt->maxbps;
1297 eld = &per_pin->sink_eld;
1298 /* Restrict capabilities by ELD if this isn't disabled */
1299 if (!static_hdmi_pcm && eld->eld_valid) {
1300 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1301 if (hinfo->channels_min > hinfo->channels_max ||
1302 !hinfo->rates || !hinfo->formats) {
1303 per_cvt->assigned = 0;
1305 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1311 /* Store the updated parameters */
1312 runtime->hw.channels_min = hinfo->channels_min;
1313 runtime->hw.channels_max = hinfo->channels_max;
1314 runtime->hw.formats = hinfo->formats;
1315 runtime->hw.rates = hinfo->rates;
1317 snd_pcm_hw_constraint_step(substream->runtime, 0,
1318 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1320 mutex_unlock(&spec->pcm_lock);
1325 * HDA/HDMI auto parsing
1327 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1329 struct hdmi_spec *spec = codec->spec;
1330 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1331 hda_nid_t pin_nid = per_pin->pin_nid;
1332 int dev_id = per_pin->dev_id;
1335 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1337 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n",
1338 pin_nid, get_wcaps(codec, pin_nid));
1342 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1344 if (spec->intel_hsw_fixup) {
1345 conns = spec->num_cvts;
1346 memcpy(per_pin->mux_nids, spec->cvt_nids,
1347 sizeof(hda_nid_t) * conns);
1349 conns = snd_hda_get_raw_connections(codec, pin_nid,
1351 HDA_MAX_CONNECTIONS);
1354 /* all the device entries on the same pin have the same conn list */
1355 per_pin->num_mux_nids = conns;
1360 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1361 struct hdmi_spec_per_pin *per_pin)
1365 /* on the new machines, try to assign the pcm slot dynamically,
1366 * not use the preferred fixed map (legacy way) anymore.
1368 if (spec->dyn_pcm_no_legacy)
1372 * generic_hdmi_build_pcms() may allocate extra PCMs on some
1373 * platforms (with maximum of 'num_nids + dev_num - 1')
1375 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
1376 * if m==0. This guarantees that dynamic pcm assignments are compatible
1377 * with the legacy static per_pin-pcm assignment that existed in the
1378 * days before DP-MST.
1380 * Intel DP-MST prefers this legacy behavior for compatibility, too.
1382 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
1385 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
1386 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1387 return per_pin->pin_nid_idx;
1389 i = spec->num_nids + (per_pin->dev_id - 1);
1390 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
1394 /* have a second try; check the area over num_nids */
1395 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1396 if (!test_bit(i, &spec->pcm_bitmap))
1401 /* the last try; check the empty slots in pins */
1402 for (i = 0; i < spec->pcm_used; i++) {
1403 if (!test_bit(i, &spec->pcm_bitmap))
1409 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1410 struct hdmi_spec_per_pin *per_pin)
1414 /* pcm already be attached to the pin */
1417 idx = hdmi_find_pcm_slot(spec, per_pin);
1420 per_pin->pcm_idx = idx;
1421 per_pin->pcm = get_hdmi_pcm(spec, idx);
1422 set_bit(idx, &spec->pcm_bitmap);
1425 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1426 struct hdmi_spec_per_pin *per_pin)
1430 /* pcm already be detached from the pin */
1433 idx = per_pin->pcm_idx;
1434 per_pin->pcm_idx = -1;
1435 per_pin->pcm = NULL;
1436 if (idx >= 0 && idx < spec->pcm_used)
1437 clear_bit(idx, &spec->pcm_bitmap);
1440 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1441 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1445 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1446 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1451 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1453 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1454 struct hdmi_spec_per_pin *per_pin)
1456 struct hda_codec *codec = per_pin->codec;
1457 struct hda_pcm *pcm;
1458 struct hda_pcm_stream *hinfo;
1459 struct snd_pcm_substream *substream;
1463 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1464 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1469 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1472 /* hdmi audio only uses playback and one substream */
1473 hinfo = pcm->stream;
1474 substream = pcm->pcm->streams[0].substream;
1476 per_pin->cvt_nid = hinfo->nid;
1478 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1479 if (mux_idx < per_pin->num_mux_nids) {
1480 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1482 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1483 AC_VERB_SET_CONNECT_SEL,
1486 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1488 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1489 if (substream->runtime)
1490 per_pin->channels = substream->runtime->channels;
1491 per_pin->setup = true;
1492 per_pin->mux_idx = mux_idx;
1494 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1497 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1498 struct hdmi_spec_per_pin *per_pin)
1500 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1501 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1503 per_pin->chmap_set = false;
1504 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1506 per_pin->setup = false;
1507 per_pin->channels = 0;
1510 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1511 struct hdmi_spec_per_pin *per_pin)
1513 struct hdmi_spec *spec = codec->spec;
1515 if (per_pin->pcm_idx >= 0)
1516 return spec->pcm_rec[per_pin->pcm_idx].jack;
1521 /* update per_pin ELD from the given new ELD;
1522 * setup info frame and notification accordingly
1523 * also notify ELD kctl and report jack status changes
1525 static void update_eld(struct hda_codec *codec,
1526 struct hdmi_spec_per_pin *per_pin,
1527 struct hdmi_eld *eld,
1530 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1531 struct hdmi_spec *spec = codec->spec;
1532 struct snd_jack *pcm_jack;
1533 bool old_eld_valid = pin_eld->eld_valid;
1537 if (eld->eld_valid) {
1538 if (eld->eld_size <= 0 ||
1539 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1540 eld->eld_size) < 0) {
1541 eld->eld_valid = false;
1543 schedule_delayed_work(&per_pin->work,
1544 msecs_to_jiffies(300));
1550 if (!eld->eld_valid || eld->eld_size <= 0) {
1551 eld->eld_valid = false;
1555 /* for monitor disconnection, save pcm_idx firstly */
1556 pcm_idx = per_pin->pcm_idx;
1559 * pcm_idx >=0 before update_eld() means it is in monitor
1560 * disconnected event. Jack must be fetched before update_eld().
1562 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1564 if (spec->dyn_pcm_assign) {
1565 if (eld->eld_valid) {
1566 hdmi_attach_hda_pcm(spec, per_pin);
1567 hdmi_pcm_setup_pin(spec, per_pin);
1569 hdmi_pcm_reset_pin(spec, per_pin);
1570 hdmi_detach_hda_pcm(spec, per_pin);
1573 /* if pcm_idx == -1, it means this is in monitor connection event
1574 * we can get the correct pcm_idx now.
1577 pcm_idx = per_pin->pcm_idx;
1579 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1582 snd_hdmi_show_eld(codec, &eld->info);
1584 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1585 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1586 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1587 if (pin_eld->eld_size != eld->eld_size ||
1588 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1589 eld->eld_size) != 0)
1593 pin_eld->monitor_present = eld->monitor_present;
1594 pin_eld->eld_valid = eld->eld_valid;
1595 pin_eld->eld_size = eld->eld_size;
1597 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1599 pin_eld->info = eld->info;
1603 * Re-setup pin and infoframe. This is needed e.g. when
1604 * - sink is first plugged-in
1605 * - transcoder can change during stream playback on Haswell
1606 * and this can make HW reset converter selection on a pin.
1608 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1609 pin_cvt_fixup(codec, per_pin, 0);
1610 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1613 if (eld_changed && pcm_idx >= 0)
1614 snd_ctl_notify(codec->card,
1615 SNDRV_CTL_EVENT_MASK_VALUE |
1616 SNDRV_CTL_EVENT_MASK_INFO,
1617 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1619 if (eld_changed && pcm_jack)
1620 snd_jack_report(pcm_jack,
1621 (eld->monitor_present && eld->eld_valid) ?
1622 SND_JACK_AVOUT : 0);
1625 /* update ELD and jack state via HD-audio verbs */
1626 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1629 struct hda_codec *codec = per_pin->codec;
1630 struct hdmi_spec *spec = codec->spec;
1631 struct hdmi_eld *eld = &spec->temp_eld;
1632 struct device *dev = hda_codec_dev(codec);
1633 hda_nid_t pin_nid = per_pin->pin_nid;
1634 int dev_id = per_pin->dev_id;
1636 * Always execute a GetPinSense verb here, even when called from
1637 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1638 * response's PD bit is not the real PD value, but indicates that
1639 * the real PD value changed. An older version of the HD-audio
1640 * specification worked this way. Hence, we just ignore the data in
1641 * the unsolicited response to avoid custom WARs.
1647 if (dev->power.runtime_status == RPM_SUSPENDING)
1651 ret = snd_hda_power_up_pm(codec);
1652 if (ret < 0 && pm_runtime_suspended(dev))
1655 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1657 mutex_lock(&per_pin->lock);
1658 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1659 if (eld->monitor_present)
1660 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1662 eld->eld_valid = false;
1665 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n",
1666 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1668 if (eld->eld_valid) {
1669 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1670 eld->eld_buffer, &eld->eld_size) < 0)
1671 eld->eld_valid = false;
1674 update_eld(codec, per_pin, eld, repoll);
1675 mutex_unlock(&per_pin->lock);
1677 snd_hda_power_down_pm(codec);
1680 #define I915_SILENT_RATE 48000
1681 #define I915_SILENT_CHANNELS 2
1682 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE
1683 #define I915_SILENT_FORMAT_BITS 16
1684 #define I915_SILENT_FMT_MASK 0xf
1686 static void silent_stream_enable(struct hda_codec *codec,
1687 struct hdmi_spec_per_pin *per_pin)
1689 struct hdmi_spec *spec = codec->spec;
1690 struct hdmi_spec_per_cvt *per_cvt;
1691 int cvt_idx, pin_idx, err;
1692 unsigned int format;
1694 mutex_lock(&per_pin->lock);
1696 if (per_pin->setup) {
1697 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
1701 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
1702 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1704 codec_err(codec, "hdmi: no free converter to enable silent mode\n");
1708 per_cvt = get_cvt(spec, cvt_idx);
1709 per_cvt->assigned = 1;
1710 per_pin->cvt_nid = per_cvt->cvt_nid;
1711 per_pin->silent_stream = true;
1713 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
1714 per_pin->pin_nid, per_cvt->cvt_nid);
1716 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1717 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1718 AC_VERB_SET_CONNECT_SEL,
1721 /* configure unused pins to choose other converters */
1722 pin_cvt_fixup(codec, per_pin, 0);
1724 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1725 per_pin->dev_id, I915_SILENT_RATE);
1727 /* trigger silent stream generation in hw */
1728 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS,
1729 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0);
1730 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
1731 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
1732 usleep_range(100, 200);
1733 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
1735 per_pin->channels = I915_SILENT_CHANNELS;
1736 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1739 mutex_unlock(&per_pin->lock);
1742 static void silent_stream_disable(struct hda_codec *codec,
1743 struct hdmi_spec_per_pin *per_pin)
1745 struct hdmi_spec *spec = codec->spec;
1746 struct hdmi_spec_per_cvt *per_cvt;
1749 mutex_lock(&per_pin->lock);
1750 if (!per_pin->silent_stream)
1753 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
1754 per_pin->pin_nid, per_pin->cvt_nid);
1756 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1757 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
1758 per_cvt = get_cvt(spec, cvt_idx);
1759 per_cvt->assigned = 0;
1762 per_pin->cvt_nid = 0;
1763 per_pin->silent_stream = false;
1766 mutex_unlock(&per_pin->lock);
1769 /* update ELD and jack state via audio component */
1770 static void sync_eld_via_acomp(struct hda_codec *codec,
1771 struct hdmi_spec_per_pin *per_pin)
1773 struct hdmi_spec *spec = codec->spec;
1774 struct hdmi_eld *eld = &spec->temp_eld;
1775 bool monitor_prev, monitor_next;
1777 mutex_lock(&per_pin->lock);
1778 eld->monitor_present = false;
1779 monitor_prev = per_pin->sink_eld.monitor_present;
1780 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1781 per_pin->dev_id, &eld->monitor_present,
1782 eld->eld_buffer, ELD_MAX_SIZE);
1783 eld->eld_valid = (eld->eld_size > 0);
1784 update_eld(codec, per_pin, eld, 0);
1785 monitor_next = per_pin->sink_eld.monitor_present;
1786 mutex_unlock(&per_pin->lock);
1789 * Power-up will call hdmi_present_sense, so the PM calls
1790 * have to be done without mutex held.
1793 if (spec->send_silent_stream) {
1796 if (!monitor_prev && monitor_next) {
1797 pm_ret = snd_hda_power_up_pm(codec);
1800 "Monitor plugged-in, Failed to power up codec ret=[%d]\n",
1802 silent_stream_enable(codec, per_pin);
1803 } else if (monitor_prev && !monitor_next) {
1804 silent_stream_disable(codec, per_pin);
1805 pm_ret = snd_hda_power_down_pm(codec);
1808 "Monitor plugged-out, Failed to power down codec ret=[%d]\n",
1814 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1816 struct hda_codec *codec = per_pin->codec;
1818 if (!codec_has_acomp(codec))
1819 hdmi_present_sense_via_verbs(per_pin, repoll);
1821 sync_eld_via_acomp(codec, per_pin);
1824 static void hdmi_repoll_eld(struct work_struct *work)
1826 struct hdmi_spec_per_pin *per_pin =
1827 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1828 struct hda_codec *codec = per_pin->codec;
1829 struct hdmi_spec *spec = codec->spec;
1830 struct hda_jack_tbl *jack;
1832 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1835 jack->jack_dirty = 1;
1837 if (per_pin->repoll_count++ > 6)
1838 per_pin->repoll_count = 0;
1840 mutex_lock(&spec->pcm_lock);
1841 hdmi_present_sense(per_pin, per_pin->repoll_count);
1842 mutex_unlock(&spec->pcm_lock);
1845 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1847 struct hdmi_spec *spec = codec->spec;
1848 unsigned int caps, config;
1850 struct hdmi_spec_per_pin *per_pin;
1854 caps = snd_hda_query_pin_caps(codec, pin_nid);
1855 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1859 * For DP MST audio, Configuration Default is the same for
1860 * all device entries on the same pin
1862 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1863 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1864 !spec->force_connect)
1868 * To simplify the implementation, malloc all
1869 * the virtual pins in the initialization statically
1871 if (spec->intel_hsw_fixup) {
1873 * On Intel platforms, device entries count returned
1874 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on
1875 * the type of receiver that is connected. Allocate pin
1876 * structures based on worst case.
1878 dev_num = spec->dev_num;
1879 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1880 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1882 * spec->dev_num is the maxinum number of device entries
1883 * among all the pins
1885 spec->dev_num = (spec->dev_num > dev_num) ?
1886 spec->dev_num : dev_num;
1889 * If the platform doesn't support DP MST,
1890 * manually set dev_num to 1. This means
1891 * the pin has only one device entry.
1897 for (i = 0; i < dev_num; i++) {
1898 pin_idx = spec->num_pins;
1899 per_pin = snd_array_new(&spec->pins);
1904 if (spec->dyn_pcm_assign) {
1905 per_pin->pcm = NULL;
1906 per_pin->pcm_idx = -1;
1908 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1909 per_pin->pcm_idx = pin_idx;
1911 per_pin->pin_nid = pin_nid;
1912 per_pin->pin_nid_idx = spec->num_nids;
1913 per_pin->dev_id = i;
1914 per_pin->non_pcm = false;
1915 snd_hda_set_dev_select(codec, pin_nid, i);
1916 err = hdmi_read_pin_conn(codec, pin_idx);
1926 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1928 struct hdmi_spec *spec = codec->spec;
1929 struct hdmi_spec_per_cvt *per_cvt;
1933 chans = get_wcaps(codec, cvt_nid);
1934 chans = get_wcaps_channels(chans);
1936 per_cvt = snd_array_new(&spec->cvts);
1940 per_cvt->cvt_nid = cvt_nid;
1941 per_cvt->channels_min = 2;
1943 per_cvt->channels_max = chans;
1944 if (chans > spec->chmap.channels_max)
1945 spec->chmap.channels_max = chans;
1948 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1955 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1956 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1962 static const struct snd_pci_quirk force_connect_list[] = {
1963 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1964 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1965 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
1966 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
1967 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
1971 static int hdmi_parse_codec(struct hda_codec *codec)
1973 struct hdmi_spec *spec = codec->spec;
1974 hda_nid_t start_nid;
1977 const struct snd_pci_quirk *q;
1979 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
1980 if (!start_nid || nodes < 0) {
1981 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1985 if (enable_all_pins)
1986 spec->force_connect = true;
1988 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
1991 spec->force_connect = true;
1994 * hdmi_add_pin() assumes total amount of converters to
1995 * be known, so first discover all converters
1997 for (i = 0; i < nodes; i++) {
1998 hda_nid_t nid = start_nid + i;
2000 caps = get_wcaps(codec, nid);
2002 if (!(caps & AC_WCAP_DIGITAL))
2005 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
2006 hdmi_add_cvt(codec, nid);
2009 /* discover audio pins */
2010 for (i = 0; i < nodes; i++) {
2011 hda_nid_t nid = start_nid + i;
2013 caps = get_wcaps(codec, nid);
2015 if (!(caps & AC_WCAP_DIGITAL))
2018 if (get_wcaps_type(caps) == AC_WID_PIN)
2019 hdmi_add_pin(codec, nid);
2027 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2029 struct hda_spdif_out *spdif;
2032 mutex_lock(&codec->spdif_mutex);
2033 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2034 /* Add sanity check to pass klockwork check.
2035 * This should never happen.
2037 if (WARN_ON(spdif == NULL)) {
2038 mutex_unlock(&codec->spdif_mutex);
2041 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2042 mutex_unlock(&codec->spdif_mutex);
2050 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2051 struct hda_codec *codec,
2052 unsigned int stream_tag,
2053 unsigned int format,
2054 struct snd_pcm_substream *substream)
2056 hda_nid_t cvt_nid = hinfo->nid;
2057 struct hdmi_spec *spec = codec->spec;
2059 struct hdmi_spec_per_pin *per_pin;
2060 struct snd_pcm_runtime *runtime = substream->runtime;
2065 mutex_lock(&spec->pcm_lock);
2066 pin_idx = hinfo_to_pin_index(codec, hinfo);
2067 if (spec->dyn_pcm_assign && pin_idx < 0) {
2068 /* when dyn_pcm_assign and pcm is not bound to a pin
2069 * skip pin setup and return 0 to make audio playback
2072 pin_cvt_fixup(codec, NULL, cvt_nid);
2073 snd_hda_codec_setup_stream(codec, cvt_nid,
2074 stream_tag, 0, format);
2078 if (snd_BUG_ON(pin_idx < 0)) {
2082 per_pin = get_pin(spec, pin_idx);
2084 /* Verify pin:cvt selections to avoid silent audio after S3.
2085 * After S3, the audio driver restores pin:cvt selections
2086 * but this can happen before gfx is ready and such selection
2087 * is overlooked by HW. Thus multiple pins can share a same
2088 * default convertor and mute control will affect each other,
2089 * which can cause a resumed audio playback become silent
2092 pin_cvt_fixup(codec, per_pin, 0);
2094 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2095 /* Todo: add DP1.2 MST audio support later */
2096 if (codec_has_acomp(codec))
2097 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
2098 per_pin->dev_id, runtime->rate);
2100 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
2101 mutex_lock(&per_pin->lock);
2102 per_pin->channels = substream->runtime->channels;
2103 per_pin->setup = true;
2105 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2106 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2108 snd_hda_codec_write(codec, cvt_nid, 0,
2109 AC_VERB_SET_STRIPE_CONTROL,
2113 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2114 mutex_unlock(&per_pin->lock);
2115 if (spec->dyn_pin_out) {
2116 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2118 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2119 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2120 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2121 AC_VERB_SET_PIN_WIDGET_CONTROL,
2125 /* snd_hda_set_dev_select() has been called before */
2126 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2127 per_pin->dev_id, stream_tag, format);
2129 mutex_unlock(&spec->pcm_lock);
2133 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2134 struct hda_codec *codec,
2135 struct snd_pcm_substream *substream)
2137 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2141 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2142 struct hda_codec *codec,
2143 struct snd_pcm_substream *substream)
2145 struct hdmi_spec *spec = codec->spec;
2146 int cvt_idx, pin_idx, pcm_idx;
2147 struct hdmi_spec_per_cvt *per_cvt;
2148 struct hdmi_spec_per_pin *per_pin;
2152 mutex_lock(&spec->pcm_lock);
2154 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2155 if (snd_BUG_ON(pcm_idx < 0)) {
2159 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2160 if (snd_BUG_ON(cvt_idx < 0)) {
2164 per_cvt = get_cvt(spec, cvt_idx);
2165 per_cvt->assigned = 0;
2168 azx_stream(get_azx_dev(substream))->stripe = 0;
2170 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2171 clear_bit(pcm_idx, &spec->pcm_in_use);
2172 pin_idx = hinfo_to_pin_index(codec, hinfo);
2173 if (spec->dyn_pcm_assign && pin_idx < 0)
2176 if (snd_BUG_ON(pin_idx < 0)) {
2180 per_pin = get_pin(spec, pin_idx);
2182 if (spec->dyn_pin_out) {
2183 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2185 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2186 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2187 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2188 AC_VERB_SET_PIN_WIDGET_CONTROL,
2192 mutex_lock(&per_pin->lock);
2193 per_pin->chmap_set = false;
2194 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2196 per_pin->setup = false;
2197 per_pin->channels = 0;
2198 mutex_unlock(&per_pin->lock);
2202 mutex_unlock(&spec->pcm_lock);
2207 static const struct hda_pcm_ops generic_ops = {
2208 .open = hdmi_pcm_open,
2209 .close = hdmi_pcm_close,
2210 .prepare = generic_hdmi_playback_pcm_prepare,
2211 .cleanup = generic_hdmi_playback_pcm_cleanup,
2214 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2216 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2217 struct hdmi_spec *spec = codec->spec;
2218 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2223 return per_pin->sink_eld.info.spk_alloc;
2226 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2227 unsigned char *chmap)
2229 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2230 struct hdmi_spec *spec = codec->spec;
2231 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2233 /* chmap is already set to 0 in caller */
2237 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2240 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2241 unsigned char *chmap, int prepared)
2243 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2244 struct hdmi_spec *spec = codec->spec;
2245 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2249 mutex_lock(&per_pin->lock);
2250 per_pin->chmap_set = true;
2251 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2253 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2254 mutex_unlock(&per_pin->lock);
2257 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2259 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2260 struct hdmi_spec *spec = codec->spec;
2261 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2263 return per_pin ? true:false;
2266 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2268 struct hdmi_spec *spec = codec->spec;
2272 * for non-mst mode, pcm number is the same as before
2273 * for DP MST mode without extra PCM, pcm number is same
2274 * for DP MST mode with extra PCMs, pcm number is
2275 * (nid number + dev_num - 1)
2276 * dev_num is the device entry number in a pin
2279 if (spec->dyn_pcm_no_legacy && codec->mst_no_extra_pcms)
2280 pcm_num = spec->num_cvts;
2281 else if (codec->mst_no_extra_pcms)
2282 pcm_num = spec->num_nids;
2284 pcm_num = spec->num_nids + spec->dev_num - 1;
2286 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2288 for (idx = 0; idx < pcm_num; idx++) {
2289 struct hda_pcm *info;
2290 struct hda_pcm_stream *pstr;
2292 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2296 spec->pcm_rec[idx].pcm = info;
2298 info->pcm_type = HDA_PCM_TYPE_HDMI;
2299 info->own_chmap = true;
2301 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2302 pstr->substreams = 1;
2303 pstr->ops = generic_ops;
2304 /* pcm number is less than 16 */
2305 if (spec->pcm_used >= 16)
2307 /* other pstr fields are set in open */
2313 static void free_hdmi_jack_priv(struct snd_jack *jack)
2315 struct hdmi_pcm *pcm = jack->private_data;
2320 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2322 char hdmi_str[32] = "HDMI/DP";
2323 struct hdmi_spec *spec = codec->spec;
2324 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
2325 struct snd_jack *jack;
2326 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2330 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2331 if (!spec->dyn_pcm_assign &&
2332 !is_jack_detectable(codec, per_pin->pin_nid))
2333 strncat(hdmi_str, " Phantom",
2334 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2336 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2341 spec->pcm_rec[pcm_idx].jack = jack;
2342 jack->private_data = &spec->pcm_rec[pcm_idx];
2343 jack->private_free = free_hdmi_jack_priv;
2347 static int generic_hdmi_build_controls(struct hda_codec *codec)
2349 struct hdmi_spec *spec = codec->spec;
2351 int pin_idx, pcm_idx;
2353 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2354 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2355 /* no PCM: mark this for skipping permanently */
2356 set_bit(pcm_idx, &spec->pcm_bitmap);
2360 err = generic_hdmi_build_jack(codec, pcm_idx);
2364 /* create the spdif for each pcm
2365 * pin will be bound when monitor is connected
2367 if (spec->dyn_pcm_assign)
2368 err = snd_hda_create_dig_out_ctls(codec,
2369 0, spec->cvt_nids[0],
2372 struct hdmi_spec_per_pin *per_pin =
2373 get_pin(spec, pcm_idx);
2374 err = snd_hda_create_dig_out_ctls(codec,
2376 per_pin->mux_nids[0],
2381 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2383 dev = get_pcm_rec(spec, pcm_idx)->device;
2384 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2385 /* add control for ELD Bytes */
2386 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2392 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2393 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2394 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2396 pin_eld->eld_valid = false;
2397 hdmi_present_sense(per_pin, 0);
2400 /* add channel maps */
2401 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2402 struct hda_pcm *pcm;
2404 pcm = get_pcm_rec(spec, pcm_idx);
2405 if (!pcm || !pcm->pcm)
2407 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2415 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2417 struct hdmi_spec *spec = codec->spec;
2420 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2421 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2423 per_pin->codec = codec;
2424 mutex_init(&per_pin->lock);
2425 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2426 eld_proc_new(per_pin, pin_idx);
2431 static int generic_hdmi_init(struct hda_codec *codec)
2433 struct hdmi_spec *spec = codec->spec;
2436 mutex_lock(&spec->bind_lock);
2437 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2438 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2439 hda_nid_t pin_nid = per_pin->pin_nid;
2440 int dev_id = per_pin->dev_id;
2442 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2443 hdmi_init_pin(codec, pin_nid);
2444 if (codec_has_acomp(codec))
2446 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2449 mutex_unlock(&spec->bind_lock);
2453 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2455 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2456 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2459 static void hdmi_array_free(struct hdmi_spec *spec)
2461 snd_array_free(&spec->pins);
2462 snd_array_free(&spec->cvts);
2465 static void generic_spec_free(struct hda_codec *codec)
2467 struct hdmi_spec *spec = codec->spec;
2470 hdmi_array_free(spec);
2474 codec->dp_mst = false;
2477 static void generic_hdmi_free(struct hda_codec *codec)
2479 struct hdmi_spec *spec = codec->spec;
2480 int pin_idx, pcm_idx;
2482 if (spec->acomp_registered) {
2483 snd_hdac_acomp_exit(&codec->bus->core);
2484 } else if (codec_has_acomp(codec)) {
2485 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2487 codec->relaxed_resume = 0;
2489 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2490 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2491 cancel_delayed_work_sync(&per_pin->work);
2492 eld_proc_free(per_pin);
2495 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2496 if (spec->pcm_rec[pcm_idx].jack == NULL)
2498 if (spec->dyn_pcm_assign)
2499 snd_device_free(codec->card,
2500 spec->pcm_rec[pcm_idx].jack);
2502 spec->pcm_rec[pcm_idx].jack = NULL;
2505 generic_spec_free(codec);
2509 static int generic_hdmi_suspend(struct hda_codec *codec)
2511 struct hdmi_spec *spec = codec->spec;
2514 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2515 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2516 cancel_delayed_work_sync(&per_pin->work);
2521 static int generic_hdmi_resume(struct hda_codec *codec)
2523 struct hdmi_spec *spec = codec->spec;
2526 codec->patch_ops.init(codec);
2527 snd_hda_regmap_sync(codec);
2529 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2530 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2531 hdmi_present_sense(per_pin, 1);
2537 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2538 .init = generic_hdmi_init,
2539 .free = generic_hdmi_free,
2540 .build_pcms = generic_hdmi_build_pcms,
2541 .build_controls = generic_hdmi_build_controls,
2542 .unsol_event = hdmi_unsol_event,
2544 .suspend = generic_hdmi_suspend,
2545 .resume = generic_hdmi_resume,
2549 static const struct hdmi_ops generic_standard_hdmi_ops = {
2550 .pin_get_eld = hdmi_pin_get_eld,
2551 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2552 .pin_hbr_setup = hdmi_pin_hbr_setup,
2553 .setup_stream = hdmi_setup_stream,
2556 /* allocate codec->spec and assign/initialize generic parser ops */
2557 static int alloc_generic_hdmi(struct hda_codec *codec)
2559 struct hdmi_spec *spec;
2561 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2565 spec->codec = codec;
2566 spec->ops = generic_standard_hdmi_ops;
2567 spec->dev_num = 1; /* initialize to 1 */
2568 mutex_init(&spec->pcm_lock);
2569 mutex_init(&spec->bind_lock);
2570 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2572 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2573 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2574 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2575 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
2578 hdmi_array_init(spec, 4);
2580 codec->patch_ops = generic_hdmi_patch_ops;
2585 /* generic HDMI parser */
2586 static int patch_generic_hdmi(struct hda_codec *codec)
2590 err = alloc_generic_hdmi(codec);
2594 err = hdmi_parse_codec(codec);
2596 generic_spec_free(codec);
2600 generic_hdmi_init_per_pins(codec);
2605 * generic audio component binding
2608 /* turn on / off the unsol event jack detection dynamically */
2609 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2610 int dev_id, bool use_acomp)
2612 struct hda_jack_tbl *tbl;
2614 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2616 /* clear unsol even if component notifier is used, or re-enable
2617 * if notifier is cleared
2619 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2620 snd_hda_codec_write_cache(codec, nid, 0,
2621 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2625 /* set up / clear component notifier dynamically */
2626 static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2629 struct hdmi_spec *spec;
2632 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2633 mutex_lock(&spec->bind_lock);
2634 spec->use_acomp_notifier = use_acomp;
2635 spec->codec->relaxed_resume = use_acomp;
2636 spec->codec->bus->keep_power = 0;
2637 /* reprogram each jack detection logic depending on the notifier */
2638 for (i = 0; i < spec->num_pins; i++)
2639 reprogram_jack_detect(spec->codec,
2640 get_pin(spec, i)->pin_nid,
2641 get_pin(spec, i)->dev_id,
2643 mutex_unlock(&spec->bind_lock);
2646 /* enable / disable the notifier via master bind / unbind */
2647 static int generic_acomp_master_bind(struct device *dev,
2648 struct drm_audio_component *acomp)
2650 generic_acomp_notifier_set(acomp, true);
2654 static void generic_acomp_master_unbind(struct device *dev,
2655 struct drm_audio_component *acomp)
2657 generic_acomp_notifier_set(acomp, false);
2660 /* check whether both HD-audio and DRM PCI devices belong to the same bus */
2661 static int match_bound_vga(struct device *dev, int subtype, void *data)
2663 struct hdac_bus *bus = data;
2664 struct pci_dev *pci, *master;
2666 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2668 master = to_pci_dev(bus->dev);
2669 pci = to_pci_dev(dev);
2670 return master->bus == pci->bus;
2673 /* audio component notifier for AMD/Nvidia HDMI codecs */
2674 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2676 struct hda_codec *codec = audio_ptr;
2677 struct hdmi_spec *spec = codec->spec;
2678 hda_nid_t pin_nid = spec->port2pin(codec, port);
2682 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2684 /* skip notification during system suspend (but not in runtime PM);
2685 * the state will be updated at resume
2687 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2690 check_presence_and_report(codec, pin_nid, dev_id);
2693 /* set up the private drm_audio_ops from the template */
2694 static void setup_drm_audio_ops(struct hda_codec *codec,
2695 const struct drm_audio_component_audio_ops *ops)
2697 struct hdmi_spec *spec = codec->spec;
2699 spec->drm_audio_ops.audio_ptr = codec;
2700 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2701 * will call pin_eld_notify with using audio_ptr pointer
2702 * We need make sure audio_ptr is really setup
2705 spec->drm_audio_ops.pin2port = ops->pin2port;
2706 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2707 spec->drm_audio_ops.master_bind = ops->master_bind;
2708 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2711 /* initialize the generic HDMI audio component */
2712 static void generic_acomp_init(struct hda_codec *codec,
2713 const struct drm_audio_component_audio_ops *ops,
2714 int (*port2pin)(struct hda_codec *, int))
2716 struct hdmi_spec *spec = codec->spec;
2718 if (!enable_acomp) {
2719 codec_info(codec, "audio component disabled by module option\n");
2723 spec->port2pin = port2pin;
2724 setup_drm_audio_ops(codec, ops);
2725 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2726 match_bound_vga, 0)) {
2727 spec->acomp_registered = true;
2732 * Intel codec parsers and helpers
2735 #define INTEL_GET_VENDOR_VERB 0xf81
2736 #define INTEL_SET_VENDOR_VERB 0x781
2737 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2738 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2740 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2743 unsigned int vendor_param;
2744 struct hdmi_spec *spec = codec->spec;
2746 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2747 INTEL_GET_VENDOR_VERB, 0);
2748 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2751 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2752 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2753 INTEL_SET_VENDOR_VERB, vendor_param);
2754 if (vendor_param == -1)
2758 snd_hda_codec_update_widgets(codec);
2761 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2763 unsigned int vendor_param;
2764 struct hdmi_spec *spec = codec->spec;
2766 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2767 INTEL_GET_VENDOR_VERB, 0);
2768 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2771 /* enable DP1.2 mode */
2772 vendor_param |= INTEL_EN_DP12;
2773 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2774 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2775 INTEL_SET_VENDOR_VERB, vendor_param);
2778 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2779 * Otherwise you may get severe h/w communication errors.
2781 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2782 unsigned int power_state)
2784 if (power_state == AC_PWRST_D0) {
2785 intel_haswell_enable_all_pins(codec, false);
2786 intel_haswell_fixup_enable_dp12(codec);
2789 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2790 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2793 /* There is a fixed mapping between audio pin node and display port.
2794 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2795 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2796 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2797 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2800 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2801 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2802 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2804 static int intel_base_nid(struct hda_codec *codec)
2806 switch (codec->core.vendor_id) {
2807 case 0x80860054: /* ILK */
2808 case 0x80862804: /* ILK */
2809 case 0x80862882: /* VLV */
2816 static int intel_pin2port(void *audio_ptr, int pin_nid)
2818 struct hda_codec *codec = audio_ptr;
2819 struct hdmi_spec *spec = codec->spec;
2822 if (!spec->port_num) {
2823 base_nid = intel_base_nid(codec);
2824 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2826 return pin_nid - base_nid + 1;
2830 * looking for the pin number in the mapping table and return
2831 * the index which indicate the port number
2833 for (i = 0; i < spec->port_num; i++) {
2834 if (pin_nid == spec->port_map[i])
2838 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
2842 static int intel_port2pin(struct hda_codec *codec, int port)
2844 struct hdmi_spec *spec = codec->spec;
2846 if (!spec->port_num) {
2847 /* we assume only from port-B to port-D */
2848 if (port < 1 || port > 3)
2850 return port + intel_base_nid(codec) - 1;
2853 if (port < 0 || port >= spec->port_num)
2855 return spec->port_map[port];
2858 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2860 struct hda_codec *codec = audio_ptr;
2864 pin_nid = intel_port2pin(codec, port);
2867 /* skip notification during system suspend (but not in runtime PM);
2868 * the state will be updated at resume
2870 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2873 snd_hdac_i915_set_bclk(&codec->bus->core);
2874 check_presence_and_report(codec, pin_nid, dev_id);
2877 static const struct drm_audio_component_audio_ops intel_audio_ops = {
2878 .pin2port = intel_pin2port,
2879 .pin_eld_notify = intel_pin_eld_notify,
2882 /* register i915 component pin_eld_notify callback */
2883 static void register_i915_notifier(struct hda_codec *codec)
2885 struct hdmi_spec *spec = codec->spec;
2887 spec->use_acomp_notifier = true;
2888 spec->port2pin = intel_port2pin;
2889 setup_drm_audio_ops(codec, &intel_audio_ops);
2890 snd_hdac_acomp_register_notifier(&codec->bus->core,
2891 &spec->drm_audio_ops);
2892 /* no need for forcible resume for jack check thanks to notifier */
2893 codec->relaxed_resume = 1;
2896 /* setup_stream ops override for HSW+ */
2897 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2898 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2901 haswell_verify_D0(codec, cvt_nid, pin_nid);
2902 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2903 stream_tag, format);
2906 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2907 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2908 struct hdmi_spec_per_pin *per_pin,
2912 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2913 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2915 intel_verify_pin_cvt_connect(codec, per_pin);
2916 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2917 per_pin->dev_id, per_pin->mux_idx);
2919 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2923 /* precondition and allocation for Intel codecs */
2924 static int alloc_intel_hdmi(struct hda_codec *codec)
2928 /* requires i915 binding */
2929 if (!codec->bus->core.audio_component) {
2930 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2931 /* set probe_id here to prevent generic fallback binding */
2932 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2936 err = alloc_generic_hdmi(codec);
2939 /* no need to handle unsol events */
2940 codec->patch_ops.unsol_event = NULL;
2944 /* parse and post-process for Intel codecs */
2945 static int parse_intel_hdmi(struct hda_codec *codec)
2947 int err, retries = 3;
2950 err = hdmi_parse_codec(codec);
2951 } while (err < 0 && retries--);
2954 generic_spec_free(codec);
2958 generic_hdmi_init_per_pins(codec);
2959 register_i915_notifier(codec);
2963 /* Intel Haswell and onwards; audio component with eld notifier */
2964 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2965 const int *port_map, int port_num, int dev_num,
2966 bool send_silent_stream)
2968 struct hdmi_spec *spec;
2971 err = alloc_intel_hdmi(codec);
2975 codec->dp_mst = true;
2976 spec->dyn_pcm_assign = true;
2977 spec->vendor_nid = vendor_nid;
2978 spec->port_map = port_map;
2979 spec->port_num = port_num;
2980 spec->intel_hsw_fixup = true;
2981 spec->dev_num = dev_num;
2983 intel_haswell_enable_all_pins(codec, true);
2984 intel_haswell_fixup_enable_dp12(codec);
2986 codec->display_power_control = 1;
2988 codec->patch_ops.set_power_state = haswell_set_power_state;
2989 codec->depop_delay = 0;
2990 codec->auto_runtime_pm = 1;
2992 spec->ops.setup_stream = i915_hsw_setup_stream;
2993 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2996 * Enable silent stream feature, if it is enabled via
2997 * module param or Kconfig option
2999 if (send_silent_stream)
3000 spec->send_silent_stream = true;
3002 return parse_intel_hdmi(codec);
3005 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
3007 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
3008 enable_silent_stream);
3011 static int patch_i915_glk_hdmi(struct hda_codec *codec)
3014 * Silent stream calls audio component .get_power() from
3015 * .pin_eld_notify(). On GLK this will deadlock in i915 due
3016 * to the audio vs. CDCLK workaround.
3018 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
3021 static int patch_i915_icl_hdmi(struct hda_codec *codec)
3024 * pin to port mapping table where the value indicate the pin number and
3025 * the index indicate the port number.
3027 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
3029 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
3030 enable_silent_stream);
3033 static int patch_i915_tgl_hdmi(struct hda_codec *codec)
3036 * pin to port mapping table where the value indicate the pin number and
3037 * the index indicate the port number.
3039 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
3042 ret = intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
3043 enable_silent_stream);
3045 struct hdmi_spec *spec = codec->spec;
3047 spec->dyn_pcm_no_legacy = true;
3053 /* Intel Baytrail and Braswell; with eld notifier */
3054 static int patch_i915_byt_hdmi(struct hda_codec *codec)
3056 struct hdmi_spec *spec;
3059 err = alloc_intel_hdmi(codec);
3064 /* For Valleyview/Cherryview, only the display codec is in the display
3065 * power well and can use link_power ops to request/release the power.
3067 codec->display_power_control = 1;
3069 codec->depop_delay = 0;
3070 codec->auto_runtime_pm = 1;
3072 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3074 return parse_intel_hdmi(codec);
3077 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
3078 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
3082 err = alloc_intel_hdmi(codec);
3085 return parse_intel_hdmi(codec);
3089 * Shared non-generic implementations
3092 static int simple_playback_build_pcms(struct hda_codec *codec)
3094 struct hdmi_spec *spec = codec->spec;
3095 struct hda_pcm *info;
3097 struct hda_pcm_stream *pstr;
3098 struct hdmi_spec_per_cvt *per_cvt;
3100 per_cvt = get_cvt(spec, 0);
3101 chans = get_wcaps(codec, per_cvt->cvt_nid);
3102 chans = get_wcaps_channels(chans);
3104 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
3107 spec->pcm_rec[0].pcm = info;
3108 info->pcm_type = HDA_PCM_TYPE_HDMI;
3109 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
3110 *pstr = spec->pcm_playback;
3111 pstr->nid = per_cvt->cvt_nid;
3112 if (pstr->channels_max <= 2 && chans && chans <= 16)
3113 pstr->channels_max = chans;
3118 /* unsolicited event for jack sensing */
3119 static void simple_hdmi_unsol_event(struct hda_codec *codec,
3122 snd_hda_jack_set_dirty_all(codec);
3123 snd_hda_jack_report_sync(codec);
3126 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
3127 * as long as spec->pins[] is set correctly
3129 #define simple_hdmi_build_jack generic_hdmi_build_jack
3131 static int simple_playback_build_controls(struct hda_codec *codec)
3133 struct hdmi_spec *spec = codec->spec;
3134 struct hdmi_spec_per_cvt *per_cvt;
3137 per_cvt = get_cvt(spec, 0);
3138 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3143 return simple_hdmi_build_jack(codec, 0);
3146 static int simple_playback_init(struct hda_codec *codec)
3148 struct hdmi_spec *spec = codec->spec;
3149 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3150 hda_nid_t pin = per_pin->pin_nid;
3152 snd_hda_codec_write(codec, pin, 0,
3153 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3154 /* some codecs require to unmute the pin */
3155 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3156 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3158 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3162 static void simple_playback_free(struct hda_codec *codec)
3164 struct hdmi_spec *spec = codec->spec;
3166 hdmi_array_free(spec);
3171 * Nvidia specific implementations
3174 #define Nv_VERB_SET_Channel_Allocation 0xF79
3175 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3176 #define Nv_VERB_SET_Audio_Protection_On 0xF98
3177 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
3179 #define nvhdmi_master_con_nid_7x 0x04
3180 #define nvhdmi_master_pin_nid_7x 0x05
3182 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3183 /*front, rear, clfe, rear_surr */
3187 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3188 /* set audio protect on */
3189 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3190 /* enable digital output on pin widget */
3191 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3195 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3196 /* set audio protect on */
3197 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3198 /* enable digital output on pin widget */
3199 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3200 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3201 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3202 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3203 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3207 #ifdef LIMITED_RATE_FMT_SUPPORT
3208 /* support only the safe format and rate */
3209 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3210 #define SUPPORTED_MAXBPS 16
3211 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3213 /* support all rates and formats */
3214 #define SUPPORTED_RATES \
3215 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3216 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3217 SNDRV_PCM_RATE_192000)
3218 #define SUPPORTED_MAXBPS 24
3219 #define SUPPORTED_FORMATS \
3220 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3223 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3225 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3229 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3231 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3235 static const unsigned int channels_2_6_8[] = {
3239 static const unsigned int channels_2_8[] = {
3243 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3244 .count = ARRAY_SIZE(channels_2_6_8),
3245 .list = channels_2_6_8,
3249 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3250 .count = ARRAY_SIZE(channels_2_8),
3251 .list = channels_2_8,
3255 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3256 struct hda_codec *codec,
3257 struct snd_pcm_substream *substream)
3259 struct hdmi_spec *spec = codec->spec;
3260 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3262 switch (codec->preset->vendor_id) {
3267 hw_constraints_channels = &hw_constraints_2_8_channels;
3270 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3276 if (hw_constraints_channels != NULL) {
3277 snd_pcm_hw_constraint_list(substream->runtime, 0,
3278 SNDRV_PCM_HW_PARAM_CHANNELS,
3279 hw_constraints_channels);
3281 snd_pcm_hw_constraint_step(substream->runtime, 0,
3282 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3285 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3288 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3289 struct hda_codec *codec,
3290 struct snd_pcm_substream *substream)
3292 struct hdmi_spec *spec = codec->spec;
3293 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3296 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3297 struct hda_codec *codec,
3298 unsigned int stream_tag,
3299 unsigned int format,
3300 struct snd_pcm_substream *substream)
3302 struct hdmi_spec *spec = codec->spec;
3303 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3304 stream_tag, format, substream);
3307 static const struct hda_pcm_stream simple_pcm_playback = {
3312 .open = simple_playback_pcm_open,
3313 .close = simple_playback_pcm_close,
3314 .prepare = simple_playback_pcm_prepare
3318 static const struct hda_codec_ops simple_hdmi_patch_ops = {
3319 .build_controls = simple_playback_build_controls,
3320 .build_pcms = simple_playback_build_pcms,
3321 .init = simple_playback_init,
3322 .free = simple_playback_free,
3323 .unsol_event = simple_hdmi_unsol_event,
3326 static int patch_simple_hdmi(struct hda_codec *codec,
3327 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3329 struct hdmi_spec *spec;
3330 struct hdmi_spec_per_cvt *per_cvt;
3331 struct hdmi_spec_per_pin *per_pin;
3333 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3337 spec->codec = codec;
3339 hdmi_array_init(spec, 1);
3341 spec->multiout.num_dacs = 0; /* no analog */
3342 spec->multiout.max_channels = 2;
3343 spec->multiout.dig_out_nid = cvt_nid;
3346 per_pin = snd_array_new(&spec->pins);
3347 per_cvt = snd_array_new(&spec->cvts);
3348 if (!per_pin || !per_cvt) {
3349 simple_playback_free(codec);
3352 per_cvt->cvt_nid = cvt_nid;
3353 per_pin->pin_nid = pin_nid;
3354 spec->pcm_playback = simple_pcm_playback;
3356 codec->patch_ops = simple_hdmi_patch_ops;
3361 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3364 unsigned int chanmask;
3365 int chan = channels ? (channels - 1) : 1;
3384 /* Set the audio infoframe channel allocation and checksum fields. The
3385 * channel count is computed implicitly by the hardware. */
3386 snd_hda_codec_write(codec, 0x1, 0,
3387 Nv_VERB_SET_Channel_Allocation, chanmask);
3389 snd_hda_codec_write(codec, 0x1, 0,
3390 Nv_VERB_SET_Info_Frame_Checksum,
3391 (0x71 - chan - chanmask));
3394 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3395 struct hda_codec *codec,
3396 struct snd_pcm_substream *substream)
3398 struct hdmi_spec *spec = codec->spec;
3401 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3402 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3403 for (i = 0; i < 4; i++) {
3404 /* set the stream id */
3405 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3406 AC_VERB_SET_CHANNEL_STREAMID, 0);
3407 /* set the stream format */
3408 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3409 AC_VERB_SET_STREAM_FORMAT, 0);
3412 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3413 * streams are disabled. */
3414 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3416 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3419 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3420 struct hda_codec *codec,
3421 unsigned int stream_tag,
3422 unsigned int format,
3423 struct snd_pcm_substream *substream)
3426 unsigned int dataDCC2, channel_id;
3428 struct hdmi_spec *spec = codec->spec;
3429 struct hda_spdif_out *spdif;
3430 struct hdmi_spec_per_cvt *per_cvt;
3432 mutex_lock(&codec->spdif_mutex);
3433 per_cvt = get_cvt(spec, 0);
3434 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3436 chs = substream->runtime->channels;
3440 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3441 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3442 snd_hda_codec_write(codec,
3443 nvhdmi_master_con_nid_7x,
3445 AC_VERB_SET_DIGI_CONVERT_1,
3446 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3448 /* set the stream id */
3449 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3450 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3452 /* set the stream format */
3453 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3454 AC_VERB_SET_STREAM_FORMAT, format);
3456 /* turn on again (if needed) */
3457 /* enable and set the channel status audio/data flag */
3458 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3459 snd_hda_codec_write(codec,
3460 nvhdmi_master_con_nid_7x,
3462 AC_VERB_SET_DIGI_CONVERT_1,
3463 spdif->ctls & 0xff);
3464 snd_hda_codec_write(codec,
3465 nvhdmi_master_con_nid_7x,
3467 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3470 for (i = 0; i < 4; i++) {
3476 /* turn off SPDIF once;
3477 *otherwise the IEC958 bits won't be updated
3479 if (codec->spdif_status_reset &&
3480 (spdif->ctls & AC_DIG1_ENABLE))
3481 snd_hda_codec_write(codec,
3482 nvhdmi_con_nids_7x[i],
3484 AC_VERB_SET_DIGI_CONVERT_1,
3485 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3486 /* set the stream id */
3487 snd_hda_codec_write(codec,
3488 nvhdmi_con_nids_7x[i],
3490 AC_VERB_SET_CHANNEL_STREAMID,
3491 (stream_tag << 4) | channel_id);
3492 /* set the stream format */
3493 snd_hda_codec_write(codec,
3494 nvhdmi_con_nids_7x[i],
3496 AC_VERB_SET_STREAM_FORMAT,
3498 /* turn on again (if needed) */
3499 /* enable and set the channel status audio/data flag */
3500 if (codec->spdif_status_reset &&
3501 (spdif->ctls & AC_DIG1_ENABLE)) {
3502 snd_hda_codec_write(codec,
3503 nvhdmi_con_nids_7x[i],
3505 AC_VERB_SET_DIGI_CONVERT_1,
3506 spdif->ctls & 0xff);
3507 snd_hda_codec_write(codec,
3508 nvhdmi_con_nids_7x[i],
3510 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3514 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3516 mutex_unlock(&codec->spdif_mutex);
3520 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3524 .nid = nvhdmi_master_con_nid_7x,
3525 .rates = SUPPORTED_RATES,
3526 .maxbps = SUPPORTED_MAXBPS,
3527 .formats = SUPPORTED_FORMATS,
3529 .open = simple_playback_pcm_open,
3530 .close = nvhdmi_8ch_7x_pcm_close,
3531 .prepare = nvhdmi_8ch_7x_pcm_prepare
3535 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3537 struct hdmi_spec *spec;
3538 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3539 nvhdmi_master_pin_nid_7x);
3543 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3544 /* override the PCM rates, etc, as the codec doesn't give full list */
3546 spec->pcm_playback.rates = SUPPORTED_RATES;
3547 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3548 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3549 spec->nv_dp_workaround = true;
3553 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3555 struct hdmi_spec *spec = codec->spec;
3556 int err = simple_playback_build_pcms(codec);
3558 struct hda_pcm *info = get_pcm_rec(spec, 0);
3559 info->own_chmap = true;
3564 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3566 struct hdmi_spec *spec = codec->spec;
3567 struct hda_pcm *info;
3568 struct snd_pcm_chmap *chmap;
3571 err = simple_playback_build_controls(codec);
3575 /* add channel maps */
3576 info = get_pcm_rec(spec, 0);
3577 err = snd_pcm_add_chmap_ctls(info->pcm,
3578 SNDRV_PCM_STREAM_PLAYBACK,
3579 snd_pcm_alt_chmaps, 8, 0, &chmap);
3582 switch (codec->preset->vendor_id) {
3587 chmap->channel_mask = (1U << 2) | (1U << 8);
3590 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3595 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3597 struct hdmi_spec *spec;
3598 int err = patch_nvhdmi_2ch(codec);
3602 spec->multiout.max_channels = 8;
3603 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3604 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3605 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3606 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3608 /* Initialize the audio infoframe channel mask and checksum to something
3610 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3616 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3620 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3621 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3623 if (cap->ca_index == 0x00 && channels == 2)
3624 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3626 /* If the speaker allocation matches the channel count, it is OK. */
3627 if (cap->channels != channels)
3630 /* all channels are remappable freely */
3631 return SNDRV_CTL_TLVT_CHMAP_VAR;
3634 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3635 int ca, int chs, unsigned char *map)
3637 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3643 /* map from pin NID to port; port is 0-based */
3644 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3645 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3650 /* reverse-map from port to pin NID: see above */
3651 static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3656 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3657 .pin2port = nvhdmi_pin2port,
3658 .pin_eld_notify = generic_acomp_pin_eld_notify,
3659 .master_bind = generic_acomp_master_bind,
3660 .master_unbind = generic_acomp_master_unbind,
3663 static int patch_nvhdmi(struct hda_codec *codec)
3665 struct hdmi_spec *spec;
3668 err = alloc_generic_hdmi(codec);
3671 codec->dp_mst = true;
3674 spec->dyn_pcm_assign = true;
3676 err = hdmi_parse_codec(codec);
3678 generic_spec_free(codec);
3682 generic_hdmi_init_per_pins(codec);
3684 spec->dyn_pin_out = true;
3686 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3687 nvhdmi_chmap_cea_alloc_validate_get_type;
3688 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3689 spec->nv_dp_workaround = true;
3691 codec->link_down_at_suspend = 1;
3693 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3698 static int patch_nvhdmi_legacy(struct hda_codec *codec)
3700 struct hdmi_spec *spec;
3703 err = patch_generic_hdmi(codec);
3708 spec->dyn_pin_out = true;
3710 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3711 nvhdmi_chmap_cea_alloc_validate_get_type;
3712 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3713 spec->nv_dp_workaround = true;
3715 codec->link_down_at_suspend = 1;
3721 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3722 * accessed using vendor-defined verbs. These registers can be used for
3723 * interoperability between the HDA and HDMI drivers.
3726 /* Audio Function Group node */
3727 #define NVIDIA_AFG_NID 0x01
3730 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3731 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3732 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3733 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3734 * additional bit (at position 30) to signal the validity of the format.
3736 * | 31 | 30 | 29 16 | 15 0 |
3737 * +---------+-------+--------+--------+
3738 * | TRIGGER | VALID | UNUSED | FORMAT |
3739 * +-----------------------------------|
3741 * Note that for the trigger bit to take effect it needs to change value
3742 * (i.e. it needs to be toggled).
3744 #define NVIDIA_GET_SCRATCH0 0xfa6
3745 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3746 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3747 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3748 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3749 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3750 #define NVIDIA_SCRATCH_VALID (1 << 6)
3752 #define NVIDIA_GET_SCRATCH1 0xfab
3753 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3754 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3755 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3756 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3759 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3760 * the format is invalidated so that the HDMI codec can be disabled.
3762 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3766 /* bits [31:30] contain the trigger and valid bits */
3767 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3768 NVIDIA_GET_SCRATCH0, 0);
3769 value = (value >> 24) & 0xff;
3771 /* bits [15:0] are used to store the HDA format */
3772 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3773 NVIDIA_SET_SCRATCH0_BYTE0,
3774 (format >> 0) & 0xff);
3775 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3776 NVIDIA_SET_SCRATCH0_BYTE1,
3777 (format >> 8) & 0xff);
3779 /* bits [16:24] are unused */
3780 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3781 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3784 * Bit 30 signals that the data is valid and hence that HDMI audio can
3788 value &= ~NVIDIA_SCRATCH_VALID;
3790 value |= NVIDIA_SCRATCH_VALID;
3793 * Whenever the trigger bit is toggled, an interrupt is raised in the
3794 * HDMI codec. The HDMI driver will use that as trigger to update its
3797 value ^= NVIDIA_SCRATCH_TRIGGER;
3799 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3800 NVIDIA_SET_SCRATCH0_BYTE3, value);
3803 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3804 struct hda_codec *codec,
3805 unsigned int stream_tag,
3806 unsigned int format,
3807 struct snd_pcm_substream *substream)
3811 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3816 /* notify the HDMI codec of the format change */
3817 tegra_hdmi_set_format(codec, format);
3822 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3823 struct hda_codec *codec,
3824 struct snd_pcm_substream *substream)
3826 /* invalidate the format in the HDMI codec */
3827 tegra_hdmi_set_format(codec, 0);
3829 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3832 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3834 struct hdmi_spec *spec = codec->spec;
3837 for (i = 0; i < spec->num_pins; i++) {
3838 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3840 if (pcm->pcm_type == type)
3847 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3849 struct hda_pcm_stream *stream;
3850 struct hda_pcm *pcm;
3853 err = generic_hdmi_build_pcms(codec);
3857 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3862 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3863 * codec about format changes.
3865 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3866 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3867 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3872 static int patch_tegra_hdmi(struct hda_codec *codec)
3874 struct hdmi_spec *spec;
3877 err = patch_generic_hdmi(codec);
3881 codec->depop_delay = 10;
3882 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3884 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3885 nvhdmi_chmap_cea_alloc_validate_get_type;
3886 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3887 spec->nv_dp_workaround = true;
3893 * ATI/AMD-specific implementations
3896 #define is_amdhdmi_rev3_or_later(codec) \
3897 ((codec)->core.vendor_id == 0x1002aa01 && \
3898 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3899 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3901 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3902 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3903 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3904 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3905 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3906 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3907 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3908 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3909 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3910 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3911 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3912 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3913 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3914 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3915 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3916 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3917 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3918 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3919 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3920 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3921 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3922 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3923 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3924 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3925 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3927 /* AMD specific HDA cvt verbs */
3928 #define ATI_VERB_SET_RAMP_RATE 0x770
3929 #define ATI_VERB_GET_RAMP_RATE 0xf70
3931 #define ATI_OUT_ENABLE 0x1
3933 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3934 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3936 #define ATI_HBR_CAPABLE 0x01
3937 #define ATI_HBR_ENABLE 0x10
3939 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3940 int dev_id, unsigned char *buf, int *eld_size)
3942 WARN_ON(dev_id != 0);
3943 /* call hda_eld.c ATI/AMD-specific function */
3944 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3945 is_amdhdmi_rev3_or_later(codec));
3948 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
3949 hda_nid_t pin_nid, int dev_id, int ca,
3950 int active_channels, int conn_type)
3952 WARN_ON(dev_id != 0);
3953 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3956 static int atihdmi_paired_swap_fc_lfe(int pos)
3959 * ATI/AMD have automatic FC/LFE swap built-in
3960 * when in pairwise mapping mode.
3964 /* see channel_allocations[].speakers[] */
3973 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3974 int ca, int chs, unsigned char *map)
3976 struct hdac_cea_channel_speaker_allocation *cap;
3979 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3981 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3982 for (i = 0; i < chs; ++i) {
3983 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3985 bool companion_ok = false;
3990 for (j = 0 + i % 2; j < 8; j += 2) {
3991 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3992 if (cap->speakers[chan_idx] == mask) {
3993 /* channel is in a supported position */
3996 if (i % 2 == 0 && i + 1 < chs) {
3997 /* even channel, check the odd companion */
3998 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3999 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
4000 int comp_mask_act = cap->speakers[comp_chan_idx];
4002 if (comp_mask_req == comp_mask_act)
4003 companion_ok = true;
4015 i++; /* companion channel already checked */
4021 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
4022 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
4024 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4026 int ati_channel_setup = 0;
4031 if (!has_amd_full_remap_support(codec)) {
4032 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
4034 /* In case this is an odd slot but without stream channel, do not
4035 * disable the slot since the corresponding even slot could have a
4036 * channel. In case neither have a channel, the slot pair will be
4037 * disabled when this function is called for the even slot. */
4038 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
4041 hdmi_slot -= hdmi_slot % 2;
4043 if (stream_channel != 0xf)
4044 stream_channel -= stream_channel % 2;
4047 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
4049 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
4051 if (stream_channel != 0xf)
4052 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
4054 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
4057 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
4058 hda_nid_t pin_nid, int asp_slot)
4060 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4061 bool was_odd = false;
4062 int ati_asp_slot = asp_slot;
4064 int ati_channel_setup;
4069 if (!has_amd_full_remap_support(codec)) {
4070 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
4071 if (ati_asp_slot % 2 != 0) {
4077 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
4079 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
4081 if (!(ati_channel_setup & ATI_OUT_ENABLE))
4084 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
4087 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
4088 struct hdac_chmap *chmap,
4089 struct hdac_cea_channel_speaker_allocation *cap,
4095 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
4096 * we need to take that into account (a single channel may take 2
4097 * channel slots if we need to carry a silent channel next to it).
4098 * On Rev3+ AMD codecs this function is not used.
4102 /* We only produce even-numbered channel count TLVs */
4103 if ((channels % 2) != 0)
4106 for (c = 0; c < 7; c += 2) {
4107 if (cap->speakers[c] || cap->speakers[c+1])
4111 if (chanpairs * 2 != channels)
4114 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
4117 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
4118 struct hdac_cea_channel_speaker_allocation *cap,
4119 unsigned int *chmap, int channels)
4121 /* produce paired maps for pre-rev3 ATI/AMD codecs */
4125 for (c = 7; c >= 0; c--) {
4126 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
4127 int spk = cap->speakers[chan];
4129 /* add N/A channel if the companion channel is occupied */
4130 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
4131 chmap[count++] = SNDRV_CHMAP_NA;
4136 chmap[count++] = snd_hdac_spk_to_chmap(spk);
4139 WARN_ON(count != channels);
4142 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4143 int dev_id, bool hbr)
4145 int hbr_ctl, hbr_ctl_new;
4147 WARN_ON(dev_id != 0);
4149 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4150 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4152 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4154 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4157 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4159 hbr_ctl == hbr_ctl_new ? "" : "new-",
4162 if (hbr_ctl != hbr_ctl_new)
4163 snd_hda_codec_write(codec, pin_nid, 0,
4164 ATI_VERB_SET_HBR_CONTROL,
4173 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4174 hda_nid_t pin_nid, int dev_id,
4175 u32 stream_tag, int format)
4177 if (is_amdhdmi_rev3_or_later(codec)) {
4178 int ramp_rate = 180; /* default as per AMD spec */
4179 /* disable ramp-up/down for non-pcm as per AMD spec */
4180 if (format & AC_FMT_TYPE_NON_PCM)
4183 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4186 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4187 stream_tag, format);
4191 static int atihdmi_init(struct hda_codec *codec)
4193 struct hdmi_spec *spec = codec->spec;
4196 err = generic_hdmi_init(codec);
4201 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4202 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4204 /* make sure downmix information in infoframe is zero */
4205 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4207 /* enable channel-wise remap mode if supported */
4208 if (has_amd_full_remap_support(codec))
4209 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4210 ATI_VERB_SET_MULTICHANNEL_MODE,
4211 ATI_MULTICHANNEL_MODE_SINGLE);
4213 codec->auto_runtime_pm = 1;
4218 /* map from pin NID to port; port is 0-based */
4219 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4220 static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4222 return pin_nid / 2 - 1;
4225 /* reverse-map from port to pin NID: see above */
4226 static int atihdmi_port2pin(struct hda_codec *codec, int port)
4228 return port * 2 + 3;
4231 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4232 .pin2port = atihdmi_pin2port,
4233 .pin_eld_notify = generic_acomp_pin_eld_notify,
4234 .master_bind = generic_acomp_master_bind,
4235 .master_unbind = generic_acomp_master_unbind,
4238 static int patch_atihdmi(struct hda_codec *codec)
4240 struct hdmi_spec *spec;
4241 struct hdmi_spec_per_cvt *per_cvt;
4244 err = patch_generic_hdmi(codec);
4249 codec->patch_ops.init = atihdmi_init;
4253 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4254 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4255 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4256 spec->ops.setup_stream = atihdmi_setup_stream;
4258 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4259 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4261 if (!has_amd_full_remap_support(codec)) {
4262 /* override to ATI/AMD-specific versions with pairwise mapping */
4263 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4264 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4265 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4266 atihdmi_paired_cea_alloc_to_tlv_chmap;
4267 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4270 /* ATI/AMD converters do not advertise all of their capabilities */
4271 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4272 per_cvt = get_cvt(spec, cvt_idx);
4273 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4274 per_cvt->rates |= SUPPORTED_RATES;
4275 per_cvt->formats |= SUPPORTED_FORMATS;
4276 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4279 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4281 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4282 * the link-down as is. Tell the core to allow it.
4284 codec->link_down_at_suspend = 1;
4286 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4291 /* VIA HDMI Implementation */
4292 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4293 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4295 static int patch_via_hdmi(struct hda_codec *codec)
4297 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4303 static const struct hda_device_id snd_hda_id_hdmi[] = {
4304 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4305 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4306 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4307 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4308 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4309 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4310 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4311 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4312 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4313 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4314 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4315 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4316 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4317 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4318 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4319 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4320 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4321 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4322 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4323 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4324 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4325 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4326 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4327 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4328 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4329 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4330 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4331 /* 17 is known to be absent */
4332 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4333 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4334 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4335 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4336 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4337 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4338 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4339 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4340 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4341 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4342 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4343 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4344 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4345 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4346 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4347 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4348 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4349 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4350 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4351 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4352 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4353 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4354 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4355 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4356 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4357 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4358 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4359 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4360 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4361 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4362 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4363 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4364 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4365 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4366 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4367 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4368 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4369 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4370 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4371 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4372 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4373 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4374 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4375 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4376 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4377 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4378 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4379 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4380 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4381 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4382 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4383 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4384 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4385 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4386 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4387 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4388 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4389 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4390 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4391 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4392 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4393 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4394 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4395 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4396 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4397 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4398 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4399 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4400 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4401 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4402 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4403 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4404 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4405 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4406 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4407 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4408 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4409 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4410 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
4411 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
4412 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4413 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi),
4414 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4415 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4416 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_tgl_hdmi),
4417 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4418 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4419 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4420 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4421 /* special ID for generic HDMI */
4422 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4425 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4427 MODULE_LICENSE("GPL");
4428 MODULE_DESCRIPTION("HDMI HD-audio codec");
4429 MODULE_ALIAS("snd-hda-codec-intelhdmi");
4430 MODULE_ALIAS("snd-hda-codec-nvhdmi");
4431 MODULE_ALIAS("snd-hda-codec-atihdmi");
4433 static struct hda_codec_driver hdmi_driver = {
4434 .id = snd_hda_id_hdmi,
4437 module_hda_codec_driver(hdmi_driver);