3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <linux/pm_runtime.h>
37 #include <sound/core.h>
38 #include <sound/jack.h>
39 #include <sound/asoundef.h>
40 #include <sound/tlv.h>
41 #include <sound/hdaudio.h>
42 #include <sound/hda_i915.h>
43 #include <sound/hda_chmap.h>
44 #include <sound/hda_codec.h>
45 #include "hda_local.h"
48 static bool static_hdmi_pcm;
49 module_param(static_hdmi_pcm, bool, 0644);
50 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
52 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
53 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
54 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
55 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
56 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
57 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
58 ((codec)->core.vendor_id == 0x80862800))
59 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
60 #define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f)
61 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
62 || is_skylake(codec) || is_broxton(codec) \
63 || is_kabylake(codec) || is_geminilake(codec) \
64 || is_cannonlake(codec) || is_icelake(codec))
65 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
66 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
67 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
69 struct hdmi_spec_per_cvt {
72 unsigned int channels_min;
73 unsigned int channels_max;
79 /* max. connections to a widget */
80 #define HDA_MAX_CONNECTIONS 32
82 struct hdmi_spec_per_pin {
85 /* pin idx, different device entries on the same pin use the same idx */
88 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
92 struct hda_codec *codec;
93 struct hdmi_eld sink_eld;
95 struct delayed_work work;
96 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
97 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
99 bool setup; /* the stream has been set up by prepare callback */
100 int channels; /* current number of channels */
102 bool chmap_set; /* channel-map override by ALSA API? */
103 unsigned char chmap[8]; /* ALSA API channel-map */
104 #ifdef CONFIG_SND_PROC_FS
105 struct snd_info_entry *proc_entry;
109 /* operations used by generic code that can be overridden by patches */
111 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
112 unsigned char *buf, int *eld_size);
114 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
115 int ca, int active_channels, int conn_type);
117 /* enable/disable HBR (HD passthrough) */
118 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
120 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
121 hda_nid_t pin_nid, u32 stream_tag, int format);
123 void (*pin_cvt_fixup)(struct hda_codec *codec,
124 struct hdmi_spec_per_pin *per_pin,
130 struct snd_jack *jack;
131 struct snd_kcontrol *eld_ctl;
136 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
137 hda_nid_t cvt_nids[4]; /* only for haswell fix */
140 * num_pins is the number of virtual pins
141 * for example, there are 3 pins, and each pin
142 * has 4 device entries, then the num_pins is 12
146 * num_nids is the number of real pins
147 * In the above example, num_nids is 3
151 * dev_num is the number of device entries
153 * In the above example, dev_num is 4
156 struct snd_array pins; /* struct hdmi_spec_per_pin */
157 struct hdmi_pcm pcm_rec[16];
158 struct mutex pcm_lock;
159 /* pcm_bitmap means which pcms have been assigned to pins*/
160 unsigned long pcm_bitmap;
161 int pcm_used; /* counter of pcm_rec[] */
162 /* bitmap shows whether the pcm is opened in user space
163 * bit 0 means the first playback PCM (PCM3);
164 * bit 1 means the second playback PCM, and so on.
166 unsigned long pcm_in_use;
168 struct hdmi_eld temp_eld;
174 * Non-generic VIA/NVIDIA specific
176 struct hda_multi_out multiout;
177 struct hda_pcm_stream pcm_playback;
179 /* i915/powerwell (Haswell+/Valleyview+) specific */
180 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
181 struct drm_audio_component_audio_ops drm_audio_ops;
183 struct hdac_chmap chmap;
184 hda_nid_t vendor_nid;
189 #ifdef CONFIG_SND_HDA_COMPONENT
190 static inline bool codec_has_acomp(struct hda_codec *codec)
192 struct hdmi_spec *spec = codec->spec;
193 return spec->use_acomp_notifier;
196 #define codec_has_acomp(codec) false
199 struct hdmi_audio_infoframe {
206 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
210 u8 LFEPBL01_LSV36_DM_INH7;
213 struct dp_audio_infoframe {
216 u8 ver; /* 0x11 << 2 */
218 u8 CC02_CT47; /* match with HDMI infoframe from this on */
222 u8 LFEPBL01_LSV36_DM_INH7;
225 union audio_infoframe {
226 struct hdmi_audio_infoframe hdmi;
227 struct dp_audio_infoframe dp;
235 #define get_pin(spec, idx) \
236 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
237 #define get_cvt(spec, idx) \
238 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
239 /* obtain hdmi_pcm object assigned to idx */
240 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
241 /* obtain hda_pcm object assigned to idx */
242 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
244 static int pin_id_to_pin_index(struct hda_codec *codec,
245 hda_nid_t pin_nid, int dev_id)
247 struct hdmi_spec *spec = codec->spec;
249 struct hdmi_spec_per_pin *per_pin;
252 * (dev_id == -1) means it is NON-MST pin
253 * return the first virtual pin on this port
258 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
259 per_pin = get_pin(spec, pin_idx);
260 if ((per_pin->pin_nid == pin_nid) &&
261 (per_pin->dev_id == dev_id))
265 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
269 static int hinfo_to_pcm_index(struct hda_codec *codec,
270 struct hda_pcm_stream *hinfo)
272 struct hdmi_spec *spec = codec->spec;
275 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
276 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
279 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
283 static int hinfo_to_pin_index(struct hda_codec *codec,
284 struct hda_pcm_stream *hinfo)
286 struct hdmi_spec *spec = codec->spec;
287 struct hdmi_spec_per_pin *per_pin;
290 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
291 per_pin = get_pin(spec, pin_idx);
293 per_pin->pcm->pcm->stream == hinfo)
297 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
301 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
305 struct hdmi_spec_per_pin *per_pin;
307 for (i = 0; i < spec->num_pins; i++) {
308 per_pin = get_pin(spec, i);
309 if (per_pin->pcm_idx == pcm_idx)
315 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
317 struct hdmi_spec *spec = codec->spec;
320 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
321 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
324 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
328 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
329 struct snd_ctl_elem_info *uinfo)
331 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
332 struct hdmi_spec *spec = codec->spec;
333 struct hdmi_spec_per_pin *per_pin;
334 struct hdmi_eld *eld;
337 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
339 pcm_idx = kcontrol->private_value;
340 mutex_lock(&spec->pcm_lock);
341 per_pin = pcm_idx_to_pin(spec, pcm_idx);
343 /* no pin is bound to the pcm */
347 eld = &per_pin->sink_eld;
348 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
351 mutex_unlock(&spec->pcm_lock);
355 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
356 struct snd_ctl_elem_value *ucontrol)
358 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
359 struct hdmi_spec *spec = codec->spec;
360 struct hdmi_spec_per_pin *per_pin;
361 struct hdmi_eld *eld;
365 pcm_idx = kcontrol->private_value;
366 mutex_lock(&spec->pcm_lock);
367 per_pin = pcm_idx_to_pin(spec, pcm_idx);
369 /* no pin is bound to the pcm */
370 memset(ucontrol->value.bytes.data, 0,
371 ARRAY_SIZE(ucontrol->value.bytes.data));
375 eld = &per_pin->sink_eld;
376 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
377 eld->eld_size > ELD_MAX_SIZE) {
383 memset(ucontrol->value.bytes.data, 0,
384 ARRAY_SIZE(ucontrol->value.bytes.data));
386 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
390 mutex_unlock(&spec->pcm_lock);
394 static const struct snd_kcontrol_new eld_bytes_ctl = {
395 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
396 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
398 .info = hdmi_eld_ctl_info,
399 .get = hdmi_eld_ctl_get,
402 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
405 struct snd_kcontrol *kctl;
406 struct hdmi_spec *spec = codec->spec;
409 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
412 kctl->private_value = pcm_idx;
413 kctl->id.device = device;
415 /* no pin nid is associated with the kctl now
416 * tbd: associate pin nid to eld ctl later
418 err = snd_hda_ctl_add(codec, 0, kctl);
422 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
427 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
428 int *packet_index, int *byte_index)
432 val = snd_hda_codec_read(codec, pin_nid, 0,
433 AC_VERB_GET_HDMI_DIP_INDEX, 0);
435 *packet_index = val >> 5;
436 *byte_index = val & 0x1f;
440 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
441 int packet_index, int byte_index)
445 val = (packet_index << 5) | (byte_index & 0x1f);
447 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
450 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
453 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
456 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
458 struct hdmi_spec *spec = codec->spec;
462 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
463 snd_hda_codec_write(codec, pin_nid, 0,
464 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
466 if (spec->dyn_pin_out)
467 /* Disable pin out until stream is active */
470 /* Enable pin out: some machines with GM965 gets broken output
471 * when the pin is disabled or changed while using with HDMI
475 snd_hda_codec_write(codec, pin_nid, 0,
476 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
483 #ifdef CONFIG_SND_PROC_FS
484 static void print_eld_info(struct snd_info_entry *entry,
485 struct snd_info_buffer *buffer)
487 struct hdmi_spec_per_pin *per_pin = entry->private_data;
489 mutex_lock(&per_pin->lock);
490 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
491 mutex_unlock(&per_pin->lock);
494 static void write_eld_info(struct snd_info_entry *entry,
495 struct snd_info_buffer *buffer)
497 struct hdmi_spec_per_pin *per_pin = entry->private_data;
499 mutex_lock(&per_pin->lock);
500 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
501 mutex_unlock(&per_pin->lock);
504 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
507 struct hda_codec *codec = per_pin->codec;
508 struct snd_info_entry *entry;
511 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
512 err = snd_card_proc_new(codec->card, name, &entry);
516 snd_info_set_text_ops(entry, per_pin, print_eld_info);
517 entry->c.text.write = write_eld_info;
519 per_pin->proc_entry = entry;
524 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
526 if (!per_pin->codec->bus->shutdown) {
527 snd_info_free_entry(per_pin->proc_entry);
528 per_pin->proc_entry = NULL;
532 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
537 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
543 * Audio InfoFrame routines
547 * Enable Audio InfoFrame Transmission
549 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
552 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
553 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
558 * Disable Audio InfoFrame Transmission
560 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
563 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
564 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
568 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
570 #ifdef CONFIG_SND_DEBUG_VERBOSE
574 size = snd_hdmi_get_eld_size(codec, pin_nid);
575 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
577 for (i = 0; i < 8; i++) {
578 size = snd_hda_codec_read(codec, pin_nid, 0,
579 AC_VERB_GET_HDMI_DIP_SIZE, i);
580 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
585 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
591 for (i = 0; i < 8; i++) {
592 size = snd_hda_codec_read(codec, pin_nid, 0,
593 AC_VERB_GET_HDMI_DIP_SIZE, i);
597 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
598 for (j = 1; j < 1000; j++) {
599 hdmi_write_dip_byte(codec, pin_nid, 0x0);
600 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
602 codec_dbg(codec, "dip index %d: %d != %d\n",
604 if (bi == 0) /* byte index wrapped around */
608 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
614 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
616 u8 *bytes = (u8 *)hdmi_ai;
620 hdmi_ai->checksum = 0;
622 for (i = 0; i < sizeof(*hdmi_ai); i++)
625 hdmi_ai->checksum = -sum;
628 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
634 hdmi_debug_dip_size(codec, pin_nid);
635 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
637 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
638 for (i = 0; i < size; i++)
639 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
642 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
648 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
652 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
653 for (i = 0; i < size; i++) {
654 val = snd_hda_codec_read(codec, pin_nid, 0,
655 AC_VERB_GET_HDMI_DIP_DATA, 0);
663 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
665 int ca, int active_channels,
668 union audio_infoframe ai;
670 memset(&ai, 0, sizeof(ai));
671 if (conn_type == 0) { /* HDMI */
672 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
674 hdmi_ai->type = 0x84;
677 hdmi_ai->CC02_CT47 = active_channels - 1;
679 hdmi_checksum_audio_infoframe(hdmi_ai);
680 } else if (conn_type == 1) { /* DisplayPort */
681 struct dp_audio_infoframe *dp_ai = &ai.dp;
685 dp_ai->ver = 0x11 << 2;
686 dp_ai->CC02_CT47 = active_channels - 1;
689 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
695 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
696 * sizeof(*dp_ai) to avoid partial match/update problems when
697 * the user switches between HDMI/DP monitors.
699 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
702 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
704 active_channels, ca);
705 hdmi_stop_infoframe_trans(codec, pin_nid);
706 hdmi_fill_audio_infoframe(codec, pin_nid,
707 ai.bytes, sizeof(ai));
708 hdmi_start_infoframe_trans(codec, pin_nid);
712 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
713 struct hdmi_spec_per_pin *per_pin,
716 struct hdmi_spec *spec = codec->spec;
717 struct hdac_chmap *chmap = &spec->chmap;
718 hda_nid_t pin_nid = per_pin->pin_nid;
719 int channels = per_pin->channels;
721 struct hdmi_eld *eld;
727 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
728 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
729 snd_hda_codec_write(codec, pin_nid, 0,
730 AC_VERB_SET_AMP_GAIN_MUTE,
733 eld = &per_pin->sink_eld;
735 ca = snd_hdac_channel_allocation(&codec->core,
736 eld->info.spk_alloc, channels,
737 per_pin->chmap_set, non_pcm, per_pin->chmap);
739 active_channels = snd_hdac_get_active_channels(ca);
741 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
745 * always configure channel mapping, it may have been changed by the
746 * user in the meantime
748 snd_hdac_setup_channel_mapping(&spec->chmap,
749 pin_nid, non_pcm, ca, channels,
750 per_pin->chmap, per_pin->chmap_set);
752 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
753 eld->info.conn_type);
755 per_pin->non_pcm = non_pcm;
762 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
764 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
767 struct hdmi_spec *spec = codec->spec;
768 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
772 mutex_lock(&spec->pcm_lock);
773 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
774 snd_hda_jack_report_sync(codec);
775 mutex_unlock(&spec->pcm_lock);
778 static void jack_callback(struct hda_codec *codec,
779 struct hda_jack_callback *jack)
781 /* hda_jack don't support DP MST */
782 check_presence_and_report(codec, jack->nid, 0);
785 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
787 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
788 struct hda_jack_tbl *jack;
789 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
792 * assume DP MST uses dyn_pcm_assign and acomp and
794 * if DP MST supports unsol event, below code need
797 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
800 jack->jack_dirty = 1;
803 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
804 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
805 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
807 /* hda_jack don't support DP MST */
808 check_presence_and_report(codec, jack->nid, 0);
811 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
813 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
814 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
815 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
816 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
819 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
834 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
836 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
837 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
839 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
840 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
845 hdmi_intrinsic_event(codec, res);
847 hdmi_non_intrinsic_event(codec, res);
850 static void haswell_verify_D0(struct hda_codec *codec,
851 hda_nid_t cvt_nid, hda_nid_t nid)
855 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
856 * thus pins could only choose converter 0 for use. Make sure the
857 * converters are in correct power state */
858 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
859 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
861 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
862 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
865 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
866 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
867 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
875 /* HBR should be Non-PCM, 8 channels */
876 #define is_hbr_format(format) \
877 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
879 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
882 int pinctl, new_pinctl;
884 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
885 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
886 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
889 return hbr ? -EINVAL : 0;
891 new_pinctl = pinctl & ~AC_PINCTL_EPT;
893 new_pinctl |= AC_PINCTL_EPT_HBR;
895 new_pinctl |= AC_PINCTL_EPT_NATIVE;
898 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
900 pinctl == new_pinctl ? "" : "new-",
903 if (pinctl != new_pinctl)
904 snd_hda_codec_write(codec, pin_nid, 0,
905 AC_VERB_SET_PIN_WIDGET_CONTROL,
913 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
914 hda_nid_t pin_nid, u32 stream_tag, int format)
916 struct hdmi_spec *spec = codec->spec;
920 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
923 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
927 if (is_haswell_plus(codec)) {
930 * on recent platforms IEC Coding Type is required for HBR
931 * support, read current Digital Converter settings and set
932 * ICT bitfield if needed.
934 param = snd_hda_codec_read(codec, cvt_nid, 0,
935 AC_VERB_GET_DIGI_CONVERT_1, 0);
937 param = (param >> 16) & ~(AC_DIG3_ICT);
939 /* on recent platforms ICT mode is required for HBR support */
940 if (is_hbr_format(format))
943 snd_hda_codec_write(codec, cvt_nid, 0,
944 AC_VERB_SET_DIGI_CONVERT_3, param);
947 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
951 /* Try to find an available converter
952 * If pin_idx is less then zero, just try to find an available converter.
953 * Otherwise, try to find an available converter and get the cvt mux index
956 static int hdmi_choose_cvt(struct hda_codec *codec,
957 int pin_idx, int *cvt_id)
959 struct hdmi_spec *spec = codec->spec;
960 struct hdmi_spec_per_pin *per_pin;
961 struct hdmi_spec_per_cvt *per_cvt = NULL;
962 int cvt_idx, mux_idx = 0;
964 /* pin_idx < 0 means no pin will be bound to the converter */
968 per_pin = get_pin(spec, pin_idx);
970 /* Dynamically assign converter to stream */
971 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
972 per_cvt = get_cvt(spec, cvt_idx);
974 /* Must not already be assigned */
975 if (per_cvt->assigned)
979 /* Must be in pin's mux's list of converters */
980 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
981 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
983 /* Not in mux list */
984 if (mux_idx == per_pin->num_mux_nids)
989 /* No free converters */
990 if (cvt_idx == spec->num_cvts)
994 per_pin->mux_idx = mux_idx;
1002 /* Assure the pin select the right convetor */
1003 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1004 struct hdmi_spec_per_pin *per_pin)
1006 hda_nid_t pin_nid = per_pin->pin_nid;
1009 mux_idx = per_pin->mux_idx;
1010 curr = snd_hda_codec_read(codec, pin_nid, 0,
1011 AC_VERB_GET_CONNECT_SEL, 0);
1012 if (curr != mux_idx)
1013 snd_hda_codec_write_cache(codec, pin_nid, 0,
1014 AC_VERB_SET_CONNECT_SEL,
1018 /* get the mux index for the converter of the pins
1019 * converter's mux index is the same for all pins on Intel platform
1021 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1026 for (i = 0; i < spec->num_cvts; i++)
1027 if (spec->cvt_nids[i] == cvt_nid)
1032 /* Intel HDMI workaround to fix audio routing issue:
1033 * For some Intel display codecs, pins share the same connection list.
1034 * So a conveter can be selected by multiple pins and playback on any of these
1035 * pins will generate sound on the external display, because audio flows from
1036 * the same converter to the display pipeline. Also muting one pin may make
1037 * other pins have no sound output.
1038 * So this function assures that an assigned converter for a pin is not selected
1039 * by any other pins.
1041 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1043 int dev_id, int mux_idx)
1045 struct hdmi_spec *spec = codec->spec;
1048 struct hdmi_spec_per_cvt *per_cvt;
1049 struct hdmi_spec_per_pin *per_pin;
1052 /* configure the pins connections */
1053 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1057 per_pin = get_pin(spec, pin_idx);
1059 * pin not connected to monitor
1060 * no need to operate on it
1065 if ((per_pin->pin_nid == pin_nid) &&
1066 (per_pin->dev_id == dev_id))
1070 * if per_pin->dev_id >= dev_num,
1071 * snd_hda_get_dev_select() will fail,
1072 * and the following operation is unpredictable.
1073 * So skip this situation.
1075 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1076 if (per_pin->dev_id >= dev_num)
1079 nid = per_pin->pin_nid;
1082 * Calling this function should not impact
1083 * on the device entry selection
1084 * So let's save the dev id for each pin,
1085 * and restore it when return
1087 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1088 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1089 curr = snd_hda_codec_read(codec, nid, 0,
1090 AC_VERB_GET_CONNECT_SEL, 0);
1091 if (curr != mux_idx) {
1092 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1097 /* choose an unassigned converter. The conveters in the
1098 * connection list are in the same order as in the codec.
1100 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1101 per_cvt = get_cvt(spec, cvt_idx);
1102 if (!per_cvt->assigned) {
1104 "choose cvt %d for pin nid %d\n",
1106 snd_hda_codec_write_cache(codec, nid, 0,
1107 AC_VERB_SET_CONNECT_SEL,
1112 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1116 /* A wrapper of intel_not_share_asigned_cvt() */
1117 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1118 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1121 struct hdmi_spec *spec = codec->spec;
1123 /* On Intel platform, the mapping of converter nid to
1124 * mux index of the pins are always the same.
1125 * The pin nid may be 0, this means all pins will not
1126 * share the converter.
1128 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1130 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1133 /* skeleton caller of pin_cvt_fixup ops */
1134 static void pin_cvt_fixup(struct hda_codec *codec,
1135 struct hdmi_spec_per_pin *per_pin,
1138 struct hdmi_spec *spec = codec->spec;
1140 if (spec->ops.pin_cvt_fixup)
1141 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1144 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1145 * in dyn_pcm_assign mode.
1147 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1148 struct hda_codec *codec,
1149 struct snd_pcm_substream *substream)
1151 struct hdmi_spec *spec = codec->spec;
1152 struct snd_pcm_runtime *runtime = substream->runtime;
1153 int cvt_idx, pcm_idx;
1154 struct hdmi_spec_per_cvt *per_cvt = NULL;
1157 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1161 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1165 per_cvt = get_cvt(spec, cvt_idx);
1166 per_cvt->assigned = 1;
1167 hinfo->nid = per_cvt->cvt_nid;
1169 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1171 set_bit(pcm_idx, &spec->pcm_in_use);
1172 /* todo: setup spdif ctls assign */
1174 /* Initially set the converter's capabilities */
1175 hinfo->channels_min = per_cvt->channels_min;
1176 hinfo->channels_max = per_cvt->channels_max;
1177 hinfo->rates = per_cvt->rates;
1178 hinfo->formats = per_cvt->formats;
1179 hinfo->maxbps = per_cvt->maxbps;
1181 /* Store the updated parameters */
1182 runtime->hw.channels_min = hinfo->channels_min;
1183 runtime->hw.channels_max = hinfo->channels_max;
1184 runtime->hw.formats = hinfo->formats;
1185 runtime->hw.rates = hinfo->rates;
1187 snd_pcm_hw_constraint_step(substream->runtime, 0,
1188 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1195 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1196 struct hda_codec *codec,
1197 struct snd_pcm_substream *substream)
1199 struct hdmi_spec *spec = codec->spec;
1200 struct snd_pcm_runtime *runtime = substream->runtime;
1201 int pin_idx, cvt_idx, pcm_idx;
1202 struct hdmi_spec_per_pin *per_pin;
1203 struct hdmi_eld *eld;
1204 struct hdmi_spec_per_cvt *per_cvt = NULL;
1207 /* Validate hinfo */
1208 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1212 mutex_lock(&spec->pcm_lock);
1213 pin_idx = hinfo_to_pin_index(codec, hinfo);
1214 if (!spec->dyn_pcm_assign) {
1215 if (snd_BUG_ON(pin_idx < 0)) {
1220 /* no pin is assigned to the PCM
1221 * PA need pcm open successfully when probe
1224 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1229 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1233 per_cvt = get_cvt(spec, cvt_idx);
1234 /* Claim converter */
1235 per_cvt->assigned = 1;
1237 set_bit(pcm_idx, &spec->pcm_in_use);
1238 per_pin = get_pin(spec, pin_idx);
1239 per_pin->cvt_nid = per_cvt->cvt_nid;
1240 hinfo->nid = per_cvt->cvt_nid;
1242 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1243 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1244 AC_VERB_SET_CONNECT_SEL,
1247 /* configure unused pins to choose other converters */
1248 pin_cvt_fixup(codec, per_pin, 0);
1250 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1252 /* Initially set the converter's capabilities */
1253 hinfo->channels_min = per_cvt->channels_min;
1254 hinfo->channels_max = per_cvt->channels_max;
1255 hinfo->rates = per_cvt->rates;
1256 hinfo->formats = per_cvt->formats;
1257 hinfo->maxbps = per_cvt->maxbps;
1259 eld = &per_pin->sink_eld;
1260 /* Restrict capabilities by ELD if this isn't disabled */
1261 if (!static_hdmi_pcm && eld->eld_valid) {
1262 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1263 if (hinfo->channels_min > hinfo->channels_max ||
1264 !hinfo->rates || !hinfo->formats) {
1265 per_cvt->assigned = 0;
1267 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1273 /* Store the updated parameters */
1274 runtime->hw.channels_min = hinfo->channels_min;
1275 runtime->hw.channels_max = hinfo->channels_max;
1276 runtime->hw.formats = hinfo->formats;
1277 runtime->hw.rates = hinfo->rates;
1279 snd_pcm_hw_constraint_step(substream->runtime, 0,
1280 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1282 mutex_unlock(&spec->pcm_lock);
1287 * HDA/HDMI auto parsing
1289 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1291 struct hdmi_spec *spec = codec->spec;
1292 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1293 hda_nid_t pin_nid = per_pin->pin_nid;
1295 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1297 "HDMI: pin %d wcaps %#x does not support connection list\n",
1298 pin_nid, get_wcaps(codec, pin_nid));
1302 /* all the device entries on the same pin have the same conn list */
1303 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1305 HDA_MAX_CONNECTIONS);
1310 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1311 struct hdmi_spec_per_pin *per_pin)
1315 /* try the prefer PCM */
1316 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1317 return per_pin->pin_nid_idx;
1319 /* have a second try; check the "reserved area" over num_pins */
1320 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1321 if (!test_bit(i, &spec->pcm_bitmap))
1325 /* the last try; check the empty slots in pins */
1326 for (i = 0; i < spec->num_nids; i++) {
1327 if (!test_bit(i, &spec->pcm_bitmap))
1333 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1334 struct hdmi_spec_per_pin *per_pin)
1338 /* pcm already be attached to the pin */
1341 idx = hdmi_find_pcm_slot(spec, per_pin);
1344 per_pin->pcm_idx = idx;
1345 per_pin->pcm = get_hdmi_pcm(spec, idx);
1346 set_bit(idx, &spec->pcm_bitmap);
1349 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1350 struct hdmi_spec_per_pin *per_pin)
1354 /* pcm already be detached from the pin */
1357 idx = per_pin->pcm_idx;
1358 per_pin->pcm_idx = -1;
1359 per_pin->pcm = NULL;
1360 if (idx >= 0 && idx < spec->pcm_used)
1361 clear_bit(idx, &spec->pcm_bitmap);
1364 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1365 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1369 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1370 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1375 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1377 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1378 struct hdmi_spec_per_pin *per_pin)
1380 struct hda_codec *codec = per_pin->codec;
1381 struct hda_pcm *pcm;
1382 struct hda_pcm_stream *hinfo;
1383 struct snd_pcm_substream *substream;
1387 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1388 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1393 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1396 /* hdmi audio only uses playback and one substream */
1397 hinfo = pcm->stream;
1398 substream = pcm->pcm->streams[0].substream;
1400 per_pin->cvt_nid = hinfo->nid;
1402 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1403 if (mux_idx < per_pin->num_mux_nids) {
1404 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1406 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1407 AC_VERB_SET_CONNECT_SEL,
1410 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1412 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1413 if (substream->runtime)
1414 per_pin->channels = substream->runtime->channels;
1415 per_pin->setup = true;
1416 per_pin->mux_idx = mux_idx;
1418 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1421 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1422 struct hdmi_spec_per_pin *per_pin)
1424 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1425 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1427 per_pin->chmap_set = false;
1428 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1430 per_pin->setup = false;
1431 per_pin->channels = 0;
1434 /* update per_pin ELD from the given new ELD;
1435 * setup info frame and notification accordingly
1437 static void update_eld(struct hda_codec *codec,
1438 struct hdmi_spec_per_pin *per_pin,
1439 struct hdmi_eld *eld)
1441 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1442 struct hdmi_spec *spec = codec->spec;
1443 bool old_eld_valid = pin_eld->eld_valid;
1447 /* for monitor disconnection, save pcm_idx firstly */
1448 pcm_idx = per_pin->pcm_idx;
1449 if (spec->dyn_pcm_assign) {
1450 if (eld->eld_valid) {
1451 hdmi_attach_hda_pcm(spec, per_pin);
1452 hdmi_pcm_setup_pin(spec, per_pin);
1454 hdmi_pcm_reset_pin(spec, per_pin);
1455 hdmi_detach_hda_pcm(spec, per_pin);
1458 /* if pcm_idx == -1, it means this is in monitor connection event
1459 * we can get the correct pcm_idx now.
1462 pcm_idx = per_pin->pcm_idx;
1465 snd_hdmi_show_eld(codec, &eld->info);
1467 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1468 if (eld->eld_valid && pin_eld->eld_valid)
1469 if (pin_eld->eld_size != eld->eld_size ||
1470 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1471 eld->eld_size) != 0)
1474 pin_eld->monitor_present = eld->monitor_present;
1475 pin_eld->eld_valid = eld->eld_valid;
1476 pin_eld->eld_size = eld->eld_size;
1478 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1479 pin_eld->info = eld->info;
1482 * Re-setup pin and infoframe. This is needed e.g. when
1483 * - sink is first plugged-in
1484 * - transcoder can change during stream playback on Haswell
1485 * and this can make HW reset converter selection on a pin.
1487 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1488 pin_cvt_fixup(codec, per_pin, 0);
1489 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1492 if (eld_changed && pcm_idx >= 0)
1493 snd_ctl_notify(codec->card,
1494 SNDRV_CTL_EVENT_MASK_VALUE |
1495 SNDRV_CTL_EVENT_MASK_INFO,
1496 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1499 /* update ELD and jack state via HD-audio verbs */
1500 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1503 struct hda_jack_tbl *jack;
1504 struct hda_codec *codec = per_pin->codec;
1505 struct hdmi_spec *spec = codec->spec;
1506 struct hdmi_eld *eld = &spec->temp_eld;
1507 hda_nid_t pin_nid = per_pin->pin_nid;
1509 * Always execute a GetPinSense verb here, even when called from
1510 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1511 * response's PD bit is not the real PD value, but indicates that
1512 * the real PD value changed. An older version of the HD-audio
1513 * specification worked this way. Hence, we just ignore the data in
1514 * the unsolicited response to avoid custom WARs.
1518 bool do_repoll = false;
1520 present = snd_hda_pin_sense(codec, pin_nid);
1522 mutex_lock(&per_pin->lock);
1523 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1524 if (eld->monitor_present)
1525 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1527 eld->eld_valid = false;
1530 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1531 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1533 if (eld->eld_valid) {
1534 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1535 &eld->eld_size) < 0)
1536 eld->eld_valid = false;
1538 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1540 eld->eld_valid = false;
1542 if (!eld->eld_valid && repoll)
1547 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1549 update_eld(codec, per_pin, eld);
1551 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1553 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1555 jack->block_report = !ret;
1557 mutex_unlock(&per_pin->lock);
1561 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1562 struct hdmi_spec_per_pin *per_pin)
1564 struct hdmi_spec *spec = codec->spec;
1565 struct snd_jack *jack = NULL;
1566 struct hda_jack_tbl *jack_tbl;
1568 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1569 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1570 * NULL even after snd_hda_jack_tbl_clear() is called to
1571 * free snd_jack. This may cause access invalid memory
1572 * when calling snd_jack_report
1574 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1575 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1576 else if (!spec->dyn_pcm_assign) {
1578 * jack tbl doesn't support DP MST
1579 * DP MST will use dyn_pcm_assign,
1580 * so DP MST will never come here
1582 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1584 jack = jack_tbl->jack;
1589 /* update ELD and jack state via audio component */
1590 static void sync_eld_via_acomp(struct hda_codec *codec,
1591 struct hdmi_spec_per_pin *per_pin)
1593 struct hdmi_spec *spec = codec->spec;
1594 struct hdmi_eld *eld = &spec->temp_eld;
1595 struct snd_jack *jack = NULL;
1598 mutex_lock(&per_pin->lock);
1599 eld->monitor_present = false;
1600 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1601 per_pin->dev_id, &eld->monitor_present,
1602 eld->eld_buffer, ELD_MAX_SIZE);
1604 size = min(size, ELD_MAX_SIZE);
1605 if (snd_hdmi_parse_eld(codec, &eld->info,
1606 eld->eld_buffer, size) < 0)
1611 eld->eld_valid = true;
1612 eld->eld_size = size;
1614 eld->eld_valid = false;
1618 /* pcm_idx >=0 before update_eld() means it is in monitor
1619 * disconnected event. Jack must be fetched before update_eld()
1621 jack = pin_idx_to_jack(codec, per_pin);
1622 update_eld(codec, per_pin, eld);
1624 jack = pin_idx_to_jack(codec, per_pin);
1627 snd_jack_report(jack,
1628 eld->monitor_present ? SND_JACK_AVOUT : 0);
1630 mutex_unlock(&per_pin->lock);
1633 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1635 struct hda_codec *codec = per_pin->codec;
1638 /* no temporary power up/down needed for component notifier */
1639 if (!codec_has_acomp(codec)) {
1640 ret = snd_hda_power_up_pm(codec);
1641 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1642 snd_hda_power_down_pm(codec);
1647 if (codec_has_acomp(codec)) {
1648 sync_eld_via_acomp(codec, per_pin);
1649 ret = false; /* don't call snd_hda_jack_report_sync() */
1651 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1654 if (!codec_has_acomp(codec))
1655 snd_hda_power_down_pm(codec);
1660 static void hdmi_repoll_eld(struct work_struct *work)
1662 struct hdmi_spec_per_pin *per_pin =
1663 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1664 struct hda_codec *codec = per_pin->codec;
1665 struct hdmi_spec *spec = codec->spec;
1666 struct hda_jack_tbl *jack;
1668 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1670 jack->jack_dirty = 1;
1672 if (per_pin->repoll_count++ > 6)
1673 per_pin->repoll_count = 0;
1675 mutex_lock(&spec->pcm_lock);
1676 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1677 snd_hda_jack_report_sync(per_pin->codec);
1678 mutex_unlock(&spec->pcm_lock);
1681 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1684 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1686 struct hdmi_spec *spec = codec->spec;
1687 unsigned int caps, config;
1689 struct hdmi_spec_per_pin *per_pin;
1693 caps = snd_hda_query_pin_caps(codec, pin_nid);
1694 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1698 * For DP MST audio, Configuration Default is the same for
1699 * all device entries on the same pin
1701 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1702 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1706 * To simplify the implementation, malloc all
1707 * the virtual pins in the initialization statically
1709 if (is_haswell_plus(codec)) {
1711 * On Intel platforms, device entries number is
1712 * changed dynamically. If there is a DP MST
1713 * hub connected, the device entries number is 3.
1714 * Otherwise, it is 1.
1715 * Here we manually set dev_num to 3, so that
1716 * we can initialize all the device entries when
1717 * bootup statically.
1721 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1722 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1724 * spec->dev_num is the maxinum number of device entries
1725 * among all the pins
1727 spec->dev_num = (spec->dev_num > dev_num) ?
1728 spec->dev_num : dev_num;
1731 * If the platform doesn't support DP MST,
1732 * manually set dev_num to 1. This means
1733 * the pin has only one device entry.
1739 for (i = 0; i < dev_num; i++) {
1740 pin_idx = spec->num_pins;
1741 per_pin = snd_array_new(&spec->pins);
1746 if (spec->dyn_pcm_assign) {
1747 per_pin->pcm = NULL;
1748 per_pin->pcm_idx = -1;
1750 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1751 per_pin->pcm_idx = pin_idx;
1753 per_pin->pin_nid = pin_nid;
1754 per_pin->pin_nid_idx = spec->num_nids;
1755 per_pin->dev_id = i;
1756 per_pin->non_pcm = false;
1757 snd_hda_set_dev_select(codec, pin_nid, i);
1758 if (is_haswell_plus(codec))
1759 intel_haswell_fixup_connect_list(codec, pin_nid);
1760 err = hdmi_read_pin_conn(codec, pin_idx);
1770 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1772 struct hdmi_spec *spec = codec->spec;
1773 struct hdmi_spec_per_cvt *per_cvt;
1777 chans = get_wcaps(codec, cvt_nid);
1778 chans = get_wcaps_channels(chans);
1780 per_cvt = snd_array_new(&spec->cvts);
1784 per_cvt->cvt_nid = cvt_nid;
1785 per_cvt->channels_min = 2;
1787 per_cvt->channels_max = chans;
1788 if (chans > spec->chmap.channels_max)
1789 spec->chmap.channels_max = chans;
1792 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1799 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1800 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1806 static int hdmi_parse_codec(struct hda_codec *codec)
1811 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1812 if (!nid || nodes < 0) {
1813 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1817 for (i = 0; i < nodes; i++, nid++) {
1821 caps = get_wcaps(codec, nid);
1822 type = get_wcaps_type(caps);
1824 if (!(caps & AC_WCAP_DIGITAL))
1828 case AC_WID_AUD_OUT:
1829 hdmi_add_cvt(codec, nid);
1832 hdmi_add_pin(codec, nid);
1842 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1844 struct hda_spdif_out *spdif;
1847 mutex_lock(&codec->spdif_mutex);
1848 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1849 /* Add sanity check to pass klockwork check.
1850 * This should never happen.
1852 if (WARN_ON(spdif == NULL))
1854 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1855 mutex_unlock(&codec->spdif_mutex);
1863 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1864 struct hda_codec *codec,
1865 unsigned int stream_tag,
1866 unsigned int format,
1867 struct snd_pcm_substream *substream)
1869 hda_nid_t cvt_nid = hinfo->nid;
1870 struct hdmi_spec *spec = codec->spec;
1872 struct hdmi_spec_per_pin *per_pin;
1874 struct snd_pcm_runtime *runtime = substream->runtime;
1879 mutex_lock(&spec->pcm_lock);
1880 pin_idx = hinfo_to_pin_index(codec, hinfo);
1881 if (spec->dyn_pcm_assign && pin_idx < 0) {
1882 /* when dyn_pcm_assign and pcm is not bound to a pin
1883 * skip pin setup and return 0 to make audio playback
1886 pin_cvt_fixup(codec, NULL, cvt_nid);
1887 snd_hda_codec_setup_stream(codec, cvt_nid,
1888 stream_tag, 0, format);
1892 if (snd_BUG_ON(pin_idx < 0)) {
1896 per_pin = get_pin(spec, pin_idx);
1897 pin_nid = per_pin->pin_nid;
1899 /* Verify pin:cvt selections to avoid silent audio after S3.
1900 * After S3, the audio driver restores pin:cvt selections
1901 * but this can happen before gfx is ready and such selection
1902 * is overlooked by HW. Thus multiple pins can share a same
1903 * default convertor and mute control will affect each other,
1904 * which can cause a resumed audio playback become silent
1907 pin_cvt_fixup(codec, per_pin, 0);
1909 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1910 /* Todo: add DP1.2 MST audio support later */
1911 if (codec_has_acomp(codec))
1912 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1915 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1916 mutex_lock(&per_pin->lock);
1917 per_pin->channels = substream->runtime->channels;
1918 per_pin->setup = true;
1920 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
1921 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
1923 snd_hda_codec_write(codec, cvt_nid, 0,
1924 AC_VERB_SET_STRIPE_CONTROL,
1928 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1929 mutex_unlock(&per_pin->lock);
1930 if (spec->dyn_pin_out) {
1931 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1932 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1933 snd_hda_codec_write(codec, pin_nid, 0,
1934 AC_VERB_SET_PIN_WIDGET_CONTROL,
1938 /* snd_hda_set_dev_select() has been called before */
1939 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1940 stream_tag, format);
1942 mutex_unlock(&spec->pcm_lock);
1946 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1947 struct hda_codec *codec,
1948 struct snd_pcm_substream *substream)
1950 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1954 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1955 struct hda_codec *codec,
1956 struct snd_pcm_substream *substream)
1958 struct hdmi_spec *spec = codec->spec;
1959 int cvt_idx, pin_idx, pcm_idx;
1960 struct hdmi_spec_per_cvt *per_cvt;
1961 struct hdmi_spec_per_pin *per_pin;
1966 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1967 if (snd_BUG_ON(pcm_idx < 0))
1969 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1970 if (snd_BUG_ON(cvt_idx < 0))
1972 per_cvt = get_cvt(spec, cvt_idx);
1974 snd_BUG_ON(!per_cvt->assigned);
1975 per_cvt->assigned = 0;
1978 mutex_lock(&spec->pcm_lock);
1979 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1980 clear_bit(pcm_idx, &spec->pcm_in_use);
1981 pin_idx = hinfo_to_pin_index(codec, hinfo);
1982 if (spec->dyn_pcm_assign && pin_idx < 0)
1985 if (snd_BUG_ON(pin_idx < 0)) {
1989 per_pin = get_pin(spec, pin_idx);
1991 if (spec->dyn_pin_out) {
1992 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1993 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1994 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1995 AC_VERB_SET_PIN_WIDGET_CONTROL,
1999 mutex_lock(&per_pin->lock);
2000 per_pin->chmap_set = false;
2001 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2003 per_pin->setup = false;
2004 per_pin->channels = 0;
2005 mutex_unlock(&per_pin->lock);
2007 mutex_unlock(&spec->pcm_lock);
2013 static const struct hda_pcm_ops generic_ops = {
2014 .open = hdmi_pcm_open,
2015 .close = hdmi_pcm_close,
2016 .prepare = generic_hdmi_playback_pcm_prepare,
2017 .cleanup = generic_hdmi_playback_pcm_cleanup,
2020 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2022 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2023 struct hdmi_spec *spec = codec->spec;
2024 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2029 return per_pin->sink_eld.info.spk_alloc;
2032 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2033 unsigned char *chmap)
2035 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2036 struct hdmi_spec *spec = codec->spec;
2037 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2039 /* chmap is already set to 0 in caller */
2043 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2046 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2047 unsigned char *chmap, int prepared)
2049 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2050 struct hdmi_spec *spec = codec->spec;
2051 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2055 mutex_lock(&per_pin->lock);
2056 per_pin->chmap_set = true;
2057 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2059 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2060 mutex_unlock(&per_pin->lock);
2063 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2065 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2066 struct hdmi_spec *spec = codec->spec;
2067 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2069 return per_pin ? true:false;
2072 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2074 struct hdmi_spec *spec = codec->spec;
2078 * for non-mst mode, pcm number is the same as before
2079 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2080 * dev_num is the device entry number in a pin
2083 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2084 struct hda_pcm *info;
2085 struct hda_pcm_stream *pstr;
2087 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2091 spec->pcm_rec[idx].pcm = info;
2093 info->pcm_type = HDA_PCM_TYPE_HDMI;
2094 info->own_chmap = true;
2096 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2097 pstr->substreams = 1;
2098 pstr->ops = generic_ops;
2099 /* pcm number is less than 16 */
2100 if (spec->pcm_used >= 16)
2102 /* other pstr fields are set in open */
2108 static void free_hdmi_jack_priv(struct snd_jack *jack)
2110 struct hdmi_pcm *pcm = jack->private_data;
2115 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2116 struct hdmi_spec *spec,
2120 struct snd_jack *jack;
2123 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2128 spec->pcm_rec[pcm_idx].jack = jack;
2129 jack->private_data = &spec->pcm_rec[pcm_idx];
2130 jack->private_free = free_hdmi_jack_priv;
2134 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2136 char hdmi_str[32] = "HDMI/DP";
2137 struct hdmi_spec *spec = codec->spec;
2138 struct hdmi_spec_per_pin *per_pin;
2139 struct hda_jack_tbl *jack;
2140 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2145 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2147 if (spec->dyn_pcm_assign)
2148 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2150 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2151 /* if !dyn_pcm_assign, it must be non-MST mode.
2152 * This means pcms and pins are statically mapped.
2153 * And pcm_idx is pin_idx.
2155 per_pin = get_pin(spec, pcm_idx);
2156 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2158 strncat(hdmi_str, " Phantom",
2159 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2160 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2161 phantom_jack, 0, NULL);
2164 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2167 /* assign jack->jack to pcm_rec[].jack to
2168 * align with dyn_pcm_assign mode
2170 spec->pcm_rec[pcm_idx].jack = jack->jack;
2174 static int generic_hdmi_build_controls(struct hda_codec *codec)
2176 struct hdmi_spec *spec = codec->spec;
2178 int pin_idx, pcm_idx;
2180 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2181 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2182 /* no PCM: mark this for skipping permanently */
2183 set_bit(pcm_idx, &spec->pcm_bitmap);
2187 err = generic_hdmi_build_jack(codec, pcm_idx);
2191 /* create the spdif for each pcm
2192 * pin will be bound when monitor is connected
2194 if (spec->dyn_pcm_assign)
2195 err = snd_hda_create_dig_out_ctls(codec,
2196 0, spec->cvt_nids[0],
2199 struct hdmi_spec_per_pin *per_pin =
2200 get_pin(spec, pcm_idx);
2201 err = snd_hda_create_dig_out_ctls(codec,
2203 per_pin->mux_nids[0],
2208 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2210 dev = get_pcm_rec(spec, pcm_idx)->device;
2211 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2212 /* add control for ELD Bytes */
2213 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2219 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2220 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2222 hdmi_present_sense(per_pin, 0);
2225 /* add channel maps */
2226 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2227 struct hda_pcm *pcm;
2229 pcm = get_pcm_rec(spec, pcm_idx);
2230 if (!pcm || !pcm->pcm)
2232 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2240 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2242 struct hdmi_spec *spec = codec->spec;
2245 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2246 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2248 per_pin->codec = codec;
2249 mutex_init(&per_pin->lock);
2250 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2251 eld_proc_new(per_pin, pin_idx);
2256 static int generic_hdmi_init(struct hda_codec *codec)
2258 struct hdmi_spec *spec = codec->spec;
2261 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2262 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2263 hda_nid_t pin_nid = per_pin->pin_nid;
2264 int dev_id = per_pin->dev_id;
2266 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2267 hdmi_init_pin(codec, pin_nid);
2268 if (!codec_has_acomp(codec))
2269 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2270 codec->jackpoll_interval > 0 ?
2271 jack_callback : NULL);
2276 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2278 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2279 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2282 static void hdmi_array_free(struct hdmi_spec *spec)
2284 snd_array_free(&spec->pins);
2285 snd_array_free(&spec->cvts);
2288 static void generic_spec_free(struct hda_codec *codec)
2290 struct hdmi_spec *spec = codec->spec;
2293 hdmi_array_free(spec);
2297 codec->dp_mst = false;
2300 static void generic_hdmi_free(struct hda_codec *codec)
2302 struct hdmi_spec *spec = codec->spec;
2303 int pin_idx, pcm_idx;
2305 if (codec_has_acomp(codec))
2306 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2308 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2309 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2310 cancel_delayed_work_sync(&per_pin->work);
2311 eld_proc_free(per_pin);
2314 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2315 if (spec->pcm_rec[pcm_idx].jack == NULL)
2317 if (spec->dyn_pcm_assign)
2318 snd_device_free(codec->card,
2319 spec->pcm_rec[pcm_idx].jack);
2321 spec->pcm_rec[pcm_idx].jack = NULL;
2324 generic_spec_free(codec);
2328 static int generic_hdmi_resume(struct hda_codec *codec)
2330 struct hdmi_spec *spec = codec->spec;
2333 codec->patch_ops.init(codec);
2334 regcache_sync(codec->core.regmap);
2336 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2337 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2338 hdmi_present_sense(per_pin, 1);
2344 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2345 .init = generic_hdmi_init,
2346 .free = generic_hdmi_free,
2347 .build_pcms = generic_hdmi_build_pcms,
2348 .build_controls = generic_hdmi_build_controls,
2349 .unsol_event = hdmi_unsol_event,
2351 .resume = generic_hdmi_resume,
2355 static const struct hdmi_ops generic_standard_hdmi_ops = {
2356 .pin_get_eld = snd_hdmi_get_eld,
2357 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2358 .pin_hbr_setup = hdmi_pin_hbr_setup,
2359 .setup_stream = hdmi_setup_stream,
2362 /* allocate codec->spec and assign/initialize generic parser ops */
2363 static int alloc_generic_hdmi(struct hda_codec *codec)
2365 struct hdmi_spec *spec;
2367 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2371 spec->ops = generic_standard_hdmi_ops;
2372 spec->dev_num = 1; /* initialize to 1 */
2373 mutex_init(&spec->pcm_lock);
2374 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2376 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2377 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2378 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2379 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2382 hdmi_array_init(spec, 4);
2384 codec->patch_ops = generic_hdmi_patch_ops;
2389 /* generic HDMI parser */
2390 static int patch_generic_hdmi(struct hda_codec *codec)
2394 err = alloc_generic_hdmi(codec);
2398 err = hdmi_parse_codec(codec);
2400 generic_spec_free(codec);
2404 generic_hdmi_init_per_pins(codec);
2409 * Intel codec parsers and helpers
2412 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2415 struct hdmi_spec *spec = codec->spec;
2419 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2420 if (nconns == spec->num_cvts &&
2421 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2424 /* override pins connection list */
2425 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2426 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2429 #define INTEL_GET_VENDOR_VERB 0xf81
2430 #define INTEL_GET_VENDOR_VERB 0xf81
2431 #define INTEL_SET_VENDOR_VERB 0x781
2432 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2433 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2435 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2438 unsigned int vendor_param;
2439 struct hdmi_spec *spec = codec->spec;
2441 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2442 INTEL_GET_VENDOR_VERB, 0);
2443 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2446 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2447 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2448 INTEL_SET_VENDOR_VERB, vendor_param);
2449 if (vendor_param == -1)
2453 snd_hda_codec_update_widgets(codec);
2456 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2458 unsigned int vendor_param;
2459 struct hdmi_spec *spec = codec->spec;
2461 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2462 INTEL_GET_VENDOR_VERB, 0);
2463 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2466 /* enable DP1.2 mode */
2467 vendor_param |= INTEL_EN_DP12;
2468 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2469 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2470 INTEL_SET_VENDOR_VERB, vendor_param);
2473 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2474 * Otherwise you may get severe h/w communication errors.
2476 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2477 unsigned int power_state)
2479 if (power_state == AC_PWRST_D0) {
2480 intel_haswell_enable_all_pins(codec, false);
2481 intel_haswell_fixup_enable_dp12(codec);
2484 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2485 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2488 /* There is a fixed mapping between audio pin node and display port.
2489 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2490 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2491 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2492 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2495 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2496 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2497 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2499 static int intel_base_nid(struct hda_codec *codec)
2501 switch (codec->core.vendor_id) {
2502 case 0x80860054: /* ILK */
2503 case 0x80862804: /* ILK */
2504 case 0x80862882: /* VLV */
2511 static int intel_pin2port(void *audio_ptr, int pin_nid)
2513 struct hda_codec *codec = audio_ptr;
2514 struct hdmi_spec *spec = codec->spec;
2517 if (!spec->port_num) {
2518 base_nid = intel_base_nid(codec);
2519 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2521 return pin_nid - base_nid + 1; /* intel port is 1-based */
2525 * looking for the pin number in the mapping table and return
2526 * the index which indicate the port number
2528 for (i = 0; i < spec->port_num; i++) {
2529 if (pin_nid == spec->port_map[i])
2533 /* return -1 if pin number exceeds our expectation */
2534 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2538 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2540 struct hda_codec *codec = audio_ptr;
2544 /* we assume only from port-B to port-D */
2545 if (port < 1 || port > 3)
2548 pin_nid = port + intel_base_nid(codec) - 1; /* intel port is 1-based */
2550 /* skip notification during system suspend (but not in runtime PM);
2551 * the state will be updated at resume
2553 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2555 /* ditto during suspend/resume process itself */
2556 if (snd_hdac_is_in_pm(&codec->core))
2559 snd_hdac_i915_set_bclk(&codec->bus->core);
2560 check_presence_and_report(codec, pin_nid, dev_id);
2563 /* register i915 component pin_eld_notify callback */
2564 static void register_i915_notifier(struct hda_codec *codec)
2566 struct hdmi_spec *spec = codec->spec;
2568 spec->use_acomp_notifier = true;
2569 spec->drm_audio_ops.audio_ptr = codec;
2570 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2571 * will call pin_eld_notify with using audio_ptr pointer
2572 * We need make sure audio_ptr is really setup
2575 spec->drm_audio_ops.pin2port = intel_pin2port;
2576 spec->drm_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2577 snd_hdac_acomp_register_notifier(&codec->bus->core,
2578 &spec->drm_audio_ops);
2581 /* setup_stream ops override for HSW+ */
2582 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2583 hda_nid_t pin_nid, u32 stream_tag, int format)
2585 haswell_verify_D0(codec, cvt_nid, pin_nid);
2586 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2589 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2590 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2591 struct hdmi_spec_per_pin *per_pin,
2595 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2597 intel_verify_pin_cvt_connect(codec, per_pin);
2598 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2599 per_pin->dev_id, per_pin->mux_idx);
2601 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2605 /* precondition and allocation for Intel codecs */
2606 static int alloc_intel_hdmi(struct hda_codec *codec)
2608 /* requires i915 binding */
2609 if (!codec->bus->core.audio_component) {
2610 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2611 /* set probe_id here to prevent generic fallback binding */
2612 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2616 return alloc_generic_hdmi(codec);
2619 /* parse and post-process for Intel codecs */
2620 static int parse_intel_hdmi(struct hda_codec *codec)
2624 err = hdmi_parse_codec(codec);
2626 generic_spec_free(codec);
2630 generic_hdmi_init_per_pins(codec);
2631 register_i915_notifier(codec);
2635 /* Intel Haswell and onwards; audio component with eld notifier */
2636 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2637 const int *port_map, int port_num)
2639 struct hdmi_spec *spec;
2642 err = alloc_intel_hdmi(codec);
2646 codec->dp_mst = true;
2647 spec->dyn_pcm_assign = true;
2648 spec->vendor_nid = vendor_nid;
2649 spec->port_map = port_map;
2650 spec->port_num = port_num;
2652 intel_haswell_enable_all_pins(codec, true);
2653 intel_haswell_fixup_enable_dp12(codec);
2655 codec->display_power_control = 1;
2657 codec->patch_ops.set_power_state = haswell_set_power_state;
2658 codec->depop_delay = 0;
2659 codec->auto_runtime_pm = 1;
2661 spec->ops.setup_stream = i915_hsw_setup_stream;
2662 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2664 return parse_intel_hdmi(codec);
2667 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2669 return intel_hsw_common_init(codec, 0x08, NULL, 0);
2672 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2674 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2677 static int patch_i915_icl_hdmi(struct hda_codec *codec)
2680 * pin to port mapping table where the value indicate the pin number and
2681 * the index indicate the port number with 1 base.
2683 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb};
2685 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2688 /* Intel Baytrail and Braswell; with eld notifier */
2689 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2691 struct hdmi_spec *spec;
2694 err = alloc_intel_hdmi(codec);
2699 /* For Valleyview/Cherryview, only the display codec is in the display
2700 * power well and can use link_power ops to request/release the power.
2702 codec->display_power_control = 1;
2704 codec->depop_delay = 0;
2705 codec->auto_runtime_pm = 1;
2707 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2709 return parse_intel_hdmi(codec);
2712 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2713 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2717 err = alloc_intel_hdmi(codec);
2720 return parse_intel_hdmi(codec);
2724 * Shared non-generic implementations
2727 static int simple_playback_build_pcms(struct hda_codec *codec)
2729 struct hdmi_spec *spec = codec->spec;
2730 struct hda_pcm *info;
2732 struct hda_pcm_stream *pstr;
2733 struct hdmi_spec_per_cvt *per_cvt;
2735 per_cvt = get_cvt(spec, 0);
2736 chans = get_wcaps(codec, per_cvt->cvt_nid);
2737 chans = get_wcaps_channels(chans);
2739 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2742 spec->pcm_rec[0].pcm = info;
2743 info->pcm_type = HDA_PCM_TYPE_HDMI;
2744 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2745 *pstr = spec->pcm_playback;
2746 pstr->nid = per_cvt->cvt_nid;
2747 if (pstr->channels_max <= 2 && chans && chans <= 16)
2748 pstr->channels_max = chans;
2753 /* unsolicited event for jack sensing */
2754 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2757 snd_hda_jack_set_dirty_all(codec);
2758 snd_hda_jack_report_sync(codec);
2761 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2762 * as long as spec->pins[] is set correctly
2764 #define simple_hdmi_build_jack generic_hdmi_build_jack
2766 static int simple_playback_build_controls(struct hda_codec *codec)
2768 struct hdmi_spec *spec = codec->spec;
2769 struct hdmi_spec_per_cvt *per_cvt;
2772 per_cvt = get_cvt(spec, 0);
2773 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2778 return simple_hdmi_build_jack(codec, 0);
2781 static int simple_playback_init(struct hda_codec *codec)
2783 struct hdmi_spec *spec = codec->spec;
2784 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2785 hda_nid_t pin = per_pin->pin_nid;
2787 snd_hda_codec_write(codec, pin, 0,
2788 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2789 /* some codecs require to unmute the pin */
2790 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2791 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2793 snd_hda_jack_detect_enable(codec, pin);
2797 static void simple_playback_free(struct hda_codec *codec)
2799 struct hdmi_spec *spec = codec->spec;
2801 hdmi_array_free(spec);
2806 * Nvidia specific implementations
2809 #define Nv_VERB_SET_Channel_Allocation 0xF79
2810 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2811 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2812 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2814 #define nvhdmi_master_con_nid_7x 0x04
2815 #define nvhdmi_master_pin_nid_7x 0x05
2817 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2818 /*front, rear, clfe, rear_surr */
2822 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2823 /* set audio protect on */
2824 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2825 /* enable digital output on pin widget */
2826 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2830 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2831 /* set audio protect on */
2832 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2833 /* enable digital output on pin widget */
2834 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2835 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2836 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2837 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2838 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2842 #ifdef LIMITED_RATE_FMT_SUPPORT
2843 /* support only the safe format and rate */
2844 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2845 #define SUPPORTED_MAXBPS 16
2846 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2848 /* support all rates and formats */
2849 #define SUPPORTED_RATES \
2850 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2851 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2852 SNDRV_PCM_RATE_192000)
2853 #define SUPPORTED_MAXBPS 24
2854 #define SUPPORTED_FORMATS \
2855 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2858 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2860 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2864 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2866 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2870 static const unsigned int channels_2_6_8[] = {
2874 static const unsigned int channels_2_8[] = {
2878 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2879 .count = ARRAY_SIZE(channels_2_6_8),
2880 .list = channels_2_6_8,
2884 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2885 .count = ARRAY_SIZE(channels_2_8),
2886 .list = channels_2_8,
2890 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2891 struct hda_codec *codec,
2892 struct snd_pcm_substream *substream)
2894 struct hdmi_spec *spec = codec->spec;
2895 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2897 switch (codec->preset->vendor_id) {
2902 hw_constraints_channels = &hw_constraints_2_8_channels;
2905 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2911 if (hw_constraints_channels != NULL) {
2912 snd_pcm_hw_constraint_list(substream->runtime, 0,
2913 SNDRV_PCM_HW_PARAM_CHANNELS,
2914 hw_constraints_channels);
2916 snd_pcm_hw_constraint_step(substream->runtime, 0,
2917 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2920 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2923 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2924 struct hda_codec *codec,
2925 struct snd_pcm_substream *substream)
2927 struct hdmi_spec *spec = codec->spec;
2928 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2931 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2932 struct hda_codec *codec,
2933 unsigned int stream_tag,
2934 unsigned int format,
2935 struct snd_pcm_substream *substream)
2937 struct hdmi_spec *spec = codec->spec;
2938 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2939 stream_tag, format, substream);
2942 static const struct hda_pcm_stream simple_pcm_playback = {
2947 .open = simple_playback_pcm_open,
2948 .close = simple_playback_pcm_close,
2949 .prepare = simple_playback_pcm_prepare
2953 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2954 .build_controls = simple_playback_build_controls,
2955 .build_pcms = simple_playback_build_pcms,
2956 .init = simple_playback_init,
2957 .free = simple_playback_free,
2958 .unsol_event = simple_hdmi_unsol_event,
2961 static int patch_simple_hdmi(struct hda_codec *codec,
2962 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2964 struct hdmi_spec *spec;
2965 struct hdmi_spec_per_cvt *per_cvt;
2966 struct hdmi_spec_per_pin *per_pin;
2968 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2973 hdmi_array_init(spec, 1);
2975 spec->multiout.num_dacs = 0; /* no analog */
2976 spec->multiout.max_channels = 2;
2977 spec->multiout.dig_out_nid = cvt_nid;
2980 per_pin = snd_array_new(&spec->pins);
2981 per_cvt = snd_array_new(&spec->cvts);
2982 if (!per_pin || !per_cvt) {
2983 simple_playback_free(codec);
2986 per_cvt->cvt_nid = cvt_nid;
2987 per_pin->pin_nid = pin_nid;
2988 spec->pcm_playback = simple_pcm_playback;
2990 codec->patch_ops = simple_hdmi_patch_ops;
2995 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2998 unsigned int chanmask;
2999 int chan = channels ? (channels - 1) : 1;
3018 /* Set the audio infoframe channel allocation and checksum fields. The
3019 * channel count is computed implicitly by the hardware. */
3020 snd_hda_codec_write(codec, 0x1, 0,
3021 Nv_VERB_SET_Channel_Allocation, chanmask);
3023 snd_hda_codec_write(codec, 0x1, 0,
3024 Nv_VERB_SET_Info_Frame_Checksum,
3025 (0x71 - chan - chanmask));
3028 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3029 struct hda_codec *codec,
3030 struct snd_pcm_substream *substream)
3032 struct hdmi_spec *spec = codec->spec;
3035 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3036 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3037 for (i = 0; i < 4; i++) {
3038 /* set the stream id */
3039 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3040 AC_VERB_SET_CHANNEL_STREAMID, 0);
3041 /* set the stream format */
3042 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3043 AC_VERB_SET_STREAM_FORMAT, 0);
3046 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3047 * streams are disabled. */
3048 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3050 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3053 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3054 struct hda_codec *codec,
3055 unsigned int stream_tag,
3056 unsigned int format,
3057 struct snd_pcm_substream *substream)
3060 unsigned int dataDCC2, channel_id;
3062 struct hdmi_spec *spec = codec->spec;
3063 struct hda_spdif_out *spdif;
3064 struct hdmi_spec_per_cvt *per_cvt;
3066 mutex_lock(&codec->spdif_mutex);
3067 per_cvt = get_cvt(spec, 0);
3068 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3070 chs = substream->runtime->channels;
3074 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3075 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3076 snd_hda_codec_write(codec,
3077 nvhdmi_master_con_nid_7x,
3079 AC_VERB_SET_DIGI_CONVERT_1,
3080 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3082 /* set the stream id */
3083 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3084 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3086 /* set the stream format */
3087 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3088 AC_VERB_SET_STREAM_FORMAT, format);
3090 /* turn on again (if needed) */
3091 /* enable and set the channel status audio/data flag */
3092 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3093 snd_hda_codec_write(codec,
3094 nvhdmi_master_con_nid_7x,
3096 AC_VERB_SET_DIGI_CONVERT_1,
3097 spdif->ctls & 0xff);
3098 snd_hda_codec_write(codec,
3099 nvhdmi_master_con_nid_7x,
3101 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3104 for (i = 0; i < 4; i++) {
3110 /* turn off SPDIF once;
3111 *otherwise the IEC958 bits won't be updated
3113 if (codec->spdif_status_reset &&
3114 (spdif->ctls & AC_DIG1_ENABLE))
3115 snd_hda_codec_write(codec,
3116 nvhdmi_con_nids_7x[i],
3118 AC_VERB_SET_DIGI_CONVERT_1,
3119 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3120 /* set the stream id */
3121 snd_hda_codec_write(codec,
3122 nvhdmi_con_nids_7x[i],
3124 AC_VERB_SET_CHANNEL_STREAMID,
3125 (stream_tag << 4) | channel_id);
3126 /* set the stream format */
3127 snd_hda_codec_write(codec,
3128 nvhdmi_con_nids_7x[i],
3130 AC_VERB_SET_STREAM_FORMAT,
3132 /* turn on again (if needed) */
3133 /* enable and set the channel status audio/data flag */
3134 if (codec->spdif_status_reset &&
3135 (spdif->ctls & AC_DIG1_ENABLE)) {
3136 snd_hda_codec_write(codec,
3137 nvhdmi_con_nids_7x[i],
3139 AC_VERB_SET_DIGI_CONVERT_1,
3140 spdif->ctls & 0xff);
3141 snd_hda_codec_write(codec,
3142 nvhdmi_con_nids_7x[i],
3144 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3148 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3150 mutex_unlock(&codec->spdif_mutex);
3154 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3158 .nid = nvhdmi_master_con_nid_7x,
3159 .rates = SUPPORTED_RATES,
3160 .maxbps = SUPPORTED_MAXBPS,
3161 .formats = SUPPORTED_FORMATS,
3163 .open = simple_playback_pcm_open,
3164 .close = nvhdmi_8ch_7x_pcm_close,
3165 .prepare = nvhdmi_8ch_7x_pcm_prepare
3169 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3171 struct hdmi_spec *spec;
3172 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3173 nvhdmi_master_pin_nid_7x);
3177 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3178 /* override the PCM rates, etc, as the codec doesn't give full list */
3180 spec->pcm_playback.rates = SUPPORTED_RATES;
3181 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3182 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3186 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3188 struct hdmi_spec *spec = codec->spec;
3189 int err = simple_playback_build_pcms(codec);
3191 struct hda_pcm *info = get_pcm_rec(spec, 0);
3192 info->own_chmap = true;
3197 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3199 struct hdmi_spec *spec = codec->spec;
3200 struct hda_pcm *info;
3201 struct snd_pcm_chmap *chmap;
3204 err = simple_playback_build_controls(codec);
3208 /* add channel maps */
3209 info = get_pcm_rec(spec, 0);
3210 err = snd_pcm_add_chmap_ctls(info->pcm,
3211 SNDRV_PCM_STREAM_PLAYBACK,
3212 snd_pcm_alt_chmaps, 8, 0, &chmap);
3215 switch (codec->preset->vendor_id) {
3220 chmap->channel_mask = (1U << 2) | (1U << 8);
3223 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3228 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3230 struct hdmi_spec *spec;
3231 int err = patch_nvhdmi_2ch(codec);
3235 spec->multiout.max_channels = 8;
3236 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3237 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3238 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3239 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3241 /* Initialize the audio infoframe channel mask and checksum to something
3243 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3249 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3253 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3254 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3256 if (cap->ca_index == 0x00 && channels == 2)
3257 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3259 /* If the speaker allocation matches the channel count, it is OK. */
3260 if (cap->channels != channels)
3263 /* all channels are remappable freely */
3264 return SNDRV_CTL_TLVT_CHMAP_VAR;
3267 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3268 int ca, int chs, unsigned char *map)
3270 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3276 static int patch_nvhdmi(struct hda_codec *codec)
3278 struct hdmi_spec *spec;
3281 err = patch_generic_hdmi(codec);
3286 spec->dyn_pin_out = true;
3288 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3289 nvhdmi_chmap_cea_alloc_validate_get_type;
3290 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3296 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3297 * accessed using vendor-defined verbs. These registers can be used for
3298 * interoperability between the HDA and HDMI drivers.
3301 /* Audio Function Group node */
3302 #define NVIDIA_AFG_NID 0x01
3305 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3306 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3307 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3308 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3309 * additional bit (at position 30) to signal the validity of the format.
3311 * | 31 | 30 | 29 16 | 15 0 |
3312 * +---------+-------+--------+--------+
3313 * | TRIGGER | VALID | UNUSED | FORMAT |
3314 * +-----------------------------------|
3316 * Note that for the trigger bit to take effect it needs to change value
3317 * (i.e. it needs to be toggled).
3319 #define NVIDIA_GET_SCRATCH0 0xfa6
3320 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3321 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3322 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3323 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3324 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3325 #define NVIDIA_SCRATCH_VALID (1 << 6)
3327 #define NVIDIA_GET_SCRATCH1 0xfab
3328 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3329 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3330 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3331 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3334 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3335 * the format is invalidated so that the HDMI codec can be disabled.
3337 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3341 /* bits [31:30] contain the trigger and valid bits */
3342 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3343 NVIDIA_GET_SCRATCH0, 0);
3344 value = (value >> 24) & 0xff;
3346 /* bits [15:0] are used to store the HDA format */
3347 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3348 NVIDIA_SET_SCRATCH0_BYTE0,
3349 (format >> 0) & 0xff);
3350 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3351 NVIDIA_SET_SCRATCH0_BYTE1,
3352 (format >> 8) & 0xff);
3354 /* bits [16:24] are unused */
3355 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3356 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3359 * Bit 30 signals that the data is valid and hence that HDMI audio can
3363 value &= ~NVIDIA_SCRATCH_VALID;
3365 value |= NVIDIA_SCRATCH_VALID;
3368 * Whenever the trigger bit is toggled, an interrupt is raised in the
3369 * HDMI codec. The HDMI driver will use that as trigger to update its
3372 value ^= NVIDIA_SCRATCH_TRIGGER;
3374 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3375 NVIDIA_SET_SCRATCH0_BYTE3, value);
3378 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3379 struct hda_codec *codec,
3380 unsigned int stream_tag,
3381 unsigned int format,
3382 struct snd_pcm_substream *substream)
3386 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3391 /* notify the HDMI codec of the format change */
3392 tegra_hdmi_set_format(codec, format);
3397 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3398 struct hda_codec *codec,
3399 struct snd_pcm_substream *substream)
3401 /* invalidate the format in the HDMI codec */
3402 tegra_hdmi_set_format(codec, 0);
3404 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3407 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3409 struct hdmi_spec *spec = codec->spec;
3412 for (i = 0; i < spec->num_pins; i++) {
3413 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3415 if (pcm->pcm_type == type)
3422 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3424 struct hda_pcm_stream *stream;
3425 struct hda_pcm *pcm;
3428 err = generic_hdmi_build_pcms(codec);
3432 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3437 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3438 * codec about format changes.
3440 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3441 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3442 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3447 static int patch_tegra_hdmi(struct hda_codec *codec)
3451 err = patch_generic_hdmi(codec);
3455 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3461 * ATI/AMD-specific implementations
3464 #define is_amdhdmi_rev3_or_later(codec) \
3465 ((codec)->core.vendor_id == 0x1002aa01 && \
3466 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3467 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3469 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3470 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3471 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3472 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3473 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3474 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3475 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3476 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3477 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3478 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3479 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3480 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3481 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3482 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3483 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3484 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3485 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3486 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3487 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3488 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3489 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3490 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3491 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3492 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3493 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3495 /* AMD specific HDA cvt verbs */
3496 #define ATI_VERB_SET_RAMP_RATE 0x770
3497 #define ATI_VERB_GET_RAMP_RATE 0xf70
3499 #define ATI_OUT_ENABLE 0x1
3501 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3502 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3504 #define ATI_HBR_CAPABLE 0x01
3505 #define ATI_HBR_ENABLE 0x10
3507 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3508 unsigned char *buf, int *eld_size)
3510 /* call hda_eld.c ATI/AMD-specific function */
3511 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3512 is_amdhdmi_rev3_or_later(codec));
3515 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3516 int active_channels, int conn_type)
3518 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3521 static int atihdmi_paired_swap_fc_lfe(int pos)
3524 * ATI/AMD have automatic FC/LFE swap built-in
3525 * when in pairwise mapping mode.
3529 /* see channel_allocations[].speakers[] */
3538 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3539 int ca, int chs, unsigned char *map)
3541 struct hdac_cea_channel_speaker_allocation *cap;
3544 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3546 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3547 for (i = 0; i < chs; ++i) {
3548 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3550 bool companion_ok = false;
3555 for (j = 0 + i % 2; j < 8; j += 2) {
3556 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3557 if (cap->speakers[chan_idx] == mask) {
3558 /* channel is in a supported position */
3561 if (i % 2 == 0 && i + 1 < chs) {
3562 /* even channel, check the odd companion */
3563 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3564 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3565 int comp_mask_act = cap->speakers[comp_chan_idx];
3567 if (comp_mask_req == comp_mask_act)
3568 companion_ok = true;
3580 i++; /* companion channel already checked */
3586 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3587 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3589 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3591 int ati_channel_setup = 0;
3596 if (!has_amd_full_remap_support(codec)) {
3597 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3599 /* In case this is an odd slot but without stream channel, do not
3600 * disable the slot since the corresponding even slot could have a
3601 * channel. In case neither have a channel, the slot pair will be
3602 * disabled when this function is called for the even slot. */
3603 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3606 hdmi_slot -= hdmi_slot % 2;
3608 if (stream_channel != 0xf)
3609 stream_channel -= stream_channel % 2;
3612 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3614 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3616 if (stream_channel != 0xf)
3617 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3619 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3622 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3623 hda_nid_t pin_nid, int asp_slot)
3625 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3626 bool was_odd = false;
3627 int ati_asp_slot = asp_slot;
3629 int ati_channel_setup;
3634 if (!has_amd_full_remap_support(codec)) {
3635 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3636 if (ati_asp_slot % 2 != 0) {
3642 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3644 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3646 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3649 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3652 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3653 struct hdac_chmap *chmap,
3654 struct hdac_cea_channel_speaker_allocation *cap,
3660 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3661 * we need to take that into account (a single channel may take 2
3662 * channel slots if we need to carry a silent channel next to it).
3663 * On Rev3+ AMD codecs this function is not used.
3667 /* We only produce even-numbered channel count TLVs */
3668 if ((channels % 2) != 0)
3671 for (c = 0; c < 7; c += 2) {
3672 if (cap->speakers[c] || cap->speakers[c+1])
3676 if (chanpairs * 2 != channels)
3679 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3682 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3683 struct hdac_cea_channel_speaker_allocation *cap,
3684 unsigned int *chmap, int channels)
3686 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3690 for (c = 7; c >= 0; c--) {
3691 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3692 int spk = cap->speakers[chan];
3694 /* add N/A channel if the companion channel is occupied */
3695 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3696 chmap[count++] = SNDRV_CHMAP_NA;
3701 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3704 WARN_ON(count != channels);
3707 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3710 int hbr_ctl, hbr_ctl_new;
3712 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3713 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3715 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3717 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3720 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3722 hbr_ctl == hbr_ctl_new ? "" : "new-",
3725 if (hbr_ctl != hbr_ctl_new)
3726 snd_hda_codec_write(codec, pin_nid, 0,
3727 ATI_VERB_SET_HBR_CONTROL,
3736 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3737 hda_nid_t pin_nid, u32 stream_tag, int format)
3740 if (is_amdhdmi_rev3_or_later(codec)) {
3741 int ramp_rate = 180; /* default as per AMD spec */
3742 /* disable ramp-up/down for non-pcm as per AMD spec */
3743 if (format & AC_FMT_TYPE_NON_PCM)
3746 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3749 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3753 static int atihdmi_init(struct hda_codec *codec)
3755 struct hdmi_spec *spec = codec->spec;
3758 err = generic_hdmi_init(codec);
3763 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3764 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3766 /* make sure downmix information in infoframe is zero */
3767 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3769 /* enable channel-wise remap mode if supported */
3770 if (has_amd_full_remap_support(codec))
3771 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3772 ATI_VERB_SET_MULTICHANNEL_MODE,
3773 ATI_MULTICHANNEL_MODE_SINGLE);
3779 static int patch_atihdmi(struct hda_codec *codec)
3781 struct hdmi_spec *spec;
3782 struct hdmi_spec_per_cvt *per_cvt;
3785 err = patch_generic_hdmi(codec);
3790 codec->patch_ops.init = atihdmi_init;
3794 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3795 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3796 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3797 spec->ops.setup_stream = atihdmi_setup_stream;
3799 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3800 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3802 if (!has_amd_full_remap_support(codec)) {
3803 /* override to ATI/AMD-specific versions with pairwise mapping */
3804 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3805 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3806 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3807 atihdmi_paired_cea_alloc_to_tlv_chmap;
3808 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3811 /* ATI/AMD converters do not advertise all of their capabilities */
3812 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3813 per_cvt = get_cvt(spec, cvt_idx);
3814 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3815 per_cvt->rates |= SUPPORTED_RATES;
3816 per_cvt->formats |= SUPPORTED_FORMATS;
3817 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3820 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3822 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
3823 * the link-down as is. Tell the core to allow it.
3825 codec->link_down_at_suspend = 1;
3830 /* VIA HDMI Implementation */
3831 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3832 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3834 static int patch_via_hdmi(struct hda_codec *codec)
3836 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3842 static const struct hda_device_id snd_hda_id_hdmi[] = {
3843 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3844 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3845 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3846 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3847 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3848 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3849 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3850 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3851 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3852 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3853 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3854 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3855 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3856 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3857 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3858 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3859 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3860 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3861 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3862 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3863 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3864 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3865 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3866 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3867 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3868 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3869 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3870 /* 17 is known to be absent */
3871 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3872 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3873 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3874 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3875 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3876 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3877 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3878 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3879 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3880 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
3881 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
3882 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
3883 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
3884 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3885 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3886 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3887 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3888 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3889 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3890 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3891 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3892 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3893 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3894 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3895 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3896 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3897 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3898 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3899 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3900 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3901 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3902 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3903 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3904 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3905 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3906 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3907 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3908 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3909 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3910 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3911 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3912 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3913 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3914 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3915 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3916 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3917 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3918 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3919 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3920 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3921 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3922 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3923 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3924 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3925 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3926 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3927 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3928 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
3929 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3930 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3931 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3932 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3933 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3934 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3935 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3936 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3937 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3938 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3939 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3940 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
3941 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
3942 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
3943 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3944 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3945 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3946 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3947 /* special ID for generic HDMI */
3948 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3951 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3953 MODULE_LICENSE("GPL");
3954 MODULE_DESCRIPTION("HDMI HD-audio codec");
3955 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3956 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3957 MODULE_ALIAS("snd-hda-codec-atihdmi");
3959 static struct hda_codec_driver hdmi_driver = {
3960 .id = snd_hda_id_hdmi,
3963 module_hda_codec_driver(hdmi_driver);