3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <linux/vgaarb.h>
61 #include <linux/vga_switcheroo.h>
62 #include <linux/firmware.h>
63 #include "hda_codec.h"
66 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
67 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
68 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
69 static char *model[SNDRV_CARDS];
70 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
71 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
72 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int probe_only[SNDRV_CARDS];
74 static int jackpoll_ms[SNDRV_CARDS];
75 static bool single_cmd;
76 static int enable_msi = -1;
77 #ifdef CONFIG_SND_HDA_PATCH_LOADER
78 static char *patch[SNDRV_CARDS];
80 #ifdef CONFIG_SND_HDA_INPUT_BEEP
81 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
82 CONFIG_SND_HDA_INPUT_BEEP_MODE};
85 module_param_array(index, int, NULL, 0444);
86 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
87 module_param_array(id, charp, NULL, 0444);
88 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
89 module_param_array(enable, bool, NULL, 0444);
90 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
91 module_param_array(model, charp, NULL, 0444);
92 MODULE_PARM_DESC(model, "Use the given board model.");
93 module_param_array(position_fix, int, NULL, 0444);
94 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
95 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
96 module_param_array(bdl_pos_adj, int, NULL, 0644);
97 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
98 module_param_array(probe_mask, int, NULL, 0444);
99 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
100 module_param_array(probe_only, int, NULL, 0444);
101 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
102 module_param_array(jackpoll_ms, int, NULL, 0444);
103 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
104 module_param(single_cmd, bool, 0444);
105 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
106 "(for debugging only).");
107 module_param(enable_msi, bint, 0444);
108 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
109 #ifdef CONFIG_SND_HDA_PATCH_LOADER
110 module_param_array(patch, charp, NULL, 0444);
111 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113 #ifdef CONFIG_SND_HDA_INPUT_BEEP
114 module_param_array(beep_mode, bool, NULL, 0444);
115 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
116 "(0=off, 1=on) (default=1).");
120 static int param_set_xint(const char *val, const struct kernel_param *kp);
121 static struct kernel_param_ops param_ops_xint = {
122 .set = param_set_xint,
123 .get = param_get_int,
125 #define param_check_xint param_check_int
127 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
128 module_param(power_save, xint, 0644);
129 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
130 "(in second, 0 = disable).");
132 /* reset the HD-audio controller in power save mode.
133 * this may give more power-saving, but will take longer time to
136 static bool power_save_controller = 1;
137 module_param(power_save_controller, bool, 0644);
138 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
139 #endif /* CONFIG_PM */
141 static int align_buffer_size = -1;
142 module_param(align_buffer_size, bint, 0644);
143 MODULE_PARM_DESC(align_buffer_size,
144 "Force buffer and period sizes to be multiple of 128 bytes.");
147 static bool hda_snoop = true;
148 module_param_named(snoop, hda_snoop, bool, 0444);
149 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
150 #define azx_snoop(chip) (chip)->snoop
152 #define hda_snoop true
153 #define azx_snoop(chip) true
157 MODULE_LICENSE("GPL");
158 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
189 MODULE_DESCRIPTION("Intel HDA driver");
191 #ifdef CONFIG_SND_VERBOSE_PRINTK
192 #define SFX /* nop */
194 #define SFX "hda-intel: "
197 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
198 #ifdef CONFIG_SND_HDA_CODEC_HDMI
199 #define SUPPORT_VGA_SWITCHEROO
207 #define ICH6_REG_GCAP 0x00
208 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
209 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
210 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
211 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
212 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
213 #define ICH6_REG_VMIN 0x02
214 #define ICH6_REG_VMAJ 0x03
215 #define ICH6_REG_OUTPAY 0x04
216 #define ICH6_REG_INPAY 0x06
217 #define ICH6_REG_GCTL 0x08
218 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
219 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
220 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
221 #define ICH6_REG_WAKEEN 0x0c
222 #define ICH6_REG_STATESTS 0x0e
223 #define ICH6_REG_GSTS 0x10
224 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
225 #define ICH6_REG_INTCTL 0x20
226 #define ICH6_REG_INTSTS 0x24
227 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
228 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
229 #define ICH6_REG_SSYNC 0x38
230 #define ICH6_REG_CORBLBASE 0x40
231 #define ICH6_REG_CORBUBASE 0x44
232 #define ICH6_REG_CORBWP 0x48
233 #define ICH6_REG_CORBRP 0x4a
234 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
235 #define ICH6_REG_CORBCTL 0x4c
236 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
237 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
238 #define ICH6_REG_CORBSTS 0x4d
239 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
240 #define ICH6_REG_CORBSIZE 0x4e
242 #define ICH6_REG_RIRBLBASE 0x50
243 #define ICH6_REG_RIRBUBASE 0x54
244 #define ICH6_REG_RIRBWP 0x58
245 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
246 #define ICH6_REG_RINTCNT 0x5a
247 #define ICH6_REG_RIRBCTL 0x5c
248 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
249 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
250 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
251 #define ICH6_REG_RIRBSTS 0x5d
252 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
253 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
254 #define ICH6_REG_RIRBSIZE 0x5e
256 #define ICH6_REG_IC 0x60
257 #define ICH6_REG_IR 0x64
258 #define ICH6_REG_IRS 0x68
259 #define ICH6_IRS_VALID (1<<1)
260 #define ICH6_IRS_BUSY (1<<0)
262 #define ICH6_REG_DPLBASE 0x70
263 #define ICH6_REG_DPUBASE 0x74
264 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
266 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
267 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269 /* stream register offsets from stream base */
270 #define ICH6_REG_SD_CTL 0x00
271 #define ICH6_REG_SD_STS 0x03
272 #define ICH6_REG_SD_LPIB 0x04
273 #define ICH6_REG_SD_CBL 0x08
274 #define ICH6_REG_SD_LVI 0x0c
275 #define ICH6_REG_SD_FIFOW 0x0e
276 #define ICH6_REG_SD_FIFOSIZE 0x10
277 #define ICH6_REG_SD_FORMAT 0x12
278 #define ICH6_REG_SD_BDLPL 0x18
279 #define ICH6_REG_SD_BDLPU 0x1c
282 #define ICH6_PCIREG_TCSEL 0x44
288 /* max number of SDs */
289 /* ICH, ATI and VIA have 4 playback and 4 capture */
290 #define ICH6_NUM_CAPTURE 4
291 #define ICH6_NUM_PLAYBACK 4
293 /* ULI has 6 playback and 5 capture */
294 #define ULI_NUM_CAPTURE 5
295 #define ULI_NUM_PLAYBACK 6
297 /* ATI HDMI has 1 playback and 0 capture */
298 #define ATIHDMI_NUM_CAPTURE 0
299 #define ATIHDMI_NUM_PLAYBACK 1
301 /* TERA has 4 playback and 3 capture */
302 #define TERA_NUM_CAPTURE 3
303 #define TERA_NUM_PLAYBACK 4
305 /* this number is statically defined for simplicity */
306 #define MAX_AZX_DEV 16
308 /* max number of fragments - we may use more if allocating more pages for BDL */
309 #define BDL_SIZE 4096
310 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
311 #define AZX_MAX_FRAG 32
312 /* max buffer size - no h/w limit, you can increase as you like */
313 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
315 /* RIRB int mask: overrun[2], response[0] */
316 #define RIRB_INT_RESPONSE 0x01
317 #define RIRB_INT_OVERRUN 0x04
318 #define RIRB_INT_MASK 0x05
320 /* STATESTS int mask: S3,SD2,SD1,SD0 */
321 #define AZX_MAX_CODECS 8
322 #define AZX_DEFAULT_CODECS 4
323 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
326 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
327 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
328 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
329 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
330 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
331 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
332 #define SD_CTL_STREAM_TAG_SHIFT 20
334 /* SD_CTL and SD_STS */
335 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
336 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
337 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
338 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
342 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
344 /* INTCTL and INTSTS */
345 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
346 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
347 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
349 /* below are so far hardcoded - should read registers in future */
350 #define ICH6_MAX_CORB_ENTRIES 256
351 #define ICH6_MAX_RIRB_ENTRIES 256
353 /* position fix mode */
362 /* Defines for ATI HD Audio support in SB450 south bridge */
363 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
364 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
366 /* Defines for Nvidia HDA support */
367 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
368 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
369 #define NVIDIA_HDA_ISTRM_COH 0x4d
370 #define NVIDIA_HDA_OSTRM_COH 0x4c
371 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
373 /* Defines for Intel SCH HDA snoop control */
374 #define INTEL_SCH_HDA_DEVC 0x78
375 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
377 /* Define IN stream 0 FIFO size offset in VIA controller */
378 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
379 /* Define VIA HD Audio Device ID*/
380 #define VIA_HDAC_DEVICE_ID 0x3288
382 /* HD Audio class code */
383 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
389 struct snd_dma_buffer bdl; /* BDL buffer */
390 u32 *posbuf; /* position buffer pointer */
392 unsigned int bufsize; /* size of the play buffer in bytes */
393 unsigned int period_bytes; /* size of the period in bytes */
394 unsigned int frags; /* number for period in the play buffer */
395 unsigned int fifo_size; /* FIFO size */
396 unsigned long start_wallclk; /* start + minimum wallclk */
397 unsigned long period_wallclk; /* wallclk for period */
399 void __iomem *sd_addr; /* stream descriptor pointer */
401 u32 sd_int_sta_mask; /* stream int status mask */
404 struct snd_pcm_substream *substream; /* assigned substream,
407 unsigned int format_val; /* format value to be set in the
408 * controller and the codec
410 unsigned char stream_tag; /* assigned stream */
411 unsigned char index; /* stream index */
412 int assigned_key; /* last device# key assigned to */
414 unsigned int opened :1;
415 unsigned int running :1;
416 unsigned int irq_pending :1;
419 * A flag to ensure DMA position is 0
420 * when link position is not greater than FIFO size
422 unsigned int insufficient :1;
423 unsigned int wc_marked:1;
424 unsigned int no_period_wakeup:1;
426 struct timecounter azx_tc;
427 struct cyclecounter azx_cc;
432 u32 *buf; /* CORB/RIRB buffer
433 * Each CORB entry is 4byte, RIRB is 8byte
435 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
437 unsigned short rp, wp; /* read/write pointers */
438 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
439 u32 res[AZX_MAX_CODECS]; /* last read value */
445 struct hda_codec *codec;
446 struct hda_pcm_stream *hinfo[2];
447 struct list_head list;
451 struct snd_card *card;
455 /* chip type specific */
457 unsigned int driver_caps;
458 int playback_streams;
459 int playback_index_offset;
461 int capture_index_offset;
466 void __iomem *remap_addr;
471 struct mutex open_mutex;
473 /* streams (x num_streams) */
474 struct azx_dev *azx_dev;
477 struct list_head pcm_list; /* azx_pcm list */
480 unsigned short codec_mask;
481 int codec_probe_mask; /* copied from probe_mask option */
483 unsigned int beep_mode;
489 /* CORB/RIRB and position buffers */
490 struct snd_dma_buffer rb;
491 struct snd_dma_buffer posbuf;
493 #ifdef CONFIG_SND_HDA_PATCH_LOADER
494 const struct firmware *fw;
498 int position_fix[2]; /* for both playback/capture streams */
500 unsigned int running :1;
501 unsigned int initialized :1;
502 unsigned int single_cmd :1;
503 unsigned int polling_mode :1;
505 unsigned int irq_pending_warned :1;
506 unsigned int probing :1; /* codec probing phase */
507 unsigned int snoop:1;
508 unsigned int align_buffer_size:1;
509 unsigned int region_requested:1;
511 /* VGA-switcheroo setup */
512 unsigned int use_vga_switcheroo:1;
513 unsigned int vga_switcheroo_registered:1;
514 unsigned int init_failed:1; /* delayed init failed */
515 unsigned int disabled:1; /* disabled by VGA-switcher */
518 unsigned int last_cmd[AZX_MAX_CODECS];
520 /* for pending irqs */
521 struct work_struct irq_pending_work;
523 /* reboot notifier (for mysterious hangup problem at power-down) */
524 struct notifier_block reboot_notifier;
526 /* card list (for power_save trigger) */
527 struct list_head list;
530 #define CREATE_TRACE_POINTS
531 #include "hda_intel_trace.h"
540 AZX_DRIVER_ATIHDMI_NS,
549 AZX_NUM_DRIVERS, /* keep this as last entry */
552 /* driver quirks (capabilities) */
553 /* bits 0-7 are used for indicating driver type */
554 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
555 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
556 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
557 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
558 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
559 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
560 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
561 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
562 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
563 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
564 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
565 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
566 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
567 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
568 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
569 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
570 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
572 /* quirks for ATI SB / AMD Hudson */
573 #define AZX_DCAPS_PRESET_ATI_SB \
574 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
575 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
577 /* quirks for ATI/AMD HDMI */
578 #define AZX_DCAPS_PRESET_ATI_HDMI \
579 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
581 /* quirks for Nvidia */
582 #define AZX_DCAPS_PRESET_NVIDIA \
583 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
584 AZX_DCAPS_ALIGN_BUFSIZE)
586 #define AZX_DCAPS_PRESET_CTHDA \
587 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
590 * VGA-switcher support
592 #ifdef SUPPORT_VGA_SWITCHEROO
593 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
595 #define use_vga_switcheroo(chip) 0
598 #if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
599 #define DELAYED_INIT_MARK
600 #define DELAYED_INITDATA_MARK
602 #define DELAYED_INIT_MARK __devinit
603 #define DELAYED_INITDATA_MARK __devinitdata
606 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
607 [AZX_DRIVER_ICH] = "HDA Intel",
608 [AZX_DRIVER_PCH] = "HDA Intel PCH",
609 [AZX_DRIVER_SCH] = "HDA Intel MID",
610 [AZX_DRIVER_ATI] = "HDA ATI SB",
611 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
612 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
613 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
614 [AZX_DRIVER_SIS] = "HDA SIS966",
615 [AZX_DRIVER_ULI] = "HDA ULI M5461",
616 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
617 [AZX_DRIVER_TERA] = "HDA Teradici",
618 [AZX_DRIVER_CTX] = "HDA Creative",
619 [AZX_DRIVER_CTHDA] = "HDA Creative",
620 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
624 * macros for easy use
626 #define azx_writel(chip,reg,value) \
627 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
628 #define azx_readl(chip,reg) \
629 readl((chip)->remap_addr + ICH6_REG_##reg)
630 #define azx_writew(chip,reg,value) \
631 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
632 #define azx_readw(chip,reg) \
633 readw((chip)->remap_addr + ICH6_REG_##reg)
634 #define azx_writeb(chip,reg,value) \
635 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
636 #define azx_readb(chip,reg) \
637 readb((chip)->remap_addr + ICH6_REG_##reg)
639 #define azx_sd_writel(dev,reg,value) \
640 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
641 #define azx_sd_readl(dev,reg) \
642 readl((dev)->sd_addr + ICH6_REG_##reg)
643 #define azx_sd_writew(dev,reg,value) \
644 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
645 #define azx_sd_readw(dev,reg) \
646 readw((dev)->sd_addr + ICH6_REG_##reg)
647 #define azx_sd_writeb(dev,reg,value) \
648 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
649 #define azx_sd_readb(dev,reg) \
650 readb((dev)->sd_addr + ICH6_REG_##reg)
652 /* for pcm support */
653 #define get_azx_dev(substream) (substream->runtime->private_data)
656 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
661 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
663 set_memory_wc((unsigned long)addr, pages);
665 set_memory_wb((unsigned long)addr, pages);
669 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
672 __mark_pages_wc(chip, buf->area, buf->bytes, on);
674 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
675 struct snd_pcm_runtime *runtime, bool on)
677 if (azx_dev->wc_marked != on) {
678 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
679 azx_dev->wc_marked = on;
683 /* NOP for other archs */
684 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
688 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
689 struct snd_pcm_runtime *runtime, bool on)
694 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
695 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
697 * Interface for HD codec
701 * CORB / RIRB interface
703 static int azx_alloc_cmd_io(struct azx *chip)
707 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
708 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
709 snd_dma_pci_data(chip->pci),
710 PAGE_SIZE, &chip->rb);
712 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
715 mark_pages_wc(chip, &chip->rb, true);
719 static void azx_init_cmd_io(struct azx *chip)
721 spin_lock_irq(&chip->reg_lock);
723 chip->corb.addr = chip->rb.addr;
724 chip->corb.buf = (u32 *)chip->rb.area;
725 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
726 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
728 /* set the corb size to 256 entries (ULI requires explicitly) */
729 azx_writeb(chip, CORBSIZE, 0x02);
730 /* set the corb write pointer to 0 */
731 azx_writew(chip, CORBWP, 0);
732 /* reset the corb hw read pointer */
733 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
734 /* enable corb dma */
735 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
738 chip->rirb.addr = chip->rb.addr + 2048;
739 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
740 chip->rirb.wp = chip->rirb.rp = 0;
741 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
742 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
743 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
745 /* set the rirb size to 256 entries (ULI requires explicitly) */
746 azx_writeb(chip, RIRBSIZE, 0x02);
747 /* reset the rirb hw write pointer */
748 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
749 /* set N=1, get RIRB response interrupt for new entry */
750 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
751 azx_writew(chip, RINTCNT, 0xc0);
753 azx_writew(chip, RINTCNT, 1);
754 /* enable rirb dma and response irq */
755 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
756 spin_unlock_irq(&chip->reg_lock);
759 static void azx_free_cmd_io(struct azx *chip)
761 spin_lock_irq(&chip->reg_lock);
762 /* disable ringbuffer DMAs */
763 azx_writeb(chip, RIRBCTL, 0);
764 azx_writeb(chip, CORBCTL, 0);
765 spin_unlock_irq(&chip->reg_lock);
768 static unsigned int azx_command_addr(u32 cmd)
770 unsigned int addr = cmd >> 28;
772 if (addr >= AZX_MAX_CODECS) {
780 static unsigned int azx_response_addr(u32 res)
782 unsigned int addr = res & 0xf;
784 if (addr >= AZX_MAX_CODECS) {
793 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
795 struct azx *chip = bus->private_data;
796 unsigned int addr = azx_command_addr(val);
799 spin_lock_irq(&chip->reg_lock);
801 /* add command to corb */
802 wp = azx_readb(chip, CORBWP);
804 wp %= ICH6_MAX_CORB_ENTRIES;
806 chip->rirb.cmds[addr]++;
807 chip->corb.buf[wp] = cpu_to_le32(val);
808 azx_writel(chip, CORBWP, wp);
810 spin_unlock_irq(&chip->reg_lock);
815 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
817 /* retrieve RIRB entry - called from interrupt handler */
818 static void azx_update_rirb(struct azx *chip)
824 wp = azx_readb(chip, RIRBWP);
825 if (wp == chip->rirb.wp)
829 while (chip->rirb.rp != wp) {
831 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
833 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
834 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
835 res = le32_to_cpu(chip->rirb.buf[rp]);
836 addr = azx_response_addr(res_ex);
837 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
838 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
839 else if (chip->rirb.cmds[addr]) {
840 chip->rirb.res[addr] = res;
842 chip->rirb.cmds[addr]--;
844 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
848 chip->last_cmd[addr]);
852 /* receive a response */
853 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
856 struct azx *chip = bus->private_data;
857 unsigned long timeout;
858 unsigned long loopcounter;
862 timeout = jiffies + msecs_to_jiffies(1000);
864 for (loopcounter = 0;; loopcounter++) {
865 if (chip->polling_mode || do_poll) {
866 spin_lock_irq(&chip->reg_lock);
867 azx_update_rirb(chip);
868 spin_unlock_irq(&chip->reg_lock);
870 if (!chip->rirb.cmds[addr]) {
875 chip->poll_count = 0;
876 return chip->rirb.res[addr]; /* the last value */
878 if (time_after(jiffies, timeout))
880 if (bus->needs_damn_long_delay || loopcounter > 3000)
881 msleep(2); /* temporary workaround */
888 if (!chip->polling_mode && chip->poll_count < 2) {
889 snd_printdd(SFX "azx_get_response timeout, "
890 "polling the codec once: last cmd=0x%08x\n",
891 chip->last_cmd[addr]);
898 if (!chip->polling_mode) {
899 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
900 "switching to polling mode: last cmd=0x%08x\n",
901 chip->last_cmd[addr]);
902 chip->polling_mode = 1;
907 snd_printk(KERN_WARNING SFX "No response from codec, "
908 "disabling MSI: last cmd=0x%08x\n",
909 chip->last_cmd[addr]);
910 free_irq(chip->irq, chip);
912 pci_disable_msi(chip->pci);
914 if (azx_acquire_irq(chip, 1) < 0) {
922 /* If this critical timeout happens during the codec probing
923 * phase, this is likely an access to a non-existing codec
924 * slot. Better to return an error and reset the system.
929 /* a fatal communication error; need either to reset or to fallback
930 * to the single_cmd mode
933 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
934 bus->response_reset = 1;
935 return -1; /* give a chance to retry */
938 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
939 "switching to single_cmd mode: last cmd=0x%08x\n",
940 chip->last_cmd[addr]);
941 chip->single_cmd = 1;
942 bus->response_reset = 0;
943 /* release CORB/RIRB */
944 azx_free_cmd_io(chip);
945 /* disable unsolicited responses */
946 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
951 * Use the single immediate command instead of CORB/RIRB for simplicity
953 * Note: according to Intel, this is not preferred use. The command was
954 * intended for the BIOS only, and may get confused with unsolicited
955 * responses. So, we shouldn't use it for normal operation from the
957 * I left the codes, however, for debugging/testing purposes.
960 /* receive a response */
961 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
966 /* check IRV busy bit */
967 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
968 /* reuse rirb.res as the response return value */
969 chip->rirb.res[addr] = azx_readl(chip, IR);
974 if (printk_ratelimit())
975 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
976 azx_readw(chip, IRS));
977 chip->rirb.res[addr] = -1;
982 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
984 struct azx *chip = bus->private_data;
985 unsigned int addr = azx_command_addr(val);
990 /* check ICB busy bit */
991 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
992 /* Clear IRV valid bit */
993 azx_writew(chip, IRS, azx_readw(chip, IRS) |
995 azx_writel(chip, IC, val);
996 azx_writew(chip, IRS, azx_readw(chip, IRS) |
998 return azx_single_wait_for_response(chip, addr);
1002 if (printk_ratelimit())
1003 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1004 azx_readw(chip, IRS), val);
1008 /* receive a response */
1009 static unsigned int azx_single_get_response(struct hda_bus *bus,
1012 struct azx *chip = bus->private_data;
1013 return chip->rirb.res[addr];
1017 * The below are the main callbacks from hda_codec.
1019 * They are just the skeleton to call sub-callbacks according to the
1020 * current setting of chip->single_cmd.
1023 /* send a command */
1024 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1026 struct azx *chip = bus->private_data;
1030 chip->last_cmd[azx_command_addr(val)] = val;
1031 if (chip->single_cmd)
1032 return azx_single_send_cmd(bus, val);
1034 return azx_corb_send_cmd(bus, val);
1037 /* get a response */
1038 static unsigned int azx_get_response(struct hda_bus *bus,
1041 struct azx *chip = bus->private_data;
1044 if (chip->single_cmd)
1045 return azx_single_get_response(bus, addr);
1047 return azx_rirb_get_response(bus, addr);
1051 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1054 /* reset codec link */
1055 static int azx_reset(struct azx *chip, int full_reset)
1062 /* clear STATESTS */
1063 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1065 /* reset controller */
1066 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1069 while (azx_readb(chip, GCTL) && --count)
1072 /* delay for >= 100us for codec PLL to settle per spec
1073 * Rev 0.9 section 5.5.1
1077 /* Bring controller out of reset */
1078 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1081 while (!azx_readb(chip, GCTL) && --count)
1084 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1088 /* check to see if controller is ready */
1089 if (!azx_readb(chip, GCTL)) {
1090 snd_printd(SFX "azx_reset: controller not ready!\n");
1094 /* Accept unsolicited responses */
1095 if (!chip->single_cmd)
1096 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1100 if (!chip->codec_mask) {
1101 chip->codec_mask = azx_readw(chip, STATESTS);
1102 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1110 * Lowlevel interface
1113 /* enable interrupts */
1114 static void azx_int_enable(struct azx *chip)
1116 /* enable controller CIE and GIE */
1117 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1118 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1121 /* disable interrupts */
1122 static void azx_int_disable(struct azx *chip)
1126 /* disable interrupts in stream descriptor */
1127 for (i = 0; i < chip->num_streams; i++) {
1128 struct azx_dev *azx_dev = &chip->azx_dev[i];
1129 azx_sd_writeb(azx_dev, SD_CTL,
1130 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1133 /* disable SIE for all streams */
1134 azx_writeb(chip, INTCTL, 0);
1136 /* disable controller CIE and GIE */
1137 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1138 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1141 /* clear interrupts */
1142 static void azx_int_clear(struct azx *chip)
1146 /* clear stream status */
1147 for (i = 0; i < chip->num_streams; i++) {
1148 struct azx_dev *azx_dev = &chip->azx_dev[i];
1149 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1152 /* clear STATESTS */
1153 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1155 /* clear rirb status */
1156 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1158 /* clear int status */
1159 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1162 /* start a stream */
1163 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1166 * Before stream start, initialize parameter
1168 azx_dev->insufficient = 1;
1171 azx_writel(chip, INTCTL,
1172 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1173 /* set DMA start and interrupt mask */
1174 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1175 SD_CTL_DMA_START | SD_INT_MASK);
1179 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1181 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1182 ~(SD_CTL_DMA_START | SD_INT_MASK));
1183 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1187 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1189 azx_stream_clear(chip, azx_dev);
1191 azx_writel(chip, INTCTL,
1192 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1197 * reset and start the controller registers
1199 static void azx_init_chip(struct azx *chip, int full_reset)
1201 if (chip->initialized)
1204 /* reset controller */
1205 azx_reset(chip, full_reset);
1207 /* initialize interrupts */
1208 azx_int_clear(chip);
1209 azx_int_enable(chip);
1211 /* initialize the codec command I/O */
1212 if (!chip->single_cmd)
1213 azx_init_cmd_io(chip);
1215 /* program the position buffer */
1216 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1217 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1219 chip->initialized = 1;
1223 * initialize the PCI registers
1225 /* update bits in a PCI register byte */
1226 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1227 unsigned char mask, unsigned char val)
1231 pci_read_config_byte(pci, reg, &data);
1233 data |= (val & mask);
1234 pci_write_config_byte(pci, reg, data);
1237 static void azx_init_pci(struct azx *chip)
1239 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1240 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1241 * Ensuring these bits are 0 clears playback static on some HD Audio
1243 * The PCI register TCSEL is defined in the Intel manuals.
1245 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1246 snd_printdd(SFX "Clearing TCSEL\n");
1247 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1250 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1251 * we need to enable snoop.
1253 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1254 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1255 update_pci_byte(chip->pci,
1256 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1257 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1260 /* For NVIDIA HDA, enable snoop */
1261 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1262 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1263 update_pci_byte(chip->pci,
1264 NVIDIA_HDA_TRANSREG_ADDR,
1265 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1266 update_pci_byte(chip->pci,
1267 NVIDIA_HDA_ISTRM_COH,
1268 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1269 update_pci_byte(chip->pci,
1270 NVIDIA_HDA_OSTRM_COH,
1271 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1274 /* Enable SCH/PCH snoop if needed */
1275 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1276 unsigned short snoop;
1277 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1278 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1279 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1280 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1281 if (!azx_snoop(chip))
1282 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1283 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1284 pci_read_config_word(chip->pci,
1285 INTEL_SCH_HDA_DEVC, &snoop);
1287 snd_printdd(SFX "SCH snoop: %s\n",
1288 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1289 ? "Disabled" : "Enabled");
1294 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1299 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1301 struct azx *chip = dev_id;
1302 struct azx_dev *azx_dev;
1307 #ifdef CONFIG_PM_RUNTIME
1308 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1312 spin_lock(&chip->reg_lock);
1314 if (chip->disabled) {
1315 spin_unlock(&chip->reg_lock);
1319 status = azx_readl(chip, INTSTS);
1321 spin_unlock(&chip->reg_lock);
1325 for (i = 0; i < chip->num_streams; i++) {
1326 azx_dev = &chip->azx_dev[i];
1327 if (status & azx_dev->sd_int_sta_mask) {
1328 sd_status = azx_sd_readb(azx_dev, SD_STS);
1329 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1330 if (!azx_dev->substream || !azx_dev->running ||
1331 !(sd_status & SD_INT_COMPLETE))
1333 /* check whether this IRQ is really acceptable */
1334 ok = azx_position_ok(chip, azx_dev);
1336 azx_dev->irq_pending = 0;
1337 spin_unlock(&chip->reg_lock);
1338 snd_pcm_period_elapsed(azx_dev->substream);
1339 spin_lock(&chip->reg_lock);
1340 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1341 /* bogus IRQ, process it later */
1342 azx_dev->irq_pending = 1;
1343 queue_work(chip->bus->workq,
1344 &chip->irq_pending_work);
1349 /* clear rirb int */
1350 status = azx_readb(chip, RIRBSTS);
1351 if (status & RIRB_INT_MASK) {
1352 if (status & RIRB_INT_RESPONSE) {
1353 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1355 azx_update_rirb(chip);
1357 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1361 /* clear state status int */
1362 if (azx_readb(chip, STATESTS) & 0x04)
1363 azx_writeb(chip, STATESTS, 0x04);
1365 spin_unlock(&chip->reg_lock);
1372 * set up a BDL entry
1374 static int setup_bdle(struct azx *chip,
1375 struct snd_pcm_substream *substream,
1376 struct azx_dev *azx_dev, u32 **bdlp,
1377 int ofs, int size, int with_ioc)
1385 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1388 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1389 /* program the address field of the BDL entry */
1390 bdl[0] = cpu_to_le32((u32)addr);
1391 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1392 /* program the size field of the BDL entry */
1393 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1394 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1395 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1396 u32 remain = 0x1000 - (ofs & 0xfff);
1400 bdl[2] = cpu_to_le32(chunk);
1401 /* program the IOC to enable interrupt
1402 * only when the whole fragment is processed
1405 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1415 * set up BDL entries
1417 static int azx_setup_periods(struct azx *chip,
1418 struct snd_pcm_substream *substream,
1419 struct azx_dev *azx_dev)
1422 int i, ofs, periods, period_bytes;
1425 /* reset BDL address */
1426 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1427 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1429 period_bytes = azx_dev->period_bytes;
1430 periods = azx_dev->bufsize / period_bytes;
1432 /* program the initial BDL entries */
1433 bdl = (u32 *)azx_dev->bdl.area;
1436 pos_adj = bdl_pos_adj[chip->dev_index];
1437 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1438 struct snd_pcm_runtime *runtime = substream->runtime;
1439 int pos_align = pos_adj;
1440 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1442 pos_adj = pos_align;
1444 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1446 pos_adj = frames_to_bytes(runtime, pos_adj);
1447 if (pos_adj >= period_bytes) {
1448 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1449 bdl_pos_adj[chip->dev_index]);
1452 ofs = setup_bdle(chip, substream, azx_dev,
1453 &bdl, ofs, pos_adj, true);
1459 for (i = 0; i < periods; i++) {
1460 if (i == periods - 1 && pos_adj)
1461 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1462 period_bytes - pos_adj, 0);
1464 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1466 !azx_dev->no_period_wakeup);
1473 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1474 azx_dev->bufsize, period_bytes);
1479 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1484 azx_stream_clear(chip, azx_dev);
1486 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1487 SD_CTL_STREAM_RESET);
1490 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1493 val &= ~SD_CTL_STREAM_RESET;
1494 azx_sd_writeb(azx_dev, SD_CTL, val);
1498 /* waiting for hardware to report that the stream is out of reset */
1499 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1503 /* reset first position - may not be synced with hw at this time */
1504 *azx_dev->posbuf = 0;
1508 * set up the SD for streaming
1510 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1513 /* make sure the run bit is zero for SD */
1514 azx_stream_clear(chip, azx_dev);
1515 /* program the stream_tag */
1516 val = azx_sd_readl(azx_dev, SD_CTL);
1517 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1518 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1519 if (!azx_snoop(chip))
1520 val |= SD_CTL_TRAFFIC_PRIO;
1521 azx_sd_writel(azx_dev, SD_CTL, val);
1523 /* program the length of samples in cyclic buffer */
1524 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1526 /* program the stream format */
1527 /* this value needs to be the same as the one programmed */
1528 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1530 /* program the stream LVI (last valid index) of the BDL */
1531 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1533 /* program the BDL address */
1534 /* lower BDL address */
1535 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1536 /* upper BDL address */
1537 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1539 /* enable the position buffer */
1540 if (chip->position_fix[0] != POS_FIX_LPIB ||
1541 chip->position_fix[1] != POS_FIX_LPIB) {
1542 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1543 azx_writel(chip, DPLBASE,
1544 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1547 /* set the interrupt enable bits in the descriptor control register */
1548 azx_sd_writel(azx_dev, SD_CTL,
1549 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1555 * Probe the given codec address
1557 static int probe_codec(struct azx *chip, int addr)
1559 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1560 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1563 mutex_lock(&chip->bus->cmd_mutex);
1565 azx_send_cmd(chip->bus, cmd);
1566 res = azx_get_response(chip->bus, addr);
1568 mutex_unlock(&chip->bus->cmd_mutex);
1571 snd_printdd(SFX "codec #%d probed OK\n", addr);
1575 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1576 struct hda_pcm *cpcm);
1577 static void azx_stop_chip(struct azx *chip);
1579 static void azx_bus_reset(struct hda_bus *bus)
1581 struct azx *chip = bus->private_data;
1584 azx_stop_chip(chip);
1585 azx_init_chip(chip, 1);
1587 if (chip->initialized) {
1589 list_for_each_entry(p, &chip->pcm_list, list)
1590 snd_pcm_suspend_all(p->pcm);
1591 snd_hda_suspend(chip->bus);
1592 snd_hda_resume(chip->bus);
1598 static int get_jackpoll_interval(struct azx *chip)
1600 int i = jackpoll_ms[chip->dev_index];
1604 if (i < 50 || i > 60000)
1607 j = msecs_to_jiffies(i);
1609 snd_printk(KERN_WARNING SFX
1610 "jackpoll_ms value out of range: %d\n", i);
1615 * Codec initialization
1618 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1619 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1620 [AZX_DRIVER_NVIDIA] = 8,
1621 [AZX_DRIVER_TERA] = 1,
1624 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1626 struct hda_bus_template bus_temp;
1630 memset(&bus_temp, 0, sizeof(bus_temp));
1631 bus_temp.private_data = chip;
1632 bus_temp.modelname = model;
1633 bus_temp.pci = chip->pci;
1634 bus_temp.ops.command = azx_send_cmd;
1635 bus_temp.ops.get_response = azx_get_response;
1636 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1637 bus_temp.ops.bus_reset = azx_bus_reset;
1639 bus_temp.power_save = &power_save;
1640 bus_temp.ops.pm_notify = azx_power_notify;
1643 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1647 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1648 snd_printd(SFX "Enable delay in RIRB handling\n");
1649 chip->bus->needs_damn_long_delay = 1;
1653 max_slots = azx_max_codecs[chip->driver_type];
1655 max_slots = AZX_DEFAULT_CODECS;
1657 /* First try to probe all given codec slots */
1658 for (c = 0; c < max_slots; c++) {
1659 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1660 if (probe_codec(chip, c) < 0) {
1661 /* Some BIOSen give you wrong codec addresses
1664 snd_printk(KERN_WARNING SFX
1665 "Codec #%d probe error; "
1666 "disabling it...\n", c);
1667 chip->codec_mask &= ~(1 << c);
1668 /* More badly, accessing to a non-existing
1669 * codec often screws up the controller chip,
1670 * and disturbs the further communications.
1671 * Thus if an error occurs during probing,
1672 * better to reset the controller chip to
1673 * get back to the sanity state.
1675 azx_stop_chip(chip);
1676 azx_init_chip(chip, 1);
1681 /* AMD chipsets often cause the communication stalls upon certain
1682 * sequence like the pin-detection. It seems that forcing the synced
1683 * access works around the stall. Grrr...
1685 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1686 snd_printd(SFX "Enable sync_write for stable communication\n");
1687 chip->bus->sync_write = 1;
1688 chip->bus->allow_bus_reset = 1;
1691 /* Then create codec instances */
1692 for (c = 0; c < max_slots; c++) {
1693 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1694 struct hda_codec *codec;
1695 err = snd_hda_codec_new(chip->bus, c, &codec);
1698 codec->jackpoll_interval = get_jackpoll_interval(chip);
1699 codec->beep_mode = chip->beep_mode;
1704 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1710 /* configure each codec instance */
1711 static int __devinit azx_codec_configure(struct azx *chip)
1713 struct hda_codec *codec;
1714 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1715 snd_hda_codec_configure(codec);
1725 /* assign a stream for the PCM */
1726 static inline struct azx_dev *
1727 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1730 struct azx_dev *res = NULL;
1731 /* make a non-zero unique key for the substream */
1732 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1733 (substream->stream + 1);
1735 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1736 dev = chip->playback_index_offset;
1737 nums = chip->playback_streams;
1739 dev = chip->capture_index_offset;
1740 nums = chip->capture_streams;
1742 for (i = 0; i < nums; i++, dev++)
1743 if (!chip->azx_dev[dev].opened) {
1744 res = &chip->azx_dev[dev];
1745 if (res->assigned_key == key)
1750 res->assigned_key = key;
1755 /* release the assigned stream */
1756 static inline void azx_release_device(struct azx_dev *azx_dev)
1758 azx_dev->opened = 0;
1761 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1763 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1764 struct snd_pcm_substream *substream = azx_dev->substream;
1765 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1766 struct azx *chip = apcm->chip;
1768 return azx_readl(chip, WALLCLK);
1771 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1772 bool force, cycle_t last)
1774 struct azx_dev *azx_dev = get_azx_dev(substream);
1775 struct timecounter *tc = &azx_dev->azx_tc;
1776 struct cyclecounter *cc = &azx_dev->azx_cc;
1779 cc->read = azx_cc_read;
1780 cc->mask = CLOCKSOURCE_MASK(32);
1783 * Converting from 24 MHz to ns means applying a 125/3 factor.
1784 * To avoid any saturation issues in intermediate operations,
1785 * the 125 factor is applied first. The division is applied
1786 * last after reading the timecounter value.
1787 * Applying the 1/3 factor as part of the multiplication
1788 * requires at least 20 bits for a decent precision, however
1789 * overflows occur after about 4 hours or less, not a option.
1792 cc->mult = 125; /* saturation after 195 years */
1795 nsec = 0; /* audio time is elapsed time since trigger */
1796 timecounter_init(tc, cc, nsec);
1799 * force timecounter to use predefined value,
1800 * used for synchronized starts
1802 tc->cycle_last = last;
1805 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1806 struct timespec *ts)
1808 struct azx_dev *azx_dev = get_azx_dev(substream);
1811 nsec = timecounter_read(&azx_dev->azx_tc);
1812 nsec = div_u64(nsec, 3); /* can be optimized */
1814 *ts = ns_to_timespec(nsec);
1819 static struct snd_pcm_hardware azx_pcm_hw = {
1820 .info = (SNDRV_PCM_INFO_MMAP |
1821 SNDRV_PCM_INFO_INTERLEAVED |
1822 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1823 SNDRV_PCM_INFO_MMAP_VALID |
1824 /* No full-resume yet implemented */
1825 /* SNDRV_PCM_INFO_RESUME |*/
1826 SNDRV_PCM_INFO_PAUSE |
1827 SNDRV_PCM_INFO_SYNC_START |
1828 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1829 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1830 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1831 .rates = SNDRV_PCM_RATE_48000,
1836 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1837 .period_bytes_min = 128,
1838 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1840 .periods_max = AZX_MAX_FRAG,
1844 static int azx_pcm_open(struct snd_pcm_substream *substream)
1846 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1847 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1848 struct azx *chip = apcm->chip;
1849 struct azx_dev *azx_dev;
1850 struct snd_pcm_runtime *runtime = substream->runtime;
1851 unsigned long flags;
1855 mutex_lock(&chip->open_mutex);
1856 azx_dev = azx_assign_device(chip, substream);
1857 if (azx_dev == NULL) {
1858 mutex_unlock(&chip->open_mutex);
1861 runtime->hw = azx_pcm_hw;
1862 runtime->hw.channels_min = hinfo->channels_min;
1863 runtime->hw.channels_max = hinfo->channels_max;
1864 runtime->hw.formats = hinfo->formats;
1865 runtime->hw.rates = hinfo->rates;
1866 snd_pcm_limit_hw_rates(runtime);
1867 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1869 /* avoid wrap-around with wall-clock */
1870 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1874 if (chip->align_buffer_size)
1875 /* constrain buffer sizes to be multiple of 128
1876 bytes. This is more efficient in terms of memory
1877 access but isn't required by the HDA spec and
1878 prevents users from specifying exact period/buffer
1879 sizes. For example for 44.1kHz, a period size set
1880 to 20ms will be rounded to 19.59ms. */
1883 /* Don't enforce steps on buffer sizes, still need to
1884 be multiple of 4 bytes (HDA spec). Tested on Intel
1885 HDA controllers, may not work on all devices where
1886 option needs to be disabled */
1889 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1891 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1893 snd_hda_power_up_d3wait(apcm->codec);
1894 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1896 azx_release_device(azx_dev);
1897 snd_hda_power_down(apcm->codec);
1898 mutex_unlock(&chip->open_mutex);
1901 snd_pcm_limit_hw_rates(runtime);
1903 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1904 snd_BUG_ON(!runtime->hw.channels_max) ||
1905 snd_BUG_ON(!runtime->hw.formats) ||
1906 snd_BUG_ON(!runtime->hw.rates)) {
1907 azx_release_device(azx_dev);
1908 hinfo->ops.close(hinfo, apcm->codec, substream);
1909 snd_hda_power_down(apcm->codec);
1910 mutex_unlock(&chip->open_mutex);
1914 /* disable WALLCLOCK timestamps for capture streams
1915 until we figure out how to handle digital inputs */
1916 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1917 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1919 spin_lock_irqsave(&chip->reg_lock, flags);
1920 azx_dev->substream = substream;
1921 azx_dev->running = 0;
1922 spin_unlock_irqrestore(&chip->reg_lock, flags);
1924 runtime->private_data = azx_dev;
1925 snd_pcm_set_sync(substream);
1926 mutex_unlock(&chip->open_mutex);
1930 static int azx_pcm_close(struct snd_pcm_substream *substream)
1932 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1933 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1934 struct azx *chip = apcm->chip;
1935 struct azx_dev *azx_dev = get_azx_dev(substream);
1936 unsigned long flags;
1938 mutex_lock(&chip->open_mutex);
1939 spin_lock_irqsave(&chip->reg_lock, flags);
1940 azx_dev->substream = NULL;
1941 azx_dev->running = 0;
1942 spin_unlock_irqrestore(&chip->reg_lock, flags);
1943 azx_release_device(azx_dev);
1944 hinfo->ops.close(hinfo, apcm->codec, substream);
1945 snd_hda_power_down(apcm->codec);
1946 mutex_unlock(&chip->open_mutex);
1950 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1951 struct snd_pcm_hw_params *hw_params)
1953 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1954 struct azx *chip = apcm->chip;
1955 struct snd_pcm_runtime *runtime = substream->runtime;
1956 struct azx_dev *azx_dev = get_azx_dev(substream);
1959 mark_runtime_wc(chip, azx_dev, runtime, false);
1960 azx_dev->bufsize = 0;
1961 azx_dev->period_bytes = 0;
1962 azx_dev->format_val = 0;
1963 ret = snd_pcm_lib_malloc_pages(substream,
1964 params_buffer_bytes(hw_params));
1967 mark_runtime_wc(chip, azx_dev, runtime, true);
1971 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1973 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1974 struct azx_dev *azx_dev = get_azx_dev(substream);
1975 struct azx *chip = apcm->chip;
1976 struct snd_pcm_runtime *runtime = substream->runtime;
1977 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1979 /* reset BDL address */
1980 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1981 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1982 azx_sd_writel(azx_dev, SD_CTL, 0);
1983 azx_dev->bufsize = 0;
1984 azx_dev->period_bytes = 0;
1985 azx_dev->format_val = 0;
1987 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1989 mark_runtime_wc(chip, azx_dev, runtime, false);
1990 return snd_pcm_lib_free_pages(substream);
1993 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1995 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1996 struct azx *chip = apcm->chip;
1997 struct azx_dev *azx_dev = get_azx_dev(substream);
1998 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1999 struct snd_pcm_runtime *runtime = substream->runtime;
2000 unsigned int bufsize, period_bytes, format_val, stream_tag;
2002 struct hda_spdif_out *spdif =
2003 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2004 unsigned short ctls = spdif ? spdif->ctls : 0;
2006 azx_stream_reset(chip, azx_dev);
2007 format_val = snd_hda_calc_stream_format(runtime->rate,
2013 snd_printk(KERN_ERR SFX
2014 "invalid format_val, rate=%d, ch=%d, format=%d\n",
2015 runtime->rate, runtime->channels, runtime->format);
2019 bufsize = snd_pcm_lib_buffer_bytes(substream);
2020 period_bytes = snd_pcm_lib_period_bytes(substream);
2022 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2023 bufsize, format_val);
2025 if (bufsize != azx_dev->bufsize ||
2026 period_bytes != azx_dev->period_bytes ||
2027 format_val != azx_dev->format_val ||
2028 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2029 azx_dev->bufsize = bufsize;
2030 azx_dev->period_bytes = period_bytes;
2031 azx_dev->format_val = format_val;
2032 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2033 err = azx_setup_periods(chip, substream, azx_dev);
2038 /* wallclk has 24Mhz clock source */
2039 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2040 runtime->rate) * 1000);
2041 azx_setup_controller(chip, azx_dev);
2042 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2043 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2045 azx_dev->fifo_size = 0;
2047 stream_tag = azx_dev->stream_tag;
2048 /* CA-IBG chips need the playback stream starting from 1 */
2049 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2050 stream_tag > chip->capture_streams)
2051 stream_tag -= chip->capture_streams;
2052 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2053 azx_dev->format_val, substream);
2056 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2058 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2059 struct azx *chip = apcm->chip;
2060 struct azx_dev *azx_dev;
2061 struct snd_pcm_substream *s;
2062 int rstart = 0, start, nsync = 0, sbits = 0;
2065 azx_dev = get_azx_dev(substream);
2066 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2069 case SNDRV_PCM_TRIGGER_START:
2071 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2072 case SNDRV_PCM_TRIGGER_RESUME:
2075 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2076 case SNDRV_PCM_TRIGGER_SUSPEND:
2077 case SNDRV_PCM_TRIGGER_STOP:
2084 snd_pcm_group_for_each_entry(s, substream) {
2085 if (s->pcm->card != substream->pcm->card)
2087 azx_dev = get_azx_dev(s);
2088 sbits |= 1 << azx_dev->index;
2090 snd_pcm_trigger_done(s, substream);
2093 spin_lock(&chip->reg_lock);
2095 /* first, set SYNC bits of corresponding streams */
2096 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2097 azx_writel(chip, OLD_SSYNC,
2098 azx_readl(chip, OLD_SSYNC) | sbits);
2100 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2102 snd_pcm_group_for_each_entry(s, substream) {
2103 if (s->pcm->card != substream->pcm->card)
2105 azx_dev = get_azx_dev(s);
2107 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2109 azx_dev->start_wallclk -=
2110 azx_dev->period_wallclk;
2111 azx_stream_start(chip, azx_dev);
2113 azx_stream_stop(chip, azx_dev);
2115 azx_dev->running = start;
2117 spin_unlock(&chip->reg_lock);
2119 /* wait until all FIFOs get ready */
2120 for (timeout = 5000; timeout; timeout--) {
2122 snd_pcm_group_for_each_entry(s, substream) {
2123 if (s->pcm->card != substream->pcm->card)
2125 azx_dev = get_azx_dev(s);
2126 if (!(azx_sd_readb(azx_dev, SD_STS) &
2135 /* wait until all RUN bits are cleared */
2136 for (timeout = 5000; timeout; timeout--) {
2138 snd_pcm_group_for_each_entry(s, substream) {
2139 if (s->pcm->card != substream->pcm->card)
2141 azx_dev = get_azx_dev(s);
2142 if (azx_sd_readb(azx_dev, SD_CTL) &
2151 spin_lock(&chip->reg_lock);
2152 /* reset SYNC bits */
2153 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2154 azx_writel(chip, OLD_SSYNC,
2155 azx_readl(chip, OLD_SSYNC) & ~sbits);
2157 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2159 azx_timecounter_init(substream, 0, 0);
2163 /* same start cycle for master and group */
2164 azx_dev = get_azx_dev(substream);
2165 cycle_last = azx_dev->azx_tc.cycle_last;
2167 snd_pcm_group_for_each_entry(s, substream) {
2168 if (s->pcm->card != substream->pcm->card)
2170 azx_timecounter_init(s, 1, cycle_last);
2174 spin_unlock(&chip->reg_lock);
2178 /* get the current DMA position with correction on VIA chips */
2179 static unsigned int azx_via_get_position(struct azx *chip,
2180 struct azx_dev *azx_dev)
2182 unsigned int link_pos, mini_pos, bound_pos;
2183 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2184 unsigned int fifo_size;
2186 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2187 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2188 /* Playback, no problem using link position */
2194 * use mod to get the DMA position just like old chipset
2196 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2197 mod_dma_pos %= azx_dev->period_bytes;
2199 /* azx_dev->fifo_size can't get FIFO size of in stream.
2200 * Get from base address + offset.
2202 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2204 if (azx_dev->insufficient) {
2205 /* Link position never gather than FIFO size */
2206 if (link_pos <= fifo_size)
2209 azx_dev->insufficient = 0;
2212 if (link_pos <= fifo_size)
2213 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2215 mini_pos = link_pos - fifo_size;
2217 /* Find nearest previous boudary */
2218 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2219 mod_link_pos = link_pos % azx_dev->period_bytes;
2220 if (mod_link_pos >= fifo_size)
2221 bound_pos = link_pos - mod_link_pos;
2222 else if (mod_dma_pos >= mod_mini_pos)
2223 bound_pos = mini_pos - mod_mini_pos;
2225 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2226 if (bound_pos >= azx_dev->bufsize)
2230 /* Calculate real DMA position we want */
2231 return bound_pos + mod_dma_pos;
2234 static unsigned int azx_get_position(struct azx *chip,
2235 struct azx_dev *azx_dev,
2239 int stream = azx_dev->substream->stream;
2242 switch (chip->position_fix[stream]) {
2245 pos = azx_sd_readl(azx_dev, SD_LPIB);
2247 case POS_FIX_VIACOMBO:
2248 pos = azx_via_get_position(chip, azx_dev);
2251 /* use the position buffer */
2252 pos = le32_to_cpu(*azx_dev->posbuf);
2253 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2254 if (!pos || pos == (u32)-1) {
2256 "hda-intel: Invalid position buffer, "
2257 "using LPIB read method instead.\n");
2258 chip->position_fix[stream] = POS_FIX_LPIB;
2259 pos = azx_sd_readl(azx_dev, SD_LPIB);
2261 chip->position_fix[stream] = POS_FIX_POSBUF;
2266 if (pos >= azx_dev->bufsize)
2269 /* calculate runtime delay from LPIB */
2270 if (azx_dev->substream->runtime &&
2271 chip->position_fix[stream] == POS_FIX_POSBUF &&
2272 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2273 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2274 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2275 delay = pos - lpib_pos;
2277 delay = lpib_pos - pos;
2279 delay += azx_dev->bufsize;
2280 if (delay >= azx_dev->period_bytes) {
2281 snd_printdd("delay %d > period_bytes %d\n",
2282 delay, azx_dev->period_bytes);
2283 delay = 0; /* something is wrong */
2285 azx_dev->substream->runtime->delay =
2286 bytes_to_frames(azx_dev->substream->runtime, delay);
2288 trace_azx_get_position(chip, azx_dev, pos, delay);
2292 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2294 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2295 struct azx *chip = apcm->chip;
2296 struct azx_dev *azx_dev = get_azx_dev(substream);
2297 return bytes_to_frames(substream->runtime,
2298 azx_get_position(chip, azx_dev, false));
2302 * Check whether the current DMA position is acceptable for updating
2303 * periods. Returns non-zero if it's OK.
2305 * Many HD-audio controllers appear pretty inaccurate about
2306 * the update-IRQ timing. The IRQ is issued before actually the
2307 * data is processed. So, we need to process it afterwords in a
2310 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2315 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2316 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2317 return -1; /* bogus (too early) interrupt */
2319 pos = azx_get_position(chip, azx_dev, true);
2321 if (WARN_ONCE(!azx_dev->period_bytes,
2322 "hda-intel: zero azx_dev->period_bytes"))
2323 return -1; /* this shouldn't happen! */
2324 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2325 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2326 /* NG - it's below the first next period boundary */
2327 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2328 azx_dev->start_wallclk += wallclk;
2329 return 1; /* OK, it's fine */
2333 * The work for pending PCM period updates.
2335 static void azx_irq_pending_work(struct work_struct *work)
2337 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2340 if (!chip->irq_pending_warned) {
2342 "hda-intel: IRQ timing workaround is activated "
2343 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2344 chip->card->number);
2345 chip->irq_pending_warned = 1;
2350 spin_lock_irq(&chip->reg_lock);
2351 for (i = 0; i < chip->num_streams; i++) {
2352 struct azx_dev *azx_dev = &chip->azx_dev[i];
2353 if (!azx_dev->irq_pending ||
2354 !azx_dev->substream ||
2357 ok = azx_position_ok(chip, azx_dev);
2359 azx_dev->irq_pending = 0;
2360 spin_unlock(&chip->reg_lock);
2361 snd_pcm_period_elapsed(azx_dev->substream);
2362 spin_lock(&chip->reg_lock);
2363 } else if (ok < 0) {
2364 pending = 0; /* too early */
2368 spin_unlock_irq(&chip->reg_lock);
2375 /* clear irq_pending flags and assure no on-going workq */
2376 static void azx_clear_irq_pending(struct azx *chip)
2380 spin_lock_irq(&chip->reg_lock);
2381 for (i = 0; i < chip->num_streams; i++)
2382 chip->azx_dev[i].irq_pending = 0;
2383 spin_unlock_irq(&chip->reg_lock);
2387 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2388 struct vm_area_struct *area)
2390 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2391 struct azx *chip = apcm->chip;
2392 if (!azx_snoop(chip))
2393 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2394 return snd_pcm_lib_default_mmap(substream, area);
2397 #define azx_pcm_mmap NULL
2400 static struct snd_pcm_ops azx_pcm_ops = {
2401 .open = azx_pcm_open,
2402 .close = azx_pcm_close,
2403 .ioctl = snd_pcm_lib_ioctl,
2404 .hw_params = azx_pcm_hw_params,
2405 .hw_free = azx_pcm_hw_free,
2406 .prepare = azx_pcm_prepare,
2407 .trigger = azx_pcm_trigger,
2408 .pointer = azx_pcm_pointer,
2409 .wall_clock = azx_get_wallclock_tstamp,
2410 .mmap = azx_pcm_mmap,
2411 .page = snd_pcm_sgbuf_ops_page,
2414 static void azx_pcm_free(struct snd_pcm *pcm)
2416 struct azx_pcm *apcm = pcm->private_data;
2418 list_del(&apcm->list);
2423 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2426 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2427 struct hda_pcm *cpcm)
2429 struct azx *chip = bus->private_data;
2430 struct snd_pcm *pcm;
2431 struct azx_pcm *apcm;
2432 int pcm_dev = cpcm->device;
2436 list_for_each_entry(apcm, &chip->pcm_list, list) {
2437 if (apcm->pcm->device == pcm_dev) {
2438 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2442 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2443 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2444 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2448 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2449 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2454 apcm->codec = codec;
2455 pcm->private_data = apcm;
2456 pcm->private_free = azx_pcm_free;
2457 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2458 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2459 list_add_tail(&apcm->list, &chip->pcm_list);
2461 for (s = 0; s < 2; s++) {
2462 apcm->hinfo[s] = &cpcm->stream[s];
2463 if (cpcm->stream[s].substreams)
2464 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2466 /* buffer pre-allocation */
2467 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2468 if (size > MAX_PREALLOC_SIZE)
2469 size = MAX_PREALLOC_SIZE;
2470 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2471 snd_dma_pci_data(chip->pci),
2472 size, MAX_PREALLOC_SIZE);
2477 * mixer creation - all stuff is implemented in hda module
2479 static int __devinit azx_mixer_create(struct azx *chip)
2481 return snd_hda_build_controls(chip->bus);
2486 * initialize SD streams
2488 static int __devinit azx_init_stream(struct azx *chip)
2492 /* initialize each stream (aka device)
2493 * assign the starting bdl address to each stream (device)
2496 for (i = 0; i < chip->num_streams; i++) {
2497 struct azx_dev *azx_dev = &chip->azx_dev[i];
2498 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2499 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2500 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2501 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2502 azx_dev->sd_int_sta_mask = 1 << i;
2503 /* stream tag: must be non-zero and unique */
2505 azx_dev->stream_tag = i + 1;
2511 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2513 if (request_irq(chip->pci->irq, azx_interrupt,
2514 chip->msi ? 0 : IRQF_SHARED,
2515 KBUILD_MODNAME, chip)) {
2516 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2517 "disabling device\n", chip->pci->irq);
2519 snd_card_disconnect(chip->card);
2522 chip->irq = chip->pci->irq;
2523 pci_intx(chip->pci, !chip->msi);
2528 static void azx_stop_chip(struct azx *chip)
2530 if (!chip->initialized)
2533 /* disable interrupts */
2534 azx_int_disable(chip);
2535 azx_int_clear(chip);
2537 /* disable CORB/RIRB */
2538 azx_free_cmd_io(chip);
2540 /* disable position buffer */
2541 azx_writel(chip, DPLBASE, 0);
2542 azx_writel(chip, DPUBASE, 0);
2544 chip->initialized = 0;
2548 /* power-up/down the controller */
2549 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2551 struct azx *chip = bus->private_data;
2554 pm_runtime_get_sync(&chip->pci->dev);
2556 pm_runtime_put_sync(&chip->pci->dev);
2559 static DEFINE_MUTEX(card_list_lock);
2560 static LIST_HEAD(card_list);
2562 static void azx_add_card_list(struct azx *chip)
2564 mutex_lock(&card_list_lock);
2565 list_add(&chip->list, &card_list);
2566 mutex_unlock(&card_list_lock);
2569 static void azx_del_card_list(struct azx *chip)
2571 mutex_lock(&card_list_lock);
2572 list_del_init(&chip->list);
2573 mutex_unlock(&card_list_lock);
2576 /* trigger power-save check at writing parameter */
2577 static int param_set_xint(const char *val, const struct kernel_param *kp)
2580 struct hda_codec *c;
2581 int prev = power_save;
2582 int ret = param_set_int(val, kp);
2584 if (ret || prev == power_save)
2587 mutex_lock(&card_list_lock);
2588 list_for_each_entry(chip, &card_list, list) {
2589 if (!chip->bus || chip->disabled)
2591 list_for_each_entry(c, &chip->bus->codec_list, list)
2592 snd_hda_power_sync(c);
2594 mutex_unlock(&card_list_lock);
2598 #define azx_add_card_list(chip) /* NOP */
2599 #define azx_del_card_list(chip) /* NOP */
2600 #endif /* CONFIG_PM */
2602 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2606 static int azx_suspend(struct device *dev)
2608 struct pci_dev *pci = to_pci_dev(dev);
2609 struct snd_card *card = dev_get_drvdata(dev);
2610 struct azx *chip = card->private_data;
2613 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2614 azx_clear_irq_pending(chip);
2615 list_for_each_entry(p, &chip->pcm_list, list)
2616 snd_pcm_suspend_all(p->pcm);
2617 if (chip->initialized)
2618 snd_hda_suspend(chip->bus);
2619 azx_stop_chip(chip);
2620 if (chip->irq >= 0) {
2621 free_irq(chip->irq, chip);
2625 pci_disable_msi(chip->pci);
2626 pci_disable_device(pci);
2627 pci_save_state(pci);
2628 pci_set_power_state(pci, PCI_D3hot);
2632 static int azx_resume(struct device *dev)
2634 struct pci_dev *pci = to_pci_dev(dev);
2635 struct snd_card *card = dev_get_drvdata(dev);
2636 struct azx *chip = card->private_data;
2638 pci_set_power_state(pci, PCI_D0);
2639 pci_restore_state(pci);
2640 if (pci_enable_device(pci) < 0) {
2641 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2642 "disabling device\n");
2643 snd_card_disconnect(card);
2646 pci_set_master(pci);
2648 if (pci_enable_msi(pci) < 0)
2650 if (azx_acquire_irq(chip, 1) < 0)
2654 azx_init_chip(chip, 1);
2656 snd_hda_resume(chip->bus);
2657 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2660 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2662 #ifdef CONFIG_PM_RUNTIME
2663 static int azx_runtime_suspend(struct device *dev)
2665 struct snd_card *card = dev_get_drvdata(dev);
2666 struct azx *chip = card->private_data;
2668 if (!power_save_controller)
2671 azx_stop_chip(chip);
2672 azx_clear_irq_pending(chip);
2676 static int azx_runtime_resume(struct device *dev)
2678 struct snd_card *card = dev_get_drvdata(dev);
2679 struct azx *chip = card->private_data;
2682 azx_init_chip(chip, 1);
2685 #endif /* CONFIG_PM_RUNTIME */
2688 static const struct dev_pm_ops azx_pm = {
2689 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2690 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2693 #define AZX_PM_OPS &azx_pm
2695 #define AZX_PM_OPS NULL
2696 #endif /* CONFIG_PM */
2700 * reboot notifier for hang-up problem at power-down
2702 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2704 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2705 snd_hda_bus_reboot_notify(chip->bus);
2706 azx_stop_chip(chip);
2710 static void azx_notifier_register(struct azx *chip)
2712 chip->reboot_notifier.notifier_call = azx_halt;
2713 register_reboot_notifier(&chip->reboot_notifier);
2716 static void azx_notifier_unregister(struct azx *chip)
2718 if (chip->reboot_notifier.notifier_call)
2719 unregister_reboot_notifier(&chip->reboot_notifier);
2722 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2723 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2725 #ifdef SUPPORT_VGA_SWITCHEROO
2726 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2728 static void azx_vs_set_state(struct pci_dev *pci,
2729 enum vga_switcheroo_state state)
2731 struct snd_card *card = pci_get_drvdata(pci);
2732 struct azx *chip = card->private_data;
2735 if (chip->init_failed)
2738 disabled = (state == VGA_SWITCHEROO_OFF);
2739 if (chip->disabled == disabled)
2743 chip->disabled = disabled;
2745 snd_printk(KERN_INFO SFX
2746 "%s: Start delayed initialization\n",
2747 pci_name(chip->pci));
2748 if (azx_first_init(chip) < 0 ||
2749 azx_probe_continue(chip) < 0) {
2750 snd_printk(KERN_ERR SFX
2751 "%s: initialization error\n",
2752 pci_name(chip->pci));
2753 chip->init_failed = true;
2757 snd_printk(KERN_INFO SFX
2758 "%s %s via VGA-switcheroo\n",
2759 disabled ? "Disabling" : "Enabling",
2760 pci_name(chip->pci));
2762 azx_suspend(&pci->dev);
2763 chip->disabled = true;
2764 if (snd_hda_lock_devices(chip->bus))
2765 snd_printk(KERN_WARNING SFX
2766 "Cannot lock devices!\n");
2768 snd_hda_unlock_devices(chip->bus);
2769 chip->disabled = false;
2770 azx_resume(&pci->dev);
2775 static bool azx_vs_can_switch(struct pci_dev *pci)
2777 struct snd_card *card = pci_get_drvdata(pci);
2778 struct azx *chip = card->private_data;
2780 if (chip->init_failed)
2782 if (chip->disabled || !chip->bus)
2784 if (snd_hda_lock_devices(chip->bus))
2786 snd_hda_unlock_devices(chip->bus);
2790 static void __devinit init_vga_switcheroo(struct azx *chip)
2792 struct pci_dev *p = get_bound_vga(chip->pci);
2794 snd_printk(KERN_INFO SFX
2795 "%s: Handle VGA-switcheroo audio client\n",
2796 pci_name(chip->pci));
2797 chip->use_vga_switcheroo = 1;
2802 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2803 .set_gpu_state = azx_vs_set_state,
2804 .can_switch = azx_vs_can_switch,
2807 static int __devinit register_vga_switcheroo(struct azx *chip)
2811 if (!chip->use_vga_switcheroo)
2813 /* FIXME: currently only handling DIS controller
2814 * is there any machine with two switchable HDMI audio controllers?
2816 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2821 chip->vga_switcheroo_registered = 1;
2825 #define init_vga_switcheroo(chip) /* NOP */
2826 #define register_vga_switcheroo(chip) 0
2827 #define check_hdmi_disabled(pci) false
2828 #endif /* SUPPORT_VGA_SWITCHER */
2833 static int azx_free(struct azx *chip)
2837 azx_del_card_list(chip);
2839 azx_notifier_unregister(chip);
2841 if (use_vga_switcheroo(chip)) {
2842 if (chip->disabled && chip->bus)
2843 snd_hda_unlock_devices(chip->bus);
2844 if (chip->vga_switcheroo_registered)
2845 vga_switcheroo_unregister_client(chip->pci);
2848 if (chip->initialized) {
2849 azx_clear_irq_pending(chip);
2850 for (i = 0; i < chip->num_streams; i++)
2851 azx_stream_stop(chip, &chip->azx_dev[i]);
2852 azx_stop_chip(chip);
2856 free_irq(chip->irq, (void*)chip);
2858 pci_disable_msi(chip->pci);
2859 if (chip->remap_addr)
2860 iounmap(chip->remap_addr);
2862 if (chip->azx_dev) {
2863 for (i = 0; i < chip->num_streams; i++)
2864 if (chip->azx_dev[i].bdl.area) {
2865 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2866 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2869 if (chip->rb.area) {
2870 mark_pages_wc(chip, &chip->rb, false);
2871 snd_dma_free_pages(&chip->rb);
2873 if (chip->posbuf.area) {
2874 mark_pages_wc(chip, &chip->posbuf, false);
2875 snd_dma_free_pages(&chip->posbuf);
2877 if (chip->region_requested)
2878 pci_release_regions(chip->pci);
2879 pci_disable_device(chip->pci);
2880 kfree(chip->azx_dev);
2881 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2883 release_firmware(chip->fw);
2890 static int azx_dev_free(struct snd_device *device)
2892 return azx_free(device->device_data);
2895 #ifdef SUPPORT_VGA_SWITCHEROO
2897 * Check of disabled HDMI controller by vga-switcheroo
2899 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2903 /* check only discrete GPU */
2904 switch (pci->vendor) {
2905 case PCI_VENDOR_ID_ATI:
2906 case PCI_VENDOR_ID_AMD:
2907 case PCI_VENDOR_ID_NVIDIA:
2908 if (pci->devfn == 1) {
2909 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2910 pci->bus->number, 0);
2912 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2922 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2924 bool vga_inactive = false;
2925 struct pci_dev *p = get_bound_vga(pci);
2928 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2929 vga_inactive = true;
2932 return vga_inactive;
2934 #endif /* SUPPORT_VGA_SWITCHEROO */
2937 * white/black-listing for position_fix
2939 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2940 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2941 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2942 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2943 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2944 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2945 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2946 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2947 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2948 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2949 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2950 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2951 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2952 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2953 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2957 static int __devinit check_position_fix(struct azx *chip, int fix)
2959 const struct snd_pci_quirk *q;
2964 case POS_FIX_POSBUF:
2965 case POS_FIX_VIACOMBO:
2970 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2973 "hda_intel: position_fix set to %d "
2974 "for device %04x:%04x\n",
2975 q->value, q->subvendor, q->subdevice);
2979 /* Check VIA/ATI HD Audio Controller exist */
2980 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2981 snd_printd(SFX "Using VIACOMBO position fix\n");
2982 return POS_FIX_VIACOMBO;
2984 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2985 snd_printd(SFX "Using LPIB position fix\n");
2986 return POS_FIX_LPIB;
2988 return POS_FIX_AUTO;
2992 * black-lists for probe_mask
2994 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2995 /* Thinkpad often breaks the controller communication when accessing
2996 * to the non-working (or non-existing) modem codec slot.
2998 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2999 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3000 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3002 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3003 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3004 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3005 /* forced codec slots */
3006 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3007 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3008 /* WinFast VP200 H (Teradici) user reported broken communication */
3009 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3013 #define AZX_FORCE_CODEC_MASK 0x100
3015 static void __devinit check_probe_mask(struct azx *chip, int dev)
3017 const struct snd_pci_quirk *q;
3019 chip->codec_probe_mask = probe_mask[dev];
3020 if (chip->codec_probe_mask == -1) {
3021 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3024 "hda_intel: probe_mask set to 0x%x "
3025 "for device %04x:%04x\n",
3026 q->value, q->subvendor, q->subdevice);
3027 chip->codec_probe_mask = q->value;
3031 /* check forced option */
3032 if (chip->codec_probe_mask != -1 &&
3033 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3034 chip->codec_mask = chip->codec_probe_mask & 0xff;
3035 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3041 * white/black-list for enable_msi
3043 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
3044 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3045 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3046 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3047 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3048 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3052 static void __devinit check_msi(struct azx *chip)
3054 const struct snd_pci_quirk *q;
3056 if (enable_msi >= 0) {
3057 chip->msi = !!enable_msi;
3060 chip->msi = 1; /* enable MSI as default */
3061 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3064 "hda_intel: msi for device %04x:%04x set to %d\n",
3065 q->subvendor, q->subdevice, q->value);
3066 chip->msi = q->value;
3070 /* NVidia chipsets seem to cause troubles with MSI */
3071 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3072 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3077 /* check the snoop mode availability */
3078 static void __devinit azx_check_snoop_available(struct azx *chip)
3080 bool snoop = chip->snoop;
3082 switch (chip->driver_type) {
3083 case AZX_DRIVER_VIA:
3084 /* force to non-snoop mode for a new VIA controller
3089 pci_read_config_byte(chip->pci, 0x42, &val);
3090 if (!(val & 0x80) && chip->pci->revision == 0x30)
3094 case AZX_DRIVER_ATIHDMI_NS:
3095 /* new ATI HDMI requires non-snoop */
3100 if (snoop != chip->snoop) {
3101 snd_printk(KERN_INFO SFX "Force to %s mode\n",
3102 snoop ? "snoop" : "non-snoop");
3103 chip->snoop = snoop;
3110 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
3111 int dev, unsigned int driver_caps,
3114 static struct snd_device_ops ops = {
3115 .dev_free = azx_dev_free,
3122 err = pci_enable_device(pci);
3126 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3128 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
3129 pci_disable_device(pci);
3133 spin_lock_init(&chip->reg_lock);
3134 mutex_init(&chip->open_mutex);
3138 chip->driver_caps = driver_caps;
3139 chip->driver_type = driver_caps & 0xff;
3141 chip->dev_index = dev;
3142 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3143 INIT_LIST_HEAD(&chip->pcm_list);
3144 INIT_LIST_HEAD(&chip->list);
3145 init_vga_switcheroo(chip);
3147 chip->position_fix[0] = chip->position_fix[1] =
3148 check_position_fix(chip, position_fix[dev]);
3149 /* combo mode uses LPIB for playback */
3150 if (chip->position_fix[0] == POS_FIX_COMBO) {
3151 chip->position_fix[0] = POS_FIX_LPIB;
3152 chip->position_fix[1] = POS_FIX_AUTO;
3155 check_probe_mask(chip, dev);
3157 chip->single_cmd = single_cmd;
3158 chip->snoop = hda_snoop;
3159 azx_check_snoop_available(chip);
3161 if (bdl_pos_adj[dev] < 0) {
3162 switch (chip->driver_type) {
3163 case AZX_DRIVER_ICH:
3164 case AZX_DRIVER_PCH:
3165 bdl_pos_adj[dev] = 1;
3168 bdl_pos_adj[dev] = 32;
3173 if (check_hdmi_disabled(pci)) {
3174 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3176 if (use_vga_switcheroo(chip)) {
3177 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3178 chip->disabled = true;
3182 pci_disable_device(pci);
3186 err = azx_first_init(chip);
3193 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3195 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3204 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3206 int dev = chip->dev_index;
3207 struct pci_dev *pci = chip->pci;
3208 struct snd_card *card = chip->card;
3210 unsigned short gcap;
3212 #if BITS_PER_LONG != 64
3213 /* Fix up base address on ULI M5461 */
3214 if (chip->driver_type == AZX_DRIVER_ULI) {
3216 pci_read_config_word(pci, 0x40, &tmp3);
3217 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3218 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3222 err = pci_request_regions(pci, "ICH HD audio");
3225 chip->region_requested = 1;
3227 chip->addr = pci_resource_start(pci, 0);
3228 chip->remap_addr = pci_ioremap_bar(pci, 0);
3229 if (chip->remap_addr == NULL) {
3230 snd_printk(KERN_ERR SFX "ioremap error\n");
3235 if (pci_enable_msi(pci) < 0)
3238 if (azx_acquire_irq(chip, 0) < 0)
3241 pci_set_master(pci);
3242 synchronize_irq(chip->irq);
3244 gcap = azx_readw(chip, GCAP);
3245 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3247 /* disable SB600 64bit support for safety */
3248 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3249 struct pci_dev *p_smbus;
3250 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3251 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3254 if (p_smbus->revision < 0x30)
3255 gcap &= ~ICH6_GCAP_64OK;
3256 pci_dev_put(p_smbus);
3260 /* disable 64bit DMA address on some devices */
3261 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3262 snd_printd(SFX "Disabling 64bit DMA\n");
3263 gcap &= ~ICH6_GCAP_64OK;
3266 /* disable buffer size rounding to 128-byte multiples if supported */
3267 if (align_buffer_size >= 0)
3268 chip->align_buffer_size = !!align_buffer_size;
3270 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3271 chip->align_buffer_size = 0;
3272 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3273 chip->align_buffer_size = 1;
3275 chip->align_buffer_size = 1;
3278 /* allow 64bit DMA address if supported by H/W */
3279 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3280 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3282 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3283 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3286 /* read number of streams from GCAP register instead of using
3289 chip->capture_streams = (gcap >> 8) & 0x0f;
3290 chip->playback_streams = (gcap >> 12) & 0x0f;
3291 if (!chip->playback_streams && !chip->capture_streams) {
3292 /* gcap didn't give any info, switching to old method */
3294 switch (chip->driver_type) {
3295 case AZX_DRIVER_ULI:
3296 chip->playback_streams = ULI_NUM_PLAYBACK;
3297 chip->capture_streams = ULI_NUM_CAPTURE;
3299 case AZX_DRIVER_ATIHDMI:
3300 case AZX_DRIVER_ATIHDMI_NS:
3301 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3302 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3304 case AZX_DRIVER_GENERIC:
3306 chip->playback_streams = ICH6_NUM_PLAYBACK;
3307 chip->capture_streams = ICH6_NUM_CAPTURE;
3311 chip->capture_index_offset = 0;
3312 chip->playback_index_offset = chip->capture_streams;
3313 chip->num_streams = chip->playback_streams + chip->capture_streams;
3314 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3316 if (!chip->azx_dev) {
3317 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3321 for (i = 0; i < chip->num_streams; i++) {
3322 /* allocate memory for the BDL for each stream */
3323 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3324 snd_dma_pci_data(chip->pci),
3325 BDL_SIZE, &chip->azx_dev[i].bdl);
3327 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3330 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3332 /* allocate memory for the position buffer */
3333 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3334 snd_dma_pci_data(chip->pci),
3335 chip->num_streams * 8, &chip->posbuf);
3337 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3340 mark_pages_wc(chip, &chip->posbuf, true);
3341 /* allocate CORB/RIRB */
3342 err = azx_alloc_cmd_io(chip);
3346 /* initialize streams */
3347 azx_init_stream(chip);
3349 /* initialize chip */
3351 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3353 /* codec detection */
3354 if (!chip->codec_mask) {
3355 snd_printk(KERN_ERR SFX "no codecs found!\n");
3359 strcpy(card->driver, "HDA-Intel");
3360 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3361 sizeof(card->shortname));
3362 snprintf(card->longname, sizeof(card->longname),
3363 "%s at 0x%lx irq %i",
3364 card->shortname, chip->addr, chip->irq);
3369 static void power_down_all_codecs(struct azx *chip)
3372 /* The codecs were powered up in snd_hda_codec_new().
3373 * Now all initialization done, so turn them down if possible
3375 struct hda_codec *codec;
3376 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3377 snd_hda_power_down(codec);
3382 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3383 /* callback from request_firmware_nowait() */
3384 static void azx_firmware_cb(const struct firmware *fw, void *context)
3386 struct snd_card *card = context;
3387 struct azx *chip = card->private_data;
3388 struct pci_dev *pci = chip->pci;
3391 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3396 if (!chip->disabled) {
3397 /* continue probing */
3398 if (azx_probe_continue(chip))
3404 snd_card_free(card);
3405 pci_set_drvdata(pci, NULL);
3409 static int __devinit azx_probe(struct pci_dev *pci,
3410 const struct pci_device_id *pci_id)
3413 struct snd_card *card;
3418 if (dev >= SNDRV_CARDS)
3425 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3427 snd_printk(KERN_ERR SFX "Error creating card!\n");
3431 snd_card_set_dev(card, &pci->dev);
3433 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3436 card->private_data = chip;
3437 probe_now = !chip->disabled;
3439 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3440 if (patch[dev] && *patch[dev]) {
3441 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3443 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3444 &pci->dev, GFP_KERNEL, card,
3448 probe_now = false; /* continued in azx_firmware_cb() */
3450 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3453 err = azx_probe_continue(chip);
3458 pci_set_drvdata(pci, card);
3460 if (pci_dev_run_wake(pci))
3461 pm_runtime_put_noidle(&pci->dev);
3463 err = register_vga_switcheroo(chip);
3465 snd_printk(KERN_ERR SFX
3466 "Error registering VGA-switcheroo client\n");
3474 snd_card_free(card);
3478 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3480 int dev = chip->dev_index;
3483 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3484 chip->beep_mode = beep_mode[dev];
3487 /* create codec instances */
3488 err = azx_codec_create(chip, model[dev]);
3491 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3493 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3497 release_firmware(chip->fw); /* no longer needed */
3501 if ((probe_only[dev] & 1) == 0) {
3502 err = azx_codec_configure(chip);
3507 /* create PCM streams */
3508 err = snd_hda_build_pcms(chip->bus);
3512 /* create mixer controls */
3513 err = azx_mixer_create(chip);
3517 err = snd_card_register(chip->card);
3522 power_down_all_codecs(chip);
3523 azx_notifier_register(chip);
3524 azx_add_card_list(chip);
3529 chip->init_failed = 1;
3533 static void __devexit azx_remove(struct pci_dev *pci)
3535 struct snd_card *card = pci_get_drvdata(pci);
3537 if (pci_dev_run_wake(pci))
3538 pm_runtime_get_noresume(&pci->dev);
3541 snd_card_free(card);
3542 pci_set_drvdata(pci, NULL);
3546 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3548 { PCI_DEVICE(0x8086, 0x1c20),
3549 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3550 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3552 { PCI_DEVICE(0x8086, 0x1d20),
3553 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3556 { PCI_DEVICE(0x8086, 0x1e20),
3557 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3558 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3560 { PCI_DEVICE(0x8086, 0x8c20),
3561 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3562 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3564 { PCI_DEVICE(0x8086, 0x9c20),
3565 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3566 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3568 { PCI_DEVICE(0x8086, 0x9c21),
3569 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3570 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3572 { PCI_DEVICE(0x8086, 0x0c0c),
3573 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3574 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3575 { PCI_DEVICE(0x8086, 0x0d0c),
3576 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3577 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3579 { PCI_DEVICE(0x8086, 0x3b56),
3580 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3581 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3583 { PCI_DEVICE(0x8086, 0x811b),
3584 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3585 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3586 { PCI_DEVICE(0x8086, 0x080a),
3587 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3588 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3590 { PCI_DEVICE(0x8086, 0x2668),
3591 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3592 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3593 { PCI_DEVICE(0x8086, 0x27d8),
3594 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3595 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3596 { PCI_DEVICE(0x8086, 0x269a),
3597 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3598 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3599 { PCI_DEVICE(0x8086, 0x284b),
3600 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3601 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3602 { PCI_DEVICE(0x8086, 0x293e),
3603 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3604 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3605 { PCI_DEVICE(0x8086, 0x293f),
3606 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3607 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3608 { PCI_DEVICE(0x8086, 0x3a3e),
3609 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3610 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3611 { PCI_DEVICE(0x8086, 0x3a6e),
3612 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3613 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3616 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3617 .class_mask = 0xffffff,
3618 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3619 /* ATI SB 450/600/700/800/900 */
3620 { PCI_DEVICE(0x1002, 0x437b),
3621 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3622 { PCI_DEVICE(0x1002, 0x4383),
3623 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3625 { PCI_DEVICE(0x1022, 0x780d),
3626 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3628 { PCI_DEVICE(0x1002, 0x793b),
3629 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3630 { PCI_DEVICE(0x1002, 0x7919),
3631 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3632 { PCI_DEVICE(0x1002, 0x960f),
3633 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3634 { PCI_DEVICE(0x1002, 0x970f),
3635 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3636 { PCI_DEVICE(0x1002, 0xaa00),
3637 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3638 { PCI_DEVICE(0x1002, 0xaa08),
3639 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3640 { PCI_DEVICE(0x1002, 0xaa10),
3641 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3642 { PCI_DEVICE(0x1002, 0xaa18),
3643 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3644 { PCI_DEVICE(0x1002, 0xaa20),
3645 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3646 { PCI_DEVICE(0x1002, 0xaa28),
3647 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3648 { PCI_DEVICE(0x1002, 0xaa30),
3649 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3650 { PCI_DEVICE(0x1002, 0xaa38),
3651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3652 { PCI_DEVICE(0x1002, 0xaa40),
3653 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3654 { PCI_DEVICE(0x1002, 0xaa48),
3655 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3656 { PCI_DEVICE(0x1002, 0x9902),
3657 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3658 { PCI_DEVICE(0x1002, 0xaaa0),
3659 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3660 { PCI_DEVICE(0x1002, 0xaaa8),
3661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3662 { PCI_DEVICE(0x1002, 0xaab0),
3663 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3664 /* VIA VT8251/VT8237A */
3665 { PCI_DEVICE(0x1106, 0x3288),
3666 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3667 /* VIA GFX VT7122/VX900 */
3668 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3669 /* VIA GFX VT6122/VX11 */
3670 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3672 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3674 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3676 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3677 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3678 .class_mask = 0xffffff,
3679 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3681 { PCI_DEVICE(0x6549, 0x1200),
3682 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3683 /* Creative X-Fi (CA0110-IBG) */
3685 { PCI_DEVICE(0x1102, 0x0010),
3686 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3687 { PCI_DEVICE(0x1102, 0x0012),
3688 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3689 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3690 /* the following entry conflicts with snd-ctxfi driver,
3691 * as ctxfi driver mutates from HD-audio to native mode with
3692 * a special command sequence.
3694 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3695 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3696 .class_mask = 0xffffff,
3697 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3698 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3700 /* this entry seems still valid -- i.e. without emu20kx chip */
3701 { PCI_DEVICE(0x1102, 0x0009),
3702 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3703 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3706 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3707 /* VMware HDAudio */
3708 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3709 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3710 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3711 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3712 .class_mask = 0xffffff,
3713 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3714 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3715 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3716 .class_mask = 0xffffff,
3717 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3720 MODULE_DEVICE_TABLE(pci, azx_ids);
3722 /* pci_driver definition */
3723 static struct pci_driver azx_driver = {
3724 .name = KBUILD_MODNAME,
3725 .id_table = azx_ids,
3727 .remove = __devexit_p(azx_remove),
3733 module_pci_driver(azx_driver);