sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #ifdef CONFIG_X86
  50 /* for snoop control */
  51 #include <asm/pgtable.h>
  52 #include <asm/cacheflush.h>
  53 #endif
  54 #include <sound/core.h>
  55 #include <sound/initval.h>
  56 #include "hda_codec.h"
  57
  58
  59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  61 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  62 static char *model[SNDRV_CARDS];
  63 static int position_fix[SNDRV_CARDS];
  64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  66 static int probe_only[SNDRV_CARDS];
  67 static int single_cmd;
  68 static int enable_msi = -1;
  69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  70 static char *patch[SNDRV_CARDS];
  71 #endif
  72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  74                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  75 #endif
  76
  77 module_param_array(index, int, NULL, 0444);
  78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  79 module_param_array(id, charp, NULL, 0444);
  80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  81 module_param_array(enable, bool, NULL, 0444);
  82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  83 module_param_array(model, charp, NULL, 0444);
  84 MODULE_PARM_DESC(model, "Use the given board model.");
  85 module_param_array(position_fix, int, NULL, 0444);
  86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  87                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
  88 module_param_array(bdl_pos_adj, int, NULL, 0644);
  89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  90 module_param_array(probe_mask, int, NULL, 0444);
  91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  92 module_param_array(probe_only, int, NULL, 0444);
  93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  94 module_param(single_cmd, bool, 0444);
  95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  96                  "(for debugging only).");
  97 module_param(enable_msi, int, 0444);
  98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 100 module_param_array(patch, charp, NULL, 0444);
 101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 102 #endif
 103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 104 module_param_array(beep_mode, int, NULL, 0444);
 105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 106                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 107 #endif
 108
 109 #ifdef CONFIG_SND_HDA_POWER_SAVE
 110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 111 module_param(power_save, int, 0644);
 112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 113                  "(in second, 0 = disable).");
 114
 115 /* reset the HD-audio controller in power save mode.
 116  * this may give more power-saving, but will take longer time to
 117  * wake up.
 118  */
 119 static int power_save_controller = 1;
 120 module_param(power_save_controller, bool, 0644);
 121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 122 #endif
 123
 124 static int align_buffer_size = 1;
 125 module_param(align_buffer_size, bool, 0644);
 126 MODULE_PARM_DESC(align_buffer_size,
 127                 "Force buffer and period sizes to be multiple of 128 bytes.");
 128
 129 #ifdef CONFIG_X86
 130 static bool hda_snoop = true;
 131 module_param_named(snoop, hda_snoop, bool, 0444);
 132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 133 #define azx_snoop(chip)         (chip)->snoop
 134 #else
 135 #define hda_snoop               true
 136 #define azx_snoop(chip)         true
 137 #endif
 138
 139
 140 MODULE_LICENSE("GPL");
 141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 142                          "{Intel, ICH6M},"
 143                          "{Intel, ICH7},"
 144                          "{Intel, ESB2},"
 145                          "{Intel, ICH8},"
 146                          "{Intel, ICH9},"
 147                          "{Intel, ICH10},"
 148                          "{Intel, PCH},"
 149                          "{Intel, CPT},"
 150                          "{Intel, PPT},"
 151                          "{Intel, PBG},"
 152                          "{Intel, SCH},"
 153                          "{ATI, SB450},"
 154                          "{ATI, SB600},"
 155                          "{ATI, RS600},"
 156                          "{ATI, RS690},"
 157                          "{ATI, RS780},"
 158                          "{ATI, R600},"
 159                          "{ATI, RV630},"
 160                          "{ATI, RV610},"
 161                          "{ATI, RV670},"
 162                          "{ATI, RV635},"
 163                          "{ATI, RV620},"
 164                          "{ATI, RV770},"
 165                          "{VIA, VT8251},"
 166                          "{VIA, VT8237A},"
 167                          "{SiS, SIS966},"
 168                          "{ULI, M5461}}");
 169 MODULE_DESCRIPTION("Intel HDA driver");
 170
 171 #ifdef CONFIG_SND_VERBOSE_PRINTK
 172 #define SFX     /* nop */
 173 #else
 174 #define SFX     "hda-intel: "
 175 #endif
 176
 177 /*
 178  * registers
 179  */
 180 #define ICH6_REG_GCAP                   0x00
 181 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 182 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 183 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 184 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 185 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 186 #define ICH6_REG_VMIN                   0x02
 187 #define ICH6_REG_VMAJ                   0x03
 188 #define ICH6_REG_OUTPAY                 0x04
 189 #define ICH6_REG_INPAY                  0x06
 190 #define ICH6_REG_GCTL                   0x08
 191 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 192 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 193 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 194 #define ICH6_REG_WAKEEN                 0x0c
 195 #define ICH6_REG_STATESTS               0x0e
 196 #define ICH6_REG_GSTS                   0x10
 197 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 198 #define ICH6_REG_INTCTL                 0x20
 199 #define ICH6_REG_INTSTS                 0x24
 200 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 201 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 202 #define ICH6_REG_SSYNC                  0x38
 203 #define ICH6_REG_CORBLBASE              0x40
 204 #define ICH6_REG_CORBUBASE              0x44
 205 #define ICH6_REG_CORBWP                 0x48
 206 #define ICH6_REG_CORBRP                 0x4a
 207 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 208 #define ICH6_REG_CORBCTL                0x4c
 209 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 210 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 211 #define ICH6_REG_CORBSTS                0x4d
 212 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 213 #define ICH6_REG_CORBSIZE               0x4e
 214
 215 #define ICH6_REG_RIRBLBASE              0x50
 216 #define ICH6_REG_RIRBUBASE              0x54
 217 #define ICH6_REG_RIRBWP                 0x58
 218 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 219 #define ICH6_REG_RINTCNT                0x5a
 220 #define ICH6_REG_RIRBCTL                0x5c
 221 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 222 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 223 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 224 #define ICH6_REG_RIRBSTS                0x5d
 225 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 226 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 227 #define ICH6_REG_RIRBSIZE               0x5e
 228
 229 #define ICH6_REG_IC                     0x60
 230 #define ICH6_REG_IR                     0x64
 231 #define ICH6_REG_IRS                    0x68
 232 #define   ICH6_IRS_VALID        (1<<1)
 233 #define   ICH6_IRS_BUSY         (1<<0)
 234
 235 #define ICH6_REG_DPLBASE                0x70
 236 #define ICH6_REG_DPUBASE                0x74
 237 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 238
 239 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 240 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 241
 242 /* stream register offsets from stream base */
 243 #define ICH6_REG_SD_CTL                 0x00
 244 #define ICH6_REG_SD_STS                 0x03
 245 #define ICH6_REG_SD_LPIB                0x04
 246 #define ICH6_REG_SD_CBL                 0x08
 247 #define ICH6_REG_SD_LVI                 0x0c
 248 #define ICH6_REG_SD_FIFOW               0x0e
 249 #define ICH6_REG_SD_FIFOSIZE            0x10
 250 #define ICH6_REG_SD_FORMAT              0x12
 251 #define ICH6_REG_SD_BDLPL               0x18
 252 #define ICH6_REG_SD_BDLPU               0x1c
 253
 254 /* PCI space */
 255 #define ICH6_PCIREG_TCSEL       0x44
 256
 257 /*
 258  * other constants
 259  */
 260
 261 /* max number of SDs */
 262 /* ICH, ATI and VIA have 4 playback and 4 capture */
 263 #define ICH6_NUM_CAPTURE        4
 264 #define ICH6_NUM_PLAYBACK       4
 265
 266 /* ULI has 6 playback and 5 capture */
 267 #define ULI_NUM_CAPTURE         5
 268 #define ULI_NUM_PLAYBACK        6
 269
 270 /* ATI HDMI has 1 playback and 0 capture */
 271 #define ATIHDMI_NUM_CAPTURE     0
 272 #define ATIHDMI_NUM_PLAYBACK    1
 273
 274 /* TERA has 4 playback and 3 capture */
 275 #define TERA_NUM_CAPTURE        3
 276 #define TERA_NUM_PLAYBACK       4
 277
 278 /* this number is statically defined for simplicity */
 279 #define MAX_AZX_DEV             16
 280
 281 /* max number of fragments - we may use more if allocating more pages for BDL */
 282 #define BDL_SIZE                4096
 283 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 284 #define AZX_MAX_FRAG            32
 285 /* max buffer size - no h/w limit, you can increase as you like */
 286 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 287
 288 /* RIRB int mask: overrun[2], response[0] */
 289 #define RIRB_INT_RESPONSE       0x01
 290 #define RIRB_INT_OVERRUN        0x04
 291 #define RIRB_INT_MASK           0x05
 292
 293 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 294 #define AZX_MAX_CODECS          8
 295 #define AZX_DEFAULT_CODECS      4
 296 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 297
 298 /* SD_CTL bits */
 299 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 300 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 301 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 302 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 303 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 304 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 305 #define SD_CTL_STREAM_TAG_SHIFT 20
 306
 307 /* SD_CTL and SD_STS */
 308 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 309 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 310 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 311 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 312                                  SD_INT_COMPLETE)
 313
 314 /* SD_STS */
 315 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 316
 317 /* INTCTL and INTSTS */
 318 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 319 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 320 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 321
 322 /* below are so far hardcoded - should read registers in future */
 323 #define ICH6_MAX_CORB_ENTRIES   256
 324 #define ICH6_MAX_RIRB_ENTRIES   256
 325
 326 /* position fix mode */
 327 enum {
 328         POS_FIX_AUTO,
 329         POS_FIX_LPIB,
 330         POS_FIX_POSBUF,
 331         POS_FIX_VIACOMBO,
 332 };
 333
 334 /* Defines for ATI HD Audio support in SB450 south bridge */
 335 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 336 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 337
 338 /* Defines for Nvidia HDA support */
 339 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 340 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 341 #define NVIDIA_HDA_ISTRM_COH          0x4d
 342 #define NVIDIA_HDA_OSTRM_COH          0x4c
 343 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 344
 345 /* Defines for Intel SCH HDA snoop control */
 346 #define INTEL_SCH_HDA_DEVC      0x78
 347 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 348
 349 /* Define IN stream 0 FIFO size offset in VIA controller */
 350 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 351 /* Define VIA HD Audio Device ID*/
 352 #define VIA_HDAC_DEVICE_ID              0x3288
 353
 354 /* HD Audio class code */
 355 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 356
 357 /*
 358  */
 359
 360 struct azx_dev {
 361         struct snd_dma_buffer bdl; /* BDL buffer */
 362         u32 *posbuf;            /* position buffer pointer */
 363
 364         unsigned int bufsize;   /* size of the play buffer in bytes */
 365         unsigned int period_bytes; /* size of the period in bytes */
 366         unsigned int frags;     /* number for period in the play buffer */
 367         unsigned int fifo_size; /* FIFO size */
 368         unsigned long start_wallclk;    /* start + minimum wallclk */
 369         unsigned long period_wallclk;   /* wallclk for period */
 370
 371         void __iomem *sd_addr;  /* stream descriptor pointer */
 372
 373         u32 sd_int_sta_mask;    /* stream int status mask */
 374
 375         /* pcm support */
 376         struct snd_pcm_substream *substream;    /* assigned substream,
 377                                                  * set in PCM open
 378                                                  */
 379         unsigned int format_val;        /* format value to be set in the
 380                                          * controller and the codec
 381                                          */
 382         unsigned char stream_tag;       /* assigned stream */
 383         unsigned char index;            /* stream index */
 384         int assigned_key;               /* last device# key assigned to */
 385
 386         unsigned int opened :1;
 387         unsigned int running :1;
 388         unsigned int irq_pending :1;
 389         /*
 390          * For VIA:
 391          *  A flag to ensure DMA position is 0
 392          *  when link position is not greater than FIFO size
 393          */
 394         unsigned int insufficient :1;
 395         unsigned int wc_marked:1;
 396 };
 397
 398 /* CORB/RIRB */
 399 struct azx_rb {
 400         u32 *buf;               /* CORB/RIRB buffer
 401                                  * Each CORB entry is 4byte, RIRB is 8byte
 402                                  */
 403         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 404         /* for RIRB */
 405         unsigned short rp, wp;  /* read/write pointers */
 406         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 407         u32 res[AZX_MAX_CODECS];        /* last read value */
 408 };
 409
 410 struct azx_pcm {
 411         struct azx *chip;
 412         struct snd_pcm *pcm;
 413         struct hda_codec *codec;
 414         struct hda_pcm_stream *hinfo[2];
 415         struct list_head list;
 416 };
 417
 418 struct azx {
 419         struct snd_card *card;
 420         struct pci_dev *pci;
 421         int dev_index;
 422
 423         /* chip type specific */
 424         int driver_type;
 425         unsigned int driver_caps;
 426         int playback_streams;
 427         int playback_index_offset;
 428         int capture_streams;
 429         int capture_index_offset;
 430         int num_streams;
 431
 432         /* pci resources */
 433         unsigned long addr;
 434         void __iomem *remap_addr;
 435         int irq;
 436
 437         /* locks */
 438         spinlock_t reg_lock;
 439         struct mutex open_mutex;
 440
 441         /* streams (x num_streams) */
 442         struct azx_dev *azx_dev;
 443
 444         /* PCM */
 445         struct list_head pcm_list; /* azx_pcm list */
 446
 447         /* HD codec */
 448         unsigned short codec_mask;
 449         int  codec_probe_mask; /* copied from probe_mask option */
 450         struct hda_bus *bus;
 451         unsigned int beep_mode;
 452
 453         /* CORB/RIRB */
 454         struct azx_rb corb;
 455         struct azx_rb rirb;
 456
 457         /* CORB/RIRB and position buffers */
 458         struct snd_dma_buffer rb;
 459         struct snd_dma_buffer posbuf;
 460
 461         /* flags */
 462         int position_fix[2]; /* for both playback/capture streams */
 463         int poll_count;
 464         unsigned int running :1;
 465         unsigned int initialized :1;
 466         unsigned int single_cmd :1;
 467         unsigned int polling_mode :1;
 468         unsigned int msi :1;
 469         unsigned int irq_pending_warned :1;
 470         unsigned int probing :1; /* codec probing phase */
 471         unsigned int snoop:1;
 472
 473         /* for debugging */
 474         unsigned int last_cmd[AZX_MAX_CODECS];
 475
 476         /* for pending irqs */
 477         struct work_struct irq_pending_work;
 478
 479         /* reboot notifier (for mysterious hangup problem at power-down) */
 480         struct notifier_block reboot_notifier;
 481 };
 482
 483 /* driver types */
 484 enum {
 485         AZX_DRIVER_ICH,
 486         AZX_DRIVER_PCH,
 487         AZX_DRIVER_SCH,
 488         AZX_DRIVER_ATI,
 489         AZX_DRIVER_ATIHDMI,
 490         AZX_DRIVER_VIA,
 491         AZX_DRIVER_SIS,
 492         AZX_DRIVER_ULI,
 493         AZX_DRIVER_NVIDIA,
 494         AZX_DRIVER_TERA,
 495         AZX_DRIVER_CTX,
 496         AZX_DRIVER_GENERIC,
 497         AZX_NUM_DRIVERS, /* keep this as last entry */
 498 };
 499
 500 /* driver quirks (capabilities) */
 501 /* bits 0-7 are used for indicating driver type */
 502 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 503 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 504 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 505 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 506 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 507 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 508 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 509 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 510 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 511 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 512 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 513 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 514 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 515 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 516
 517 /* quirks for ATI SB / AMD Hudson */
 518 #define AZX_DCAPS_PRESET_ATI_SB \
 519         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 520          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 521
 522 /* quirks for ATI/AMD HDMI */
 523 #define AZX_DCAPS_PRESET_ATI_HDMI \
 524         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 525
 526 /* quirks for Nvidia */
 527 #define AZX_DCAPS_PRESET_NVIDIA \
 528         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
 529
 530 static char *driver_short_names[] __devinitdata = {
 531         [AZX_DRIVER_ICH] = "HDA Intel",
 532         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 533         [AZX_DRIVER_SCH] = "HDA Intel MID",
 534         [AZX_DRIVER_ATI] = "HDA ATI SB",
 535         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 536         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 537         [AZX_DRIVER_SIS] = "HDA SIS966",
 538         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 539         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 540         [AZX_DRIVER_TERA] = "HDA Teradici",
 541         [AZX_DRIVER_CTX] = "HDA Creative",
 542         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 543 };
 544
 545 /*
 546  * macros for easy use
 547  */
 548 #define azx_writel(chip,reg,value) \
 549         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 550 #define azx_readl(chip,reg) \
 551         readl((chip)->remap_addr + ICH6_REG_##reg)
 552 #define azx_writew(chip,reg,value) \
 553         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 554 #define azx_readw(chip,reg) \
 555         readw((chip)->remap_addr + ICH6_REG_##reg)
 556 #define azx_writeb(chip,reg,value) \
 557         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 558 #define azx_readb(chip,reg) \
 559         readb((chip)->remap_addr + ICH6_REG_##reg)
 560
 561 #define azx_sd_writel(dev,reg,value) \
 562         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 563 #define azx_sd_readl(dev,reg) \
 564         readl((dev)->sd_addr + ICH6_REG_##reg)
 565 #define azx_sd_writew(dev,reg,value) \
 566         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 567 #define azx_sd_readw(dev,reg) \
 568         readw((dev)->sd_addr + ICH6_REG_##reg)
 569 #define azx_sd_writeb(dev,reg,value) \
 570         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 571 #define azx_sd_readb(dev,reg) \
 572         readb((dev)->sd_addr + ICH6_REG_##reg)
 573
 574 /* for pcm support */
 575 #define get_azx_dev(substream) (substream->runtime->private_data)
 576
 577 #ifdef CONFIG_X86
 578 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
 579 {
 580         if (azx_snoop(chip))
 581                 return;
 582         if (addr && size) {
 583                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 584                 if (on)
 585                         set_memory_wc((unsigned long)addr, pages);
 586                 else
 587                         set_memory_wb((unsigned long)addr, pages);
 588         }
 589 }
 590
 591 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 592                                  bool on)
 593 {
 594         __mark_pages_wc(chip, buf->area, buf->bytes, on);
 595 }
 596 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 597                                    struct snd_pcm_runtime *runtime, bool on)
 598 {
 599         if (azx_dev->wc_marked != on) {
 600                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
 601                 azx_dev->wc_marked = on;
 602         }
 603 }
 604 #else
 605 /* NOP for other archs */
 606 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 607                                  bool on)
 608 {
 609 }
 610 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 611                                    struct snd_pcm_runtime *runtime, bool on)
 612 {
 613 }
 614 #endif
 615
 616 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 617 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 618 /*
 619  * Interface for HD codec
 620  */
 621
 622 /*
 623  * CORB / RIRB interface
 624  */
 625 static int azx_alloc_cmd_io(struct azx *chip)
 626 {
 627         int err;
 628
 629         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 630         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 631                                   snd_dma_pci_data(chip->pci),
 632                                   PAGE_SIZE, &chip->rb);
 633         if (err < 0) {
 634                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 635                 return err;
 636         }
 637         mark_pages_wc(chip, &chip->rb, true);
 638         return 0;
 639 }
 640
 641 static void azx_init_cmd_io(struct azx *chip)
 642 {
 643         spin_lock_irq(&chip->reg_lock);
 644         /* CORB set up */
 645         chip->corb.addr = chip->rb.addr;
 646         chip->corb.buf = (u32 *)chip->rb.area;
 647         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 648         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 649
 650         /* set the corb size to 256 entries (ULI requires explicitly) */
 651         azx_writeb(chip, CORBSIZE, 0x02);
 652         /* set the corb write pointer to 0 */
 653         azx_writew(chip, CORBWP, 0);
 654         /* reset the corb hw read pointer */
 655         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 656         /* enable corb dma */
 657         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 658
 659         /* RIRB set up */
 660         chip->rirb.addr = chip->rb.addr + 2048;
 661         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 662         chip->rirb.wp = chip->rirb.rp = 0;
 663         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 664         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 665         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 666
 667         /* set the rirb size to 256 entries (ULI requires explicitly) */
 668         azx_writeb(chip, RIRBSIZE, 0x02);
 669         /* reset the rirb hw write pointer */
 670         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 671         /* set N=1, get RIRB response interrupt for new entry */
 672         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 673                 azx_writew(chip, RINTCNT, 0xc0);
 674         else
 675                 azx_writew(chip, RINTCNT, 1);
 676         /* enable rirb dma and response irq */
 677         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 678         spin_unlock_irq(&chip->reg_lock);
 679 }
 680
 681 static void azx_free_cmd_io(struct azx *chip)
 682 {
 683         spin_lock_irq(&chip->reg_lock);
 684         /* disable ringbuffer DMAs */
 685         azx_writeb(chip, RIRBCTL, 0);
 686         azx_writeb(chip, CORBCTL, 0);
 687         spin_unlock_irq(&chip->reg_lock);
 688 }
 689
 690 static unsigned int azx_command_addr(u32 cmd)
 691 {
 692         unsigned int addr = cmd >> 28;
 693
 694         if (addr >= AZX_MAX_CODECS) {
 695                 snd_BUG();
 696                 addr = 0;
 697         }
 698
 699         return addr;
 700 }
 701
 702 static unsigned int azx_response_addr(u32 res)
 703 {
 704         unsigned int addr = res & 0xf;
 705
 706         if (addr >= AZX_MAX_CODECS) {
 707                 snd_BUG();
 708                 addr = 0;
 709         }
 710
 711         return addr;
 712 }
 713
 714 /* send a command */
 715 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 716 {
 717         struct azx *chip = bus->private_data;
 718         unsigned int addr = azx_command_addr(val);
 719         unsigned int wp;
 720
 721         spin_lock_irq(&chip->reg_lock);
 722
 723         /* add command to corb */
 724         wp = azx_readb(chip, CORBWP);
 725         wp++;
 726         wp %= ICH6_MAX_CORB_ENTRIES;
 727
 728         chip->rirb.cmds[addr]++;
 729         chip->corb.buf[wp] = cpu_to_le32(val);
 730         azx_writel(chip, CORBWP, wp);
 731
 732         spin_unlock_irq(&chip->reg_lock);
 733
 734         return 0;
 735 }
 736
 737 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 738
 739 /* retrieve RIRB entry - called from interrupt handler */
 740 static void azx_update_rirb(struct azx *chip)
 741 {
 742         unsigned int rp, wp;
 743         unsigned int addr;
 744         u32 res, res_ex;
 745
 746         wp = azx_readb(chip, RIRBWP);
 747         if (wp == chip->rirb.wp)
 748                 return;
 749         chip->rirb.wp = wp;
 750
 751         while (chip->rirb.rp != wp) {
 752                 chip->rirb.rp++;
 753                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 754
 755                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 756                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 757                 res = le32_to_cpu(chip->rirb.buf[rp]);
 758                 addr = azx_response_addr(res_ex);
 759                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 760                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 761                 else if (chip->rirb.cmds[addr]) {
 762                         chip->rirb.res[addr] = res;
 763                         smp_wmb();
 764                         chip->rirb.cmds[addr]--;
 765                 } else
 766                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 767                                    "last cmd=%#08x\n",
 768                                    res, res_ex,
 769                                    chip->last_cmd[addr]);
 770         }
 771 }
 772
 773 /* receive a response */
 774 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 775                                           unsigned int addr)
 776 {
 777         struct azx *chip = bus->private_data;
 778         unsigned long timeout;
 779         int do_poll = 0;
 780
 781  again:
 782         timeout = jiffies + msecs_to_jiffies(1000);
 783         for (;;) {
 784                 if (chip->polling_mode || do_poll) {
 785                         spin_lock_irq(&chip->reg_lock);
 786                         azx_update_rirb(chip);
 787                         spin_unlock_irq(&chip->reg_lock);
 788                 }
 789                 if (!chip->rirb.cmds[addr]) {
 790                         smp_rmb();
 791                         bus->rirb_error = 0;
 792
 793                         if (!do_poll)
 794                                 chip->poll_count = 0;
 795                         return chip->rirb.res[addr]; /* the last value */
 796                 }
 797                 if (time_after(jiffies, timeout))
 798                         break;
 799                 if (bus->needs_damn_long_delay)
 800                         msleep(2); /* temporary workaround */
 801                 else {
 802                         udelay(10);
 803                         cond_resched();
 804                 }
 805         }
 806
 807         if (!chip->polling_mode && chip->poll_count < 2) {
 808                 snd_printdd(SFX "azx_get_response timeout, "
 809                            "polling the codec once: last cmd=0x%08x\n",
 810                            chip->last_cmd[addr]);
 811                 do_poll = 1;
 812                 chip->poll_count++;
 813                 goto again;
 814         }
 815
 816
 817         if (!chip->polling_mode) {
 818                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 819                            "switching to polling mode: last cmd=0x%08x\n",
 820                            chip->last_cmd[addr]);
 821                 chip->polling_mode = 1;
 822                 goto again;
 823         }
 824
 825         if (chip->msi) {
 826                 snd_printk(KERN_WARNING SFX "No response from codec, "
 827                            "disabling MSI: last cmd=0x%08x\n",
 828                            chip->last_cmd[addr]);
 829                 free_irq(chip->irq, chip);
 830                 chip->irq = -1;
 831                 pci_disable_msi(chip->pci);
 832                 chip->msi = 0;
 833                 if (azx_acquire_irq(chip, 1) < 0) {
 834                         bus->rirb_error = 1;
 835                         return -1;
 836                 }
 837                 goto again;
 838         }
 839
 840         if (chip->probing) {
 841                 /* If this critical timeout happens during the codec probing
 842                  * phase, this is likely an access to a non-existing codec
 843                  * slot.  Better to return an error and reset the system.
 844                  */
 845                 return -1;
 846         }
 847
 848         /* a fatal communication error; need either to reset or to fallback
 849          * to the single_cmd mode
 850          */
 851         bus->rirb_error = 1;
 852         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 853                 bus->response_reset = 1;
 854                 return -1; /* give a chance to retry */
 855         }
 856
 857         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 858                    "switching to single_cmd mode: last cmd=0x%08x\n",
 859                    chip->last_cmd[addr]);
 860         chip->single_cmd = 1;
 861         bus->response_reset = 0;
 862         /* release CORB/RIRB */
 863         azx_free_cmd_io(chip);
 864         /* disable unsolicited responses */
 865         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 866         return -1;
 867 }
 868
 869 /*
 870  * Use the single immediate command instead of CORB/RIRB for simplicity
 871  *
 872  * Note: according to Intel, this is not preferred use.  The command was
 873  *       intended for the BIOS only, and may get confused with unsolicited
 874  *       responses.  So, we shouldn't use it for normal operation from the
 875  *       driver.
 876  *       I left the codes, however, for debugging/testing purposes.
 877  */
 878
 879 /* receive a response */
 880 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 881 {
 882         int timeout = 50;
 883
 884         while (timeout--) {
 885                 /* check IRV busy bit */
 886                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 887                         /* reuse rirb.res as the response return value */
 888                         chip->rirb.res[addr] = azx_readl(chip, IR);
 889                         return 0;
 890                 }
 891                 udelay(1);
 892         }
 893         if (printk_ratelimit())
 894                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 895                            azx_readw(chip, IRS));
 896         chip->rirb.res[addr] = -1;
 897         return -EIO;
 898 }
 899
 900 /* send a command */
 901 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 902 {
 903         struct azx *chip = bus->private_data;
 904         unsigned int addr = azx_command_addr(val);
 905         int timeout = 50;
 906
 907         bus->rirb_error = 0;
 908         while (timeout--) {
 909                 /* check ICB busy bit */
 910                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 911                         /* Clear IRV valid bit */
 912                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 913                                    ICH6_IRS_VALID);
 914                         azx_writel(chip, IC, val);
 915                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 916                                    ICH6_IRS_BUSY);
 917                         return azx_single_wait_for_response(chip, addr);
 918                 }
 919                 udelay(1);
 920         }
 921         if (printk_ratelimit())
 922                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 923                            azx_readw(chip, IRS), val);
 924         return -EIO;
 925 }
 926
 927 /* receive a response */
 928 static unsigned int azx_single_get_response(struct hda_bus *bus,
 929                                             unsigned int addr)
 930 {
 931         struct azx *chip = bus->private_data;
 932         return chip->rirb.res[addr];
 933 }
 934
 935 /*
 936  * The below are the main callbacks from hda_codec.
 937  *
 938  * They are just the skeleton to call sub-callbacks according to the
 939  * current setting of chip->single_cmd.
 940  */
 941
 942 /* send a command */
 943 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 944 {
 945         struct azx *chip = bus->private_data;
 946
 947         chip->last_cmd[azx_command_addr(val)] = val;
 948         if (chip->single_cmd)
 949                 return azx_single_send_cmd(bus, val);
 950         else
 951                 return azx_corb_send_cmd(bus, val);
 952 }
 953
 954 /* get a response */
 955 static unsigned int azx_get_response(struct hda_bus *bus,
 956                                      unsigned int addr)
 957 {
 958         struct azx *chip = bus->private_data;
 959         if (chip->single_cmd)
 960                 return azx_single_get_response(bus, addr);
 961         else
 962                 return azx_rirb_get_response(bus, addr);
 963 }
 964
 965 #ifdef CONFIG_SND_HDA_POWER_SAVE
 966 static void azx_power_notify(struct hda_bus *bus);
 967 #endif
 968
 969 /* reset codec link */
 970 static int azx_reset(struct azx *chip, int full_reset)
 971 {
 972         int count;
 973
 974         if (!full_reset)
 975                 goto __skip;
 976
 977         /* clear STATESTS */
 978         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 979
 980         /* reset controller */
 981         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 982
 983         count = 50;
 984         while (azx_readb(chip, GCTL) && --count)
 985                 msleep(1);
 986
 987         /* delay for >= 100us for codec PLL to settle per spec
 988          * Rev 0.9 section 5.5.1
 989          */
 990         msleep(1);
 991
 992         /* Bring controller out of reset */
 993         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 994
 995         count = 50;
 996         while (!azx_readb(chip, GCTL) && --count)
 997                 msleep(1);
 998
 999         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1000         msleep(1);
1001
1002       __skip:
1003         /* check to see if controller is ready */
1004         if (!azx_readb(chip, GCTL)) {
1005                 snd_printd(SFX "azx_reset: controller not ready!\n");
1006                 return -EBUSY;
1007         }
1008
1009         /* Accept unsolicited responses */
1010         if (!chip->single_cmd)
1011                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1012                            ICH6_GCTL_UNSOL);
1013
1014         /* detect codecs */
1015         if (!chip->codec_mask) {
1016                 chip->codec_mask = azx_readw(chip, STATESTS);
1017                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1018         }
1019
1020         return 0;
1021 }
1022
1023
1024 /*
1025  * Lowlevel interface
1026  */
1027
1028 /* enable interrupts */
1029 static void azx_int_enable(struct azx *chip)
1030 {
1031         /* enable controller CIE and GIE */
1032         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1033                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1034 }
1035
1036 /* disable interrupts */
1037 static void azx_int_disable(struct azx *chip)
1038 {
1039         int i;
1040
1041         /* disable interrupts in stream descriptor */
1042         for (i = 0; i < chip->num_streams; i++) {
1043                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1044                 azx_sd_writeb(azx_dev, SD_CTL,
1045                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1046         }
1047
1048         /* disable SIE for all streams */
1049         azx_writeb(chip, INTCTL, 0);
1050
1051         /* disable controller CIE and GIE */
1052         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1053                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1054 }
1055
1056 /* clear interrupts */
1057 static void azx_int_clear(struct azx *chip)
1058 {
1059         int i;
1060
1061         /* clear stream status */
1062         for (i = 0; i < chip->num_streams; i++) {
1063                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1064                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1065         }
1066
1067         /* clear STATESTS */
1068         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1069
1070         /* clear rirb status */
1071         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1072
1073         /* clear int status */
1074         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1075 }
1076
1077 /* start a stream */
1078 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1079 {
1080         /*
1081          * Before stream start, initialize parameter
1082          */
1083         azx_dev->insufficient = 1;
1084
1085         /* enable SIE */
1086         azx_writel(chip, INTCTL,
1087                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1088         /* set DMA start and interrupt mask */
1089         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1090                       SD_CTL_DMA_START | SD_INT_MASK);
1091 }
1092
1093 /* stop DMA */
1094 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1095 {
1096         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1097                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1098         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1099 }
1100
1101 /* stop a stream */
1102 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1103 {
1104         azx_stream_clear(chip, azx_dev);
1105         /* disable SIE */
1106         azx_writel(chip, INTCTL,
1107                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1108 }
1109
1110
1111 /*
1112  * reset and start the controller registers
1113  */
1114 static void azx_init_chip(struct azx *chip, int full_reset)
1115 {
1116         if (chip->initialized)
1117                 return;
1118
1119         /* reset controller */
1120         azx_reset(chip, full_reset);
1121
1122         /* initialize interrupts */
1123         azx_int_clear(chip);
1124         azx_int_enable(chip);
1125
1126         /* initialize the codec command I/O */
1127         if (!chip->single_cmd)
1128                 azx_init_cmd_io(chip);
1129
1130         /* program the position buffer */
1131         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1132         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1133
1134         chip->initialized = 1;
1135 }
1136
1137 /*
1138  * initialize the PCI registers
1139  */
1140 /* update bits in a PCI register byte */
1141 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1142                             unsigned char mask, unsigned char val)
1143 {
1144         unsigned char data;
1145
1146         pci_read_config_byte(pci, reg, &data);
1147         data &= ~mask;
1148         data |= (val & mask);
1149         pci_write_config_byte(pci, reg, data);
1150 }
1151
1152 static void azx_init_pci(struct azx *chip)
1153 {
1154         /* force to non-snoop mode for a new VIA controller when BIOS is set */
1155         if (chip->snoop && chip->driver_type == AZX_DRIVER_VIA) {
1156                 u8 snoop;
1157                 pci_read_config_byte(chip->pci, 0x42, &snoop);
1158                 if (!(snoop & 0x80) && chip->pci->revision == 0x30) {
1159                         chip->snoop = 0;
1160                         snd_printdd(SFX "Force to non-snoop mode\n");
1161                 }
1162         }
1163
1164         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1165          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1166          * Ensuring these bits are 0 clears playback static on some HD Audio
1167          * codecs.
1168          * The PCI register TCSEL is defined in the Intel manuals.
1169          */
1170         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1171                 snd_printdd(SFX "Clearing TCSEL\n");
1172                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1173         }
1174
1175         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1176          * we need to enable snoop.
1177          */
1178         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1179                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1180                 update_pci_byte(chip->pci,
1181                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1182                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1183         }
1184
1185         /* For NVIDIA HDA, enable snoop */
1186         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1187                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1188                 update_pci_byte(chip->pci,
1189                                 NVIDIA_HDA_TRANSREG_ADDR,
1190                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1191                 update_pci_byte(chip->pci,
1192                                 NVIDIA_HDA_ISTRM_COH,
1193                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1194                 update_pci_byte(chip->pci,
1195                                 NVIDIA_HDA_OSTRM_COH,
1196                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1197         }
1198
1199         /* Enable SCH/PCH snoop if needed */
1200         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1201                 unsigned short snoop;
1202                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1203                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1204                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1205                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1206                         if (!azx_snoop(chip))
1207                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1208                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1209                         pci_read_config_word(chip->pci,
1210                                 INTEL_SCH_HDA_DEVC, &snoop);
1211                 }
1212                 snd_printdd(SFX "SCH snoop: %s\n",
1213                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1214                                 ? "Disabled" : "Enabled");
1215         }
1216 }
1217
1218
1219 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1220
1221 /*
1222  * interrupt handler
1223  */
1224 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1225 {
1226         struct azx *chip = dev_id;
1227         struct azx_dev *azx_dev;
1228         u32 status;
1229         u8 sd_status;
1230         int i, ok;
1231
1232         spin_lock(&chip->reg_lock);
1233
1234         status = azx_readl(chip, INTSTS);
1235         if (status == 0) {
1236                 spin_unlock(&chip->reg_lock);
1237                 return IRQ_NONE;
1238         }
1239
1240         for (i = 0; i < chip->num_streams; i++) {
1241                 azx_dev = &chip->azx_dev[i];
1242                 if (status & azx_dev->sd_int_sta_mask) {
1243                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1244                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1245                         if (!azx_dev->substream || !azx_dev->running ||
1246                             !(sd_status & SD_INT_COMPLETE))
1247                                 continue;
1248                         /* check whether this IRQ is really acceptable */
1249                         ok = azx_position_ok(chip, azx_dev);
1250                         if (ok == 1) {
1251                                 azx_dev->irq_pending = 0;
1252                                 spin_unlock(&chip->reg_lock);
1253                                 snd_pcm_period_elapsed(azx_dev->substream);
1254                                 spin_lock(&chip->reg_lock);
1255                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1256                                 /* bogus IRQ, process it later */
1257                                 azx_dev->irq_pending = 1;
1258                                 queue_work(chip->bus->workq,
1259                                            &chip->irq_pending_work);
1260                         }
1261                 }
1262         }
1263
1264         /* clear rirb int */
1265         status = azx_readb(chip, RIRBSTS);
1266         if (status & RIRB_INT_MASK) {
1267                 if (status & RIRB_INT_RESPONSE) {
1268                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1269                                 udelay(80);
1270                         azx_update_rirb(chip);
1271                 }
1272                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1273         }
1274
1275 #if 0
1276         /* clear state status int */
1277         if (azx_readb(chip, STATESTS) & 0x04)
1278                 azx_writeb(chip, STATESTS, 0x04);
1279 #endif
1280         spin_unlock(&chip->reg_lock);
1281
1282         return IRQ_HANDLED;
1283 }
1284
1285
1286 /*
1287  * set up a BDL entry
1288  */
1289 static int setup_bdle(struct snd_pcm_substream *substream,
1290                       struct azx_dev *azx_dev, u32 **bdlp,
1291                       int ofs, int size, int with_ioc)
1292 {
1293         u32 *bdl = *bdlp;
1294
1295         while (size > 0) {
1296                 dma_addr_t addr;
1297                 int chunk;
1298
1299                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1300                         return -EINVAL;
1301
1302                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1303                 /* program the address field of the BDL entry */
1304                 bdl[0] = cpu_to_le32((u32)addr);
1305                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1306                 /* program the size field of the BDL entry */
1307                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1308                 bdl[2] = cpu_to_le32(chunk);
1309                 /* program the IOC to enable interrupt
1310                  * only when the whole fragment is processed
1311                  */
1312                 size -= chunk;
1313                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1314                 bdl += 4;
1315                 azx_dev->frags++;
1316                 ofs += chunk;
1317         }
1318         *bdlp = bdl;
1319         return ofs;
1320 }
1321
1322 /*
1323  * set up BDL entries
1324  */
1325 static int azx_setup_periods(struct azx *chip,
1326                              struct snd_pcm_substream *substream,
1327                              struct azx_dev *azx_dev)
1328 {
1329         u32 *bdl;
1330         int i, ofs, periods, period_bytes;
1331         int pos_adj;
1332
1333         /* reset BDL address */
1334         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1335         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1336
1337         period_bytes = azx_dev->period_bytes;
1338         periods = azx_dev->bufsize / period_bytes;
1339
1340         /* program the initial BDL entries */
1341         bdl = (u32 *)azx_dev->bdl.area;
1342         ofs = 0;
1343         azx_dev->frags = 0;
1344         pos_adj = bdl_pos_adj[chip->dev_index];
1345         if (pos_adj > 0) {
1346                 struct snd_pcm_runtime *runtime = substream->runtime;
1347                 int pos_align = pos_adj;
1348                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1349                 if (!pos_adj)
1350                         pos_adj = pos_align;
1351                 else
1352                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1353                                 pos_align;
1354                 pos_adj = frames_to_bytes(runtime, pos_adj);
1355                 if (pos_adj >= period_bytes) {
1356                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1357                                    bdl_pos_adj[chip->dev_index]);
1358                         pos_adj = 0;
1359                 } else {
1360                         ofs = setup_bdle(substream, azx_dev,
1361                                          &bdl, ofs, pos_adj,
1362                                          !substream->runtime->no_period_wakeup);
1363                         if (ofs < 0)
1364                                 goto error;
1365                 }
1366         } else
1367                 pos_adj = 0;
1368         for (i = 0; i < periods; i++) {
1369                 if (i == periods - 1 && pos_adj)
1370                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1371                                          period_bytes - pos_adj, 0);
1372                 else
1373                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1374                                          period_bytes,
1375                                          !substream->runtime->no_period_wakeup);
1376                 if (ofs < 0)
1377                         goto error;
1378         }
1379         return 0;
1380
1381  error:
1382         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1383                    azx_dev->bufsize, period_bytes);
1384         return -EINVAL;
1385 }
1386
1387 /* reset stream */
1388 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1389 {
1390         unsigned char val;
1391         int timeout;
1392
1393         azx_stream_clear(chip, azx_dev);
1394
1395         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1396                       SD_CTL_STREAM_RESET);
1397         udelay(3);
1398         timeout = 300;
1399         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1400                --timeout)
1401                 ;
1402         val &= ~SD_CTL_STREAM_RESET;
1403         azx_sd_writeb(azx_dev, SD_CTL, val);
1404         udelay(3);
1405
1406         timeout = 300;
1407         /* waiting for hardware to report that the stream is out of reset */
1408         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1409                --timeout)
1410                 ;
1411
1412         /* reset first position - may not be synced with hw at this time */
1413         *azx_dev->posbuf = 0;
1414 }
1415
1416 /*
1417  * set up the SD for streaming
1418  */
1419 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1420 {
1421         unsigned int val;
1422         /* make sure the run bit is zero for SD */
1423         azx_stream_clear(chip, azx_dev);
1424         /* program the stream_tag */
1425         val = azx_sd_readl(azx_dev, SD_CTL);
1426         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1427                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1428         if (!azx_snoop(chip))
1429                 val |= SD_CTL_TRAFFIC_PRIO;
1430         azx_sd_writel(azx_dev, SD_CTL, val);
1431
1432         /* program the length of samples in cyclic buffer */
1433         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1434
1435         /* program the stream format */
1436         /* this value needs to be the same as the one programmed */
1437         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1438
1439         /* program the stream LVI (last valid index) of the BDL */
1440         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1441
1442         /* program the BDL address */
1443         /* lower BDL address */
1444         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1445         /* upper BDL address */
1446         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1447
1448         /* enable the position buffer */
1449         if (chip->position_fix[0] != POS_FIX_LPIB ||
1450             chip->position_fix[1] != POS_FIX_LPIB) {
1451                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1452                         azx_writel(chip, DPLBASE,
1453                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1454         }
1455
1456         /* set the interrupt enable bits in the descriptor control register */
1457         azx_sd_writel(azx_dev, SD_CTL,
1458                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1459
1460         return 0;
1461 }
1462
1463 /*
1464  * Probe the given codec address
1465  */
1466 static int probe_codec(struct azx *chip, int addr)
1467 {
1468         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1469                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1470         unsigned int res;
1471
1472         mutex_lock(&chip->bus->cmd_mutex);
1473         chip->probing = 1;
1474         azx_send_cmd(chip->bus, cmd);
1475         res = azx_get_response(chip->bus, addr);
1476         chip->probing = 0;
1477         mutex_unlock(&chip->bus->cmd_mutex);
1478         if (res == -1)
1479                 return -EIO;
1480         snd_printdd(SFX "codec #%d probed OK\n", addr);
1481         return 0;
1482 }
1483
1484 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1485                                  struct hda_pcm *cpcm);
1486 static void azx_stop_chip(struct azx *chip);
1487
1488 static void azx_bus_reset(struct hda_bus *bus)
1489 {
1490         struct azx *chip = bus->private_data;
1491
1492         bus->in_reset = 1;
1493         azx_stop_chip(chip);
1494         azx_init_chip(chip, 1);
1495 #ifdef CONFIG_PM
1496         if (chip->initialized) {
1497                 struct azx_pcm *p;
1498                 list_for_each_entry(p, &chip->pcm_list, list)
1499                         snd_pcm_suspend_all(p->pcm);
1500                 snd_hda_suspend(chip->bus);
1501                 snd_hda_resume(chip->bus);
1502         }
1503 #endif
1504         bus->in_reset = 0;
1505 }
1506
1507 /*
1508  * Codec initialization
1509  */
1510
1511 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1512 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1513         [AZX_DRIVER_NVIDIA] = 8,
1514         [AZX_DRIVER_TERA] = 1,
1515 };
1516
1517 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1518 {
1519         struct hda_bus_template bus_temp;
1520         int c, codecs, err;
1521         int max_slots;
1522
1523         memset(&bus_temp, 0, sizeof(bus_temp));
1524         bus_temp.private_data = chip;
1525         bus_temp.modelname = model;
1526         bus_temp.pci = chip->pci;
1527         bus_temp.ops.command = azx_send_cmd;
1528         bus_temp.ops.get_response = azx_get_response;
1529         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1530         bus_temp.ops.bus_reset = azx_bus_reset;
1531 #ifdef CONFIG_SND_HDA_POWER_SAVE
1532         bus_temp.power_save = &power_save;
1533         bus_temp.ops.pm_notify = azx_power_notify;
1534 #endif
1535
1536         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1537         if (err < 0)
1538                 return err;
1539
1540         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1541                 snd_printd(SFX "Enable delay in RIRB handling\n");
1542                 chip->bus->needs_damn_long_delay = 1;
1543         }
1544
1545         codecs = 0;
1546         max_slots = azx_max_codecs[chip->driver_type];
1547         if (!max_slots)
1548                 max_slots = AZX_DEFAULT_CODECS;
1549
1550         /* First try to probe all given codec slots */
1551         for (c = 0; c < max_slots; c++) {
1552                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1553                         if (probe_codec(chip, c) < 0) {
1554                                 /* Some BIOSen give you wrong codec addresses
1555                                  * that don't exist
1556                                  */
1557                                 snd_printk(KERN_WARNING SFX
1558                                            "Codec #%d probe error; "
1559                                            "disabling it...\n", c);
1560                                 chip->codec_mask &= ~(1 << c);
1561                                 /* More badly, accessing to a non-existing
1562                                  * codec often screws up the controller chip,
1563                                  * and disturbs the further communications.
1564                                  * Thus if an error occurs during probing,
1565                                  * better to reset the controller chip to
1566                                  * get back to the sanity state.
1567                                  */
1568                                 azx_stop_chip(chip);
1569                                 azx_init_chip(chip, 1);
1570                         }
1571                 }
1572         }
1573
1574         /* AMD chipsets often cause the communication stalls upon certain
1575          * sequence like the pin-detection.  It seems that forcing the synced
1576          * access works around the stall.  Grrr...
1577          */
1578         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1579                 snd_printd(SFX "Enable sync_write for stable communication\n");
1580                 chip->bus->sync_write = 1;
1581                 chip->bus->allow_bus_reset = 1;
1582         }
1583
1584         /* Then create codec instances */
1585         for (c = 0; c < max_slots; c++) {
1586                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1587                         struct hda_codec *codec;
1588                         err = snd_hda_codec_new(chip->bus, c, &codec);
1589                         if (err < 0)
1590                                 continue;
1591                         codec->beep_mode = chip->beep_mode;
1592                         codecs++;
1593                 }
1594         }
1595         if (!codecs) {
1596                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1597                 return -ENXIO;
1598         }
1599         return 0;
1600 }
1601
1602 /* configure each codec instance */
1603 static int __devinit azx_codec_configure(struct azx *chip)
1604 {
1605         struct hda_codec *codec;
1606         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1607                 snd_hda_codec_configure(codec);
1608         }
1609         return 0;
1610 }
1611
1612
1613 /*
1614  * PCM support
1615  */
1616
1617 /* assign a stream for the PCM */
1618 static inline struct azx_dev *
1619 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1620 {
1621         int dev, i, nums;
1622         struct azx_dev *res = NULL;
1623         /* make a non-zero unique key for the substream */
1624         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1625                 (substream->stream + 1);
1626
1627         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1628                 dev = chip->playback_index_offset;
1629                 nums = chip->playback_streams;
1630         } else {
1631                 dev = chip->capture_index_offset;
1632                 nums = chip->capture_streams;
1633         }
1634         for (i = 0; i < nums; i++, dev++)
1635                 if (!chip->azx_dev[dev].opened) {
1636                         res = &chip->azx_dev[dev];
1637                         if (res->assigned_key == key)
1638                                 break;
1639                 }
1640         if (res) {
1641                 res->opened = 1;
1642                 res->assigned_key = key;
1643         }
1644         return res;
1645 }
1646
1647 /* release the assigned stream */
1648 static inline void azx_release_device(struct azx_dev *azx_dev)
1649 {
1650         azx_dev->opened = 0;
1651 }
1652
1653 static struct snd_pcm_hardware azx_pcm_hw = {
1654         .info =                 (SNDRV_PCM_INFO_MMAP |
1655                                  SNDRV_PCM_INFO_INTERLEAVED |
1656                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1657                                  SNDRV_PCM_INFO_MMAP_VALID |
1658                                  /* No full-resume yet implemented */
1659                                  /* SNDRV_PCM_INFO_RESUME |*/
1660                                  SNDRV_PCM_INFO_PAUSE |
1661                                  SNDRV_PCM_INFO_SYNC_START |
1662                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1663         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1664         .rates =                SNDRV_PCM_RATE_48000,
1665         .rate_min =             48000,
1666         .rate_max =             48000,
1667         .channels_min =         2,
1668         .channels_max =         2,
1669         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1670         .period_bytes_min =     128,
1671         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1672         .periods_min =          2,
1673         .periods_max =          AZX_MAX_FRAG,
1674         .fifo_size =            0,
1675 };
1676
1677 static int azx_pcm_open(struct snd_pcm_substream *substream)
1678 {
1679         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1680         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1681         struct azx *chip = apcm->chip;
1682         struct azx_dev *azx_dev;
1683         struct snd_pcm_runtime *runtime = substream->runtime;
1684         unsigned long flags;
1685         int err;
1686         int buff_step;
1687
1688         mutex_lock(&chip->open_mutex);
1689         azx_dev = azx_assign_device(chip, substream);
1690         if (azx_dev == NULL) {
1691                 mutex_unlock(&chip->open_mutex);
1692                 return -EBUSY;
1693         }
1694         runtime->hw = azx_pcm_hw;
1695         runtime->hw.channels_min = hinfo->channels_min;
1696         runtime->hw.channels_max = hinfo->channels_max;
1697         runtime->hw.formats = hinfo->formats;
1698         runtime->hw.rates = hinfo->rates;
1699         snd_pcm_limit_hw_rates(runtime);
1700         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1701         if (align_buffer_size)
1702                 /* constrain buffer sizes to be multiple of 128
1703                    bytes. This is more efficient in terms of memory
1704                    access but isn't required by the HDA spec and
1705                    prevents users from specifying exact period/buffer
1706                    sizes. For example for 44.1kHz, a period size set
1707                    to 20ms will be rounded to 19.59ms. */
1708                 buff_step = 128;
1709         else
1710                 /* Don't enforce steps on buffer sizes, still need to
1711                    be multiple of 4 bytes (HDA spec). Tested on Intel
1712                    HDA controllers, may not work on all devices where
1713                    option needs to be disabled */
1714                 buff_step = 4;
1715
1716         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1717                                    buff_step);
1718         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1719                                    buff_step);
1720         snd_hda_power_up(apcm->codec);
1721         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1722         if (err < 0) {
1723                 azx_release_device(azx_dev);
1724                 snd_hda_power_down(apcm->codec);
1725                 mutex_unlock(&chip->open_mutex);
1726                 return err;
1727         }
1728         snd_pcm_limit_hw_rates(runtime);
1729         /* sanity check */
1730         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1731             snd_BUG_ON(!runtime->hw.channels_max) ||
1732             snd_BUG_ON(!runtime->hw.formats) ||
1733             snd_BUG_ON(!runtime->hw.rates)) {
1734                 azx_release_device(azx_dev);
1735                 hinfo->ops.close(hinfo, apcm->codec, substream);
1736                 snd_hda_power_down(apcm->codec);
1737                 mutex_unlock(&chip->open_mutex);
1738                 return -EINVAL;
1739         }
1740         spin_lock_irqsave(&chip->reg_lock, flags);
1741         azx_dev->substream = substream;
1742         azx_dev->running = 0;
1743         spin_unlock_irqrestore(&chip->reg_lock, flags);
1744
1745         runtime->private_data = azx_dev;
1746         snd_pcm_set_sync(substream);
1747         mutex_unlock(&chip->open_mutex);
1748         return 0;
1749 }
1750
1751 static int azx_pcm_close(struct snd_pcm_substream *substream)
1752 {
1753         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1754         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1755         struct azx *chip = apcm->chip;
1756         struct azx_dev *azx_dev = get_azx_dev(substream);
1757         unsigned long flags;
1758
1759         mutex_lock(&chip->open_mutex);
1760         spin_lock_irqsave(&chip->reg_lock, flags);
1761         azx_dev->substream = NULL;
1762         azx_dev->running = 0;
1763         spin_unlock_irqrestore(&chip->reg_lock, flags);
1764         azx_release_device(azx_dev);
1765         hinfo->ops.close(hinfo, apcm->codec, substream);
1766         snd_hda_power_down(apcm->codec);
1767         mutex_unlock(&chip->open_mutex);
1768         return 0;
1769 }
1770
1771 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1772                              struct snd_pcm_hw_params *hw_params)
1773 {
1774         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1775         struct azx *chip = apcm->chip;
1776         struct snd_pcm_runtime *runtime = substream->runtime;
1777         struct azx_dev *azx_dev = get_azx_dev(substream);
1778         int ret;
1779
1780         mark_runtime_wc(chip, azx_dev, runtime, false);
1781         azx_dev->bufsize = 0;
1782         azx_dev->period_bytes = 0;
1783         azx_dev->format_val = 0;
1784         ret = snd_pcm_lib_malloc_pages(substream,
1785                                         params_buffer_bytes(hw_params));
1786         if (ret < 0)
1787                 return ret;
1788         mark_runtime_wc(chip, azx_dev, runtime, true);
1789         return ret;
1790 }
1791
1792 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1793 {
1794         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1795         struct azx_dev *azx_dev = get_azx_dev(substream);
1796         struct azx *chip = apcm->chip;
1797         struct snd_pcm_runtime *runtime = substream->runtime;
1798         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1799
1800         /* reset BDL address */
1801         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1802         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1803         azx_sd_writel(azx_dev, SD_CTL, 0);
1804         azx_dev->bufsize = 0;
1805         azx_dev->period_bytes = 0;
1806         azx_dev->format_val = 0;
1807
1808         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1809
1810         mark_runtime_wc(chip, azx_dev, runtime, false);
1811         return snd_pcm_lib_free_pages(substream);
1812 }
1813
1814 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1815 {
1816         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1817         struct azx *chip = apcm->chip;
1818         struct azx_dev *azx_dev = get_azx_dev(substream);
1819         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1820         struct snd_pcm_runtime *runtime = substream->runtime;
1821         unsigned int bufsize, period_bytes, format_val, stream_tag;
1822         int err;
1823         struct hda_spdif_out *spdif =
1824                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1825         unsigned short ctls = spdif ? spdif->ctls : 0;
1826
1827         azx_stream_reset(chip, azx_dev);
1828         format_val = snd_hda_calc_stream_format(runtime->rate,
1829                                                 runtime->channels,
1830                                                 runtime->format,
1831                                                 hinfo->maxbps,
1832                                                 ctls);
1833         if (!format_val) {
1834                 snd_printk(KERN_ERR SFX
1835                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1836                            runtime->rate, runtime->channels, runtime->format);
1837                 return -EINVAL;
1838         }
1839
1840         bufsize = snd_pcm_lib_buffer_bytes(substream);
1841         period_bytes = snd_pcm_lib_period_bytes(substream);
1842
1843         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1844                     bufsize, format_val);
1845
1846         if (bufsize != azx_dev->bufsize ||
1847             period_bytes != azx_dev->period_bytes ||
1848             format_val != azx_dev->format_val) {
1849                 azx_dev->bufsize = bufsize;
1850                 azx_dev->period_bytes = period_bytes;
1851                 azx_dev->format_val = format_val;
1852                 err = azx_setup_periods(chip, substream, azx_dev);
1853                 if (err < 0)
1854                         return err;
1855         }
1856
1857         /* wallclk has 24Mhz clock source */
1858         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1859                                                 runtime->rate) * 1000);
1860         azx_setup_controller(chip, azx_dev);
1861         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1862                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1863         else
1864                 azx_dev->fifo_size = 0;
1865
1866         stream_tag = azx_dev->stream_tag;
1867         /* CA-IBG chips need the playback stream starting from 1 */
1868         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1869             stream_tag > chip->capture_streams)
1870                 stream_tag -= chip->capture_streams;
1871         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1872                                      azx_dev->format_val, substream);
1873 }
1874
1875 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1876 {
1877         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1878         struct azx *chip = apcm->chip;
1879         struct azx_dev *azx_dev;
1880         struct snd_pcm_substream *s;
1881         int rstart = 0, start, nsync = 0, sbits = 0;
1882         int nwait, timeout;
1883
1884         switch (cmd) {
1885         case SNDRV_PCM_TRIGGER_START:
1886                 rstart = 1;
1887         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1888         case SNDRV_PCM_TRIGGER_RESUME:
1889                 start = 1;
1890                 break;
1891         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1892         case SNDRV_PCM_TRIGGER_SUSPEND:
1893         case SNDRV_PCM_TRIGGER_STOP:
1894                 start = 0;
1895                 break;
1896         default:
1897                 return -EINVAL;
1898         }
1899
1900         snd_pcm_group_for_each_entry(s, substream) {
1901                 if (s->pcm->card != substream->pcm->card)
1902                         continue;
1903                 azx_dev = get_azx_dev(s);
1904                 sbits |= 1 << azx_dev->index;
1905                 nsync++;
1906                 snd_pcm_trigger_done(s, substream);
1907         }
1908
1909         spin_lock(&chip->reg_lock);
1910         if (nsync > 1) {
1911                 /* first, set SYNC bits of corresponding streams */
1912                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1913                         azx_writel(chip, OLD_SSYNC,
1914                                    azx_readl(chip, OLD_SSYNC) | sbits);
1915                 else
1916                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1917         }
1918         snd_pcm_group_for_each_entry(s, substream) {
1919                 if (s->pcm->card != substream->pcm->card)
1920                         continue;
1921                 azx_dev = get_azx_dev(s);
1922                 if (start) {
1923                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1924                         if (!rstart)
1925                                 azx_dev->start_wallclk -=
1926                                                 azx_dev->period_wallclk;
1927                         azx_stream_start(chip, azx_dev);
1928                 } else {
1929                         azx_stream_stop(chip, azx_dev);
1930                 }
1931                 azx_dev->running = start;
1932         }
1933         spin_unlock(&chip->reg_lock);
1934         if (start) {
1935                 if (nsync == 1)
1936                         return 0;
1937                 /* wait until all FIFOs get ready */
1938                 for (timeout = 5000; timeout; timeout--) {
1939                         nwait = 0;
1940                         snd_pcm_group_for_each_entry(s, substream) {
1941                                 if (s->pcm->card != substream->pcm->card)
1942                                         continue;
1943                                 azx_dev = get_azx_dev(s);
1944                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1945                                       SD_STS_FIFO_READY))
1946                                         nwait++;
1947                         }
1948                         if (!nwait)
1949                                 break;
1950                         cpu_relax();
1951                 }
1952         } else {
1953                 /* wait until all RUN bits are cleared */
1954                 for (timeout = 5000; timeout; timeout--) {
1955                         nwait = 0;
1956                         snd_pcm_group_for_each_entry(s, substream) {
1957                                 if (s->pcm->card != substream->pcm->card)
1958                                         continue;
1959                                 azx_dev = get_azx_dev(s);
1960                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1961                                     SD_CTL_DMA_START)
1962                                         nwait++;
1963                         }
1964                         if (!nwait)
1965                                 break;
1966                         cpu_relax();
1967                 }
1968         }
1969         if (nsync > 1) {
1970                 spin_lock(&chip->reg_lock);
1971                 /* reset SYNC bits */
1972                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1973                         azx_writel(chip, OLD_SSYNC,
1974                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
1975                 else
1976                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1977                 spin_unlock(&chip->reg_lock);
1978         }
1979         return 0;
1980 }
1981
1982 /* get the current DMA position with correction on VIA chips */
1983 static unsigned int azx_via_get_position(struct azx *chip,
1984                                          struct azx_dev *azx_dev)
1985 {
1986         unsigned int link_pos, mini_pos, bound_pos;
1987         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1988         unsigned int fifo_size;
1989
1990         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1991         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1992                 /* Playback, no problem using link position */
1993                 return link_pos;
1994         }
1995
1996         /* Capture */
1997         /* For new chipset,
1998          * use mod to get the DMA position just like old chipset
1999          */
2000         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2001         mod_dma_pos %= azx_dev->period_bytes;
2002
2003         /* azx_dev->fifo_size can't get FIFO size of in stream.
2004          * Get from base address + offset.
2005          */
2006         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2007
2008         if (azx_dev->insufficient) {
2009                 /* Link position never gather than FIFO size */
2010                 if (link_pos <= fifo_size)
2011                         return 0;
2012
2013                 azx_dev->insufficient = 0;
2014         }
2015
2016         if (link_pos <= fifo_size)
2017                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2018         else
2019                 mini_pos = link_pos - fifo_size;
2020
2021         /* Find nearest previous boudary */
2022         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2023         mod_link_pos = link_pos % azx_dev->period_bytes;
2024         if (mod_link_pos >= fifo_size)
2025                 bound_pos = link_pos - mod_link_pos;
2026         else if (mod_dma_pos >= mod_mini_pos)
2027                 bound_pos = mini_pos - mod_mini_pos;
2028         else {
2029                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2030                 if (bound_pos >= azx_dev->bufsize)
2031                         bound_pos = 0;
2032         }
2033
2034         /* Calculate real DMA position we want */
2035         return bound_pos + mod_dma_pos;
2036 }
2037
2038 static unsigned int azx_get_position(struct azx *chip,
2039                                      struct azx_dev *azx_dev,
2040                                      bool with_check)
2041 {
2042         unsigned int pos;
2043         int stream = azx_dev->substream->stream;
2044
2045         switch (chip->position_fix[stream]) {
2046         case POS_FIX_LPIB:
2047                 /* read LPIB */
2048                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2049                 break;
2050         case POS_FIX_VIACOMBO:
2051                 pos = azx_via_get_position(chip, azx_dev);
2052                 break;
2053         default:
2054                 /* use the position buffer */
2055                 pos = le32_to_cpu(*azx_dev->posbuf);
2056                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2057                         if (!pos || pos == (u32)-1) {
2058                                 printk(KERN_WARNING
2059                                        "hda-intel: Invalid position buffer, "
2060                                        "using LPIB read method instead.\n");
2061                                 chip->position_fix[stream] = POS_FIX_LPIB;
2062                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2063                         } else
2064                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2065                 }
2066                 break;
2067         }
2068
2069         if (pos >= azx_dev->bufsize)
2070                 pos = 0;
2071         return pos;
2072 }
2073
2074 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2075 {
2076         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2077         struct azx *chip = apcm->chip;
2078         struct azx_dev *azx_dev = get_azx_dev(substream);
2079         return bytes_to_frames(substream->runtime,
2080                                azx_get_position(chip, azx_dev, false));
2081 }
2082
2083 /*
2084  * Check whether the current DMA position is acceptable for updating
2085  * periods.  Returns non-zero if it's OK.
2086  *
2087  * Many HD-audio controllers appear pretty inaccurate about
2088  * the update-IRQ timing.  The IRQ is issued before actually the
2089  * data is processed.  So, we need to process it afterwords in a
2090  * workqueue.
2091  */
2092 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2093 {
2094         u32 wallclk;
2095         unsigned int pos;
2096         int stream;
2097
2098         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2099         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2100                 return -1;      /* bogus (too early) interrupt */
2101
2102         stream = azx_dev->substream->stream;
2103         pos = azx_get_position(chip, azx_dev, true);
2104
2105         if (WARN_ONCE(!azx_dev->period_bytes,
2106                       "hda-intel: zero azx_dev->period_bytes"))
2107                 return -1; /* this shouldn't happen! */
2108         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2109             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2110                 /* NG - it's below the first next period boundary */
2111                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2112         azx_dev->start_wallclk += wallclk;
2113         return 1; /* OK, it's fine */
2114 }
2115
2116 /*
2117  * The work for pending PCM period updates.
2118  */
2119 static void azx_irq_pending_work(struct work_struct *work)
2120 {
2121         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2122         int i, pending, ok;
2123
2124         if (!chip->irq_pending_warned) {
2125                 printk(KERN_WARNING
2126                        "hda-intel: IRQ timing workaround is activated "
2127                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2128                        chip->card->number);
2129                 chip->irq_pending_warned = 1;
2130         }
2131
2132         for (;;) {
2133                 pending = 0;
2134                 spin_lock_irq(&chip->reg_lock);
2135                 for (i = 0; i < chip->num_streams; i++) {
2136                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2137                         if (!azx_dev->irq_pending ||
2138                             !azx_dev->substream ||
2139                             !azx_dev->running)
2140                                 continue;
2141                         ok = azx_position_ok(chip, azx_dev);
2142                         if (ok > 0) {
2143                                 azx_dev->irq_pending = 0;
2144                                 spin_unlock(&chip->reg_lock);
2145                                 snd_pcm_period_elapsed(azx_dev->substream);
2146                                 spin_lock(&chip->reg_lock);
2147                         } else if (ok < 0) {
2148                                 pending = 0;    /* too early */
2149                         } else
2150                                 pending++;
2151                 }
2152                 spin_unlock_irq(&chip->reg_lock);
2153                 if (!pending)
2154                         return;
2155                 msleep(1);
2156         }
2157 }
2158
2159 /* clear irq_pending flags and assure no on-going workq */
2160 static void azx_clear_irq_pending(struct azx *chip)
2161 {
2162         int i;
2163
2164         spin_lock_irq(&chip->reg_lock);
2165         for (i = 0; i < chip->num_streams; i++)
2166                 chip->azx_dev[i].irq_pending = 0;
2167         spin_unlock_irq(&chip->reg_lock);
2168 }
2169
2170 #ifdef CONFIG_X86
2171 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2172                         struct vm_area_struct *area)
2173 {
2174         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2175         struct azx *chip = apcm->chip;
2176         if (!azx_snoop(chip))
2177                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2178         return snd_pcm_lib_default_mmap(substream, area);
2179 }
2180 #else
2181 #define azx_pcm_mmap    NULL
2182 #endif
2183
2184 static struct snd_pcm_ops azx_pcm_ops = {
2185         .open = azx_pcm_open,
2186         .close = azx_pcm_close,
2187         .ioctl = snd_pcm_lib_ioctl,
2188         .hw_params = azx_pcm_hw_params,
2189         .hw_free = azx_pcm_hw_free,
2190         .prepare = azx_pcm_prepare,
2191         .trigger = azx_pcm_trigger,
2192         .pointer = azx_pcm_pointer,
2193         .mmap = azx_pcm_mmap,
2194         .page = snd_pcm_sgbuf_ops_page,
2195 };
2196
2197 static void azx_pcm_free(struct snd_pcm *pcm)
2198 {
2199         struct azx_pcm *apcm = pcm->private_data;
2200         if (apcm) {
2201                 list_del(&apcm->list);
2202                 kfree(apcm);
2203         }
2204 }
2205
2206 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2207
2208 static int
2209 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2210                       struct hda_pcm *cpcm)
2211 {
2212         struct azx *chip = bus->private_data;
2213         struct snd_pcm *pcm;
2214         struct azx_pcm *apcm;
2215         int pcm_dev = cpcm->device;
2216         unsigned int size;
2217         int s, err;
2218
2219         list_for_each_entry(apcm, &chip->pcm_list, list) {
2220                 if (apcm->pcm->device == pcm_dev) {
2221                         snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2222                         return -EBUSY;
2223                 }
2224         }
2225         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2226                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2227                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2228                           &pcm);
2229         if (err < 0)
2230                 return err;
2231         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2232         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2233         if (apcm == NULL)
2234                 return -ENOMEM;
2235         apcm->chip = chip;
2236         apcm->pcm = pcm;
2237         apcm->codec = codec;
2238         pcm->private_data = apcm;
2239         pcm->private_free = azx_pcm_free;
2240         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2241                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2242         list_add_tail(&apcm->list, &chip->pcm_list);
2243         cpcm->pcm = pcm;
2244         for (s = 0; s < 2; s++) {
2245                 apcm->hinfo[s] = &cpcm->stream[s];
2246                 if (cpcm->stream[s].substreams)
2247                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2248         }
2249         /* buffer pre-allocation */
2250         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2251         if (size > MAX_PREALLOC_SIZE)
2252                 size = MAX_PREALLOC_SIZE;
2253         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2254                                               snd_dma_pci_data(chip->pci),
2255                                               size, MAX_PREALLOC_SIZE);
2256         return 0;
2257 }
2258
2259 /*
2260  * mixer creation - all stuff is implemented in hda module
2261  */
2262 static int __devinit azx_mixer_create(struct azx *chip)
2263 {
2264         return snd_hda_build_controls(chip->bus);
2265 }
2266
2267
2268 /*
2269  * initialize SD streams
2270  */
2271 static int __devinit azx_init_stream(struct azx *chip)
2272 {
2273         int i;
2274
2275         /* initialize each stream (aka device)
2276          * assign the starting bdl address to each stream (device)
2277          * and initialize
2278          */
2279         for (i = 0; i < chip->num_streams; i++) {
2280                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2281                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2282                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2283                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2284                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2285                 azx_dev->sd_int_sta_mask = 1 << i;
2286                 /* stream tag: must be non-zero and unique */
2287                 azx_dev->index = i;
2288                 azx_dev->stream_tag = i + 1;
2289         }
2290
2291         return 0;
2292 }
2293
2294 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2295 {
2296         if (request_irq(chip->pci->irq, azx_interrupt,
2297                         chip->msi ? 0 : IRQF_SHARED,
2298                         KBUILD_MODNAME, chip)) {
2299                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2300                        "disabling device\n", chip->pci->irq);
2301                 if (do_disconnect)
2302                         snd_card_disconnect(chip->card);
2303                 return -1;
2304         }
2305         chip->irq = chip->pci->irq;
2306         pci_intx(chip->pci, !chip->msi);
2307         return 0;
2308 }
2309
2310
2311 static void azx_stop_chip(struct azx *chip)
2312 {
2313         if (!chip->initialized)
2314                 return;
2315
2316         /* disable interrupts */
2317         azx_int_disable(chip);
2318         azx_int_clear(chip);
2319
2320         /* disable CORB/RIRB */
2321         azx_free_cmd_io(chip);
2322
2323         /* disable position buffer */
2324         azx_writel(chip, DPLBASE, 0);
2325         azx_writel(chip, DPUBASE, 0);
2326
2327         chip->initialized = 0;
2328 }
2329
2330 #ifdef CONFIG_SND_HDA_POWER_SAVE
2331 /* power-up/down the controller */
2332 static void azx_power_notify(struct hda_bus *bus)
2333 {
2334         struct azx *chip = bus->private_data;
2335         struct hda_codec *c;
2336         int power_on = 0;
2337
2338         list_for_each_entry(c, &bus->codec_list, list) {
2339                 if (c->power_on) {
2340                         power_on = 1;
2341                         break;
2342                 }
2343         }
2344         if (power_on)
2345                 azx_init_chip(chip, 1);
2346         else if (chip->running && power_save_controller &&
2347                  !bus->power_keep_link_on)
2348                 azx_stop_chip(chip);
2349 }
2350 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2351
2352 #ifdef CONFIG_PM
2353 /*
2354  * power management
2355  */
2356
2357 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2358 {
2359         struct hda_codec *codec;
2360
2361         list_for_each_entry(codec, &bus->codec_list, list) {
2362                 if (snd_hda_codec_needs_resume(codec))
2363                         return 1;
2364         }
2365         return 0;
2366 }
2367
2368 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2369 {
2370         struct snd_card *card = pci_get_drvdata(pci);
2371         struct azx *chip = card->private_data;
2372         struct azx_pcm *p;
2373
2374         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2375         azx_clear_irq_pending(chip);
2376         list_for_each_entry(p, &chip->pcm_list, list)
2377                 snd_pcm_suspend_all(p->pcm);
2378         if (chip->initialized)
2379                 snd_hda_suspend(chip->bus);
2380         azx_stop_chip(chip);
2381         if (chip->irq >= 0) {
2382                 free_irq(chip->irq, chip);
2383                 chip->irq = -1;
2384         }
2385         if (chip->msi)
2386                 pci_disable_msi(chip->pci);
2387         pci_disable_device(pci);
2388         pci_save_state(pci);
2389         pci_set_power_state(pci, pci_choose_state(pci, state));
2390         return 0;
2391 }
2392
2393 static int azx_resume(struct pci_dev *pci)
2394 {
2395         struct snd_card *card = pci_get_drvdata(pci);
2396         struct azx *chip = card->private_data;
2397
2398         pci_set_power_state(pci, PCI_D0);
2399         pci_restore_state(pci);
2400         if (pci_enable_device(pci) < 0) {
2401                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2402                        "disabling device\n");
2403                 snd_card_disconnect(card);
2404                 return -EIO;
2405         }
2406         pci_set_master(pci);
2407         if (chip->msi)
2408                 if (pci_enable_msi(pci) < 0)
2409                         chip->msi = 0;
2410         if (azx_acquire_irq(chip, 1) < 0)
2411                 return -EIO;
2412         azx_init_pci(chip);
2413
2414         if (snd_hda_codecs_inuse(chip->bus))
2415                 azx_init_chip(chip, 1);
2416
2417         snd_hda_resume(chip->bus);
2418         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2419         return 0;
2420 }
2421 #endif /* CONFIG_PM */
2422
2423
2424 /*
2425  * reboot notifier for hang-up problem at power-down
2426  */
2427 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2428 {
2429         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2430         snd_hda_bus_reboot_notify(chip->bus);
2431         azx_stop_chip(chip);
2432         return NOTIFY_OK;
2433 }
2434
2435 static void azx_notifier_register(struct azx *chip)
2436 {
2437         chip->reboot_notifier.notifier_call = azx_halt;
2438         register_reboot_notifier(&chip->reboot_notifier);
2439 }
2440
2441 static void azx_notifier_unregister(struct azx *chip)
2442 {
2443         if (chip->reboot_notifier.notifier_call)
2444                 unregister_reboot_notifier(&chip->reboot_notifier);
2445 }
2446
2447 /*
2448  * destructor
2449  */
2450 static int azx_free(struct azx *chip)
2451 {
2452         int i;
2453
2454         azx_notifier_unregister(chip);
2455
2456         if (chip->initialized) {
2457                 azx_clear_irq_pending(chip);
2458                 for (i = 0; i < chip->num_streams; i++)
2459                         azx_stream_stop(chip, &chip->azx_dev[i]);
2460                 azx_stop_chip(chip);
2461         }
2462
2463         if (chip->irq >= 0)
2464                 free_irq(chip->irq, (void*)chip);
2465         if (chip->msi)
2466                 pci_disable_msi(chip->pci);
2467         if (chip->remap_addr)
2468                 iounmap(chip->remap_addr);
2469
2470         if (chip->azx_dev) {
2471                 for (i = 0; i < chip->num_streams; i++)
2472                         if (chip->azx_dev[i].bdl.area) {
2473                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2474                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2475                         }
2476         }
2477         if (chip->rb.area) {
2478                 mark_pages_wc(chip, &chip->rb, false);
2479                 snd_dma_free_pages(&chip->rb);
2480         }
2481         if (chip->posbuf.area) {
2482                 mark_pages_wc(chip, &chip->posbuf, false);
2483                 snd_dma_free_pages(&chip->posbuf);
2484         }
2485         pci_release_regions(chip->pci);
2486         pci_disable_device(chip->pci);
2487         kfree(chip->azx_dev);
2488         kfree(chip);
2489
2490         return 0;
2491 }
2492
2493 static int azx_dev_free(struct snd_device *device)
2494 {
2495         return azx_free(device->device_data);
2496 }
2497
2498 /*
2499  * white/black-listing for position_fix
2500  */
2501 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2502         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2503         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2504         SND_PCI_QUIRK(0x1028, 0x02c6, "Dell Inspiron 1010", POS_FIX_LPIB),
2505         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2506         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2507         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2508         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2509         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2510         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2511         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2512         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2513         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2514         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2515         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2516         {}
2517 };
2518
2519 static int __devinit check_position_fix(struct azx *chip, int fix)
2520 {
2521         const struct snd_pci_quirk *q;
2522
2523         switch (fix) {
2524         case POS_FIX_LPIB:
2525         case POS_FIX_POSBUF:
2526         case POS_FIX_VIACOMBO:
2527                 return fix;
2528         }
2529
2530         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2531         if (q) {
2532                 printk(KERN_INFO
2533                        "hda_intel: position_fix set to %d "
2534                        "for device %04x:%04x\n",
2535                        q->value, q->subvendor, q->subdevice);
2536                 return q->value;
2537         }
2538
2539         /* Check VIA/ATI HD Audio Controller exist */
2540         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2541                 snd_printd(SFX "Using VIACOMBO position fix\n");
2542                 return POS_FIX_VIACOMBO;
2543         }
2544         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2545                 snd_printd(SFX "Using LPIB position fix\n");
2546                 return POS_FIX_LPIB;
2547         }
2548         return POS_FIX_AUTO;
2549 }
2550
2551 /*
2552  * black-lists for probe_mask
2553  */
2554 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2555         /* Thinkpad often breaks the controller communication when accessing
2556          * to the non-working (or non-existing) modem codec slot.
2557          */
2558         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2559         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2560         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2561         /* broken BIOS */
2562         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2563         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2564         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2565         /* forced codec slots */
2566         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2567         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2568         {}
2569 };
2570
2571 #define AZX_FORCE_CODEC_MASK    0x100
2572
2573 static void __devinit check_probe_mask(struct azx *chip, int dev)
2574 {
2575         const struct snd_pci_quirk *q;
2576
2577         chip->codec_probe_mask = probe_mask[dev];
2578         if (chip->codec_probe_mask == -1) {
2579                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2580                 if (q) {
2581                         printk(KERN_INFO
2582                                "hda_intel: probe_mask set to 0x%x "
2583                                "for device %04x:%04x\n",
2584                                q->value, q->subvendor, q->subdevice);
2585                         chip->codec_probe_mask = q->value;
2586                 }
2587         }
2588
2589         /* check forced option */
2590         if (chip->codec_probe_mask != -1 &&
2591             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2592                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2593                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2594                        chip->codec_mask);
2595         }
2596 }
2597
2598 /*
2599  * white/black-list for enable_msi
2600  */
2601 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2602         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2603         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2604         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2605         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2606         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2607         {}
2608 };
2609
2610 static void __devinit check_msi(struct azx *chip)
2611 {
2612         const struct snd_pci_quirk *q;
2613
2614         if (enable_msi >= 0) {
2615                 chip->msi = !!enable_msi;
2616                 return;
2617         }
2618         chip->msi = 1;  /* enable MSI as default */
2619         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2620         if (q) {
2621                 printk(KERN_INFO
2622                        "hda_intel: msi for device %04x:%04x set to %d\n",
2623                        q->subvendor, q->subdevice, q->value);
2624                 chip->msi = q->value;
2625                 return;
2626         }
2627
2628         /* NVidia chipsets seem to cause troubles with MSI */
2629         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2630                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2631                 chip->msi = 0;
2632         }
2633 }
2634
2635
2636 /*
2637  * constructor
2638  */
2639 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2640                                 int dev, unsigned int driver_caps,
2641                                 struct azx **rchip)
2642 {
2643         struct azx *chip;
2644         int i, err;
2645         unsigned short gcap;
2646         static struct snd_device_ops ops = {
2647                 .dev_free = azx_dev_free,
2648         };
2649
2650         *rchip = NULL;
2651
2652         err = pci_enable_device(pci);
2653         if (err < 0)
2654                 return err;
2655
2656         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2657         if (!chip) {
2658                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2659                 pci_disable_device(pci);
2660                 return -ENOMEM;
2661         }
2662
2663         spin_lock_init(&chip->reg_lock);
2664         mutex_init(&chip->open_mutex);
2665         chip->card = card;
2666         chip->pci = pci;
2667         chip->irq = -1;
2668         chip->driver_caps = driver_caps;
2669         chip->driver_type = driver_caps & 0xff;
2670         check_msi(chip);
2671         chip->dev_index = dev;
2672         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2673         INIT_LIST_HEAD(&chip->pcm_list);
2674
2675         chip->position_fix[0] = chip->position_fix[1] =
2676                 check_position_fix(chip, position_fix[dev]);
2677         check_probe_mask(chip, dev);
2678
2679         chip->single_cmd = single_cmd;
2680         chip->snoop = hda_snoop;
2681
2682         if (bdl_pos_adj[dev] < 0) {
2683                 switch (chip->driver_type) {
2684                 case AZX_DRIVER_ICH:
2685                 case AZX_DRIVER_PCH:
2686                         bdl_pos_adj[dev] = 1;
2687                         break;
2688                 default:
2689                         bdl_pos_adj[dev] = 32;
2690                         break;
2691                 }
2692         }
2693
2694 #if BITS_PER_LONG != 64
2695         /* Fix up base address on ULI M5461 */
2696         if (chip->driver_type == AZX_DRIVER_ULI) {
2697                 u16 tmp3;
2698                 pci_read_config_word(pci, 0x40, &tmp3);
2699                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2700                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2701         }
2702 #endif
2703
2704         err = pci_request_regions(pci, "ICH HD audio");
2705         if (err < 0) {
2706                 kfree(chip);
2707                 pci_disable_device(pci);
2708                 return err;
2709         }
2710
2711         chip->addr = pci_resource_start(pci, 0);
2712         chip->remap_addr = pci_ioremap_bar(pci, 0);
2713         if (chip->remap_addr == NULL) {
2714                 snd_printk(KERN_ERR SFX "ioremap error\n");
2715                 err = -ENXIO;
2716                 goto errout;
2717         }
2718
2719         if (chip->msi)
2720                 if (pci_enable_msi(pci) < 0)
2721                         chip->msi = 0;
2722
2723         if (azx_acquire_irq(chip, 0) < 0) {
2724                 err = -EBUSY;
2725                 goto errout;
2726         }
2727
2728         pci_set_master(pci);
2729         synchronize_irq(chip->irq);
2730
2731         gcap = azx_readw(chip, GCAP);
2732         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2733
2734         /* disable SB600 64bit support for safety */
2735         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2736                 struct pci_dev *p_smbus;
2737                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2738                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2739                                          NULL);
2740                 if (p_smbus) {
2741                         if (p_smbus->revision < 0x30)
2742                                 gcap &= ~ICH6_GCAP_64OK;
2743                         pci_dev_put(p_smbus);
2744                 }
2745         }
2746
2747         /* disable 64bit DMA address on some devices */
2748         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2749                 snd_printd(SFX "Disabling 64bit DMA\n");
2750                 gcap &= ~ICH6_GCAP_64OK;
2751         }
2752
2753         /* disable buffer size rounding to 128-byte multiples if supported */
2754         if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2755                 align_buffer_size = 0;
2756
2757         /* allow 64bit DMA address if supported by H/W */
2758         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2759                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2760         else {
2761                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2762                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2763         }
2764
2765         /* read number of streams from GCAP register instead of using
2766          * hardcoded value
2767          */
2768         chip->capture_streams = (gcap >> 8) & 0x0f;
2769         chip->playback_streams = (gcap >> 12) & 0x0f;
2770         if (!chip->playback_streams && !chip->capture_streams) {
2771                 /* gcap didn't give any info, switching to old method */
2772
2773                 switch (chip->driver_type) {
2774                 case AZX_DRIVER_ULI:
2775                         chip->playback_streams = ULI_NUM_PLAYBACK;
2776                         chip->capture_streams = ULI_NUM_CAPTURE;
2777                         break;
2778                 case AZX_DRIVER_ATIHDMI:
2779                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2780                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2781                         break;
2782                 case AZX_DRIVER_GENERIC:
2783                 default:
2784                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2785                         chip->capture_streams = ICH6_NUM_CAPTURE;
2786                         break;
2787                 }
2788         }
2789         chip->capture_index_offset = 0;
2790         chip->playback_index_offset = chip->capture_streams;
2791         chip->num_streams = chip->playback_streams + chip->capture_streams;
2792         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2793                                 GFP_KERNEL);
2794         if (!chip->azx_dev) {
2795                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2796                 goto errout;
2797         }
2798
2799         for (i = 0; i < chip->num_streams; i++) {
2800                 /* allocate memory for the BDL for each stream */
2801                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2802                                           snd_dma_pci_data(chip->pci),
2803                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2804                 if (err < 0) {
2805                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2806                         goto errout;
2807                 }
2808                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2809         }
2810         /* allocate memory for the position buffer */
2811         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2812                                   snd_dma_pci_data(chip->pci),
2813                                   chip->num_streams * 8, &chip->posbuf);
2814         if (err < 0) {
2815                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2816                 goto errout;
2817         }
2818         mark_pages_wc(chip, &chip->posbuf, true);
2819         /* allocate CORB/RIRB */
2820         err = azx_alloc_cmd_io(chip);
2821         if (err < 0)
2822                 goto errout;
2823
2824         /* initialize streams */
2825         azx_init_stream(chip);
2826
2827         /* initialize chip */
2828         azx_init_pci(chip);
2829         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2830
2831         /* codec detection */
2832         if (!chip->codec_mask) {
2833                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2834                 err = -ENODEV;
2835                 goto errout;
2836         }
2837
2838         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2839         if (err <0) {
2840                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2841                 goto errout;
2842         }
2843
2844         strcpy(card->driver, "HDA-Intel");
2845         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2846                 sizeof(card->shortname));
2847         snprintf(card->longname, sizeof(card->longname),
2848                  "%s at 0x%lx irq %i",
2849                  card->shortname, chip->addr, chip->irq);
2850
2851         *rchip = chip;
2852         return 0;
2853
2854  errout:
2855         azx_free(chip);
2856         return err;
2857 }
2858
2859 static void power_down_all_codecs(struct azx *chip)
2860 {
2861 #ifdef CONFIG_SND_HDA_POWER_SAVE
2862         /* The codecs were powered up in snd_hda_codec_new().
2863          * Now all initialization done, so turn them down if possible
2864          */
2865         struct hda_codec *codec;
2866         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2867                 snd_hda_power_down(codec);
2868         }
2869 #endif
2870 }
2871
2872 static int __devinit azx_probe(struct pci_dev *pci,
2873                                const struct pci_device_id *pci_id)
2874 {
2875         static int dev;
2876         struct snd_card *card;
2877         struct azx *chip;
2878         int err;
2879
2880         if (dev >= SNDRV_CARDS)
2881                 return -ENODEV;
2882         if (!enable[dev]) {
2883                 dev++;
2884                 return -ENOENT;
2885         }
2886
2887         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2888         if (err < 0) {
2889                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2890                 return err;
2891         }
2892
2893         /* set this here since it's referred in snd_hda_load_patch() */
2894         snd_card_set_dev(card, &pci->dev);
2895
2896         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2897         if (err < 0)
2898                 goto out_free;
2899         card->private_data = chip;
2900
2901 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2902         chip->beep_mode = beep_mode[dev];
2903 #endif
2904
2905         /* create codec instances */
2906         err = azx_codec_create(chip, model[dev]);
2907         if (err < 0)
2908                 goto out_free;
2909 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2910         if (patch[dev] && *patch[dev]) {
2911                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2912                            patch[dev]);
2913                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2914                 if (err < 0)
2915                         goto out_free;
2916         }
2917 #endif
2918         if ((probe_only[dev] & 1) == 0) {
2919                 err = azx_codec_configure(chip);
2920                 if (err < 0)
2921                         goto out_free;
2922         }
2923
2924         /* create PCM streams */
2925         err = snd_hda_build_pcms(chip->bus);
2926         if (err < 0)
2927                 goto out_free;
2928
2929         /* create mixer controls */
2930         err = azx_mixer_create(chip);
2931         if (err < 0)
2932                 goto out_free;
2933
2934         err = snd_card_register(card);
2935         if (err < 0)
2936                 goto out_free;
2937
2938         pci_set_drvdata(pci, card);
2939         chip->running = 1;
2940         power_down_all_codecs(chip);
2941         azx_notifier_register(chip);
2942
2943         dev++;
2944         return err;
2945 out_free:
2946         snd_card_free(card);
2947         return err;
2948 }
2949
2950 static void __devexit azx_remove(struct pci_dev *pci)
2951 {
2952         snd_card_free(pci_get_drvdata(pci));
2953         pci_set_drvdata(pci, NULL);
2954 }
2955
2956 /* PCI IDs */
2957 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2958         /* CPT */
2959         { PCI_DEVICE(0x8086, 0x1c20),
2960           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2961           AZX_DCAPS_BUFSIZE },
2962         /* PBG */
2963         { PCI_DEVICE(0x8086, 0x1d20),
2964           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2965           AZX_DCAPS_BUFSIZE},
2966         /* Panther Point */
2967         { PCI_DEVICE(0x8086, 0x1e20),
2968           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2969           AZX_DCAPS_BUFSIZE},
2970         /* SCH */
2971         { PCI_DEVICE(0x8086, 0x811b),
2972           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2973           AZX_DCAPS_BUFSIZE},
2974         { PCI_DEVICE(0x8086, 0x2668),
2975           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2976           AZX_DCAPS_BUFSIZE },  /* ICH6 */
2977         { PCI_DEVICE(0x8086, 0x27d8),
2978           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2979           AZX_DCAPS_BUFSIZE },  /* ICH7 */
2980         { PCI_DEVICE(0x8086, 0x269a),
2981           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2982           AZX_DCAPS_BUFSIZE },  /* ESB2 */
2983         { PCI_DEVICE(0x8086, 0x284b),
2984           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2985           AZX_DCAPS_BUFSIZE },  /* ICH8 */
2986         { PCI_DEVICE(0x8086, 0x293e),
2987           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2988           AZX_DCAPS_BUFSIZE },  /* ICH9 */
2989         { PCI_DEVICE(0x8086, 0x293f),
2990           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2991           AZX_DCAPS_BUFSIZE },  /* ICH9 */
2992         { PCI_DEVICE(0x8086, 0x3a3e),
2993           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2994           AZX_DCAPS_BUFSIZE },  /* ICH10 */
2995         { PCI_DEVICE(0x8086, 0x3a6e),
2996           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2997           AZX_DCAPS_BUFSIZE },  /* ICH10 */
2998         /* Generic Intel */
2999         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3000           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3001           .class_mask = 0xffffff,
3002           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3003         /* ATI SB 450/600/700/800/900 */
3004         { PCI_DEVICE(0x1002, 0x437b),
3005           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3006         { PCI_DEVICE(0x1002, 0x4383),
3007           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3008         /* AMD Hudson */
3009         { PCI_DEVICE(0x1022, 0x780d),
3010           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3011         /* ATI HDMI */
3012         { PCI_DEVICE(0x1002, 0x793b),
3013           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3014         { PCI_DEVICE(0x1002, 0x7919),
3015           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3016         { PCI_DEVICE(0x1002, 0x960f),
3017           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3018         { PCI_DEVICE(0x1002, 0x970f),
3019           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3020         { PCI_DEVICE(0x1002, 0xaa00),
3021           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3022         { PCI_DEVICE(0x1002, 0xaa08),
3023           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3024         { PCI_DEVICE(0x1002, 0xaa10),
3025           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3026         { PCI_DEVICE(0x1002, 0xaa18),
3027           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3028         { PCI_DEVICE(0x1002, 0xaa20),
3029           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3030         { PCI_DEVICE(0x1002, 0xaa28),
3031           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3032         { PCI_DEVICE(0x1002, 0xaa30),
3033           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3034         { PCI_DEVICE(0x1002, 0xaa38),
3035           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3036         { PCI_DEVICE(0x1002, 0xaa40),
3037           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3038         { PCI_DEVICE(0x1002, 0xaa48),
3039           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3040         /* VIA VT8251/VT8237A */
3041         { PCI_DEVICE(0x1106, 0x3288),
3042           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3043         /* SIS966 */
3044         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3045         /* ULI M5461 */
3046         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3047         /* NVIDIA MCP */
3048         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3049           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3050           .class_mask = 0xffffff,
3051           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3052         /* Teradici */
3053         { PCI_DEVICE(0x6549, 0x1200),
3054           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3055         /* Creative X-Fi (CA0110-IBG) */
3056 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3057         /* the following entry conflicts with snd-ctxfi driver,
3058          * as ctxfi driver mutates from HD-audio to native mode with
3059          * a special command sequence.
3060          */
3061         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3062           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3063           .class_mask = 0xffffff,
3064           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3065           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3066 #else
3067         /* this entry seems still valid -- i.e. without emu20kx chip */
3068         { PCI_DEVICE(0x1102, 0x0009),
3069           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3070           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3071 #endif
3072         /* Vortex86MX */
3073         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3074         /* VMware HDAudio */
3075         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3076         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3077         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3078           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3079           .class_mask = 0xffffff,
3080           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3081         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3082           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3083           .class_mask = 0xffffff,
3084           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3085         { 0, }
3086 };
3087 MODULE_DEVICE_TABLE(pci, azx_ids);
3088
3089 /* pci_driver definition */
3090 static struct pci_driver driver = {
3091         .name = KBUILD_MODNAME,
3092         .id_table = azx_ids,
3093         .probe = azx_probe,
3094         .remove = __devexit_p(azx_remove),
3095 #ifdef CONFIG_PM
3096         .suspend = azx_suspend,
3097         .resume = azx_resume,
3098 #endif
3099 };
3100
3101 static int __init alsa_card_azx_init(void)
3102 {
3103         return pci_register_driver(&driver);
3104 }
3105
3106 static void __exit alsa_card_azx_exit(void)
3107 {
3108         pci_unregister_driver(&driver);
3109 }
3110
3111 module_init(alsa_card_azx_init)
3112 module_exit(alsa_card_azx_exit)