1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * hda_intel.c - Implementation of primary alsa driver code base
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
42 /* for snoop control */
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/firmware.h>
54 #include <sound/hda_codec.h>
55 #include "hda_controller.h"
56 #include "hda_intel.h"
58 #define CREATE_TRACE_POINTS
59 #include "hda_intel_trace.h"
61 /* position fix mode */
72 /* Defines for ATI HD Audio support in SB450 south bridge */
73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
76 /* Defines for Nvidia HDA support */
77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79 #define NVIDIA_HDA_ISTRM_COH 0x4d
80 #define NVIDIA_HDA_OSTRM_COH 0x4c
81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
83 /* Defines for Intel SCH HDA snoop control */
84 #define INTEL_HDA_CGCTL 0x48
85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
86 #define INTEL_SCH_HDA_DEVC 0x78
87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
89 /* Define VIA HD Audio Device ID*/
90 #define VIA_HDAC_DEVICE_ID 0x3288
92 /* max number of SDs */
93 /* ICH, ATI and VIA have 4 playback and 4 capture */
94 #define ICH6_NUM_CAPTURE 4
95 #define ICH6_NUM_PLAYBACK 4
97 /* ULI has 6 playback and 5 capture */
98 #define ULI_NUM_CAPTURE 5
99 #define ULI_NUM_PLAYBACK 6
101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
102 #define ATIHDMI_NUM_CAPTURE 0
103 #define ATIHDMI_NUM_PLAYBACK 8
105 /* TERA has 4 playback and 3 capture */
106 #define TERA_NUM_CAPTURE 3
107 #define TERA_NUM_PLAYBACK 4
110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
113 static char *model[SNDRV_CARDS];
114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
117 static int probe_only[SNDRV_CARDS];
118 static int jackpoll_ms[SNDRV_CARDS];
119 static int single_cmd = -1;
120 static int enable_msi = -1;
121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
122 static char *patch[SNDRV_CARDS];
124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
128 static bool dmic_detect = 1;
130 module_param_array(index, int, NULL, 0444);
131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
132 module_param_array(id, charp, NULL, 0444);
133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
134 module_param_array(enable, bool, NULL, 0444);
135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136 module_param_array(model, charp, NULL, 0444);
137 MODULE_PARM_DESC(model, "Use the given board model.");
138 module_param_array(position_fix, int, NULL, 0444);
139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
141 module_param_array(bdl_pos_adj, int, NULL, 0644);
142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
143 module_param_array(probe_mask, int, NULL, 0444);
144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
145 module_param_array(probe_only, int, NULL, 0444);
146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
147 module_param_array(jackpoll_ms, int, NULL, 0444);
148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
149 module_param(single_cmd, bint, 0444);
150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
152 module_param(enable_msi, bint, 0444);
153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
155 module_param_array(patch, charp, NULL, 0444);
156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
159 module_param_array(beep_mode, bool, NULL, 0444);
160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
161 "(0=off, 1=on) (default=1).");
163 module_param(dmic_detect, bool, 0444);
164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static const struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
174 #define param_check_xint param_check_int
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 module_param(power_save, xint, 0644);
178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
181 static bool pm_blacklist = true;
182 module_param(pm_blacklist, bool, 0644);
183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
194 #endif /* CONFIG_PM */
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
206 #define hda_snoop true
210 MODULE_LICENSE("GPL");
211 MODULE_DESCRIPTION("Intel HDA driver");
213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
215 #define SUPPORT_VGA_SWITCHEROO
232 AZX_DRIVER_ATIHDMI_NS,
243 AZX_NUM_DRIVERS, /* keep this as last entry */
246 #define azx_get_snoop_type(chip) \
247 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
248 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
250 /* quirks for old Intel chipsets */
251 #define AZX_DCAPS_INTEL_ICH \
252 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
254 /* quirks for Intel PCH */
255 #define AZX_DCAPS_INTEL_PCH_BASE \
256 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
257 AZX_DCAPS_SNOOP_TYPE(SCH))
259 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
260 #define AZX_DCAPS_INTEL_PCH_NOPM \
261 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
263 /* PCH for HSW/BDW; with runtime PM */
264 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
265 #define AZX_DCAPS_INTEL_PCH \
266 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
269 #define AZX_DCAPS_INTEL_HASWELL \
270 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
271 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
272 AZX_DCAPS_SNOOP_TYPE(SCH))
274 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
275 #define AZX_DCAPS_INTEL_BROADWELL \
276 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
277 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
278 AZX_DCAPS_SNOOP_TYPE(SCH))
280 #define AZX_DCAPS_INTEL_BAYTRAIL \
281 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
283 #define AZX_DCAPS_INTEL_BRASWELL \
284 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
285 AZX_DCAPS_I915_COMPONENT)
287 #define AZX_DCAPS_INTEL_SKYLAKE \
288 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
289 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
291 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
293 /* quirks for ATI SB / AMD Hudson */
294 #define AZX_DCAPS_PRESET_ATI_SB \
295 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
296 AZX_DCAPS_SNOOP_TYPE(ATI))
298 /* quirks for ATI/AMD HDMI */
299 #define AZX_DCAPS_PRESET_ATI_HDMI \
300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
303 /* quirks for ATI HDMI with snoop off */
304 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
305 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
307 /* quirks for AMD SB */
308 #define AZX_DCAPS_PRESET_AMD_SB \
309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
310 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
312 /* quirks for Nvidia */
313 #define AZX_DCAPS_PRESET_NVIDIA \
314 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
315 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
317 #define AZX_DCAPS_PRESET_CTHDA \
318 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
319 AZX_DCAPS_NO_64BIT |\
320 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
323 * vga_switcheroo support
325 #ifdef SUPPORT_VGA_SWITCHEROO
326 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
327 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
329 #define use_vga_switcheroo(chip) 0
330 #define needs_eld_notify_link(chip) false
333 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
334 ((pci)->device == 0x0c0c) || \
335 ((pci)->device == 0x0d0c) || \
336 ((pci)->device == 0x160c) || \
337 ((pci)->device == 0x490d))
339 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
341 static const char * const driver_short_names[] = {
342 [AZX_DRIVER_ICH] = "HDA Intel",
343 [AZX_DRIVER_PCH] = "HDA Intel PCH",
344 [AZX_DRIVER_SCH] = "HDA Intel MID",
345 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
346 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
347 [AZX_DRIVER_ATI] = "HDA ATI SB",
348 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
349 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
350 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
351 [AZX_DRIVER_SIS] = "HDA SIS966",
352 [AZX_DRIVER_ULI] = "HDA ULI M5461",
353 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
354 [AZX_DRIVER_TERA] = "HDA Teradici",
355 [AZX_DRIVER_CTX] = "HDA Creative",
356 [AZX_DRIVER_CTHDA] = "HDA Creative",
357 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
358 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
359 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
362 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
363 static void set_default_power_save(struct azx *chip);
366 * initialize the PCI registers
368 /* update bits in a PCI register byte */
369 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
370 unsigned char mask, unsigned char val)
374 pci_read_config_byte(pci, reg, &data);
376 data |= (val & mask);
377 pci_write_config_byte(pci, reg, data);
380 static void azx_init_pci(struct azx *chip)
382 int snoop_type = azx_get_snoop_type(chip);
384 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
385 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
386 * Ensuring these bits are 0 clears playback static on some HD Audio
388 * The PCI register TCSEL is defined in the Intel manuals.
390 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
391 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
392 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
395 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
396 * we need to enable snoop.
398 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
399 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
401 update_pci_byte(chip->pci,
402 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
403 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
406 /* For NVIDIA HDA, enable snoop */
407 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
408 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
410 update_pci_byte(chip->pci,
411 NVIDIA_HDA_TRANSREG_ADDR,
412 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
413 update_pci_byte(chip->pci,
414 NVIDIA_HDA_ISTRM_COH,
415 0x01, NVIDIA_HDA_ENABLE_COHBIT);
416 update_pci_byte(chip->pci,
417 NVIDIA_HDA_OSTRM_COH,
418 0x01, NVIDIA_HDA_ENABLE_COHBIT);
421 /* Enable SCH/PCH snoop if needed */
422 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
423 unsigned short snoop;
424 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
425 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
426 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
427 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
428 if (!azx_snoop(chip))
429 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
430 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
431 pci_read_config_word(chip->pci,
432 INTEL_SCH_HDA_DEVC, &snoop);
434 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
435 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
436 "Disabled" : "Enabled");
441 * In BXT-P A0, HD-Audio DMA requests is later than expected,
442 * and makes an audio stream sensitive to system latencies when
443 * 24/32 bits are playing.
444 * Adjusting threshold of DMA fifo to force the DMA request
445 * sooner to improve latency tolerance at the expense of power.
447 static void bxt_reduce_dma_latency(struct azx *chip)
451 val = azx_readl(chip, VS_EM4L);
453 azx_writel(chip, VS_EM4L, val);
458 * bit 0: 6 MHz Supported
459 * bit 1: 12 MHz Supported
460 * bit 2: 24 MHz Supported
461 * bit 3: 48 MHz Supported
462 * bit 4: 96 MHz Supported
463 * bit 5: 192 MHz Supported
465 static int intel_get_lctl_scf(struct azx *chip)
467 struct hdac_bus *bus = azx_bus(chip);
468 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
472 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
474 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
475 t = preferred_bits[i];
480 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
484 static int intel_ml_lctl_set_power(struct azx *chip, int state)
486 struct hdac_bus *bus = azx_bus(chip);
491 * the codecs are sharing the first link setting by default
492 * If other links are enabled for stream, they need similar fix
494 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
495 val &= ~AZX_MLCTL_SPA;
496 val |= state << AZX_MLCTL_SPA_SHIFT;
497 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
501 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
502 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
511 static void intel_init_lctl(struct azx *chip)
513 struct hdac_bus *bus = azx_bus(chip);
517 /* 0. check lctl register value is correct or not */
518 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
519 /* if SCF is already set, let's use it */
520 if ((val & ML_LCTL_SCF_MASK) != 0)
524 * Before operating on SPA, CPA must match SPA.
525 * Any deviation may result in undefined behavior.
527 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
528 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
531 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
532 ret = intel_ml_lctl_set_power(chip, 0);
537 /* 2. update SCF to select a properly audio clock*/
538 val &= ~ML_LCTL_SCF_MASK;
539 val |= intel_get_lctl_scf(chip);
540 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
543 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
544 intel_ml_lctl_set_power(chip, 1);
548 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
550 struct hdac_bus *bus = azx_bus(chip);
551 struct pci_dev *pci = chip->pci;
554 snd_hdac_set_codec_wakeup(bus, true);
555 if (chip->driver_type == AZX_DRIVER_SKL) {
556 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
557 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
558 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
560 azx_init_chip(chip, full_reset);
561 if (chip->driver_type == AZX_DRIVER_SKL) {
562 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
563 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
564 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
567 snd_hdac_set_codec_wakeup(bus, false);
569 /* reduce dma latency to avoid noise */
571 bxt_reduce_dma_latency(chip);
573 if (bus->mlcap != NULL)
574 intel_init_lctl(chip);
577 /* calculate runtime delay from LPIB */
578 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
581 struct snd_pcm_substream *substream = azx_dev->core.substream;
582 int stream = substream->stream;
583 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
586 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
587 delay = pos - lpib_pos;
589 delay = lpib_pos - pos;
591 if (delay >= azx_dev->core.delay_negative_threshold)
594 delay += azx_dev->core.bufsize;
597 if (delay >= azx_dev->core.period_bytes) {
598 dev_info(chip->card->dev,
599 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
600 delay, azx_dev->core.period_bytes);
602 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
603 chip->get_delay[stream] = NULL;
606 return bytes_to_frames(substream->runtime, delay);
609 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
611 /* called from IRQ */
612 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
614 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
617 ok = azx_position_ok(chip, azx_dev);
619 azx_dev->irq_pending = 0;
621 } else if (ok == 0) {
622 /* bogus IRQ, process it later */
623 azx_dev->irq_pending = 1;
624 schedule_work(&hda->irq_pending_work);
629 #define display_power(chip, enable) \
630 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
633 * Check whether the current DMA position is acceptable for updating
634 * periods. Returns non-zero if it's OK.
636 * Many HD-audio controllers appear pretty inaccurate about
637 * the update-IRQ timing. The IRQ is issued before actually the
638 * data is processed. So, we need to process it afterwords in a
641 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
643 struct snd_pcm_substream *substream = azx_dev->core.substream;
644 int stream = substream->stream;
648 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
649 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
650 return -1; /* bogus (too early) interrupt */
652 if (chip->get_position[stream])
653 pos = chip->get_position[stream](chip, azx_dev);
654 else { /* use the position buffer as default */
655 pos = azx_get_pos_posbuf(chip, azx_dev);
656 if (!pos || pos == (u32)-1) {
657 dev_info(chip->card->dev,
658 "Invalid position buffer, using LPIB read method instead.\n");
659 chip->get_position[stream] = azx_get_pos_lpib;
660 if (chip->get_position[0] == azx_get_pos_lpib &&
661 chip->get_position[1] == azx_get_pos_lpib)
662 azx_bus(chip)->use_posbuf = false;
663 pos = azx_get_pos_lpib(chip, azx_dev);
664 chip->get_delay[stream] = NULL;
666 chip->get_position[stream] = azx_get_pos_posbuf;
667 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
668 chip->get_delay[stream] = azx_get_delay_from_lpib;
672 if (pos >= azx_dev->core.bufsize)
675 if (WARN_ONCE(!azx_dev->core.period_bytes,
676 "hda-intel: zero azx_dev->period_bytes"))
677 return -1; /* this shouldn't happen! */
678 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
679 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
680 /* NG - it's below the first next period boundary */
681 return chip->bdl_pos_adj ? 0 : -1;
682 azx_dev->core.start_wallclk += wallclk;
683 return 1; /* OK, it's fine */
687 * The work for pending PCM period updates.
689 static void azx_irq_pending_work(struct work_struct *work)
691 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
692 struct azx *chip = &hda->chip;
693 struct hdac_bus *bus = azx_bus(chip);
694 struct hdac_stream *s;
697 if (!hda->irq_pending_warned) {
698 dev_info(chip->card->dev,
699 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
701 hda->irq_pending_warned = 1;
706 spin_lock_irq(&bus->reg_lock);
707 list_for_each_entry(s, &bus->stream_list, list) {
708 struct azx_dev *azx_dev = stream_to_azx_dev(s);
709 if (!azx_dev->irq_pending ||
713 ok = azx_position_ok(chip, azx_dev);
715 azx_dev->irq_pending = 0;
716 spin_unlock(&bus->reg_lock);
717 snd_pcm_period_elapsed(s->substream);
718 spin_lock(&bus->reg_lock);
720 pending = 0; /* too early */
724 spin_unlock_irq(&bus->reg_lock);
731 /* clear irq_pending flags and assure no on-going workq */
732 static void azx_clear_irq_pending(struct azx *chip)
734 struct hdac_bus *bus = azx_bus(chip);
735 struct hdac_stream *s;
737 spin_lock_irq(&bus->reg_lock);
738 list_for_each_entry(s, &bus->stream_list, list) {
739 struct azx_dev *azx_dev = stream_to_azx_dev(s);
740 azx_dev->irq_pending = 0;
742 spin_unlock_irq(&bus->reg_lock);
745 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
747 struct hdac_bus *bus = azx_bus(chip);
749 if (request_irq(chip->pci->irq, azx_interrupt,
750 chip->msi ? 0 : IRQF_SHARED,
751 chip->card->irq_descr, chip)) {
752 dev_err(chip->card->dev,
753 "unable to grab IRQ %d, disabling device\n",
756 snd_card_disconnect(chip->card);
759 bus->irq = chip->pci->irq;
760 chip->card->sync_irq = bus->irq;
761 pci_intx(chip->pci, !chip->msi);
765 /* get the current DMA position with correction on VIA chips */
766 static unsigned int azx_via_get_position(struct azx *chip,
767 struct azx_dev *azx_dev)
769 unsigned int link_pos, mini_pos, bound_pos;
770 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
771 unsigned int fifo_size;
773 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
774 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
775 /* Playback, no problem using link position */
781 * use mod to get the DMA position just like old chipset
783 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
784 mod_dma_pos %= azx_dev->core.period_bytes;
786 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
788 if (azx_dev->insufficient) {
789 /* Link position never gather than FIFO size */
790 if (link_pos <= fifo_size)
793 azx_dev->insufficient = 0;
796 if (link_pos <= fifo_size)
797 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
799 mini_pos = link_pos - fifo_size;
801 /* Find nearest previous boudary */
802 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
803 mod_link_pos = link_pos % azx_dev->core.period_bytes;
804 if (mod_link_pos >= fifo_size)
805 bound_pos = link_pos - mod_link_pos;
806 else if (mod_dma_pos >= mod_mini_pos)
807 bound_pos = mini_pos - mod_mini_pos;
809 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
810 if (bound_pos >= azx_dev->core.bufsize)
814 /* Calculate real DMA position we want */
815 return bound_pos + mod_dma_pos;
818 #define AMD_FIFO_SIZE 32
820 /* get the current DMA position with FIFO size correction */
821 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
823 struct snd_pcm_substream *substream = azx_dev->core.substream;
824 struct snd_pcm_runtime *runtime = substream->runtime;
825 unsigned int pos, delay;
827 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
831 runtime->delay = AMD_FIFO_SIZE;
832 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
833 if (azx_dev->insufficient) {
836 runtime->delay = bytes_to_frames(runtime, pos);
838 azx_dev->insufficient = 0;
842 /* correct the DMA position for capture stream */
843 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
845 pos += azx_dev->core.bufsize;
852 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
855 struct snd_pcm_substream *substream = azx_dev->core.substream;
857 /* just read back the calculated value in the above */
858 return substream->runtime->delay;
861 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
862 struct azx_dev *azx_dev)
864 return _snd_hdac_chip_readl(azx_bus(chip),
865 AZX_REG_VS_SDXDPIB_XBASE +
866 (AZX_REG_VS_SDXDPIB_XINTERVAL *
867 azx_dev->core.index));
870 /* get the current DMA position with correction on SKL+ chips */
871 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
873 /* DPIB register gives a more accurate position for playback */
874 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
875 return azx_skl_get_dpib_pos(chip, azx_dev);
877 /* For capture, we need to read posbuf, but it requires a delay
878 * for the possible boundary overlap; the read of DPIB fetches the
882 azx_skl_get_dpib_pos(chip, azx_dev);
883 return azx_get_pos_posbuf(chip, azx_dev);
886 static void azx_shutdown_chip(struct azx *chip)
889 azx_enter_link_reset(chip);
890 azx_clear_irq_pending(chip);
891 display_power(chip, false);
895 static DEFINE_MUTEX(card_list_lock);
896 static LIST_HEAD(card_list);
898 static void azx_add_card_list(struct azx *chip)
900 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
901 mutex_lock(&card_list_lock);
902 list_add(&hda->list, &card_list);
903 mutex_unlock(&card_list_lock);
906 static void azx_del_card_list(struct azx *chip)
908 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
909 mutex_lock(&card_list_lock);
910 list_del_init(&hda->list);
911 mutex_unlock(&card_list_lock);
914 /* trigger power-save check at writing parameter */
915 static int param_set_xint(const char *val, const struct kernel_param *kp)
917 struct hda_intel *hda;
919 int prev = power_save;
920 int ret = param_set_int(val, kp);
922 if (ret || prev == power_save)
925 mutex_lock(&card_list_lock);
926 list_for_each_entry(hda, &card_list, list) {
928 if (!hda->probe_continued || chip->disabled)
930 snd_hda_set_power_save(&chip->bus, power_save * 1000);
932 mutex_unlock(&card_list_lock);
939 static bool azx_is_pm_ready(struct snd_card *card)
942 struct hda_intel *hda;
946 chip = card->private_data;
947 hda = container_of(chip, struct hda_intel, chip);
948 if (chip->disabled || hda->init_failed || !chip->running)
953 static void __azx_runtime_resume(struct azx *chip)
955 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
956 struct hdac_bus *bus = azx_bus(chip);
957 struct hda_codec *codec;
960 display_power(chip, true);
961 if (hda->need_i915_power)
962 snd_hdac_i915_set_bclk(bus);
964 /* Read STATESTS before controller reset */
965 status = azx_readw(chip, STATESTS);
968 hda_intel_init_chip(chip, true);
970 /* Avoid codec resume if runtime resume is for system suspend */
971 if (!chip->pm_prepared) {
972 list_for_each_codec(codec, &chip->bus) {
973 if (codec->relaxed_resume)
976 if (codec->forced_resume || (status & (1 << codec->addr)))
977 pm_request_resume(hda_codec_dev(codec));
981 /* power down again for link-controlled chips */
982 if (!hda->need_i915_power)
983 display_power(chip, false);
986 #ifdef CONFIG_PM_SLEEP
987 static int azx_prepare(struct device *dev)
989 struct snd_card *card = dev_get_drvdata(dev);
992 if (!azx_is_pm_ready(card))
995 chip = card->private_data;
996 chip->pm_prepared = 1;
997 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
999 flush_work(&azx_bus(chip)->unsol_work);
1001 /* HDA controller always requires different WAKEEN for runtime suspend
1002 * and system suspend, so don't use direct-complete here.
1007 static void azx_complete(struct device *dev)
1009 struct snd_card *card = dev_get_drvdata(dev);
1012 if (!azx_is_pm_ready(card))
1015 chip = card->private_data;
1016 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1017 chip->pm_prepared = 0;
1020 static int azx_suspend(struct device *dev)
1022 struct snd_card *card = dev_get_drvdata(dev);
1024 struct hdac_bus *bus;
1026 if (!azx_is_pm_ready(card))
1029 chip = card->private_data;
1030 bus = azx_bus(chip);
1031 azx_shutdown_chip(chip);
1032 if (bus->irq >= 0) {
1033 free_irq(bus->irq, chip);
1035 chip->card->sync_irq = -1;
1039 pci_disable_msi(chip->pci);
1041 trace_azx_suspend(chip);
1045 static int azx_resume(struct device *dev)
1047 struct snd_card *card = dev_get_drvdata(dev);
1050 if (!azx_is_pm_ready(card))
1053 chip = card->private_data;
1055 if (pci_enable_msi(chip->pci) < 0)
1057 if (azx_acquire_irq(chip, 1) < 0)
1060 __azx_runtime_resume(chip);
1062 trace_azx_resume(chip);
1066 /* put codec down to D3 at hibernation for Intel SKL+;
1067 * otherwise BIOS may still access the codec and screw up the driver
1069 static int azx_freeze_noirq(struct device *dev)
1071 struct snd_card *card = dev_get_drvdata(dev);
1072 struct azx *chip = card->private_data;
1073 struct pci_dev *pci = to_pci_dev(dev);
1075 if (!azx_is_pm_ready(card))
1077 if (chip->driver_type == AZX_DRIVER_SKL)
1078 pci_set_power_state(pci, PCI_D3hot);
1083 static int azx_thaw_noirq(struct device *dev)
1085 struct snd_card *card = dev_get_drvdata(dev);
1086 struct azx *chip = card->private_data;
1087 struct pci_dev *pci = to_pci_dev(dev);
1089 if (!azx_is_pm_ready(card))
1091 if (chip->driver_type == AZX_DRIVER_SKL)
1092 pci_set_power_state(pci, PCI_D0);
1096 #endif /* CONFIG_PM_SLEEP */
1098 static int azx_runtime_suspend(struct device *dev)
1100 struct snd_card *card = dev_get_drvdata(dev);
1103 if (!azx_is_pm_ready(card))
1105 chip = card->private_data;
1107 /* enable controller wake up event */
1108 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1110 azx_shutdown_chip(chip);
1111 trace_azx_runtime_suspend(chip);
1115 static int azx_runtime_resume(struct device *dev)
1117 struct snd_card *card = dev_get_drvdata(dev);
1120 if (!azx_is_pm_ready(card))
1122 chip = card->private_data;
1123 __azx_runtime_resume(chip);
1125 /* disable controller Wake Up event*/
1126 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1128 trace_azx_runtime_resume(chip);
1132 static int azx_runtime_idle(struct device *dev)
1134 struct snd_card *card = dev_get_drvdata(dev);
1136 struct hda_intel *hda;
1141 chip = card->private_data;
1142 hda = container_of(chip, struct hda_intel, chip);
1143 if (chip->disabled || hda->init_failed)
1146 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1147 azx_bus(chip)->codec_powered || !chip->running)
1150 /* ELD notification gets broken when HD-audio bus is off */
1151 if (needs_eld_notify_link(chip))
1157 static const struct dev_pm_ops azx_pm = {
1158 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1159 #ifdef CONFIG_PM_SLEEP
1160 .prepare = azx_prepare,
1161 .complete = azx_complete,
1162 .freeze_noirq = azx_freeze_noirq,
1163 .thaw_noirq = azx_thaw_noirq,
1165 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1168 #define AZX_PM_OPS &azx_pm
1170 #define azx_add_card_list(chip) /* NOP */
1171 #define azx_del_card_list(chip) /* NOP */
1172 #define AZX_PM_OPS NULL
1173 #endif /* CONFIG_PM */
1176 static int azx_probe_continue(struct azx *chip);
1178 #ifdef SUPPORT_VGA_SWITCHEROO
1179 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1181 static void azx_vs_set_state(struct pci_dev *pci,
1182 enum vga_switcheroo_state state)
1184 struct snd_card *card = pci_get_drvdata(pci);
1185 struct azx *chip = card->private_data;
1186 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1187 struct hda_codec *codec;
1190 wait_for_completion(&hda->probe_wait);
1191 if (hda->init_failed)
1194 disabled = (state == VGA_SWITCHEROO_OFF);
1195 if (chip->disabled == disabled)
1198 if (!hda->probe_continued) {
1199 chip->disabled = disabled;
1201 dev_info(chip->card->dev,
1202 "Start delayed initialization\n");
1203 if (azx_probe_continue(chip) < 0)
1204 dev_err(chip->card->dev, "initialization error\n");
1207 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1208 disabled ? "Disabling" : "Enabling");
1210 list_for_each_codec(codec, &chip->bus) {
1211 pm_runtime_suspend(hda_codec_dev(codec));
1212 pm_runtime_disable(hda_codec_dev(codec));
1214 pm_runtime_suspend(card->dev);
1215 pm_runtime_disable(card->dev);
1216 /* when we get suspended by vga_switcheroo we end up in D3cold,
1217 * however we have no ACPI handle, so pci/acpi can't put us there,
1218 * put ourselves there */
1219 pci->current_state = PCI_D3cold;
1220 chip->disabled = true;
1221 if (snd_hda_lock_devices(&chip->bus))
1222 dev_warn(chip->card->dev,
1223 "Cannot lock devices!\n");
1225 snd_hda_unlock_devices(&chip->bus);
1226 chip->disabled = false;
1227 pm_runtime_enable(card->dev);
1228 list_for_each_codec(codec, &chip->bus) {
1229 pm_runtime_enable(hda_codec_dev(codec));
1230 pm_runtime_resume(hda_codec_dev(codec));
1236 static bool azx_vs_can_switch(struct pci_dev *pci)
1238 struct snd_card *card = pci_get_drvdata(pci);
1239 struct azx *chip = card->private_data;
1240 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1242 wait_for_completion(&hda->probe_wait);
1243 if (hda->init_failed)
1245 if (chip->disabled || !hda->probe_continued)
1247 if (snd_hda_lock_devices(&chip->bus))
1249 snd_hda_unlock_devices(&chip->bus);
1254 * The discrete GPU cannot power down unless the HDA controller runtime
1255 * suspends, so activate runtime PM on codecs even if power_save == 0.
1257 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1259 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1260 struct hda_codec *codec;
1262 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1263 list_for_each_codec(codec, &chip->bus)
1264 codec->auto_runtime_pm = 1;
1265 /* reset the power save setup */
1267 set_default_power_save(chip);
1271 static void azx_vs_gpu_bound(struct pci_dev *pci,
1272 enum vga_switcheroo_client_id client_id)
1274 struct snd_card *card = pci_get_drvdata(pci);
1275 struct azx *chip = card->private_data;
1277 if (client_id == VGA_SWITCHEROO_DIS)
1278 chip->bus.keep_power = 0;
1279 setup_vga_switcheroo_runtime_pm(chip);
1282 static void init_vga_switcheroo(struct azx *chip)
1284 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1285 struct pci_dev *p = get_bound_vga(chip->pci);
1286 struct pci_dev *parent;
1288 dev_info(chip->card->dev,
1289 "Handle vga_switcheroo audio client\n");
1290 hda->use_vga_switcheroo = 1;
1292 /* cleared in either gpu_bound op or codec probe, or when its
1293 * upstream port has _PR3 (i.e. dGPU).
1295 parent = pci_upstream_bridge(p);
1296 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1297 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1302 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1303 .set_gpu_state = azx_vs_set_state,
1304 .can_switch = azx_vs_can_switch,
1305 .gpu_bound = azx_vs_gpu_bound,
1308 static int register_vga_switcheroo(struct azx *chip)
1310 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1314 if (!hda->use_vga_switcheroo)
1317 p = get_bound_vga(chip->pci);
1318 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1323 hda->vga_switcheroo_registered = 1;
1328 #define init_vga_switcheroo(chip) /* NOP */
1329 #define register_vga_switcheroo(chip) 0
1330 #define check_hdmi_disabled(pci) false
1331 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1332 #endif /* SUPPORT_VGA_SWITCHER */
1337 static void azx_free(struct azx *chip)
1339 struct pci_dev *pci = chip->pci;
1340 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1341 struct hdac_bus *bus = azx_bus(chip);
1346 if (azx_has_pm_runtime(chip) && chip->running)
1347 pm_runtime_get_noresume(&pci->dev);
1350 azx_del_card_list(chip);
1352 hda->init_failed = 1; /* to be sure */
1353 complete_all(&hda->probe_wait);
1355 if (use_vga_switcheroo(hda)) {
1356 if (chip->disabled && hda->probe_continued)
1357 snd_hda_unlock_devices(&chip->bus);
1358 if (hda->vga_switcheroo_registered)
1359 vga_switcheroo_unregister_client(chip->pci);
1362 if (bus->chip_init) {
1363 azx_clear_irq_pending(chip);
1364 azx_stop_all_streams(chip);
1365 azx_stop_chip(chip);
1369 free_irq(bus->irq, (void*)chip);
1371 azx_free_stream_pages(chip);
1372 azx_free_streams(chip);
1373 snd_hdac_bus_exit(bus);
1375 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1376 release_firmware(chip->fw);
1378 display_power(chip, false);
1380 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1381 snd_hdac_i915_exit(bus);
1386 static int azx_dev_disconnect(struct snd_device *device)
1388 struct azx *chip = device->device_data;
1389 struct hdac_bus *bus = azx_bus(chip);
1391 chip->bus.shutdown = 1;
1392 cancel_work_sync(&bus->unsol_work);
1397 static int azx_dev_free(struct snd_device *device)
1399 azx_free(device->device_data);
1403 #ifdef SUPPORT_VGA_SWITCHEROO
1405 /* ATPX is in the integrated GPU's namespace */
1406 static bool atpx_present(void)
1408 struct pci_dev *pdev = NULL;
1409 acpi_handle dhandle, atpx_handle;
1412 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1413 dhandle = ACPI_HANDLE(&pdev->dev);
1415 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1416 if (ACPI_SUCCESS(status)) {
1422 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1423 dhandle = ACPI_HANDLE(&pdev->dev);
1425 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1426 if (ACPI_SUCCESS(status)) {
1435 static bool atpx_present(void)
1442 * Check of disabled HDMI controller by vga_switcheroo
1444 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1448 /* check only discrete GPU */
1449 switch (pci->vendor) {
1450 case PCI_VENDOR_ID_ATI:
1451 case PCI_VENDOR_ID_AMD:
1452 if (pci->devfn == 1) {
1453 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1454 pci->bus->number, 0);
1456 /* ATPX is in the integrated GPU's ACPI namespace
1457 * rather than the dGPU's namespace. However,
1458 * the dGPU is the one who is involved in
1461 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1468 case PCI_VENDOR_ID_NVIDIA:
1469 if (pci->devfn == 1) {
1470 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1471 pci->bus->number, 0);
1473 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1483 static bool check_hdmi_disabled(struct pci_dev *pci)
1485 bool vga_inactive = false;
1486 struct pci_dev *p = get_bound_vga(pci);
1489 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1490 vga_inactive = true;
1493 return vga_inactive;
1495 #endif /* SUPPORT_VGA_SWITCHEROO */
1498 * allow/deny-listing for position_fix
1500 static const struct snd_pci_quirk position_fix_list[] = {
1501 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1502 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1503 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1504 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1505 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1506 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1507 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1508 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1509 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1510 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1511 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1512 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1518 static int check_position_fix(struct azx *chip, int fix)
1520 const struct snd_pci_quirk *q;
1525 case POS_FIX_POSBUF:
1526 case POS_FIX_VIACOMBO:
1533 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1535 dev_info(chip->card->dev,
1536 "position_fix set to %d for device %04x:%04x\n",
1537 q->value, q->subvendor, q->subdevice);
1541 /* Check VIA/ATI HD Audio Controller exist */
1542 if (chip->driver_type == AZX_DRIVER_VIA) {
1543 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1544 return POS_FIX_VIACOMBO;
1546 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1547 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1548 return POS_FIX_FIFO;
1550 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1551 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1552 return POS_FIX_LPIB;
1554 if (chip->driver_type == AZX_DRIVER_SKL) {
1555 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1558 return POS_FIX_AUTO;
1561 static void assign_position_fix(struct azx *chip, int fix)
1563 static const azx_get_pos_callback_t callbacks[] = {
1564 [POS_FIX_AUTO] = NULL,
1565 [POS_FIX_LPIB] = azx_get_pos_lpib,
1566 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1567 [POS_FIX_VIACOMBO] = azx_via_get_position,
1568 [POS_FIX_COMBO] = azx_get_pos_lpib,
1569 [POS_FIX_SKL] = azx_get_pos_skl,
1570 [POS_FIX_FIFO] = azx_get_pos_fifo,
1573 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1575 /* combo mode uses LPIB only for playback */
1576 if (fix == POS_FIX_COMBO)
1577 chip->get_position[1] = NULL;
1579 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1580 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1581 chip->get_delay[0] = chip->get_delay[1] =
1582 azx_get_delay_from_lpib;
1585 if (fix == POS_FIX_FIFO)
1586 chip->get_delay[0] = chip->get_delay[1] =
1587 azx_get_delay_from_fifo;
1591 * deny-lists for probe_mask
1593 static const struct snd_pci_quirk probe_mask_list[] = {
1594 /* Thinkpad often breaks the controller communication when accessing
1595 * to the non-working (or non-existing) modem codec slot.
1597 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1598 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1599 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1601 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1602 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1603 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1604 /* forced codec slots */
1605 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1606 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1607 /* WinFast VP200 H (Teradici) user reported broken communication */
1608 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1612 #define AZX_FORCE_CODEC_MASK 0x100
1614 static void check_probe_mask(struct azx *chip, int dev)
1616 const struct snd_pci_quirk *q;
1618 chip->codec_probe_mask = probe_mask[dev];
1619 if (chip->codec_probe_mask == -1) {
1620 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1622 dev_info(chip->card->dev,
1623 "probe_mask set to 0x%x for device %04x:%04x\n",
1624 q->value, q->subvendor, q->subdevice);
1625 chip->codec_probe_mask = q->value;
1629 /* check forced option */
1630 if (chip->codec_probe_mask != -1 &&
1631 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1632 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1633 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1634 (int)azx_bus(chip)->codec_mask);
1639 * allow/deny-list for enable_msi
1641 static const struct snd_pci_quirk msi_deny_list[] = {
1642 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1643 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1644 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1645 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1646 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1647 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1648 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1649 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1650 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1651 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1655 static void check_msi(struct azx *chip)
1657 const struct snd_pci_quirk *q;
1659 if (enable_msi >= 0) {
1660 chip->msi = !!enable_msi;
1663 chip->msi = 1; /* enable MSI as default */
1664 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1666 dev_info(chip->card->dev,
1667 "msi for device %04x:%04x set to %d\n",
1668 q->subvendor, q->subdevice, q->value);
1669 chip->msi = q->value;
1673 /* NVidia chipsets seem to cause troubles with MSI */
1674 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1675 dev_info(chip->card->dev, "Disabling MSI\n");
1680 /* check the snoop mode availability */
1681 static void azx_check_snoop_available(struct azx *chip)
1683 int snoop = hda_snoop;
1686 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1687 snoop ? "snoop" : "non-snoop");
1688 chip->snoop = snoop;
1689 chip->uc_buffer = !snoop;
1694 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1695 chip->driver_type == AZX_DRIVER_VIA) {
1696 /* force to non-snoop mode for a new VIA controller
1700 pci_read_config_byte(chip->pci, 0x42, &val);
1701 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1702 chip->pci->revision == 0x20))
1706 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1709 chip->snoop = snoop;
1711 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1712 /* C-Media requires non-cached pages only for CORB/RIRB */
1713 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1714 chip->uc_buffer = true;
1718 static void azx_probe_work(struct work_struct *work)
1720 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1721 azx_probe_continue(&hda->chip);
1724 static int default_bdl_pos_adj(struct azx *chip)
1726 /* some exceptions: Atoms seem problematic with value 1 */
1727 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1728 switch (chip->pci->device) {
1729 case 0x0f04: /* Baytrail */
1730 case 0x2284: /* Braswell */
1735 switch (chip->driver_type) {
1736 case AZX_DRIVER_ICH:
1737 case AZX_DRIVER_PCH:
1747 static const struct hda_controller_ops pci_hda_ops;
1749 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1750 int dev, unsigned int driver_caps,
1753 static const struct snd_device_ops ops = {
1754 .dev_disconnect = azx_dev_disconnect,
1755 .dev_free = azx_dev_free,
1757 struct hda_intel *hda;
1763 err = pcim_enable_device(pci);
1767 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1772 mutex_init(&chip->open_mutex);
1775 chip->ops = &pci_hda_ops;
1776 chip->driver_caps = driver_caps;
1777 chip->driver_type = driver_caps & 0xff;
1779 chip->dev_index = dev;
1780 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1781 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1782 INIT_LIST_HEAD(&chip->pcm_list);
1783 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1784 INIT_LIST_HEAD(&hda->list);
1785 init_vga_switcheroo(chip);
1786 init_completion(&hda->probe_wait);
1788 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1790 check_probe_mask(chip, dev);
1792 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1793 chip->fallback_to_single_cmd = 1;
1794 else /* explicitly set to single_cmd or not */
1795 chip->single_cmd = single_cmd;
1797 azx_check_snoop_available(chip);
1799 if (bdl_pos_adj[dev] < 0)
1800 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1802 chip->bdl_pos_adj = bdl_pos_adj[dev];
1804 err = azx_bus_init(chip, model[dev]);
1808 /* use the non-cached pages in non-snoop mode */
1809 if (!azx_snoop(chip))
1810 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC;
1812 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1813 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1814 chip->bus.core.needs_damn_long_delay = 1;
1817 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1819 dev_err(card->dev, "Error creating device [card]!\n");
1824 /* continue probing in work context as may trigger request module */
1825 INIT_WORK(&hda->probe_work, azx_probe_work);
1832 static int azx_first_init(struct azx *chip)
1834 int dev = chip->dev_index;
1835 struct pci_dev *pci = chip->pci;
1836 struct snd_card *card = chip->card;
1837 struct hdac_bus *bus = azx_bus(chip);
1839 unsigned short gcap;
1840 unsigned int dma_bits = 64;
1842 #if BITS_PER_LONG != 64
1843 /* Fix up base address on ULI M5461 */
1844 if (chip->driver_type == AZX_DRIVER_ULI) {
1846 pci_read_config_word(pci, 0x40, &tmp3);
1847 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1848 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1852 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
1856 bus->addr = pci_resource_start(pci, 0);
1857 bus->remap_addr = pcim_iomap_table(pci)[0];
1859 if (chip->driver_type == AZX_DRIVER_SKL)
1860 snd_hdac_bus_parse_capabilities(bus);
1863 * Some Intel CPUs has always running timer (ART) feature and
1864 * controller may have Global time sync reporting capability, so
1865 * check both of these before declaring synchronized time reporting
1866 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1868 chip->gts_present = false;
1871 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1872 chip->gts_present = true;
1876 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1877 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1878 pci->no_64bit_msi = true;
1880 if (pci_enable_msi(pci) < 0)
1884 pci_set_master(pci);
1886 gcap = azx_readw(chip, GCAP);
1887 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1889 /* AMD devices support 40 or 48bit DMA, take the safe one */
1890 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1893 /* disable SB600 64bit support for safety */
1894 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1895 struct pci_dev *p_smbus;
1897 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1898 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1901 if (p_smbus->revision < 0x30)
1902 gcap &= ~AZX_GCAP_64OK;
1903 pci_dev_put(p_smbus);
1907 /* NVidia hardware normally only supports up to 40 bits of DMA */
1908 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1911 /* disable 64bit DMA address on some devices */
1912 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1913 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1914 gcap &= ~AZX_GCAP_64OK;
1917 /* disable buffer size rounding to 128-byte multiples if supported */
1918 if (align_buffer_size >= 0)
1919 chip->align_buffer_size = !!align_buffer_size;
1921 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1922 chip->align_buffer_size = 0;
1924 chip->align_buffer_size = 1;
1927 /* allow 64bit DMA address if supported by H/W */
1928 if (!(gcap & AZX_GCAP_64OK))
1930 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1931 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1933 /* read number of streams from GCAP register instead of using
1936 chip->capture_streams = (gcap >> 8) & 0x0f;
1937 chip->playback_streams = (gcap >> 12) & 0x0f;
1938 if (!chip->playback_streams && !chip->capture_streams) {
1939 /* gcap didn't give any info, switching to old method */
1941 switch (chip->driver_type) {
1942 case AZX_DRIVER_ULI:
1943 chip->playback_streams = ULI_NUM_PLAYBACK;
1944 chip->capture_streams = ULI_NUM_CAPTURE;
1946 case AZX_DRIVER_ATIHDMI:
1947 case AZX_DRIVER_ATIHDMI_NS:
1948 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1949 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1951 case AZX_DRIVER_GENERIC:
1953 chip->playback_streams = ICH6_NUM_PLAYBACK;
1954 chip->capture_streams = ICH6_NUM_CAPTURE;
1958 chip->capture_index_offset = 0;
1959 chip->playback_index_offset = chip->capture_streams;
1960 chip->num_streams = chip->playback_streams + chip->capture_streams;
1962 /* sanity check for the SDxCTL.STRM field overflow */
1963 if (chip->num_streams > 15 &&
1964 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1965 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1966 "forcing separate stream tags", chip->num_streams);
1967 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1970 /* initialize streams */
1971 err = azx_init_streams(chip);
1975 err = azx_alloc_stream_pages(chip);
1979 /* initialize chip */
1982 snd_hdac_i915_set_bclk(bus);
1984 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1986 /* codec detection */
1987 if (!azx_bus(chip)->codec_mask) {
1988 dev_err(card->dev, "no codecs found!\n");
1989 /* keep running the rest for the runtime PM */
1992 if (azx_acquire_irq(chip, 0) < 0)
1995 strcpy(card->driver, "HDA-Intel");
1996 strscpy(card->shortname, driver_short_names[chip->driver_type],
1997 sizeof(card->shortname));
1998 snprintf(card->longname, sizeof(card->longname),
1999 "%s at 0x%lx irq %i",
2000 card->shortname, bus->addr, bus->irq);
2005 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2006 /* callback from request_firmware_nowait() */
2007 static void azx_firmware_cb(const struct firmware *fw, void *context)
2009 struct snd_card *card = context;
2010 struct azx *chip = card->private_data;
2015 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2016 if (!chip->disabled) {
2017 /* continue probing */
2018 azx_probe_continue(chip);
2023 static int disable_msi_reset_irq(struct azx *chip)
2025 struct hdac_bus *bus = azx_bus(chip);
2028 free_irq(bus->irq, chip);
2030 chip->card->sync_irq = -1;
2031 pci_disable_msi(chip->pci);
2033 err = azx_acquire_irq(chip, 1);
2040 /* Denylist for skipping the whole probe:
2041 * some HD-audio PCI entries are exposed without any codecs, and such devices
2042 * should be ignored from the beginning.
2044 static const struct pci_device_id driver_denylist[] = {
2045 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2046 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2047 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2051 static const struct hda_controller_ops pci_hda_ops = {
2052 .disable_msi_reset_irq = disable_msi_reset_irq,
2053 .position_check = azx_position_check,
2056 static int azx_probe(struct pci_dev *pci,
2057 const struct pci_device_id *pci_id)
2060 struct snd_card *card;
2061 struct hda_intel *hda;
2063 bool schedule_probe;
2066 if (pci_match_id(driver_denylist, pci)) {
2067 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2071 if (dev >= SNDRV_CARDS)
2079 * stop probe if another Intel's DSP driver should be activated
2082 err = snd_intel_dsp_driver_probe(pci);
2083 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2084 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2088 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2091 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2094 dev_err(&pci->dev, "Error creating card!\n");
2098 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2101 card->private_data = chip;
2102 hda = container_of(chip, struct hda_intel, chip);
2104 pci_set_drvdata(pci, card);
2106 err = register_vga_switcheroo(chip);
2108 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2112 if (check_hdmi_disabled(pci)) {
2113 dev_info(card->dev, "VGA controller is disabled\n");
2114 dev_info(card->dev, "Delaying initialization\n");
2115 chip->disabled = true;
2118 schedule_probe = !chip->disabled;
2120 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2121 if (patch[dev] && *patch[dev]) {
2122 dev_info(card->dev, "Applying patch firmware '%s'\n",
2124 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2125 &pci->dev, GFP_KERNEL, card,
2129 schedule_probe = false; /* continued in azx_firmware_cb() */
2131 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2133 #ifndef CONFIG_SND_HDA_I915
2134 if (CONTROLLER_IN_GPU(pci))
2135 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2139 schedule_work(&hda->probe_work);
2143 complete_all(&hda->probe_wait);
2147 snd_card_free(card);
2152 /* On some boards setting power_save to a non 0 value leads to clicking /
2153 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2154 * figure out how to avoid these sounds, but that is not always feasible.
2155 * So we keep a list of devices where we disable powersaving as its known
2156 * to causes problems on these devices.
2158 static const struct snd_pci_quirk power_save_denylist[] = {
2159 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2160 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2161 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2162 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2163 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2164 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2165 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2166 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2167 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2168 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2169 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2170 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2171 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2172 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2173 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2174 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2175 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2176 /* https://bugs.launchpad.net/bugs/1821663 */
2177 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2178 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2179 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2180 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2181 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2182 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2183 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2184 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2185 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2186 /* https://bugs.launchpad.net/bugs/1821663 */
2187 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2190 #endif /* CONFIG_PM */
2192 static void set_default_power_save(struct azx *chip)
2194 int val = power_save;
2198 const struct snd_pci_quirk *q;
2200 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2202 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2203 q->subvendor, q->subdevice);
2207 #endif /* CONFIG_PM */
2208 snd_hda_set_power_save(&chip->bus, val * 1000);
2211 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2212 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2213 [AZX_DRIVER_NVIDIA] = 8,
2214 [AZX_DRIVER_TERA] = 1,
2217 static int azx_probe_continue(struct azx *chip)
2219 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2220 struct hdac_bus *bus = azx_bus(chip);
2221 struct pci_dev *pci = chip->pci;
2222 int dev = chip->dev_index;
2225 to_hda_bus(bus)->bus_probing = 1;
2226 hda->probe_continued = 1;
2228 /* bind with i915 if needed */
2229 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2230 err = snd_hdac_i915_init(bus);
2232 /* if the controller is bound only with HDMI/DP
2233 * (for HSW and BDW), we need to abort the probe;
2234 * for other chips, still continue probing as other
2235 * codecs can be on the same link.
2237 if (CONTROLLER_IN_GPU(pci)) {
2238 dev_err(chip->card->dev,
2239 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2242 /* don't bother any longer */
2243 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2247 /* HSW/BDW controllers need this power */
2248 if (CONTROLLER_IN_GPU(pci))
2249 hda->need_i915_power = true;
2252 /* Request display power well for the HDA controller or codec. For
2253 * Haswell/Broadwell, both the display HDA controller and codec need
2254 * this power. For other platforms, like Baytrail/Braswell, only the
2255 * display codec needs the power and it can be released after probe.
2257 display_power(chip, true);
2259 err = azx_first_init(chip);
2263 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2264 chip->beep_mode = beep_mode[dev];
2267 /* create codec instances */
2268 if (bus->codec_mask) {
2269 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2274 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2276 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2281 release_firmware(chip->fw); /* no longer needed */
2286 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2287 err = azx_codec_configure(chip);
2292 err = snd_card_register(chip->card);
2296 setup_vga_switcheroo_runtime_pm(chip);
2299 azx_add_card_list(chip);
2301 set_default_power_save(chip);
2303 if (azx_has_pm_runtime(chip)) {
2304 pm_runtime_use_autosuspend(&pci->dev);
2305 pm_runtime_allow(&pci->dev);
2306 pm_runtime_put_autosuspend(&pci->dev);
2315 if (!hda->need_i915_power)
2316 display_power(chip, false);
2317 complete_all(&hda->probe_wait);
2318 to_hda_bus(bus)->bus_probing = 0;
2322 static void azx_remove(struct pci_dev *pci)
2324 struct snd_card *card = pci_get_drvdata(pci);
2326 struct hda_intel *hda;
2329 /* cancel the pending probing work */
2330 chip = card->private_data;
2331 hda = container_of(chip, struct hda_intel, chip);
2332 /* FIXME: below is an ugly workaround.
2333 * Both device_release_driver() and driver_probe_device()
2334 * take *both* the device's and its parent's lock before
2335 * calling the remove() and probe() callbacks. The codec
2336 * probe takes the locks of both the codec itself and its
2337 * parent, i.e. the PCI controller dev. Meanwhile, when
2338 * the PCI controller is unbound, it takes its lock, too
2339 * ==> ouch, a deadlock!
2340 * As a workaround, we unlock temporarily here the controller
2341 * device during cancel_work_sync() call.
2343 device_unlock(&pci->dev);
2344 cancel_work_sync(&hda->probe_work);
2345 device_lock(&pci->dev);
2347 snd_card_free(card);
2351 static void azx_shutdown(struct pci_dev *pci)
2353 struct snd_card *card = pci_get_drvdata(pci);
2358 chip = card->private_data;
2359 if (chip && chip->running)
2360 azx_shutdown_chip(chip);
2364 static const struct pci_device_id azx_ids[] = {
2366 { PCI_DEVICE(0x8086, 0x1c20),
2367 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2369 { PCI_DEVICE(0x8086, 0x1d20),
2370 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2372 { PCI_DEVICE(0x8086, 0x1e20),
2373 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2375 { PCI_DEVICE(0x8086, 0x8c20),
2376 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2378 { PCI_DEVICE(0x8086, 0x8ca0),
2379 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2381 { PCI_DEVICE(0x8086, 0x8d20),
2382 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2383 { PCI_DEVICE(0x8086, 0x8d21),
2384 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2386 { PCI_DEVICE(0x8086, 0xa1f0),
2387 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2388 { PCI_DEVICE(0x8086, 0xa270),
2389 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2391 { PCI_DEVICE(0x8086, 0x9c20),
2392 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2394 { PCI_DEVICE(0x8086, 0x9c21),
2395 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2396 /* Wildcat Point-LP */
2397 { PCI_DEVICE(0x8086, 0x9ca0),
2398 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2400 { PCI_DEVICE(0x8086, 0xa170),
2401 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2402 /* Sunrise Point-LP */
2403 { PCI_DEVICE(0x8086, 0x9d70),
2404 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2406 { PCI_DEVICE(0x8086, 0xa171),
2407 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2409 { PCI_DEVICE(0x8086, 0x9d71),
2410 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2412 { PCI_DEVICE(0x8086, 0xa2f0),
2413 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2415 { PCI_DEVICE(0x8086, 0xa348),
2416 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2418 { PCI_DEVICE(0x8086, 0x9dc8),
2419 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2421 { PCI_DEVICE(0x8086, 0x02C8),
2422 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2424 { PCI_DEVICE(0x8086, 0x06C8),
2425 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2426 { PCI_DEVICE(0x8086, 0xf1c8),
2427 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2429 { PCI_DEVICE(0x8086, 0xa3f0),
2430 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2432 { PCI_DEVICE(0x8086, 0xf0c8),
2433 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2435 { PCI_DEVICE(0x8086, 0x34c8),
2436 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2438 { PCI_DEVICE(0x8086, 0x3dc8),
2439 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2441 { PCI_DEVICE(0x8086, 0x38c8),
2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2443 { PCI_DEVICE(0x8086, 0x4dc8),
2444 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2446 { PCI_DEVICE(0x8086, 0xa0c8),
2447 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2449 { PCI_DEVICE(0x8086, 0x43c8),
2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2452 { PCI_DEVICE(0x8086, 0x490d),
2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2455 { PCI_DEVICE(0x8086, 0x7ad0),
2456 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2458 { PCI_DEVICE(0x8086, 0x51c8),
2459 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2461 { PCI_DEVICE(0x8086, 0x51cc),
2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2464 { PCI_DEVICE(0x8086, 0x4b55),
2465 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2466 { PCI_DEVICE(0x8086, 0x4b58),
2467 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2468 /* Broxton-P(Apollolake) */
2469 { PCI_DEVICE(0x8086, 0x5a98),
2470 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2472 { PCI_DEVICE(0x8086, 0x1a98),
2473 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2475 { PCI_DEVICE(0x8086, 0x3198),
2476 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2478 { PCI_DEVICE(0x8086, 0x0a0c),
2479 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2480 { PCI_DEVICE(0x8086, 0x0c0c),
2481 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2482 { PCI_DEVICE(0x8086, 0x0d0c),
2483 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2485 { PCI_DEVICE(0x8086, 0x160c),
2486 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2488 { PCI_DEVICE(0x8086, 0x3b56),
2489 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2491 { PCI_DEVICE(0x8086, 0x811b),
2492 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2494 { PCI_DEVICE(0x8086, 0x080a),
2495 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2497 { PCI_DEVICE(0x8086, 0x0f04),
2498 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2500 { PCI_DEVICE(0x8086, 0x2284),
2501 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2503 { PCI_DEVICE(0x8086, 0x2668),
2504 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2506 { PCI_DEVICE(0x8086, 0x27d8),
2507 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2509 { PCI_DEVICE(0x8086, 0x269a),
2510 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2512 { PCI_DEVICE(0x8086, 0x284b),
2513 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2515 { PCI_DEVICE(0x8086, 0x293e),
2516 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2518 { PCI_DEVICE(0x8086, 0x293f),
2519 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2521 { PCI_DEVICE(0x8086, 0x3a3e),
2522 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2524 { PCI_DEVICE(0x8086, 0x3a6e),
2525 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2527 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2528 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2529 .class_mask = 0xffffff,
2530 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2531 /* ATI SB 450/600/700/800/900 */
2532 { PCI_DEVICE(0x1002, 0x437b),
2533 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2534 { PCI_DEVICE(0x1002, 0x4383),
2535 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2537 { PCI_DEVICE(0x1022, 0x780d),
2538 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2539 /* AMD, X370 & co */
2540 { PCI_DEVICE(0x1022, 0x1457),
2541 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2542 /* AMD, X570 & co */
2543 { PCI_DEVICE(0x1022, 0x1487),
2544 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2546 { PCI_DEVICE(0x1022, 0x157a),
2547 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2548 AZX_DCAPS_PM_RUNTIME },
2550 { PCI_DEVICE(0x1022, 0x15e3),
2551 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2553 { PCI_DEVICE(0x1002, 0x0002),
2554 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2555 AZX_DCAPS_PM_RUNTIME },
2556 { PCI_DEVICE(0x1002, 0x1308),
2557 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558 { PCI_DEVICE(0x1002, 0x157a),
2559 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2560 { PCI_DEVICE(0x1002, 0x15b3),
2561 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2562 { PCI_DEVICE(0x1002, 0x793b),
2563 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2564 { PCI_DEVICE(0x1002, 0x7919),
2565 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2566 { PCI_DEVICE(0x1002, 0x960f),
2567 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2568 { PCI_DEVICE(0x1002, 0x970f),
2569 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2570 { PCI_DEVICE(0x1002, 0x9840),
2571 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2572 { PCI_DEVICE(0x1002, 0xaa00),
2573 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2574 { PCI_DEVICE(0x1002, 0xaa08),
2575 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2576 { PCI_DEVICE(0x1002, 0xaa10),
2577 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2578 { PCI_DEVICE(0x1002, 0xaa18),
2579 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2580 { PCI_DEVICE(0x1002, 0xaa20),
2581 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2582 { PCI_DEVICE(0x1002, 0xaa28),
2583 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2584 { PCI_DEVICE(0x1002, 0xaa30),
2585 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2586 { PCI_DEVICE(0x1002, 0xaa38),
2587 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2588 { PCI_DEVICE(0x1002, 0xaa40),
2589 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2590 { PCI_DEVICE(0x1002, 0xaa48),
2591 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2592 { PCI_DEVICE(0x1002, 0xaa50),
2593 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2594 { PCI_DEVICE(0x1002, 0xaa58),
2595 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2596 { PCI_DEVICE(0x1002, 0xaa60),
2597 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2598 { PCI_DEVICE(0x1002, 0xaa68),
2599 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2600 { PCI_DEVICE(0x1002, 0xaa80),
2601 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2602 { PCI_DEVICE(0x1002, 0xaa88),
2603 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2604 { PCI_DEVICE(0x1002, 0xaa90),
2605 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2606 { PCI_DEVICE(0x1002, 0xaa98),
2607 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2608 { PCI_DEVICE(0x1002, 0x9902),
2609 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2610 { PCI_DEVICE(0x1002, 0xaaa0),
2611 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2612 { PCI_DEVICE(0x1002, 0xaaa8),
2613 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2614 { PCI_DEVICE(0x1002, 0xaab0),
2615 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2616 { PCI_DEVICE(0x1002, 0xaac0),
2617 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2618 AZX_DCAPS_PM_RUNTIME },
2619 { PCI_DEVICE(0x1002, 0xaac8),
2620 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2621 AZX_DCAPS_PM_RUNTIME },
2622 { PCI_DEVICE(0x1002, 0xaad8),
2623 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2624 AZX_DCAPS_PM_RUNTIME },
2625 { PCI_DEVICE(0x1002, 0xaae0),
2626 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2627 AZX_DCAPS_PM_RUNTIME },
2628 { PCI_DEVICE(0x1002, 0xaae8),
2629 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2630 AZX_DCAPS_PM_RUNTIME },
2631 { PCI_DEVICE(0x1002, 0xaaf0),
2632 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2633 AZX_DCAPS_PM_RUNTIME },
2634 { PCI_DEVICE(0x1002, 0xaaf8),
2635 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2636 AZX_DCAPS_PM_RUNTIME },
2637 { PCI_DEVICE(0x1002, 0xab00),
2638 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2639 AZX_DCAPS_PM_RUNTIME },
2640 { PCI_DEVICE(0x1002, 0xab08),
2641 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2642 AZX_DCAPS_PM_RUNTIME },
2643 { PCI_DEVICE(0x1002, 0xab10),
2644 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2645 AZX_DCAPS_PM_RUNTIME },
2646 { PCI_DEVICE(0x1002, 0xab18),
2647 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2648 AZX_DCAPS_PM_RUNTIME },
2649 { PCI_DEVICE(0x1002, 0xab20),
2650 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2651 AZX_DCAPS_PM_RUNTIME },
2652 { PCI_DEVICE(0x1002, 0xab28),
2653 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2654 AZX_DCAPS_PM_RUNTIME },
2655 { PCI_DEVICE(0x1002, 0xab38),
2656 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2657 AZX_DCAPS_PM_RUNTIME },
2658 /* VIA VT8251/VT8237A */
2659 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2660 /* VIA GFX VT7122/VX900 */
2661 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2662 /* VIA GFX VT6122/VX11 */
2663 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2665 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2667 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2669 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2670 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2671 .class_mask = 0xffffff,
2672 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2674 { PCI_DEVICE(0x6549, 0x1200),
2675 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2676 { PCI_DEVICE(0x6549, 0x2200),
2677 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2678 /* Creative X-Fi (CA0110-IBG) */
2680 { PCI_DEVICE(0x1102, 0x0010),
2681 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2682 { PCI_DEVICE(0x1102, 0x0012),
2683 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2684 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2685 /* the following entry conflicts with snd-ctxfi driver,
2686 * as ctxfi driver mutates from HD-audio to native mode with
2687 * a special command sequence.
2689 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2690 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2691 .class_mask = 0xffffff,
2692 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2693 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2695 /* this entry seems still valid -- i.e. without emu20kx chip */
2696 { PCI_DEVICE(0x1102, 0x0009),
2697 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2698 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2701 { PCI_DEVICE(0x13f6, 0x5011),
2702 .driver_data = AZX_DRIVER_CMEDIA |
2703 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2705 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2706 /* VMware HDAudio */
2707 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2708 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2709 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2710 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2711 .class_mask = 0xffffff,
2712 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2713 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2714 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2715 .class_mask = 0xffffff,
2716 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2718 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2721 MODULE_DEVICE_TABLE(pci, azx_ids);
2723 /* pci_driver definition */
2724 static struct pci_driver azx_driver = {
2725 .name = KBUILD_MODNAME,
2726 .id_table = azx_ids,
2728 .remove = azx_remove,
2729 .shutdown = azx_shutdown,
2735 module_pci_driver(azx_driver);