sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pgtable.h>
  40
  41 #ifdef CONFIG_X86
  42 /* for snoop control */
  43 #include <asm/set_memory.h>
  44 #include <asm/cpufeature.h>
  45 #endif
  46 #include <sound/core.h>
  47 #include <sound/initval.h>
  48 #include <sound/hdaudio.h>
  49 #include <sound/hda_i915.h>
  50 #include <sound/intel-dsp-config.h>
  51 #include <linux/vgaarb.h>
  52 #include <linux/vga_switcheroo.h>
  53 #include <linux/firmware.h>
  54 #include <sound/hda_codec.h>
  55 #include "hda_controller.h"
  56 #include "hda_intel.h"
  57
  58 #define CREATE_TRACE_POINTS
  59 #include "hda_intel_trace.h"
  60
  61 /* position fix mode */
  62 enum {
  63         POS_FIX_AUTO,
  64         POS_FIX_LPIB,
  65         POS_FIX_POSBUF,
  66         POS_FIX_VIACOMBO,
  67         POS_FIX_COMBO,
  68         POS_FIX_SKL,
  69         POS_FIX_FIFO,
  70 };
  71
  72 /* Defines for ATI HD Audio support in SB450 south bridge */
  73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  75
  76 /* Defines for Nvidia HDA support */
  77 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  78 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  79 #define NVIDIA_HDA_ISTRM_COH          0x4d
  80 #define NVIDIA_HDA_OSTRM_COH          0x4c
  81 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  82
  83 /* Defines for Intel SCH HDA snoop control */
  84 #define INTEL_HDA_CGCTL  0x48
  85 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  86 #define INTEL_SCH_HDA_DEVC      0x78
  87 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  88
  89 /* max number of SDs */
  90 /* ICH, ATI and VIA have 4 playback and 4 capture */
  91 #define ICH6_NUM_CAPTURE        4
  92 #define ICH6_NUM_PLAYBACK       4
  93
  94 /* ULI has 6 playback and 5 capture */
  95 #define ULI_NUM_CAPTURE         5
  96 #define ULI_NUM_PLAYBACK        6
  97
  98 /* ATI HDMI may have up to 8 playbacks and 0 capture */
  99 #define ATIHDMI_NUM_CAPTURE     0
 100 #define ATIHDMI_NUM_PLAYBACK    8
 101
 102
 103 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 104 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 105 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 106 static char *model[SNDRV_CARDS];
 107 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 108 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 109 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 110 static int probe_only[SNDRV_CARDS];
 111 static int jackpoll_ms[SNDRV_CARDS];
 112 static int single_cmd = -1;
 113 static int enable_msi = -1;
 114 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 115 static char *patch[SNDRV_CARDS];
 116 #endif
 117 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 118 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 119                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 120 #endif
 121 static bool dmic_detect = 1;
 122 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0;
 123
 124 module_param_array(index, int, NULL, 0444);
 125 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 126 module_param_array(id, charp, NULL, 0444);
 127 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 128 module_param_array(enable, bool, NULL, 0444);
 129 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 130 module_param_array(model, charp, NULL, 0444);
 131 MODULE_PARM_DESC(model, "Use the given board model.");
 132 module_param_array(position_fix, int, NULL, 0444);
 133 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 134                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 135 module_param_array(bdl_pos_adj, int, NULL, 0644);
 136 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 137 module_param_array(probe_mask, int, NULL, 0444);
 138 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 139 module_param_array(probe_only, int, NULL, 0444);
 140 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 141 module_param_array(jackpoll_ms, int, NULL, 0444);
 142 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 143 module_param(single_cmd, bint, 0444);
 144 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 145                  "(for debugging only).");
 146 module_param(enable_msi, bint, 0444);
 147 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 148 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 149 module_param_array(patch, charp, NULL, 0444);
 150 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 151 #endif
 152 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 153 module_param_array(beep_mode, bool, NULL, 0444);
 154 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 155                             "(0=off, 1=on) (default=1).");
 156 #endif
 157 module_param(dmic_detect, bool, 0444);
 158 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
 159                              "(0=off, 1=on) (default=1); "
 160                  "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
 161 module_param(ctl_dev_id, bool, 0444);
 162 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address).");
 163
 164 #ifdef CONFIG_PM
 165 static int param_set_xint(const char *val, const struct kernel_param *kp);
 166 static const struct kernel_param_ops param_ops_xint = {
 167         .set = param_set_xint,
 168         .get = param_get_int,
 169 };
 170 #define param_check_xint param_check_int
 171
 172 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 173 module_param(power_save, xint, 0644);
 174 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 175                  "(in second, 0 = disable).");
 176
 177 static bool pm_blacklist = true;
 178 module_param(pm_blacklist, bool, 0644);
 179 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
 180
 181 /* reset the HD-audio controller in power save mode.
 182  * this may give more power-saving, but will take longer time to
 183  * wake up.
 184  */
 185 static bool power_save_controller = 1;
 186 module_param(power_save_controller, bool, 0644);
 187 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 188 #else
 189 #define power_save      0
 190 #endif /* CONFIG_PM */
 191
 192 static int align_buffer_size = -1;
 193 module_param(align_buffer_size, bint, 0644);
 194 MODULE_PARM_DESC(align_buffer_size,
 195                 "Force buffer and period sizes to be multiple of 128 bytes.");
 196
 197 #ifdef CONFIG_X86
 198 static int hda_snoop = -1;
 199 module_param_named(snoop, hda_snoop, bint, 0444);
 200 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 201 #else
 202 #define hda_snoop               true
 203 #endif
 204
 205
 206 MODULE_LICENSE("GPL");
 207 MODULE_DESCRIPTION("Intel HDA driver");
 208
 209 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 210 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 211 #define SUPPORT_VGA_SWITCHEROO
 212 #endif
 213 #endif
 214
 215
 216 /*
 217  */
 218
 219 /* driver types */
 220 enum {
 221         AZX_DRIVER_ICH,
 222         AZX_DRIVER_PCH,
 223         AZX_DRIVER_SCH,
 224         AZX_DRIVER_SKL,
 225         AZX_DRIVER_HDMI,
 226         AZX_DRIVER_ATI,
 227         AZX_DRIVER_ATIHDMI,
 228         AZX_DRIVER_ATIHDMI_NS,
 229         AZX_DRIVER_VIA,
 230         AZX_DRIVER_SIS,
 231         AZX_DRIVER_ULI,
 232         AZX_DRIVER_NVIDIA,
 233         AZX_DRIVER_TERA,
 234         AZX_DRIVER_CTX,
 235         AZX_DRIVER_CTHDA,
 236         AZX_DRIVER_CMEDIA,
 237         AZX_DRIVER_ZHAOXIN,
 238         AZX_DRIVER_GENERIC,
 239         AZX_NUM_DRIVERS, /* keep this as last entry */
 240 };
 241
 242 #define azx_get_snoop_type(chip) \
 243         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 244 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 245
 246 /* quirks for old Intel chipsets */
 247 #define AZX_DCAPS_INTEL_ICH \
 248         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 249
 250 /* quirks for Intel PCH */
 251 #define AZX_DCAPS_INTEL_PCH_BASE \
 252         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 253          AZX_DCAPS_SNOOP_TYPE(SCH))
 254
 255 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 256 #define AZX_DCAPS_INTEL_PCH_NOPM \
 257         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 258
 259 /* PCH for HSW/BDW; with runtime PM */
 260 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 261 #define AZX_DCAPS_INTEL_PCH \
 262         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 263
 264 /* HSW HDMI */
 265 #define AZX_DCAPS_INTEL_HASWELL \
 266         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 267          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 268          AZX_DCAPS_SNOOP_TYPE(SCH))
 269
 270 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 271 #define AZX_DCAPS_INTEL_BROADWELL \
 272         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 273          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 274          AZX_DCAPS_SNOOP_TYPE(SCH))
 275
 276 #define AZX_DCAPS_INTEL_BAYTRAIL \
 277         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 278
 279 #define AZX_DCAPS_INTEL_BRASWELL \
 280         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 281          AZX_DCAPS_I915_COMPONENT)
 282
 283 #define AZX_DCAPS_INTEL_SKYLAKE \
 284         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 285          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 286
 287 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 288
 289 /* quirks for ATI SB / AMD Hudson */
 290 #define AZX_DCAPS_PRESET_ATI_SB \
 291         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
 292          AZX_DCAPS_SNOOP_TYPE(ATI))
 293
 294 /* quirks for ATI/AMD HDMI */
 295 #define AZX_DCAPS_PRESET_ATI_HDMI \
 296         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
 297          AZX_DCAPS_NO_MSI64)
 298
 299 /* quirks for ATI HDMI with snoop off */
 300 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 301         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 302
 303 /* quirks for AMD SB */
 304 #define AZX_DCAPS_PRESET_AMD_SB \
 305         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
 306          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
 307          AZX_DCAPS_RETRY_PROBE)
 308
 309 /* quirks for Nvidia */
 310 #define AZX_DCAPS_PRESET_NVIDIA \
 311         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 312          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 313
 314 #define AZX_DCAPS_PRESET_CTHDA \
 315         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 316          AZX_DCAPS_NO_64BIT |\
 317          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 318
 319 /*
 320  * vga_switcheroo support
 321  */
 322 #ifdef SUPPORT_VGA_SWITCHEROO
 323 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 324 #define needs_eld_notify_link(chip)     ((chip)->bus.keep_power)
 325 #else
 326 #define use_vga_switcheroo(chip)        0
 327 #define needs_eld_notify_link(chip)     false
 328 #endif
 329
 330 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 331                                         ((pci)->device == 0x0c0c) || \
 332                                         ((pci)->device == 0x0d0c) || \
 333                                         ((pci)->device == 0x160c) || \
 334                                         ((pci)->device == 0x490d) || \
 335                                         ((pci)->device == 0x4f90) || \
 336                                         ((pci)->device == 0x4f91) || \
 337                                         ((pci)->device == 0x4f92))
 338
 339 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 340
 341 static const char * const driver_short_names[] = {
 342         [AZX_DRIVER_ICH] = "HDA Intel",
 343         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 344         [AZX_DRIVER_SCH] = "HDA Intel MID",
 345         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 346         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 347         [AZX_DRIVER_ATI] = "HDA ATI SB",
 348         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 349         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 350         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 351         [AZX_DRIVER_SIS] = "HDA SIS966",
 352         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 353         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 354         [AZX_DRIVER_TERA] = "HDA Teradici",
 355         [AZX_DRIVER_CTX] = "HDA Creative",
 356         [AZX_DRIVER_CTHDA] = "HDA Creative",
 357         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 358         [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
 359         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 360 };
 361
 362 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 363 static void set_default_power_save(struct azx *chip);
 364
 365 /*
 366  * initialize the PCI registers
 367  */
 368 /* update bits in a PCI register byte */
 369 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 370                             unsigned char mask, unsigned char val)
 371 {
 372         unsigned char data;
 373
 374         pci_read_config_byte(pci, reg, &data);
 375         data &= ~mask;
 376         data |= (val & mask);
 377         pci_write_config_byte(pci, reg, data);
 378 }
 379
 380 static void azx_init_pci(struct azx *chip)
 381 {
 382         int snoop_type = azx_get_snoop_type(chip);
 383
 384         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 385          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 386          * Ensuring these bits are 0 clears playback static on some HD Audio
 387          * codecs.
 388          * The PCI register TCSEL is defined in the Intel manuals.
 389          */
 390         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 391                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 392                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 393         }
 394
 395         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 396          * we need to enable snoop.
 397          */
 398         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 399                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 400                         azx_snoop(chip));
 401                 update_pci_byte(chip->pci,
 402                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 403                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 404         }
 405
 406         /* For NVIDIA HDA, enable snoop */
 407         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 408                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 409                         azx_snoop(chip));
 410                 update_pci_byte(chip->pci,
 411                                 NVIDIA_HDA_TRANSREG_ADDR,
 412                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 413                 update_pci_byte(chip->pci,
 414                                 NVIDIA_HDA_ISTRM_COH,
 415                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 416                 update_pci_byte(chip->pci,
 417                                 NVIDIA_HDA_OSTRM_COH,
 418                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 419         }
 420
 421         /* Enable SCH/PCH snoop if needed */
 422         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 423                 unsigned short snoop;
 424                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 425                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 426                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 427                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 428                         if (!azx_snoop(chip))
 429                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 430                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 431                         pci_read_config_word(chip->pci,
 432                                 INTEL_SCH_HDA_DEVC, &snoop);
 433                 }
 434                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 435                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 436                         "Disabled" : "Enabled");
 437         }
 438 }
 439
 440 /*
 441  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 442  * and makes an audio stream sensitive to system latencies when
 443  * 24/32 bits are playing.
 444  * Adjusting threshold of DMA fifo to force the DMA request
 445  * sooner to improve latency tolerance at the expense of power.
 446  */
 447 static void bxt_reduce_dma_latency(struct azx *chip)
 448 {
 449         u32 val;
 450
 451         val = azx_readl(chip, VS_EM4L);
 452         val &= (0x3 << 20);
 453         azx_writel(chip, VS_EM4L, val);
 454 }
 455
 456 /*
 457  * ML_LCAP bits:
 458  *  bit 0: 6 MHz Supported
 459  *  bit 1: 12 MHz Supported
 460  *  bit 2: 24 MHz Supported
 461  *  bit 3: 48 MHz Supported
 462  *  bit 4: 96 MHz Supported
 463  *  bit 5: 192 MHz Supported
 464  */
 465 static int intel_get_lctl_scf(struct azx *chip)
 466 {
 467         struct hdac_bus *bus = azx_bus(chip);
 468         static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
 469         u32 val, t;
 470         int i;
 471
 472         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 473
 474         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 475                 t = preferred_bits[i];
 476                 if (val & (1 << t))
 477                         return t;
 478         }
 479
 480         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 481         return 0;
 482 }
 483
 484 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 485 {
 486         struct hdac_bus *bus = azx_bus(chip);
 487         u32 val;
 488         int timeout;
 489
 490         /*
 491          * Changes to LCTL.SCF are only needed for the first multi-link dealing
 492          * with external codecs
 493          */
 494         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 495         val &= ~AZX_ML_LCTL_SPA;
 496         val |= state << AZX_ML_LCTL_SPA_SHIFT;
 497         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 498         /* wait for CPA */
 499         timeout = 50;
 500         while (timeout) {
 501                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 502                     AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
 503                         return 0;
 504                 timeout--;
 505                 udelay(10);
 506         }
 507
 508         return -1;
 509 }
 510
 511 static void intel_init_lctl(struct azx *chip)
 512 {
 513         struct hdac_bus *bus = azx_bus(chip);
 514         u32 val;
 515         int ret;
 516
 517         /* 0. check lctl register value is correct or not */
 518         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 519         /* only perform additional configurations if the SCF is initially based on 6MHz */
 520         if ((val & AZX_ML_LCTL_SCF) != 0)
 521                 return;
 522
 523         /*
 524          * Before operating on SPA, CPA must match SPA.
 525          * Any deviation may result in undefined behavior.
 526          */
 527         if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
 528                 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
 529                 return;
 530
 531         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 532         ret = intel_ml_lctl_set_power(chip, 0);
 533         udelay(100);
 534         if (ret)
 535                 goto set_spa;
 536
 537         /* 2. update SCF to select an audio clock different from 6MHz */
 538         val &= ~AZX_ML_LCTL_SCF;
 539         val |= intel_get_lctl_scf(chip);
 540         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 541
 542 set_spa:
 543         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 544         intel_ml_lctl_set_power(chip, 1);
 545         udelay(100);
 546 }
 547
 548 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 549 {
 550         struct hdac_bus *bus = azx_bus(chip);
 551         struct pci_dev *pci = chip->pci;
 552         u32 val;
 553
 554         snd_hdac_set_codec_wakeup(bus, true);
 555         if (chip->driver_type == AZX_DRIVER_SKL) {
 556                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 557                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 558                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 559         }
 560         azx_init_chip(chip, full_reset);
 561         if (chip->driver_type == AZX_DRIVER_SKL) {
 562                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 563                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 564                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 565         }
 566
 567         snd_hdac_set_codec_wakeup(bus, false);
 568
 569         /* reduce dma latency to avoid noise */
 570         if (IS_BXT(pci))
 571                 bxt_reduce_dma_latency(chip);
 572
 573         if (bus->mlcap != NULL)
 574                 intel_init_lctl(chip);
 575 }
 576
 577 /* calculate runtime delay from LPIB */
 578 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 579                                    unsigned int pos)
 580 {
 581         struct snd_pcm_substream *substream = azx_dev->core.substream;
 582         int stream = substream->stream;
 583         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 584         int delay;
 585
 586         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 587                 delay = pos - lpib_pos;
 588         else
 589                 delay = lpib_pos - pos;
 590         if (delay < 0) {
 591                 if (delay >= azx_dev->core.delay_negative_threshold)
 592                         delay = 0;
 593                 else
 594                         delay += azx_dev->core.bufsize;
 595         }
 596
 597         if (delay >= azx_dev->core.period_bytes) {
 598                 dev_info(chip->card->dev,
 599                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 600                          delay, azx_dev->core.period_bytes);
 601                 delay = 0;
 602                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 603                 chip->get_delay[stream] = NULL;
 604         }
 605
 606         return bytes_to_frames(substream->runtime, delay);
 607 }
 608
 609 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 610
 611 /* called from IRQ */
 612 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 613 {
 614         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 615         int ok;
 616
 617         ok = azx_position_ok(chip, azx_dev);
 618         if (ok == 1) {
 619                 azx_dev->irq_pending = 0;
 620                 return ok;
 621         } else if (ok == 0) {
 622                 /* bogus IRQ, process it later */
 623                 azx_dev->irq_pending = 1;
 624                 schedule_work(&hda->irq_pending_work);
 625         }
 626         return 0;
 627 }
 628
 629 #define display_power(chip, enable) \
 630         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 631
 632 /*
 633  * Check whether the current DMA position is acceptable for updating
 634  * periods.  Returns non-zero if it's OK.
 635  *
 636  * Many HD-audio controllers appear pretty inaccurate about
 637  * the update-IRQ timing.  The IRQ is issued before actually the
 638  * data is processed.  So, we need to process it afterwords in a
 639  * workqueue.
 640  *
 641  * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
 642  */
 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 644 {
 645         struct snd_pcm_substream *substream = azx_dev->core.substream;
 646         struct snd_pcm_runtime *runtime = substream->runtime;
 647         int stream = substream->stream;
 648         u32 wallclk;
 649         unsigned int pos;
 650         snd_pcm_uframes_t hwptr, target;
 651
 652         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 653         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 654                 return -1;      /* bogus (too early) interrupt */
 655
 656         if (chip->get_position[stream])
 657                 pos = chip->get_position[stream](chip, azx_dev);
 658         else { /* use the position buffer as default */
 659                 pos = azx_get_pos_posbuf(chip, azx_dev);
 660                 if (!pos || pos == (u32)-1) {
 661                         dev_info(chip->card->dev,
 662                                  "Invalid position buffer, using LPIB read method instead.\n");
 663                         chip->get_position[stream] = azx_get_pos_lpib;
 664                         if (chip->get_position[0] == azx_get_pos_lpib &&
 665                             chip->get_position[1] == azx_get_pos_lpib)
 666                                 azx_bus(chip)->use_posbuf = false;
 667                         pos = azx_get_pos_lpib(chip, azx_dev);
 668                         chip->get_delay[stream] = NULL;
 669                 } else {
 670                         chip->get_position[stream] = azx_get_pos_posbuf;
 671                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 672                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 673                 }
 674         }
 675
 676         if (pos >= azx_dev->core.bufsize)
 677                 pos = 0;
 678
 679         if (WARN_ONCE(!azx_dev->core.period_bytes,
 680                       "hda-intel: zero azx_dev->period_bytes"))
 681                 return -1; /* this shouldn't happen! */
 682         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 683             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 684                 /* NG - it's below the first next period boundary */
 685                 return chip->bdl_pos_adj ? 0 : -1;
 686         azx_dev->core.start_wallclk += wallclk;
 687
 688         if (azx_dev->core.no_period_wakeup)
 689                 return 1; /* OK, no need to check period boundary */
 690
 691         if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
 692                 return 1; /* OK, already in hwptr updating process */
 693
 694         /* check whether the period gets really elapsed */
 695         pos = bytes_to_frames(runtime, pos);
 696         hwptr = runtime->hw_ptr_base + pos;
 697         if (hwptr < runtime->status->hw_ptr)
 698                 hwptr += runtime->buffer_size;
 699         target = runtime->hw_ptr_interrupt + runtime->period_size;
 700         if (hwptr < target) {
 701                 /* too early wakeup, process it later */
 702                 return chip->bdl_pos_adj ? 0 : -1;
 703         }
 704
 705         return 1; /* OK, it's fine */
 706 }
 707
 708 /*
 709  * The work for pending PCM period updates.
 710  */
 711 static void azx_irq_pending_work(struct work_struct *work)
 712 {
 713         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 714         struct azx *chip = &hda->chip;
 715         struct hdac_bus *bus = azx_bus(chip);
 716         struct hdac_stream *s;
 717         int pending, ok;
 718
 719         if (!hda->irq_pending_warned) {
 720                 dev_info(chip->card->dev,
 721                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 722                          chip->card->number);
 723                 hda->irq_pending_warned = 1;
 724         }
 725
 726         for (;;) {
 727                 pending = 0;
 728                 spin_lock_irq(&bus->reg_lock);
 729                 list_for_each_entry(s, &bus->stream_list, list) {
 730                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 731                         if (!azx_dev->irq_pending ||
 732                             !s->substream ||
 733                             !s->running)
 734                                 continue;
 735                         ok = azx_position_ok(chip, azx_dev);
 736                         if (ok > 0) {
 737                                 azx_dev->irq_pending = 0;
 738                                 spin_unlock(&bus->reg_lock);
 739                                 snd_pcm_period_elapsed(s->substream);
 740                                 spin_lock(&bus->reg_lock);
 741                         } else if (ok < 0) {
 742                                 pending = 0;    /* too early */
 743                         } else
 744                                 pending++;
 745                 }
 746                 spin_unlock_irq(&bus->reg_lock);
 747                 if (!pending)
 748                         return;
 749                 msleep(1);
 750         }
 751 }
 752
 753 /* clear irq_pending flags and assure no on-going workq */
 754 static void azx_clear_irq_pending(struct azx *chip)
 755 {
 756         struct hdac_bus *bus = azx_bus(chip);
 757         struct hdac_stream *s;
 758
 759         spin_lock_irq(&bus->reg_lock);
 760         list_for_each_entry(s, &bus->stream_list, list) {
 761                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 762                 azx_dev->irq_pending = 0;
 763         }
 764         spin_unlock_irq(&bus->reg_lock);
 765 }
 766
 767 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 768 {
 769         struct hdac_bus *bus = azx_bus(chip);
 770
 771         if (request_irq(chip->pci->irq, azx_interrupt,
 772                         chip->msi ? 0 : IRQF_SHARED,
 773                         chip->card->irq_descr, chip)) {
 774                 dev_err(chip->card->dev,
 775                         "unable to grab IRQ %d, disabling device\n",
 776                         chip->pci->irq);
 777                 if (do_disconnect)
 778                         snd_card_disconnect(chip->card);
 779                 return -1;
 780         }
 781         bus->irq = chip->pci->irq;
 782         chip->card->sync_irq = bus->irq;
 783         pci_intx(chip->pci, !chip->msi);
 784         return 0;
 785 }
 786
 787 /* get the current DMA position with correction on VIA chips */
 788 static unsigned int azx_via_get_position(struct azx *chip,
 789                                          struct azx_dev *azx_dev)
 790 {
 791         unsigned int link_pos, mini_pos, bound_pos;
 792         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 793         unsigned int fifo_size;
 794
 795         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 796         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 797                 /* Playback, no problem using link position */
 798                 return link_pos;
 799         }
 800
 801         /* Capture */
 802         /* For new chipset,
 803          * use mod to get the DMA position just like old chipset
 804          */
 805         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 806         mod_dma_pos %= azx_dev->core.period_bytes;
 807
 808         fifo_size = azx_stream(azx_dev)->fifo_size - 1;
 809
 810         if (azx_dev->insufficient) {
 811                 /* Link position never gather than FIFO size */
 812                 if (link_pos <= fifo_size)
 813                         return 0;
 814
 815                 azx_dev->insufficient = 0;
 816         }
 817
 818         if (link_pos <= fifo_size)
 819                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 820         else
 821                 mini_pos = link_pos - fifo_size;
 822
 823         /* Find nearest previous boudary */
 824         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 825         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 826         if (mod_link_pos >= fifo_size)
 827                 bound_pos = link_pos - mod_link_pos;
 828         else if (mod_dma_pos >= mod_mini_pos)
 829                 bound_pos = mini_pos - mod_mini_pos;
 830         else {
 831                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 832                 if (bound_pos >= azx_dev->core.bufsize)
 833                         bound_pos = 0;
 834         }
 835
 836         /* Calculate real DMA position we want */
 837         return bound_pos + mod_dma_pos;
 838 }
 839
 840 #define AMD_FIFO_SIZE   32
 841
 842 /* get the current DMA position with FIFO size correction */
 843 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 844 {
 845         struct snd_pcm_substream *substream = azx_dev->core.substream;
 846         struct snd_pcm_runtime *runtime = substream->runtime;
 847         unsigned int pos, delay;
 848
 849         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 850         if (!runtime)
 851                 return pos;
 852
 853         runtime->delay = AMD_FIFO_SIZE;
 854         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 855         if (azx_dev->insufficient) {
 856                 if (pos < delay) {
 857                         delay = pos;
 858                         runtime->delay = bytes_to_frames(runtime, pos);
 859                 } else {
 860                         azx_dev->insufficient = 0;
 861                 }
 862         }
 863
 864         /* correct the DMA position for capture stream */
 865         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 866                 if (pos < delay)
 867                         pos += azx_dev->core.bufsize;
 868                 pos -= delay;
 869         }
 870
 871         return pos;
 872 }
 873
 874 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 875                                    unsigned int pos)
 876 {
 877         struct snd_pcm_substream *substream = azx_dev->core.substream;
 878
 879         /* just read back the calculated value in the above */
 880         return substream->runtime->delay;
 881 }
 882
 883 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
 884 {
 885         azx_stop_chip(chip);
 886         if (!skip_link_reset)
 887                 azx_enter_link_reset(chip);
 888         azx_clear_irq_pending(chip);
 889         display_power(chip, false);
 890 }
 891
 892 #ifdef CONFIG_PM
 893 static DEFINE_MUTEX(card_list_lock);
 894 static LIST_HEAD(card_list);
 895
 896 static void azx_shutdown_chip(struct azx *chip)
 897 {
 898         __azx_shutdown_chip(chip, false);
 899 }
 900
 901 static void azx_add_card_list(struct azx *chip)
 902 {
 903         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 904         mutex_lock(&card_list_lock);
 905         list_add(&hda->list, &card_list);
 906         mutex_unlock(&card_list_lock);
 907 }
 908
 909 static void azx_del_card_list(struct azx *chip)
 910 {
 911         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 912         mutex_lock(&card_list_lock);
 913         list_del_init(&hda->list);
 914         mutex_unlock(&card_list_lock);
 915 }
 916
 917 /* trigger power-save check at writing parameter */
 918 static int param_set_xint(const char *val, const struct kernel_param *kp)
 919 {
 920         struct hda_intel *hda;
 921         struct azx *chip;
 922         int prev = power_save;
 923         int ret = param_set_int(val, kp);
 924
 925         if (ret || prev == power_save)
 926                 return ret;
 927
 928         mutex_lock(&card_list_lock);
 929         list_for_each_entry(hda, &card_list, list) {
 930                 chip = &hda->chip;
 931                 if (!hda->probe_continued || chip->disabled)
 932                         continue;
 933                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 934         }
 935         mutex_unlock(&card_list_lock);
 936         return 0;
 937 }
 938
 939 /*
 940  * power management
 941  */
 942 static bool azx_is_pm_ready(struct snd_card *card)
 943 {
 944         struct azx *chip;
 945         struct hda_intel *hda;
 946
 947         if (!card)
 948                 return false;
 949         chip = card->private_data;
 950         hda = container_of(chip, struct hda_intel, chip);
 951         if (chip->disabled || hda->init_failed || !chip->running)
 952                 return false;
 953         return true;
 954 }
 955
 956 static void __azx_runtime_resume(struct azx *chip)
 957 {
 958         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 959         struct hdac_bus *bus = azx_bus(chip);
 960         struct hda_codec *codec;
 961         int status;
 962
 963         display_power(chip, true);
 964         if (hda->need_i915_power)
 965                 snd_hdac_i915_set_bclk(bus);
 966
 967         /* Read STATESTS before controller reset */
 968         status = azx_readw(chip, STATESTS);
 969
 970         azx_init_pci(chip);
 971         hda_intel_init_chip(chip, true);
 972
 973         /* Avoid codec resume if runtime resume is for system suspend */
 974         if (!chip->pm_prepared) {
 975                 list_for_each_codec(codec, &chip->bus) {
 976                         if (codec->relaxed_resume)
 977                                 continue;
 978
 979                         if (codec->forced_resume || (status & (1 << codec->addr)))
 980                                 pm_request_resume(hda_codec_dev(codec));
 981                 }
 982         }
 983
 984         /* power down again for link-controlled chips */
 985         if (!hda->need_i915_power)
 986                 display_power(chip, false);
 987 }
 988
 989 #ifdef CONFIG_PM_SLEEP
 990 static int azx_prepare(struct device *dev)
 991 {
 992         struct snd_card *card = dev_get_drvdata(dev);
 993         struct azx *chip;
 994
 995         if (!azx_is_pm_ready(card))
 996                 return 0;
 997
 998         chip = card->private_data;
 999         chip->pm_prepared = 1;
1000         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1001
1002         flush_work(&azx_bus(chip)->unsol_work);
1003
1004         /* HDA controller always requires different WAKEEN for runtime suspend
1005          * and system suspend, so don't use direct-complete here.
1006          */
1007         return 0;
1008 }
1009
1010 static void azx_complete(struct device *dev)
1011 {
1012         struct snd_card *card = dev_get_drvdata(dev);
1013         struct azx *chip;
1014
1015         if (!azx_is_pm_ready(card))
1016                 return;
1017
1018         chip = card->private_data;
1019         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1020         chip->pm_prepared = 0;
1021 }
1022
1023 static int azx_suspend(struct device *dev)
1024 {
1025         struct snd_card *card = dev_get_drvdata(dev);
1026         struct azx *chip;
1027         struct hdac_bus *bus;
1028
1029         if (!azx_is_pm_ready(card))
1030                 return 0;
1031
1032         chip = card->private_data;
1033         bus = azx_bus(chip);
1034         azx_shutdown_chip(chip);
1035         if (bus->irq >= 0) {
1036                 free_irq(bus->irq, chip);
1037                 bus->irq = -1;
1038                 chip->card->sync_irq = -1;
1039         }
1040
1041         if (chip->msi)
1042                 pci_disable_msi(chip->pci);
1043
1044         trace_azx_suspend(chip);
1045         return 0;
1046 }
1047
1048 static int azx_resume(struct device *dev)
1049 {
1050         struct snd_card *card = dev_get_drvdata(dev);
1051         struct azx *chip;
1052
1053         if (!azx_is_pm_ready(card))
1054                 return 0;
1055
1056         chip = card->private_data;
1057         if (chip->msi)
1058                 if (pci_enable_msi(chip->pci) < 0)
1059                         chip->msi = 0;
1060         if (azx_acquire_irq(chip, 1) < 0)
1061                 return -EIO;
1062
1063         __azx_runtime_resume(chip);
1064
1065         trace_azx_resume(chip);
1066         return 0;
1067 }
1068
1069 /* put codec down to D3 at hibernation for Intel SKL+;
1070  * otherwise BIOS may still access the codec and screw up the driver
1071  */
1072 static int azx_freeze_noirq(struct device *dev)
1073 {
1074         struct snd_card *card = dev_get_drvdata(dev);
1075         struct azx *chip = card->private_data;
1076         struct pci_dev *pci = to_pci_dev(dev);
1077
1078         if (!azx_is_pm_ready(card))
1079                 return 0;
1080         if (chip->driver_type == AZX_DRIVER_SKL)
1081                 pci_set_power_state(pci, PCI_D3hot);
1082
1083         return 0;
1084 }
1085
1086 static int azx_thaw_noirq(struct device *dev)
1087 {
1088         struct snd_card *card = dev_get_drvdata(dev);
1089         struct azx *chip = card->private_data;
1090         struct pci_dev *pci = to_pci_dev(dev);
1091
1092         if (!azx_is_pm_ready(card))
1093                 return 0;
1094         if (chip->driver_type == AZX_DRIVER_SKL)
1095                 pci_set_power_state(pci, PCI_D0);
1096
1097         return 0;
1098 }
1099 #endif /* CONFIG_PM_SLEEP */
1100
1101 static int azx_runtime_suspend(struct device *dev)
1102 {
1103         struct snd_card *card = dev_get_drvdata(dev);
1104         struct azx *chip;
1105
1106         if (!azx_is_pm_ready(card))
1107                 return 0;
1108         chip = card->private_data;
1109
1110         /* enable controller wake up event */
1111         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1112
1113         azx_shutdown_chip(chip);
1114         trace_azx_runtime_suspend(chip);
1115         return 0;
1116 }
1117
1118 static int azx_runtime_resume(struct device *dev)
1119 {
1120         struct snd_card *card = dev_get_drvdata(dev);
1121         struct azx *chip;
1122
1123         if (!azx_is_pm_ready(card))
1124                 return 0;
1125         chip = card->private_data;
1126         __azx_runtime_resume(chip);
1127
1128         /* disable controller Wake Up event*/
1129         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1130
1131         trace_azx_runtime_resume(chip);
1132         return 0;
1133 }
1134
1135 static int azx_runtime_idle(struct device *dev)
1136 {
1137         struct snd_card *card = dev_get_drvdata(dev);
1138         struct azx *chip;
1139         struct hda_intel *hda;
1140
1141         if (!card)
1142                 return 0;
1143
1144         chip = card->private_data;
1145         hda = container_of(chip, struct hda_intel, chip);
1146         if (chip->disabled || hda->init_failed)
1147                 return 0;
1148
1149         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1150             azx_bus(chip)->codec_powered || !chip->running)
1151                 return -EBUSY;
1152
1153         /* ELD notification gets broken when HD-audio bus is off */
1154         if (needs_eld_notify_link(chip))
1155                 return -EBUSY;
1156
1157         return 0;
1158 }
1159
1160 static const struct dev_pm_ops azx_pm = {
1161         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1162 #ifdef CONFIG_PM_SLEEP
1163         .prepare = azx_prepare,
1164         .complete = azx_complete,
1165         .freeze_noirq = azx_freeze_noirq,
1166         .thaw_noirq = azx_thaw_noirq,
1167 #endif
1168         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1169 };
1170
1171 #define AZX_PM_OPS      &azx_pm
1172 #else
1173 #define azx_add_card_list(chip) /* NOP */
1174 #define azx_del_card_list(chip) /* NOP */
1175 #define AZX_PM_OPS      NULL
1176 #endif /* CONFIG_PM */
1177
1178
1179 static int azx_probe_continue(struct azx *chip);
1180
1181 #ifdef SUPPORT_VGA_SWITCHEROO
1182 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1183
1184 static void azx_vs_set_state(struct pci_dev *pci,
1185                              enum vga_switcheroo_state state)
1186 {
1187         struct snd_card *card = pci_get_drvdata(pci);
1188         struct azx *chip = card->private_data;
1189         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1190         struct hda_codec *codec;
1191         bool disabled;
1192
1193         wait_for_completion(&hda->probe_wait);
1194         if (hda->init_failed)
1195                 return;
1196
1197         disabled = (state == VGA_SWITCHEROO_OFF);
1198         if (chip->disabled == disabled)
1199                 return;
1200
1201         if (!hda->probe_continued) {
1202                 chip->disabled = disabled;
1203                 if (!disabled) {
1204                         dev_info(chip->card->dev,
1205                                  "Start delayed initialization\n");
1206                         if (azx_probe_continue(chip) < 0)
1207                                 dev_err(chip->card->dev, "initialization error\n");
1208                 }
1209         } else {
1210                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1211                          disabled ? "Disabling" : "Enabling");
1212                 if (disabled) {
1213                         list_for_each_codec(codec, &chip->bus) {
1214                                 pm_runtime_suspend(hda_codec_dev(codec));
1215                                 pm_runtime_disable(hda_codec_dev(codec));
1216                         }
1217                         pm_runtime_suspend(card->dev);
1218                         pm_runtime_disable(card->dev);
1219                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1220                          * however we have no ACPI handle, so pci/acpi can't put us there,
1221                          * put ourselves there */
1222                         pci->current_state = PCI_D3cold;
1223                         chip->disabled = true;
1224                         if (snd_hda_lock_devices(&chip->bus))
1225                                 dev_warn(chip->card->dev,
1226                                          "Cannot lock devices!\n");
1227                 } else {
1228                         snd_hda_unlock_devices(&chip->bus);
1229                         chip->disabled = false;
1230                         pm_runtime_enable(card->dev);
1231                         list_for_each_codec(codec, &chip->bus) {
1232                                 pm_runtime_enable(hda_codec_dev(codec));
1233                                 pm_runtime_resume(hda_codec_dev(codec));
1234                         }
1235                 }
1236         }
1237 }
1238
1239 static bool azx_vs_can_switch(struct pci_dev *pci)
1240 {
1241         struct snd_card *card = pci_get_drvdata(pci);
1242         struct azx *chip = card->private_data;
1243         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1244
1245         wait_for_completion(&hda->probe_wait);
1246         if (hda->init_failed)
1247                 return false;
1248         if (chip->disabled || !hda->probe_continued)
1249                 return true;
1250         if (snd_hda_lock_devices(&chip->bus))
1251                 return false;
1252         snd_hda_unlock_devices(&chip->bus);
1253         return true;
1254 }
1255
1256 /*
1257  * The discrete GPU cannot power down unless the HDA controller runtime
1258  * suspends, so activate runtime PM on codecs even if power_save == 0.
1259  */
1260 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1261 {
1262         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1263         struct hda_codec *codec;
1264
1265         if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1266                 list_for_each_codec(codec, &chip->bus)
1267                         codec->auto_runtime_pm = 1;
1268                 /* reset the power save setup */
1269                 if (chip->running)
1270                         set_default_power_save(chip);
1271         }
1272 }
1273
1274 static void azx_vs_gpu_bound(struct pci_dev *pci,
1275                              enum vga_switcheroo_client_id client_id)
1276 {
1277         struct snd_card *card = pci_get_drvdata(pci);
1278         struct azx *chip = card->private_data;
1279
1280         if (client_id == VGA_SWITCHEROO_DIS)
1281                 chip->bus.keep_power = 0;
1282         setup_vga_switcheroo_runtime_pm(chip);
1283 }
1284
1285 static void init_vga_switcheroo(struct azx *chip)
1286 {
1287         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1288         struct pci_dev *p = get_bound_vga(chip->pci);
1289         struct pci_dev *parent;
1290         if (p) {
1291                 dev_info(chip->card->dev,
1292                          "Handle vga_switcheroo audio client\n");
1293                 hda->use_vga_switcheroo = 1;
1294
1295                 /* cleared in either gpu_bound op or codec probe, or when its
1296                  * upstream port has _PR3 (i.e. dGPU).
1297                  */
1298                 parent = pci_upstream_bridge(p);
1299                 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1300                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1301                 pci_dev_put(p);
1302         }
1303 }
1304
1305 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1306         .set_gpu_state = azx_vs_set_state,
1307         .can_switch = azx_vs_can_switch,
1308         .gpu_bound = azx_vs_gpu_bound,
1309 };
1310
1311 static int register_vga_switcheroo(struct azx *chip)
1312 {
1313         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1314         struct pci_dev *p;
1315         int err;
1316
1317         if (!hda->use_vga_switcheroo)
1318                 return 0;
1319
1320         p = get_bound_vga(chip->pci);
1321         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1322         pci_dev_put(p);
1323
1324         if (err < 0)
1325                 return err;
1326         hda->vga_switcheroo_registered = 1;
1327
1328         return 0;
1329 }
1330 #else
1331 #define init_vga_switcheroo(chip)               /* NOP */
1332 #define register_vga_switcheroo(chip)           0
1333 #define check_hdmi_disabled(pci)        false
1334 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1335 #endif /* SUPPORT_VGA_SWITCHER */
1336
1337 /*
1338  * destructor
1339  */
1340 static void azx_free(struct azx *chip)
1341 {
1342         struct pci_dev *pci = chip->pci;
1343         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1344         struct hdac_bus *bus = azx_bus(chip);
1345
1346         if (hda->freed)
1347                 return;
1348
1349         if (azx_has_pm_runtime(chip) && chip->running) {
1350                 pm_runtime_get_noresume(&pci->dev);
1351                 pm_runtime_forbid(&pci->dev);
1352                 pm_runtime_dont_use_autosuspend(&pci->dev);
1353         }
1354
1355         chip->running = 0;
1356
1357         azx_del_card_list(chip);
1358
1359         hda->init_failed = 1; /* to be sure */
1360         complete_all(&hda->probe_wait);
1361
1362         if (use_vga_switcheroo(hda)) {
1363                 if (chip->disabled && hda->probe_continued)
1364                         snd_hda_unlock_devices(&chip->bus);
1365                 if (hda->vga_switcheroo_registered)
1366                         vga_switcheroo_unregister_client(chip->pci);
1367         }
1368
1369         if (bus->chip_init) {
1370                 azx_clear_irq_pending(chip);
1371                 azx_stop_all_streams(chip);
1372                 azx_stop_chip(chip);
1373         }
1374
1375         if (bus->irq >= 0)
1376                 free_irq(bus->irq, (void*)chip);
1377
1378         azx_free_stream_pages(chip);
1379         azx_free_streams(chip);
1380         snd_hdac_bus_exit(bus);
1381
1382 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1383         release_firmware(chip->fw);
1384 #endif
1385         display_power(chip, false);
1386
1387         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1388                 snd_hdac_i915_exit(bus);
1389
1390         hda->freed = 1;
1391 }
1392
1393 static int azx_dev_disconnect(struct snd_device *device)
1394 {
1395         struct azx *chip = device->device_data;
1396         struct hdac_bus *bus = azx_bus(chip);
1397
1398         chip->bus.shutdown = 1;
1399         cancel_work_sync(&bus->unsol_work);
1400
1401         return 0;
1402 }
1403
1404 static int azx_dev_free(struct snd_device *device)
1405 {
1406         azx_free(device->device_data);
1407         return 0;
1408 }
1409
1410 #ifdef SUPPORT_VGA_SWITCHEROO
1411 #ifdef CONFIG_ACPI
1412 /* ATPX is in the integrated GPU's namespace */
1413 static bool atpx_present(void)
1414 {
1415         struct pci_dev *pdev = NULL;
1416         acpi_handle dhandle, atpx_handle;
1417         acpi_status status;
1418
1419         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1420                 dhandle = ACPI_HANDLE(&pdev->dev);
1421                 if (dhandle) {
1422                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1423                         if (ACPI_SUCCESS(status)) {
1424                                 pci_dev_put(pdev);
1425                                 return true;
1426                         }
1427                 }
1428         }
1429         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1430                 dhandle = ACPI_HANDLE(&pdev->dev);
1431                 if (dhandle) {
1432                         status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1433                         if (ACPI_SUCCESS(status)) {
1434                                 pci_dev_put(pdev);
1435                                 return true;
1436                         }
1437                 }
1438         }
1439         return false;
1440 }
1441 #else
1442 static bool atpx_present(void)
1443 {
1444         return false;
1445 }
1446 #endif
1447
1448 /*
1449  * Check of disabled HDMI controller by vga_switcheroo
1450  */
1451 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1452 {
1453         struct pci_dev *p;
1454
1455         /* check only discrete GPU */
1456         switch (pci->vendor) {
1457         case PCI_VENDOR_ID_ATI:
1458         case PCI_VENDOR_ID_AMD:
1459                 if (pci->devfn == 1) {
1460                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1461                                                         pci->bus->number, 0);
1462                         if (p) {
1463                                 /* ATPX is in the integrated GPU's ACPI namespace
1464                                  * rather than the dGPU's namespace. However,
1465                                  * the dGPU is the one who is involved in
1466                                  * vgaswitcheroo.
1467                                  */
1468                                 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1469                                     atpx_present())
1470                                         return p;
1471                                 pci_dev_put(p);
1472                         }
1473                 }
1474                 break;
1475         case PCI_VENDOR_ID_NVIDIA:
1476                 if (pci->devfn == 1) {
1477                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1478                                                         pci->bus->number, 0);
1479                         if (p) {
1480                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1481                                         return p;
1482                                 pci_dev_put(p);
1483                         }
1484                 }
1485                 break;
1486         }
1487         return NULL;
1488 }
1489
1490 static bool check_hdmi_disabled(struct pci_dev *pci)
1491 {
1492         bool vga_inactive = false;
1493         struct pci_dev *p = get_bound_vga(pci);
1494
1495         if (p) {
1496                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1497                         vga_inactive = true;
1498                 pci_dev_put(p);
1499         }
1500         return vga_inactive;
1501 }
1502 #endif /* SUPPORT_VGA_SWITCHEROO */
1503
1504 /*
1505  * allow/deny-listing for position_fix
1506  */
1507 static const struct snd_pci_quirk position_fix_list[] = {
1508         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1509         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1510         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1511         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1512         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1513         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1514         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1515         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1516         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1517         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1518         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1519         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1520         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1521         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1522         {}
1523 };
1524
1525 static int check_position_fix(struct azx *chip, int fix)
1526 {
1527         const struct snd_pci_quirk *q;
1528
1529         switch (fix) {
1530         case POS_FIX_AUTO:
1531         case POS_FIX_LPIB:
1532         case POS_FIX_POSBUF:
1533         case POS_FIX_VIACOMBO:
1534         case POS_FIX_COMBO:
1535         case POS_FIX_SKL:
1536         case POS_FIX_FIFO:
1537                 return fix;
1538         }
1539
1540         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1541         if (q) {
1542                 dev_info(chip->card->dev,
1543                          "position_fix set to %d for device %04x:%04x\n",
1544                          q->value, q->subvendor, q->subdevice);
1545                 return q->value;
1546         }
1547
1548         /* Check VIA/ATI HD Audio Controller exist */
1549         if (chip->driver_type == AZX_DRIVER_VIA) {
1550                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1551                 return POS_FIX_VIACOMBO;
1552         }
1553         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1554                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1555                 return POS_FIX_FIFO;
1556         }
1557         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1558                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1559                 return POS_FIX_LPIB;
1560         }
1561         if (chip->driver_type == AZX_DRIVER_SKL) {
1562                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1563                 return POS_FIX_SKL;
1564         }
1565         return POS_FIX_AUTO;
1566 }
1567
1568 static void assign_position_fix(struct azx *chip, int fix)
1569 {
1570         static const azx_get_pos_callback_t callbacks[] = {
1571                 [POS_FIX_AUTO] = NULL,
1572                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1573                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1574                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1575                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1576                 [POS_FIX_SKL] = azx_get_pos_posbuf,
1577                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1578         };
1579
1580         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1581
1582         /* combo mode uses LPIB only for playback */
1583         if (fix == POS_FIX_COMBO)
1584                 chip->get_position[1] = NULL;
1585
1586         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1587             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1588                 chip->get_delay[0] = chip->get_delay[1] =
1589                         azx_get_delay_from_lpib;
1590         }
1591
1592         if (fix == POS_FIX_FIFO)
1593                 chip->get_delay[0] = chip->get_delay[1] =
1594                         azx_get_delay_from_fifo;
1595 }
1596
1597 /*
1598  * deny-lists for probe_mask
1599  */
1600 static const struct snd_pci_quirk probe_mask_list[] = {
1601         /* Thinkpad often breaks the controller communication when accessing
1602          * to the non-working (or non-existing) modem codec slot.
1603          */
1604         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1605         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1606         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1607         /* broken BIOS */
1608         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1609         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1610         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1611         /* forced codec slots */
1612         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1613         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1614         SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1615         /* WinFast VP200 H (Teradici) user reported broken communication */
1616         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1617         {}
1618 };
1619
1620 #define AZX_FORCE_CODEC_MASK    0x100
1621
1622 static void check_probe_mask(struct azx *chip, int dev)
1623 {
1624         const struct snd_pci_quirk *q;
1625
1626         chip->codec_probe_mask = probe_mask[dev];
1627         if (chip->codec_probe_mask == -1) {
1628                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1629                 if (q) {
1630                         dev_info(chip->card->dev,
1631                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1632                                  q->value, q->subvendor, q->subdevice);
1633                         chip->codec_probe_mask = q->value;
1634                 }
1635         }
1636
1637         /* check forced option */
1638         if (chip->codec_probe_mask != -1 &&
1639             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1640                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1641                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1642                          (int)azx_bus(chip)->codec_mask);
1643         }
1644 }
1645
1646 /*
1647  * allow/deny-list for enable_msi
1648  */
1649 static const struct snd_pci_quirk msi_deny_list[] = {
1650         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1651         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1652         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1653         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1654         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1655         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1656         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1657         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1658         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1659         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1660         {}
1661 };
1662
1663 static void check_msi(struct azx *chip)
1664 {
1665         const struct snd_pci_quirk *q;
1666
1667         if (enable_msi >= 0) {
1668                 chip->msi = !!enable_msi;
1669                 return;
1670         }
1671         chip->msi = 1;  /* enable MSI as default */
1672         q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1673         if (q) {
1674                 dev_info(chip->card->dev,
1675                          "msi for device %04x:%04x set to %d\n",
1676                          q->subvendor, q->subdevice, q->value);
1677                 chip->msi = q->value;
1678                 return;
1679         }
1680
1681         /* NVidia chipsets seem to cause troubles with MSI */
1682         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1683                 dev_info(chip->card->dev, "Disabling MSI\n");
1684                 chip->msi = 0;
1685         }
1686 }
1687
1688 /* check the snoop mode availability */
1689 static void azx_check_snoop_available(struct azx *chip)
1690 {
1691         int snoop = hda_snoop;
1692
1693         if (snoop >= 0) {
1694                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1695                          snoop ? "snoop" : "non-snoop");
1696                 chip->snoop = snoop;
1697                 chip->uc_buffer = !snoop;
1698                 return;
1699         }
1700
1701         snoop = true;
1702         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1703             chip->driver_type == AZX_DRIVER_VIA) {
1704                 /* force to non-snoop mode for a new VIA controller
1705                  * when BIOS is set
1706                  */
1707                 u8 val;
1708                 pci_read_config_byte(chip->pci, 0x42, &val);
1709                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1710                                       chip->pci->revision == 0x20))
1711                         snoop = false;
1712         }
1713
1714         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1715                 snoop = false;
1716
1717         chip->snoop = snoop;
1718         if (!snoop) {
1719                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1720                 /* C-Media requires non-cached pages only for CORB/RIRB */
1721                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1722                         chip->uc_buffer = true;
1723         }
1724 }
1725
1726 static void azx_probe_work(struct work_struct *work)
1727 {
1728         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1729         azx_probe_continue(&hda->chip);
1730 }
1731
1732 static int default_bdl_pos_adj(struct azx *chip)
1733 {
1734         /* some exceptions: Atoms seem problematic with value 1 */
1735         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1736                 switch (chip->pci->device) {
1737                 case 0x0f04: /* Baytrail */
1738                 case 0x2284: /* Braswell */
1739                         return 32;
1740                 }
1741         }
1742
1743         switch (chip->driver_type) {
1744         case AZX_DRIVER_ICH:
1745         case AZX_DRIVER_PCH:
1746                 return 1;
1747         default:
1748                 return 32;
1749         }
1750 }
1751
1752 /*
1753  * constructor
1754  */
1755 static const struct hda_controller_ops pci_hda_ops;
1756
1757 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1758                       int dev, unsigned int driver_caps,
1759                       struct azx **rchip)
1760 {
1761         static const struct snd_device_ops ops = {
1762                 .dev_disconnect = azx_dev_disconnect,
1763                 .dev_free = azx_dev_free,
1764         };
1765         struct hda_intel *hda;
1766         struct azx *chip;
1767         int err;
1768
1769         *rchip = NULL;
1770
1771         err = pcim_enable_device(pci);
1772         if (err < 0)
1773                 return err;
1774
1775         hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1776         if (!hda)
1777                 return -ENOMEM;
1778
1779         chip = &hda->chip;
1780         mutex_init(&chip->open_mutex);
1781         chip->card = card;
1782         chip->pci = pci;
1783         chip->ops = &pci_hda_ops;
1784         chip->driver_caps = driver_caps;
1785         chip->driver_type = driver_caps & 0xff;
1786         check_msi(chip);
1787         chip->dev_index = dev;
1788         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1789                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1790         INIT_LIST_HEAD(&chip->pcm_list);
1791         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1792         INIT_LIST_HEAD(&hda->list);
1793         init_vga_switcheroo(chip);
1794         init_completion(&hda->probe_wait);
1795
1796         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1797
1798         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1799                 chip->fallback_to_single_cmd = 1;
1800         else /* explicitly set to single_cmd or not */
1801                 chip->single_cmd = single_cmd;
1802
1803         azx_check_snoop_available(chip);
1804
1805         if (bdl_pos_adj[dev] < 0)
1806                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1807         else
1808                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1809
1810         err = azx_bus_init(chip, model[dev]);
1811         if (err < 0)
1812                 return err;
1813
1814         /* use the non-cached pages in non-snoop mode */
1815         if (!azx_snoop(chip))
1816                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
1817
1818         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1819                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1820                 chip->bus.core.needs_damn_long_delay = 1;
1821         }
1822
1823         check_probe_mask(chip, dev);
1824
1825         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1826         if (err < 0) {
1827                 dev_err(card->dev, "Error creating device [card]!\n");
1828                 azx_free(chip);
1829                 return err;
1830         }
1831
1832         /* continue probing in work context as may trigger request module */
1833         INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1834
1835         *rchip = chip;
1836
1837         return 0;
1838 }
1839
1840 static int azx_first_init(struct azx *chip)
1841 {
1842         int dev = chip->dev_index;
1843         struct pci_dev *pci = chip->pci;
1844         struct snd_card *card = chip->card;
1845         struct hdac_bus *bus = azx_bus(chip);
1846         int err;
1847         unsigned short gcap;
1848         unsigned int dma_bits = 64;
1849
1850 #if BITS_PER_LONG != 64
1851         /* Fix up base address on ULI M5461 */
1852         if (chip->driver_type == AZX_DRIVER_ULI) {
1853                 u16 tmp3;
1854                 pci_read_config_word(pci, 0x40, &tmp3);
1855                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1856                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1857         }
1858 #endif
1859
1860         err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
1861         if (err < 0)
1862                 return err;
1863
1864         bus->addr = pci_resource_start(pci, 0);
1865         bus->remap_addr = pcim_iomap_table(pci)[0];
1866
1867         if (chip->driver_type == AZX_DRIVER_SKL)
1868                 snd_hdac_bus_parse_capabilities(bus);
1869
1870         /*
1871          * Some Intel CPUs has always running timer (ART) feature and
1872          * controller may have Global time sync reporting capability, so
1873          * check both of these before declaring synchronized time reporting
1874          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1875          */
1876         chip->gts_present = false;
1877
1878 #ifdef CONFIG_X86
1879         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1880                 chip->gts_present = true;
1881 #endif
1882
1883         if (chip->msi) {
1884                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1885                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1886                         pci->no_64bit_msi = true;
1887                 }
1888                 if (pci_enable_msi(pci) < 0)
1889                         chip->msi = 0;
1890         }
1891
1892         pci_set_master(pci);
1893
1894         gcap = azx_readw(chip, GCAP);
1895         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1896
1897         /* AMD devices support 40 or 48bit DMA, take the safe one */
1898         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1899                 dma_bits = 40;
1900
1901         /* disable SB600 64bit support for safety */
1902         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1903                 struct pci_dev *p_smbus;
1904                 dma_bits = 40;
1905                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1906                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1907                                          NULL);
1908                 if (p_smbus) {
1909                         if (p_smbus->revision < 0x30)
1910                                 gcap &= ~AZX_GCAP_64OK;
1911                         pci_dev_put(p_smbus);
1912                 }
1913         }
1914
1915         /* NVidia hardware normally only supports up to 40 bits of DMA */
1916         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1917                 dma_bits = 40;
1918
1919         /* disable 64bit DMA address on some devices */
1920         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1921                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1922                 gcap &= ~AZX_GCAP_64OK;
1923         }
1924
1925         /* disable buffer size rounding to 128-byte multiples if supported */
1926         if (align_buffer_size >= 0)
1927                 chip->align_buffer_size = !!align_buffer_size;
1928         else {
1929                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1930                         chip->align_buffer_size = 0;
1931                 else
1932                         chip->align_buffer_size = 1;
1933         }
1934
1935         /* allow 64bit DMA address if supported by H/W */
1936         if (!(gcap & AZX_GCAP_64OK))
1937                 dma_bits = 32;
1938         if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1939                 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1940         dma_set_max_seg_size(&pci->dev, UINT_MAX);
1941
1942         /* read number of streams from GCAP register instead of using
1943          * hardcoded value
1944          */
1945         chip->capture_streams = (gcap >> 8) & 0x0f;
1946         chip->playback_streams = (gcap >> 12) & 0x0f;
1947         if (!chip->playback_streams && !chip->capture_streams) {
1948                 /* gcap didn't give any info, switching to old method */
1949
1950                 switch (chip->driver_type) {
1951                 case AZX_DRIVER_ULI:
1952                         chip->playback_streams = ULI_NUM_PLAYBACK;
1953                         chip->capture_streams = ULI_NUM_CAPTURE;
1954                         break;
1955                 case AZX_DRIVER_ATIHDMI:
1956                 case AZX_DRIVER_ATIHDMI_NS:
1957                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1958                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1959                         break;
1960                 case AZX_DRIVER_GENERIC:
1961                 default:
1962                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1963                         chip->capture_streams = ICH6_NUM_CAPTURE;
1964                         break;
1965                 }
1966         }
1967         chip->capture_index_offset = 0;
1968         chip->playback_index_offset = chip->capture_streams;
1969         chip->num_streams = chip->playback_streams + chip->capture_streams;
1970
1971         /* sanity check for the SDxCTL.STRM field overflow */
1972         if (chip->num_streams > 15 &&
1973             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1974                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1975                          "forcing separate stream tags", chip->num_streams);
1976                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1977         }
1978
1979         /* initialize streams */
1980         err = azx_init_streams(chip);
1981         if (err < 0)
1982                 return err;
1983
1984         err = azx_alloc_stream_pages(chip);
1985         if (err < 0)
1986                 return err;
1987
1988         /* initialize chip */
1989         azx_init_pci(chip);
1990
1991         snd_hdac_i915_set_bclk(bus);
1992
1993         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1994
1995         /* codec detection */
1996         if (!azx_bus(chip)->codec_mask) {
1997                 dev_err(card->dev, "no codecs found!\n");
1998                 /* keep running the rest for the runtime PM */
1999         }
2000
2001         if (azx_acquire_irq(chip, 0) < 0)
2002                 return -EBUSY;
2003
2004         strcpy(card->driver, "HDA-Intel");
2005         strscpy(card->shortname, driver_short_names[chip->driver_type],
2006                 sizeof(card->shortname));
2007         snprintf(card->longname, sizeof(card->longname),
2008                  "%s at 0x%lx irq %i",
2009                  card->shortname, bus->addr, bus->irq);
2010
2011         return 0;
2012 }
2013
2014 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2015 /* callback from request_firmware_nowait() */
2016 static void azx_firmware_cb(const struct firmware *fw, void *context)
2017 {
2018         struct snd_card *card = context;
2019         struct azx *chip = card->private_data;
2020
2021         if (fw)
2022                 chip->fw = fw;
2023         else
2024                 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2025         if (!chip->disabled) {
2026                 /* continue probing */
2027                 azx_probe_continue(chip);
2028         }
2029 }
2030 #endif
2031
2032 static int disable_msi_reset_irq(struct azx *chip)
2033 {
2034         struct hdac_bus *bus = azx_bus(chip);
2035         int err;
2036
2037         free_irq(bus->irq, chip);
2038         bus->irq = -1;
2039         chip->card->sync_irq = -1;
2040         pci_disable_msi(chip->pci);
2041         chip->msi = 0;
2042         err = azx_acquire_irq(chip, 1);
2043         if (err < 0)
2044                 return err;
2045
2046         return 0;
2047 }
2048
2049 /* Denylist for skipping the whole probe:
2050  * some HD-audio PCI entries are exposed without any codecs, and such devices
2051  * should be ignored from the beginning.
2052  */
2053 static const struct pci_device_id driver_denylist[] = {
2054         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2055         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2056         { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2057         {}
2058 };
2059
2060 static const struct hda_controller_ops pci_hda_ops = {
2061         .disable_msi_reset_irq = disable_msi_reset_irq,
2062         .position_check = azx_position_check,
2063 };
2064
2065 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2066
2067 static int azx_probe(struct pci_dev *pci,
2068                      const struct pci_device_id *pci_id)
2069 {
2070         struct snd_card *card;
2071         struct hda_intel *hda;
2072         struct azx *chip;
2073         bool schedule_probe;
2074         int dev;
2075         int err;
2076
2077         if (pci_match_id(driver_denylist, pci)) {
2078                 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2079                 return -ENODEV;
2080         }
2081
2082         dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2083         if (dev >= SNDRV_CARDS)
2084                 return -ENODEV;
2085         if (!enable[dev]) {
2086                 set_bit(dev, probed_devs);
2087                 return -ENOENT;
2088         }
2089
2090         /*
2091          * stop probe if another Intel's DSP driver should be activated
2092          */
2093         if (dmic_detect) {
2094                 err = snd_intel_dsp_driver_probe(pci);
2095                 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2096                         dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2097                         return -ENODEV;
2098                 }
2099         } else {
2100                 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2101         }
2102
2103         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2104                            0, &card);
2105         if (err < 0) {
2106                 dev_err(&pci->dev, "Error creating card!\n");
2107                 return err;
2108         }
2109
2110         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2111         if (err < 0)
2112                 goto out_free;
2113         card->private_data = chip;
2114         hda = container_of(chip, struct hda_intel, chip);
2115
2116         pci_set_drvdata(pci, card);
2117
2118         err = register_vga_switcheroo(chip);
2119         if (err < 0) {
2120                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2121                 goto out_free;
2122         }
2123
2124         if (check_hdmi_disabled(pci)) {
2125                 dev_info(card->dev, "VGA controller is disabled\n");
2126                 dev_info(card->dev, "Delaying initialization\n");
2127                 chip->disabled = true;
2128         }
2129
2130         schedule_probe = !chip->disabled;
2131
2132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2133         if (patch[dev] && *patch[dev]) {
2134                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2135                          patch[dev]);
2136                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2137                                               &pci->dev, GFP_KERNEL, card,
2138                                               azx_firmware_cb);
2139                 if (err < 0)
2140                         goto out_free;
2141                 schedule_probe = false; /* continued in azx_firmware_cb() */
2142         }
2143 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2144
2145 #ifndef CONFIG_SND_HDA_I915
2146         if (CONTROLLER_IN_GPU(pci))
2147                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2148 #endif
2149
2150         if (schedule_probe)
2151                 schedule_delayed_work(&hda->probe_work, 0);
2152
2153         set_bit(dev, probed_devs);
2154         if (chip->disabled)
2155                 complete_all(&hda->probe_wait);
2156         return 0;
2157
2158 out_free:
2159         snd_card_free(card);
2160         return err;
2161 }
2162
2163 #ifdef CONFIG_PM
2164 /* On some boards setting power_save to a non 0 value leads to clicking /
2165  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2166  * figure out how to avoid these sounds, but that is not always feasible.
2167  * So we keep a list of devices where we disable powersaving as its known
2168  * to causes problems on these devices.
2169  */
2170 static const struct snd_pci_quirk power_save_denylist[] = {
2171         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2172         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2173         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2174         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2175         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2176         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2177         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2178         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2179         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2180         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2181         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2182         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2183         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2184         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2185         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2186         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2187         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2188         /* https://bugs.launchpad.net/bugs/1821663 */
2189         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2190         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2191         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2192         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2193         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2194         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2195         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2196         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2197         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2198         /* https://bugs.launchpad.net/bugs/1821663 */
2199         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2200         {}
2201 };
2202 #endif /* CONFIG_PM */
2203
2204 static void set_default_power_save(struct azx *chip)
2205 {
2206         int val = power_save;
2207
2208 #ifdef CONFIG_PM
2209         if (pm_blacklist) {
2210                 const struct snd_pci_quirk *q;
2211
2212                 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2213                 if (q && val) {
2214                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2215                                  q->subvendor, q->subdevice);
2216                         val = 0;
2217                 }
2218         }
2219 #endif /* CONFIG_PM */
2220         snd_hda_set_power_save(&chip->bus, val * 1000);
2221 }
2222
2223 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2224 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2225         [AZX_DRIVER_NVIDIA] = 8,
2226         [AZX_DRIVER_TERA] = 1,
2227 };
2228
2229 static int azx_probe_continue(struct azx *chip)
2230 {
2231         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2232         struct hdac_bus *bus = azx_bus(chip);
2233         struct pci_dev *pci = chip->pci;
2234         int dev = chip->dev_index;
2235         int err;
2236
2237         if (chip->disabled || hda->init_failed)
2238                 return -EIO;
2239         if (hda->probe_retry)
2240                 goto probe_retry;
2241
2242         to_hda_bus(bus)->bus_probing = 1;
2243         hda->probe_continued = 1;
2244
2245         /* bind with i915 if needed */
2246         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2247                 err = snd_hdac_i915_init(bus);
2248                 if (err < 0) {
2249                         /* if the controller is bound only with HDMI/DP
2250                          * (for HSW and BDW), we need to abort the probe;
2251                          * for other chips, still continue probing as other
2252                          * codecs can be on the same link.
2253                          */
2254                         if (CONTROLLER_IN_GPU(pci)) {
2255                                 dev_err(chip->card->dev,
2256                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2257                                 goto out_free;
2258                         } else {
2259                                 /* don't bother any longer */
2260                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2261                         }
2262                 }
2263
2264                 /* HSW/BDW controllers need this power */
2265                 if (CONTROLLER_IN_GPU(pci))
2266                         hda->need_i915_power = true;
2267         }
2268
2269         /* Request display power well for the HDA controller or codec. For
2270          * Haswell/Broadwell, both the display HDA controller and codec need
2271          * this power. For other platforms, like Baytrail/Braswell, only the
2272          * display codec needs the power and it can be released after probe.
2273          */
2274         display_power(chip, true);
2275
2276         err = azx_first_init(chip);
2277         if (err < 0)
2278                 goto out_free;
2279
2280 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2281         chip->beep_mode = beep_mode[dev];
2282 #endif
2283
2284         chip->ctl_dev_id = ctl_dev_id;
2285
2286         /* create codec instances */
2287         if (bus->codec_mask) {
2288                 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2289                 if (err < 0)
2290                         goto out_free;
2291         }
2292
2293 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2294         if (chip->fw) {
2295                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2296                                          chip->fw->data);
2297                 if (err < 0)
2298                         goto out_free;
2299 #ifndef CONFIG_PM
2300                 release_firmware(chip->fw); /* no longer needed */
2301                 chip->fw = NULL;
2302 #endif
2303         }
2304 #endif
2305
2306  probe_retry:
2307         if (bus->codec_mask && !(probe_only[dev] & 1)) {
2308                 err = azx_codec_configure(chip);
2309                 if (err) {
2310                         if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2311                             ++hda->probe_retry < 60) {
2312                                 schedule_delayed_work(&hda->probe_work,
2313                                                       msecs_to_jiffies(1000));
2314                                 return 0; /* keep things up */
2315                         }
2316                         dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2317                         goto out_free;
2318                 }
2319         }
2320
2321         err = snd_card_register(chip->card);
2322         if (err < 0)
2323                 goto out_free;
2324
2325         setup_vga_switcheroo_runtime_pm(chip);
2326
2327         chip->running = 1;
2328         azx_add_card_list(chip);
2329
2330         set_default_power_save(chip);
2331
2332         if (azx_has_pm_runtime(chip)) {
2333                 pm_runtime_use_autosuspend(&pci->dev);
2334                 pm_runtime_allow(&pci->dev);
2335                 pm_runtime_put_autosuspend(&pci->dev);
2336         }
2337
2338 out_free:
2339         if (err < 0) {
2340                 pci_set_drvdata(pci, NULL);
2341                 snd_card_free(chip->card);
2342                 return err;
2343         }
2344
2345         if (!hda->need_i915_power)
2346                 display_power(chip, false);
2347         complete_all(&hda->probe_wait);
2348         to_hda_bus(bus)->bus_probing = 0;
2349         hda->probe_retry = 0;
2350         return 0;
2351 }
2352
2353 static void azx_remove(struct pci_dev *pci)
2354 {
2355         struct snd_card *card = pci_get_drvdata(pci);
2356         struct azx *chip;
2357         struct hda_intel *hda;
2358
2359         if (card) {
2360                 /* cancel the pending probing work */
2361                 chip = card->private_data;
2362                 hda = container_of(chip, struct hda_intel, chip);
2363                 /* FIXME: below is an ugly workaround.
2364                  * Both device_release_driver() and driver_probe_device()
2365                  * take *both* the device's and its parent's lock before
2366                  * calling the remove() and probe() callbacks.  The codec
2367                  * probe takes the locks of both the codec itself and its
2368                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2369                  * the PCI controller is unbound, it takes its lock, too
2370                  * ==> ouch, a deadlock!
2371                  * As a workaround, we unlock temporarily here the controller
2372                  * device during cancel_work_sync() call.
2373                  */
2374                 device_unlock(&pci->dev);
2375                 cancel_delayed_work_sync(&hda->probe_work);
2376                 device_lock(&pci->dev);
2377
2378                 clear_bit(chip->dev_index, probed_devs);
2379                 pci_set_drvdata(pci, NULL);
2380                 snd_card_free(card);
2381         }
2382 }
2383
2384 static void azx_shutdown(struct pci_dev *pci)
2385 {
2386         struct snd_card *card = pci_get_drvdata(pci);
2387         struct azx *chip;
2388
2389         if (!card)
2390                 return;
2391         chip = card->private_data;
2392         if (chip && chip->running)
2393                 __azx_shutdown_chip(chip, true);
2394 }
2395
2396 /* PCI IDs */
2397 static const struct pci_device_id azx_ids[] = {
2398         /* CPT */
2399         { PCI_DEVICE(0x8086, 0x1c20),
2400           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2401         /* PBG */
2402         { PCI_DEVICE(0x8086, 0x1d20),
2403           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2404         /* Panther Point */
2405         { PCI_DEVICE(0x8086, 0x1e20),
2406           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2407         /* Lynx Point */
2408         { PCI_DEVICE(0x8086, 0x8c20),
2409           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2410         /* 9 Series */
2411         { PCI_DEVICE(0x8086, 0x8ca0),
2412           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2413         /* Wellsburg */
2414         { PCI_DEVICE(0x8086, 0x8d20),
2415           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2416         { PCI_DEVICE(0x8086, 0x8d21),
2417           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2418         /* Lewisburg */
2419         { PCI_DEVICE(0x8086, 0xa1f0),
2420           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2421         { PCI_DEVICE(0x8086, 0xa270),
2422           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2423         /* Lynx Point-LP */
2424         { PCI_DEVICE(0x8086, 0x9c20),
2425           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2426         /* Lynx Point-LP */
2427         { PCI_DEVICE(0x8086, 0x9c21),
2428           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2429         /* Wildcat Point-LP */
2430         { PCI_DEVICE(0x8086, 0x9ca0),
2431           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2432         /* Sunrise Point */
2433         { PCI_DEVICE(0x8086, 0xa170),
2434           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2435         /* Sunrise Point-LP */
2436         { PCI_DEVICE(0x8086, 0x9d70),
2437           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2438         /* Kabylake */
2439         { PCI_DEVICE(0x8086, 0xa171),
2440           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2441         /* Kabylake-LP */
2442         { PCI_DEVICE(0x8086, 0x9d71),
2443           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2444         /* Kabylake-H */
2445         { PCI_DEVICE(0x8086, 0xa2f0),
2446           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2447         /* Coffelake */
2448         { PCI_DEVICE(0x8086, 0xa348),
2449           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2450         /* Cannonlake */
2451         { PCI_DEVICE(0x8086, 0x9dc8),
2452           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2453         /* CometLake-LP */
2454         { PCI_DEVICE(0x8086, 0x02C8),
2455           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2456         /* CometLake-H */
2457         { PCI_DEVICE(0x8086, 0x06C8),
2458           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2459         { PCI_DEVICE(0x8086, 0xf1c8),
2460           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2461         /* CometLake-S */
2462         { PCI_DEVICE(0x8086, 0xa3f0),
2463           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2464         /* CometLake-R */
2465         { PCI_DEVICE(0x8086, 0xf0c8),
2466           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2467         /* Icelake */
2468         { PCI_DEVICE(0x8086, 0x34c8),
2469           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2470         /* Icelake-H */
2471         { PCI_DEVICE(0x8086, 0x3dc8),
2472           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2473         /* Jasperlake */
2474         { PCI_DEVICE(0x8086, 0x38c8),
2475           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2476         { PCI_DEVICE(0x8086, 0x4dc8),
2477           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2478         /* Tigerlake */
2479         { PCI_DEVICE(0x8086, 0xa0c8),
2480           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2481         /* Tigerlake-H */
2482         { PCI_DEVICE(0x8086, 0x43c8),
2483           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2484         /* DG1 */
2485         { PCI_DEVICE(0x8086, 0x490d),
2486           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2487         /* DG2 */
2488         { PCI_DEVICE(0x8086, 0x4f90),
2489           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2490         { PCI_DEVICE(0x8086, 0x4f91),
2491           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2492         { PCI_DEVICE(0x8086, 0x4f92),
2493           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2494         /* Alderlake-S */
2495         { PCI_DEVICE(0x8086, 0x7ad0),
2496           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2497         /* Alderlake-P */
2498         { PCI_DEVICE(0x8086, 0x51c8),
2499           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2500         { PCI_DEVICE(0x8086, 0x51c9),
2501           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2502         { PCI_DEVICE(0x8086, 0x51cd),
2503           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2504         /* Alderlake-M */
2505         { PCI_DEVICE(0x8086, 0x51cc),
2506           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2507         /* Alderlake-N */
2508         { PCI_DEVICE(0x8086, 0x54c8),
2509           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2510         /* Elkhart Lake */
2511         { PCI_DEVICE(0x8086, 0x4b55),
2512           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2513         { PCI_DEVICE(0x8086, 0x4b58),
2514           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2515         /* Raptor Lake */
2516         { PCI_DEVICE(0x8086, 0x7a50),
2517           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2518         { PCI_DEVICE(0x8086, 0x51ca),
2519           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2520         { PCI_DEVICE(0x8086, 0x51cb),
2521           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2522         { PCI_DEVICE(0x8086, 0x51ce),
2523           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2524         { PCI_DEVICE(0x8086, 0x51cf),
2525           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2526         /* Meteorlake-P */
2527         { PCI_DEVICE(0x8086, 0x7e28),
2528           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2529         /* Broxton-P(Apollolake) */
2530         { PCI_DEVICE(0x8086, 0x5a98),
2531           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2532         /* Broxton-T */
2533         { PCI_DEVICE(0x8086, 0x1a98),
2534           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2535         /* Gemini-Lake */
2536         { PCI_DEVICE(0x8086, 0x3198),
2537           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2538         /* Haswell */
2539         { PCI_DEVICE(0x8086, 0x0a0c),
2540           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2541         { PCI_DEVICE(0x8086, 0x0c0c),
2542           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2543         { PCI_DEVICE(0x8086, 0x0d0c),
2544           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2545         /* Broadwell */
2546         { PCI_DEVICE(0x8086, 0x160c),
2547           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2548         /* 5 Series/3400 */
2549         { PCI_DEVICE(0x8086, 0x3b56),
2550           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2551         { PCI_DEVICE(0x8086, 0x3b57),
2552           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2553         /* Poulsbo */
2554         { PCI_DEVICE(0x8086, 0x811b),
2555           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE |
2556           AZX_DCAPS_POSFIX_LPIB },
2557         /* Oaktrail */
2558         { PCI_DEVICE(0x8086, 0x080a),
2559           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2560         /* BayTrail */
2561         { PCI_DEVICE(0x8086, 0x0f04),
2562           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2563         /* Braswell */
2564         { PCI_DEVICE(0x8086, 0x2284),
2565           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2566         /* ICH6 */
2567         { PCI_DEVICE(0x8086, 0x2668),
2568           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2569         /* ICH7 */
2570         { PCI_DEVICE(0x8086, 0x27d8),
2571           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2572         /* ESB2 */
2573         { PCI_DEVICE(0x8086, 0x269a),
2574           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2575         /* ICH8 */
2576         { PCI_DEVICE(0x8086, 0x284b),
2577           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2578         /* ICH9 */
2579         { PCI_DEVICE(0x8086, 0x293e),
2580           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2581         /* ICH9 */
2582         { PCI_DEVICE(0x8086, 0x293f),
2583           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2584         /* ICH10 */
2585         { PCI_DEVICE(0x8086, 0x3a3e),
2586           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2587         /* ICH10 */
2588         { PCI_DEVICE(0x8086, 0x3a6e),
2589           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2590         /* Generic Intel */
2591         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2592           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2593           .class_mask = 0xffffff,
2594           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2595         /* ATI SB 450/600/700/800/900 */
2596         { PCI_DEVICE(0x1002, 0x437b),
2597           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2598         { PCI_DEVICE(0x1002, 0x4383),
2599           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2600         /* AMD Hudson */
2601         { PCI_DEVICE(0x1022, 0x780d),
2602           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2603         /* AMD, X370 & co */
2604         { PCI_DEVICE(0x1022, 0x1457),
2605           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2606         /* AMD, X570 & co */
2607         { PCI_DEVICE(0x1022, 0x1487),
2608           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2609         /* AMD Stoney */
2610         { PCI_DEVICE(0x1022, 0x157a),
2611           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2612                          AZX_DCAPS_PM_RUNTIME },
2613         /* AMD Raven */
2614         { PCI_DEVICE(0x1022, 0x15e3),
2615           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2616         /* ATI HDMI */
2617         { PCI_DEVICE(0x1002, 0x0002),
2618           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2619           AZX_DCAPS_PM_RUNTIME },
2620         { PCI_DEVICE(0x1002, 0x1308),
2621           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2622         { PCI_DEVICE(0x1002, 0x157a),
2623           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2624         { PCI_DEVICE(0x1002, 0x15b3),
2625           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2626         { PCI_DEVICE(0x1002, 0x793b),
2627           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2628         { PCI_DEVICE(0x1002, 0x7919),
2629           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2630         { PCI_DEVICE(0x1002, 0x960f),
2631           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2632         { PCI_DEVICE(0x1002, 0x970f),
2633           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2634         { PCI_DEVICE(0x1002, 0x9840),
2635           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2636         { PCI_DEVICE(0x1002, 0xaa00),
2637           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2638         { PCI_DEVICE(0x1002, 0xaa08),
2639           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2640         { PCI_DEVICE(0x1002, 0xaa10),
2641           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2642         { PCI_DEVICE(0x1002, 0xaa18),
2643           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2644         { PCI_DEVICE(0x1002, 0xaa20),
2645           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2646         { PCI_DEVICE(0x1002, 0xaa28),
2647           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2648         { PCI_DEVICE(0x1002, 0xaa30),
2649           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2650         { PCI_DEVICE(0x1002, 0xaa38),
2651           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2652         { PCI_DEVICE(0x1002, 0xaa40),
2653           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2654         { PCI_DEVICE(0x1002, 0xaa48),
2655           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2656         { PCI_DEVICE(0x1002, 0xaa50),
2657           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2658         { PCI_DEVICE(0x1002, 0xaa58),
2659           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2660         { PCI_DEVICE(0x1002, 0xaa60),
2661           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2662         { PCI_DEVICE(0x1002, 0xaa68),
2663           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2664         { PCI_DEVICE(0x1002, 0xaa80),
2665           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2666         { PCI_DEVICE(0x1002, 0xaa88),
2667           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2668         { PCI_DEVICE(0x1002, 0xaa90),
2669           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2670         { PCI_DEVICE(0x1002, 0xaa98),
2671           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2672         { PCI_DEVICE(0x1002, 0x9902),
2673           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2674         { PCI_DEVICE(0x1002, 0xaaa0),
2675           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2676         { PCI_DEVICE(0x1002, 0xaaa8),
2677           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2678         { PCI_DEVICE(0x1002, 0xaab0),
2679           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2680         { PCI_DEVICE(0x1002, 0xaac0),
2681           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2682           AZX_DCAPS_PM_RUNTIME },
2683         { PCI_DEVICE(0x1002, 0xaac8),
2684           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2685           AZX_DCAPS_PM_RUNTIME },
2686         { PCI_DEVICE(0x1002, 0xaad8),
2687           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2688           AZX_DCAPS_PM_RUNTIME },
2689         { PCI_DEVICE(0x1002, 0xaae0),
2690           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2691           AZX_DCAPS_PM_RUNTIME },
2692         { PCI_DEVICE(0x1002, 0xaae8),
2693           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2694           AZX_DCAPS_PM_RUNTIME },
2695         { PCI_DEVICE(0x1002, 0xaaf0),
2696           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2697           AZX_DCAPS_PM_RUNTIME },
2698         { PCI_DEVICE(0x1002, 0xaaf8),
2699           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2700           AZX_DCAPS_PM_RUNTIME },
2701         { PCI_DEVICE(0x1002, 0xab00),
2702           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2703           AZX_DCAPS_PM_RUNTIME },
2704         { PCI_DEVICE(0x1002, 0xab08),
2705           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2706           AZX_DCAPS_PM_RUNTIME },
2707         { PCI_DEVICE(0x1002, 0xab10),
2708           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2709           AZX_DCAPS_PM_RUNTIME },
2710         { PCI_DEVICE(0x1002, 0xab18),
2711           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2712           AZX_DCAPS_PM_RUNTIME },
2713         { PCI_DEVICE(0x1002, 0xab20),
2714           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2715           AZX_DCAPS_PM_RUNTIME },
2716         { PCI_DEVICE(0x1002, 0xab28),
2717           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2718           AZX_DCAPS_PM_RUNTIME },
2719         { PCI_DEVICE(0x1002, 0xab30),
2720           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2721           AZX_DCAPS_PM_RUNTIME },
2722         { PCI_DEVICE(0x1002, 0xab38),
2723           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2724           AZX_DCAPS_PM_RUNTIME },
2725         /* VIA VT8251/VT8237A */
2726         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2727         /* VIA GFX VT7122/VX900 */
2728         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2729         /* VIA GFX VT6122/VX11 */
2730         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2731         /* SIS966 */
2732         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2733         /* ULI M5461 */
2734         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2735         /* NVIDIA MCP */
2736         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2737           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2738           .class_mask = 0xffffff,
2739           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2740         /* Teradici */
2741         { PCI_DEVICE(0x6549, 0x1200),
2742           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2743         { PCI_DEVICE(0x6549, 0x2200),
2744           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2745         /* Creative X-Fi (CA0110-IBG) */
2746         /* CTHDA chips */
2747         { PCI_DEVICE(0x1102, 0x0010),
2748           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2749         { PCI_DEVICE(0x1102, 0x0012),
2750           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2751 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2752         /* the following entry conflicts with snd-ctxfi driver,
2753          * as ctxfi driver mutates from HD-audio to native mode with
2754          * a special command sequence.
2755          */
2756         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2757           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2758           .class_mask = 0xffffff,
2759           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2760           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2761 #else
2762         /* this entry seems still valid -- i.e. without emu20kx chip */
2763         { PCI_DEVICE(0x1102, 0x0009),
2764           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2765           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2766 #endif
2767         /* CM8888 */
2768         { PCI_DEVICE(0x13f6, 0x5011),
2769           .driver_data = AZX_DRIVER_CMEDIA |
2770           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2771         /* Vortex86MX */
2772         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2773         /* VMware HDAudio */
2774         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2775         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2776         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2777           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2778           .class_mask = 0xffffff,
2779           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2780         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2781           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2782           .class_mask = 0xffffff,
2783           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2784         /* Zhaoxin */
2785         { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2786         { 0, }
2787 };
2788 MODULE_DEVICE_TABLE(pci, azx_ids);
2789
2790 /* pci_driver definition */
2791 static struct pci_driver azx_driver = {
2792         .name = KBUILD_MODNAME,
2793         .id_table = azx_ids,
2794         .probe = azx_probe,
2795         .remove = azx_remove,
2796         .shutdown = azx_shutdown,
2797         .driver = {
2798                 .pm = AZX_PM_OPS,
2799         },
2800 };
2801
2802 module_pci_driver(azx_driver);