sound/pci/hda/hda_intel.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *
   4  *  hda_intel.c - Implementation of primary alsa driver code base
   5  *                for Intel HD Audio.
   6  *
   7  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   8  *
   9  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  10  *                     PeiSen Hou <pshou@realtek.com.tw>
  11  *
  12  *  CONTACTS:
  13  *
  14  *  Matt Jared          matt.jared@intel.com
  15  *  Andy Kopp           andy.kopp@intel.com
  16  *  Dan Kogan           dan.d.kogan@intel.com
  17  *
  18  *  CHANGES:
  19  *
  20  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/mutex.h>
  33 #include <linux/io.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/clocksource.h>
  36 #include <linux/time.h>
  37 #include <linux/completion.h>
  38
  39 #ifdef CONFIG_X86
  40 /* for snoop control */
  41 #include <asm/pgtable.h>
  42 #include <asm/set_memory.h>
  43 #include <asm/cpufeature.h>
  44 #endif
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include <sound/hdaudio.h>
  48 #include <sound/hda_i915.h>
  49 #include <sound/intel-nhlt.h>
  50 #include <linux/vgaarb.h>
  51 #include <linux/vga_switcheroo.h>
  52 #include <linux/firmware.h>
  53 #include <sound/hda_codec.h>
  54 #include "hda_controller.h"
  55 #include "hda_intel.h"
  56
  57 #define CREATE_TRACE_POINTS
  58 #include "hda_intel_trace.h"
  59
  60 /* position fix mode */
  61 enum {
  62         POS_FIX_AUTO,
  63         POS_FIX_LPIB,
  64         POS_FIX_POSBUF,
  65         POS_FIX_VIACOMBO,
  66         POS_FIX_COMBO,
  67         POS_FIX_SKL,
  68         POS_FIX_FIFO,
  69 };
  70
  71 /* Defines for ATI HD Audio support in SB450 south bridge */
  72 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  73 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  74
  75 /* Defines for Nvidia HDA support */
  76 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  77 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  78 #define NVIDIA_HDA_ISTRM_COH          0x4d
  79 #define NVIDIA_HDA_OSTRM_COH          0x4c
  80 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  81
  82 /* Defines for Intel SCH HDA snoop control */
  83 #define INTEL_HDA_CGCTL  0x48
  84 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  85 #define INTEL_SCH_HDA_DEVC      0x78
  86 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  87
  88 /* Define IN stream 0 FIFO size offset in VIA controller */
  89 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
  90 /* Define VIA HD Audio Device ID*/
  91 #define VIA_HDAC_DEVICE_ID              0x3288
  92
  93 /* max number of SDs */
  94 /* ICH, ATI and VIA have 4 playback and 4 capture */
  95 #define ICH6_NUM_CAPTURE        4
  96 #define ICH6_NUM_PLAYBACK       4
  97
  98 /* ULI has 6 playback and 5 capture */
  99 #define ULI_NUM_CAPTURE         5
 100 #define ULI_NUM_PLAYBACK        6
 101
 102 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 103 #define ATIHDMI_NUM_CAPTURE     0
 104 #define ATIHDMI_NUM_PLAYBACK    8
 105
 106 /* TERA has 4 playback and 3 capture */
 107 #define TERA_NUM_CAPTURE        3
 108 #define TERA_NUM_PLAYBACK       4
 109
 110
 111 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 112 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 113 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 114 static char *model[SNDRV_CARDS];
 115 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 116 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 117 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 118 static int probe_only[SNDRV_CARDS];
 119 static int jackpoll_ms[SNDRV_CARDS];
 120 static int single_cmd = -1;
 121 static int enable_msi = -1;
 122 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 123 static char *patch[SNDRV_CARDS];
 124 #endif
 125 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 126 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 127                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 128 #endif
 129 static bool dmic_detect = IS_ENABLED(CONFIG_SND_HDA_INTEL_DETECT_DMIC);
 130
 131 module_param_array(index, int, NULL, 0444);
 132 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 133 module_param_array(id, charp, NULL, 0444);
 134 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 135 module_param_array(enable, bool, NULL, 0444);
 136 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 137 module_param_array(model, charp, NULL, 0444);
 138 MODULE_PARM_DESC(model, "Use the given board model.");
 139 module_param_array(position_fix, int, NULL, 0444);
 140 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 141                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
 142 module_param_array(bdl_pos_adj, int, NULL, 0644);
 143 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 144 module_param_array(probe_mask, int, NULL, 0444);
 145 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 146 module_param_array(probe_only, int, NULL, 0444);
 147 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 148 module_param_array(jackpoll_ms, int, NULL, 0444);
 149 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 150 module_param(single_cmd, bint, 0444);
 151 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 152                  "(for debugging only).");
 153 module_param(enable_msi, bint, 0444);
 154 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 155 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 156 module_param_array(patch, charp, NULL, 0444);
 157 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 158 #endif
 159 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 160 module_param_array(beep_mode, bool, NULL, 0444);
 161 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 162                             "(0=off, 1=on) (default=1).");
 163 #endif
 164 module_param(dmic_detect, bool, 0444);
 165 MODULE_PARM_DESC(dmic_detect, "DMIC detect on SKL+ platforms");
 166
 167 #ifdef CONFIG_PM
 168 static int param_set_xint(const char *val, const struct kernel_param *kp);
 169 static const struct kernel_param_ops param_ops_xint = {
 170         .set = param_set_xint,
 171         .get = param_get_int,
 172 };
 173 #define param_check_xint param_check_int
 174
 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 176 module_param(power_save, xint, 0644);
 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 178                  "(in second, 0 = disable).");
 179
 180 static bool pm_blacklist = true;
 181 module_param(pm_blacklist, bool, 0644);
 182 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
 183
 184 /* reset the HD-audio controller in power save mode.
 185  * this may give more power-saving, but will take longer time to
 186  * wake up.
 187  */
 188 static bool power_save_controller = 1;
 189 module_param(power_save_controller, bool, 0644);
 190 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 191 #else
 192 #define power_save      0
 193 #endif /* CONFIG_PM */
 194
 195 static int align_buffer_size = -1;
 196 module_param(align_buffer_size, bint, 0644);
 197 MODULE_PARM_DESC(align_buffer_size,
 198                 "Force buffer and period sizes to be multiple of 128 bytes.");
 199
 200 #ifdef CONFIG_X86
 201 static int hda_snoop = -1;
 202 module_param_named(snoop, hda_snoop, bint, 0444);
 203 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 204 #else
 205 #define hda_snoop               true
 206 #endif
 207
 208
 209 MODULE_LICENSE("GPL");
 210 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 211                          "{Intel, ICH6M},"
 212                          "{Intel, ICH7},"
 213                          "{Intel, ESB2},"
 214                          "{Intel, ICH8},"
 215                          "{Intel, ICH9},"
 216                          "{Intel, ICH10},"
 217                          "{Intel, PCH},"
 218                          "{Intel, CPT},"
 219                          "{Intel, PPT},"
 220                          "{Intel, LPT},"
 221                          "{Intel, LPT_LP},"
 222                          "{Intel, WPT_LP},"
 223                          "{Intel, SPT},"
 224                          "{Intel, SPT_LP},"
 225                          "{Intel, HPT},"
 226                          "{Intel, PBG},"
 227                          "{Intel, SCH},"
 228                          "{ATI, SB450},"
 229                          "{ATI, SB600},"
 230                          "{ATI, RS600},"
 231                          "{ATI, RS690},"
 232                          "{ATI, RS780},"
 233                          "{ATI, R600},"
 234                          "{ATI, RV630},"
 235                          "{ATI, RV610},"
 236                          "{ATI, RV670},"
 237                          "{ATI, RV635},"
 238                          "{ATI, RV620},"
 239                          "{ATI, RV770},"
 240                          "{VIA, VT8251},"
 241                          "{VIA, VT8237A},"
 242                          "{SiS, SIS966},"
 243                          "{ULI, M5461}}");
 244 MODULE_DESCRIPTION("Intel HDA driver");
 245
 246 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 247 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 248 #define SUPPORT_VGA_SWITCHEROO
 249 #endif
 250 #endif
 251
 252
 253 /*
 254  */
 255
 256 /* driver types */
 257 enum {
 258         AZX_DRIVER_ICH,
 259         AZX_DRIVER_PCH,
 260         AZX_DRIVER_SCH,
 261         AZX_DRIVER_SKL,
 262         AZX_DRIVER_HDMI,
 263         AZX_DRIVER_ATI,
 264         AZX_DRIVER_ATIHDMI,
 265         AZX_DRIVER_ATIHDMI_NS,
 266         AZX_DRIVER_VIA,
 267         AZX_DRIVER_SIS,
 268         AZX_DRIVER_ULI,
 269         AZX_DRIVER_NVIDIA,
 270         AZX_DRIVER_TERA,
 271         AZX_DRIVER_CTX,
 272         AZX_DRIVER_CTHDA,
 273         AZX_DRIVER_CMEDIA,
 274         AZX_DRIVER_GENERIC,
 275         AZX_NUM_DRIVERS, /* keep this as last entry */
 276 };
 277
 278 #define azx_get_snoop_type(chip) \
 279         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 281
 282 /* quirks for old Intel chipsets */
 283 #define AZX_DCAPS_INTEL_ICH \
 284         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 285
 286 /* quirks for Intel PCH */
 287 #define AZX_DCAPS_INTEL_PCH_BASE \
 288         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 289          AZX_DCAPS_SNOOP_TYPE(SCH))
 290
 291 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
 292 #define AZX_DCAPS_INTEL_PCH_NOPM \
 293         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 294
 295 /* PCH for HSW/BDW; with runtime PM */
 296 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
 297 #define AZX_DCAPS_INTEL_PCH \
 298         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 299
 300 /* HSW HDMI */
 301 #define AZX_DCAPS_INTEL_HASWELL \
 302         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 303          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 304          AZX_DCAPS_SNOOP_TYPE(SCH))
 305
 306 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 307 #define AZX_DCAPS_INTEL_BROADWELL \
 308         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 309          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
 310          AZX_DCAPS_SNOOP_TYPE(SCH))
 311
 312 #define AZX_DCAPS_INTEL_BAYTRAIL \
 313         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
 314
 315 #define AZX_DCAPS_INTEL_BRASWELL \
 316         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 317          AZX_DCAPS_I915_COMPONENT)
 318
 319 #define AZX_DCAPS_INTEL_SKYLAKE \
 320         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
 321          AZX_DCAPS_SYNC_WRITE |\
 322          AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
 323
 324 #define AZX_DCAPS_INTEL_BROXTON         AZX_DCAPS_INTEL_SKYLAKE
 325
 326 /* quirks for ATI SB / AMD Hudson */
 327 #define AZX_DCAPS_PRESET_ATI_SB \
 328         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 329          AZX_DCAPS_SNOOP_TYPE(ATI))
 330
 331 /* quirks for ATI/AMD HDMI */
 332 #define AZX_DCAPS_PRESET_ATI_HDMI \
 333         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 334          AZX_DCAPS_NO_MSI64)
 335
 336 /* quirks for ATI HDMI with snoop off */
 337 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 338         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 339
 340 /* quirks for AMD SB */
 341 #define AZX_DCAPS_PRESET_AMD_SB \
 342         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
 343          AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
 344
 345 /* quirks for Nvidia */
 346 #define AZX_DCAPS_PRESET_NVIDIA \
 347         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 348          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 349
 350 #define AZX_DCAPS_PRESET_CTHDA \
 351         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 352          AZX_DCAPS_NO_64BIT |\
 353          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 354
 355 /*
 356  * vga_switcheroo support
 357  */
 358 #ifdef SUPPORT_VGA_SWITCHEROO
 359 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 360 #define needs_eld_notify_link(chip)     ((chip)->need_eld_notify_link)
 361 #else
 362 #define use_vga_switcheroo(chip)        0
 363 #define needs_eld_notify_link(chip)     false
 364 #endif
 365
 366 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 367                                         ((pci)->device == 0x0c0c) || \
 368                                         ((pci)->device == 0x0d0c) || \
 369                                         ((pci)->device == 0x160c))
 370
 371 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 372 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
 373 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
 374
 375 static char *driver_short_names[] = {
 376         [AZX_DRIVER_ICH] = "HDA Intel",
 377         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 378         [AZX_DRIVER_SCH] = "HDA Intel MID",
 379         [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
 380         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 381         [AZX_DRIVER_ATI] = "HDA ATI SB",
 382         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 383         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 384         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 385         [AZX_DRIVER_SIS] = "HDA SIS966",
 386         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 387         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 388         [AZX_DRIVER_TERA] = "HDA Teradici",
 389         [AZX_DRIVER_CTX] = "HDA Creative",
 390         [AZX_DRIVER_CTHDA] = "HDA Creative",
 391         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 392         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 393 };
 394
 395 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 396 static void set_default_power_save(struct azx *chip);
 397
 398 /*
 399  * initialize the PCI registers
 400  */
 401 /* update bits in a PCI register byte */
 402 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 403                             unsigned char mask, unsigned char val)
 404 {
 405         unsigned char data;
 406
 407         pci_read_config_byte(pci, reg, &data);
 408         data &= ~mask;
 409         data |= (val & mask);
 410         pci_write_config_byte(pci, reg, data);
 411 }
 412
 413 static void azx_init_pci(struct azx *chip)
 414 {
 415         int snoop_type = azx_get_snoop_type(chip);
 416
 417         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 418          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 419          * Ensuring these bits are 0 clears playback static on some HD Audio
 420          * codecs.
 421          * The PCI register TCSEL is defined in the Intel manuals.
 422          */
 423         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 424                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 425                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 426         }
 427
 428         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 429          * we need to enable snoop.
 430          */
 431         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 432                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 433                         azx_snoop(chip));
 434                 update_pci_byte(chip->pci,
 435                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 436                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 437         }
 438
 439         /* For NVIDIA HDA, enable snoop */
 440         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 441                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 442                         azx_snoop(chip));
 443                 update_pci_byte(chip->pci,
 444                                 NVIDIA_HDA_TRANSREG_ADDR,
 445                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 446                 update_pci_byte(chip->pci,
 447                                 NVIDIA_HDA_ISTRM_COH,
 448                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 449                 update_pci_byte(chip->pci,
 450                                 NVIDIA_HDA_OSTRM_COH,
 451                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 452         }
 453
 454         /* Enable SCH/PCH snoop if needed */
 455         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 456                 unsigned short snoop;
 457                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 458                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 459                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 460                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 461                         if (!azx_snoop(chip))
 462                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 463                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 464                         pci_read_config_word(chip->pci,
 465                                 INTEL_SCH_HDA_DEVC, &snoop);
 466                 }
 467                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 468                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 469                         "Disabled" : "Enabled");
 470         }
 471 }
 472
 473 /*
 474  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 475  * and makes an audio stream sensitive to system latencies when
 476  * 24/32 bits are playing.
 477  * Adjusting threshold of DMA fifo to force the DMA request
 478  * sooner to improve latency tolerance at the expense of power.
 479  */
 480 static void bxt_reduce_dma_latency(struct azx *chip)
 481 {
 482         u32 val;
 483
 484         val = azx_readl(chip, VS_EM4L);
 485         val &= (0x3 << 20);
 486         azx_writel(chip, VS_EM4L, val);
 487 }
 488
 489 /*
 490  * ML_LCAP bits:
 491  *  bit 0: 6 MHz Supported
 492  *  bit 1: 12 MHz Supported
 493  *  bit 2: 24 MHz Supported
 494  *  bit 3: 48 MHz Supported
 495  *  bit 4: 96 MHz Supported
 496  *  bit 5: 192 MHz Supported
 497  */
 498 static int intel_get_lctl_scf(struct azx *chip)
 499 {
 500         struct hdac_bus *bus = azx_bus(chip);
 501         static int preferred_bits[] = { 2, 3, 1, 4, 5 };
 502         u32 val, t;
 503         int i;
 504
 505         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
 506
 507         for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
 508                 t = preferred_bits[i];
 509                 if (val & (1 << t))
 510                         return t;
 511         }
 512
 513         dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
 514         return 0;
 515 }
 516
 517 static int intel_ml_lctl_set_power(struct azx *chip, int state)
 518 {
 519         struct hdac_bus *bus = azx_bus(chip);
 520         u32 val;
 521         int timeout;
 522
 523         /*
 524          * the codecs are sharing the first link setting by default
 525          * If other links are enabled for stream, they need similar fix
 526          */
 527         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 528         val &= ~AZX_MLCTL_SPA;
 529         val |= state << AZX_MLCTL_SPA_SHIFT;
 530         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 531         /* wait for CPA */
 532         timeout = 50;
 533         while (timeout) {
 534                 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
 535                     AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
 536                         return 0;
 537                 timeout--;
 538                 udelay(10);
 539         }
 540
 541         return -1;
 542 }
 543
 544 static void intel_init_lctl(struct azx *chip)
 545 {
 546         struct hdac_bus *bus = azx_bus(chip);
 547         u32 val;
 548         int ret;
 549
 550         /* 0. check lctl register value is correct or not */
 551         val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 552         /* if SCF is already set, let's use it */
 553         if ((val & ML_LCTL_SCF_MASK) != 0)
 554                 return;
 555
 556         /*
 557          * Before operating on SPA, CPA must match SPA.
 558          * Any deviation may result in undefined behavior.
 559          */
 560         if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
 561                 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
 562                 return;
 563
 564         /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
 565         ret = intel_ml_lctl_set_power(chip, 0);
 566         udelay(100);
 567         if (ret)
 568                 goto set_spa;
 569
 570         /* 2. update SCF to select a properly audio clock*/
 571         val &= ~ML_LCTL_SCF_MASK;
 572         val |= intel_get_lctl_scf(chip);
 573         writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
 574
 575 set_spa:
 576         /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
 577         intel_ml_lctl_set_power(chip, 1);
 578         udelay(100);
 579 }
 580
 581 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 582 {
 583         struct hdac_bus *bus = azx_bus(chip);
 584         struct pci_dev *pci = chip->pci;
 585         u32 val;
 586
 587         snd_hdac_set_codec_wakeup(bus, true);
 588         if (chip->driver_type == AZX_DRIVER_SKL) {
 589                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 590                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 591                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 592         }
 593         azx_init_chip(chip, full_reset);
 594         if (chip->driver_type == AZX_DRIVER_SKL) {
 595                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 596                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 597                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 598         }
 599
 600         snd_hdac_set_codec_wakeup(bus, false);
 601
 602         /* reduce dma latency to avoid noise */
 603         if (IS_BXT(pci))
 604                 bxt_reduce_dma_latency(chip);
 605
 606         if (bus->mlcap != NULL)
 607                 intel_init_lctl(chip);
 608 }
 609
 610 /* calculate runtime delay from LPIB */
 611 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 612                                    unsigned int pos)
 613 {
 614         struct snd_pcm_substream *substream = azx_dev->core.substream;
 615         int stream = substream->stream;
 616         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 617         int delay;
 618
 619         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 620                 delay = pos - lpib_pos;
 621         else
 622                 delay = lpib_pos - pos;
 623         if (delay < 0) {
 624                 if (delay >= azx_dev->core.delay_negative_threshold)
 625                         delay = 0;
 626                 else
 627                         delay += azx_dev->core.bufsize;
 628         }
 629
 630         if (delay >= azx_dev->core.period_bytes) {
 631                 dev_info(chip->card->dev,
 632                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 633                          delay, azx_dev->core.period_bytes);
 634                 delay = 0;
 635                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 636                 chip->get_delay[stream] = NULL;
 637         }
 638
 639         return bytes_to_frames(substream->runtime, delay);
 640 }
 641
 642 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 643
 644 /* called from IRQ */
 645 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 646 {
 647         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 648         int ok;
 649
 650         ok = azx_position_ok(chip, azx_dev);
 651         if (ok == 1) {
 652                 azx_dev->irq_pending = 0;
 653                 return ok;
 654         } else if (ok == 0) {
 655                 /* bogus IRQ, process it later */
 656                 azx_dev->irq_pending = 1;
 657                 schedule_work(&hda->irq_pending_work);
 658         }
 659         return 0;
 660 }
 661
 662 #define display_power(chip, enable) \
 663         snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
 664
 665 /*
 666  * Check whether the current DMA position is acceptable for updating
 667  * periods.  Returns non-zero if it's OK.
 668  *
 669  * Many HD-audio controllers appear pretty inaccurate about
 670  * the update-IRQ timing.  The IRQ is issued before actually the
 671  * data is processed.  So, we need to process it afterwords in a
 672  * workqueue.
 673  */
 674 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 675 {
 676         struct snd_pcm_substream *substream = azx_dev->core.substream;
 677         int stream = substream->stream;
 678         u32 wallclk;
 679         unsigned int pos;
 680
 681         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 682         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 683                 return -1;      /* bogus (too early) interrupt */
 684
 685         if (chip->get_position[stream])
 686                 pos = chip->get_position[stream](chip, azx_dev);
 687         else { /* use the position buffer as default */
 688                 pos = azx_get_pos_posbuf(chip, azx_dev);
 689                 if (!pos || pos == (u32)-1) {
 690                         dev_info(chip->card->dev,
 691                                  "Invalid position buffer, using LPIB read method instead.\n");
 692                         chip->get_position[stream] = azx_get_pos_lpib;
 693                         if (chip->get_position[0] == azx_get_pos_lpib &&
 694                             chip->get_position[1] == azx_get_pos_lpib)
 695                                 azx_bus(chip)->use_posbuf = false;
 696                         pos = azx_get_pos_lpib(chip, azx_dev);
 697                         chip->get_delay[stream] = NULL;
 698                 } else {
 699                         chip->get_position[stream] = azx_get_pos_posbuf;
 700                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 701                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 702                 }
 703         }
 704
 705         if (pos >= azx_dev->core.bufsize)
 706                 pos = 0;
 707
 708         if (WARN_ONCE(!azx_dev->core.period_bytes,
 709                       "hda-intel: zero azx_dev->period_bytes"))
 710                 return -1; /* this shouldn't happen! */
 711         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 712             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 713                 /* NG - it's below the first next period boundary */
 714                 return chip->bdl_pos_adj ? 0 : -1;
 715         azx_dev->core.start_wallclk += wallclk;
 716         return 1; /* OK, it's fine */
 717 }
 718
 719 /*
 720  * The work for pending PCM period updates.
 721  */
 722 static void azx_irq_pending_work(struct work_struct *work)
 723 {
 724         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 725         struct azx *chip = &hda->chip;
 726         struct hdac_bus *bus = azx_bus(chip);
 727         struct hdac_stream *s;
 728         int pending, ok;
 729
 730         if (!hda->irq_pending_warned) {
 731                 dev_info(chip->card->dev,
 732                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 733                          chip->card->number);
 734                 hda->irq_pending_warned = 1;
 735         }
 736
 737         for (;;) {
 738                 pending = 0;
 739                 spin_lock_irq(&bus->reg_lock);
 740                 list_for_each_entry(s, &bus->stream_list, list) {
 741                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 742                         if (!azx_dev->irq_pending ||
 743                             !s->substream ||
 744                             !s->running)
 745                                 continue;
 746                         ok = azx_position_ok(chip, azx_dev);
 747                         if (ok > 0) {
 748                                 azx_dev->irq_pending = 0;
 749                                 spin_unlock(&bus->reg_lock);
 750                                 snd_pcm_period_elapsed(s->substream);
 751                                 spin_lock(&bus->reg_lock);
 752                         } else if (ok < 0) {
 753                                 pending = 0;    /* too early */
 754                         } else
 755                                 pending++;
 756                 }
 757                 spin_unlock_irq(&bus->reg_lock);
 758                 if (!pending)
 759                         return;
 760                 msleep(1);
 761         }
 762 }
 763
 764 /* clear irq_pending flags and assure no on-going workq */
 765 static void azx_clear_irq_pending(struct azx *chip)
 766 {
 767         struct hdac_bus *bus = azx_bus(chip);
 768         struct hdac_stream *s;
 769
 770         spin_lock_irq(&bus->reg_lock);
 771         list_for_each_entry(s, &bus->stream_list, list) {
 772                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 773                 azx_dev->irq_pending = 0;
 774         }
 775         spin_unlock_irq(&bus->reg_lock);
 776 }
 777
 778 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 779 {
 780         struct hdac_bus *bus = azx_bus(chip);
 781
 782         if (request_irq(chip->pci->irq, azx_interrupt,
 783                         chip->msi ? 0 : IRQF_SHARED,
 784                         chip->card->irq_descr, chip)) {
 785                 dev_err(chip->card->dev,
 786                         "unable to grab IRQ %d, disabling device\n",
 787                         chip->pci->irq);
 788                 if (do_disconnect)
 789                         snd_card_disconnect(chip->card);
 790                 return -1;
 791         }
 792         bus->irq = chip->pci->irq;
 793         pci_intx(chip->pci, !chip->msi);
 794         return 0;
 795 }
 796
 797 /* get the current DMA position with correction on VIA chips */
 798 static unsigned int azx_via_get_position(struct azx *chip,
 799                                          struct azx_dev *azx_dev)
 800 {
 801         unsigned int link_pos, mini_pos, bound_pos;
 802         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 803         unsigned int fifo_size;
 804
 805         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 806         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 807                 /* Playback, no problem using link position */
 808                 return link_pos;
 809         }
 810
 811         /* Capture */
 812         /* For new chipset,
 813          * use mod to get the DMA position just like old chipset
 814          */
 815         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 816         mod_dma_pos %= azx_dev->core.period_bytes;
 817
 818         /* azx_dev->fifo_size can't get FIFO size of in stream.
 819          * Get from base address + offset.
 820          */
 821         fifo_size = readw(azx_bus(chip)->remap_addr +
 822                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 823
 824         if (azx_dev->insufficient) {
 825                 /* Link position never gather than FIFO size */
 826                 if (link_pos <= fifo_size)
 827                         return 0;
 828
 829                 azx_dev->insufficient = 0;
 830         }
 831
 832         if (link_pos <= fifo_size)
 833                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 834         else
 835                 mini_pos = link_pos - fifo_size;
 836
 837         /* Find nearest previous boudary */
 838         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 839         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 840         if (mod_link_pos >= fifo_size)
 841                 bound_pos = link_pos - mod_link_pos;
 842         else if (mod_dma_pos >= mod_mini_pos)
 843                 bound_pos = mini_pos - mod_mini_pos;
 844         else {
 845                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 846                 if (bound_pos >= azx_dev->core.bufsize)
 847                         bound_pos = 0;
 848         }
 849
 850         /* Calculate real DMA position we want */
 851         return bound_pos + mod_dma_pos;
 852 }
 853
 854 #define AMD_FIFO_SIZE   32
 855
 856 /* get the current DMA position with FIFO size correction */
 857 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
 858 {
 859         struct snd_pcm_substream *substream = azx_dev->core.substream;
 860         struct snd_pcm_runtime *runtime = substream->runtime;
 861         unsigned int pos, delay;
 862
 863         pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 864         if (!runtime)
 865                 return pos;
 866
 867         runtime->delay = AMD_FIFO_SIZE;
 868         delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
 869         if (azx_dev->insufficient) {
 870                 if (pos < delay) {
 871                         delay = pos;
 872                         runtime->delay = bytes_to_frames(runtime, pos);
 873                 } else {
 874                         azx_dev->insufficient = 0;
 875                 }
 876         }
 877
 878         /* correct the DMA position for capture stream */
 879         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 880                 if (pos < delay)
 881                         pos += azx_dev->core.bufsize;
 882                 pos -= delay;
 883         }
 884
 885         return pos;
 886 }
 887
 888 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
 889                                    unsigned int pos)
 890 {
 891         struct snd_pcm_substream *substream = azx_dev->core.substream;
 892
 893         /* just read back the calculated value in the above */
 894         return substream->runtime->delay;
 895 }
 896
 897 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 898                                          struct azx_dev *azx_dev)
 899 {
 900         return _snd_hdac_chip_readl(azx_bus(chip),
 901                                     AZX_REG_VS_SDXDPIB_XBASE +
 902                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 903                                      azx_dev->core.index));
 904 }
 905
 906 /* get the current DMA position with correction on SKL+ chips */
 907 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 908 {
 909         /* DPIB register gives a more accurate position for playback */
 910         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 911                 return azx_skl_get_dpib_pos(chip, azx_dev);
 912
 913         /* For capture, we need to read posbuf, but it requires a delay
 914          * for the possible boundary overlap; the read of DPIB fetches the
 915          * actual posbuf
 916          */
 917         udelay(20);
 918         azx_skl_get_dpib_pos(chip, azx_dev);
 919         return azx_get_pos_posbuf(chip, azx_dev);
 920 }
 921
 922 #ifdef CONFIG_PM
 923 static DEFINE_MUTEX(card_list_lock);
 924 static LIST_HEAD(card_list);
 925
 926 static void azx_add_card_list(struct azx *chip)
 927 {
 928         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 929         mutex_lock(&card_list_lock);
 930         list_add(&hda->list, &card_list);
 931         mutex_unlock(&card_list_lock);
 932 }
 933
 934 static void azx_del_card_list(struct azx *chip)
 935 {
 936         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 937         mutex_lock(&card_list_lock);
 938         list_del_init(&hda->list);
 939         mutex_unlock(&card_list_lock);
 940 }
 941
 942 /* trigger power-save check at writing parameter */
 943 static int param_set_xint(const char *val, const struct kernel_param *kp)
 944 {
 945         struct hda_intel *hda;
 946         struct azx *chip;
 947         int prev = power_save;
 948         int ret = param_set_int(val, kp);
 949
 950         if (ret || prev == power_save)
 951                 return ret;
 952
 953         mutex_lock(&card_list_lock);
 954         list_for_each_entry(hda, &card_list, list) {
 955                 chip = &hda->chip;
 956                 if (!hda->probe_continued || chip->disabled)
 957                         continue;
 958                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 959         }
 960         mutex_unlock(&card_list_lock);
 961         return 0;
 962 }
 963
 964 /*
 965  * power management
 966  */
 967 static bool azx_is_pm_ready(struct snd_card *card)
 968 {
 969         struct azx *chip;
 970         struct hda_intel *hda;
 971
 972         if (!card)
 973                 return false;
 974         chip = card->private_data;
 975         hda = container_of(chip, struct hda_intel, chip);
 976         if (chip->disabled || hda->init_failed || !chip->running)
 977                 return false;
 978         return true;
 979 }
 980
 981 static void __azx_runtime_suspend(struct azx *chip)
 982 {
 983         azx_stop_chip(chip);
 984         azx_enter_link_reset(chip);
 985         azx_clear_irq_pending(chip);
 986         display_power(chip, false);
 987 }
 988
 989 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
 990 {
 991         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 992         struct hdac_bus *bus = azx_bus(chip);
 993         struct hda_codec *codec;
 994         int status;
 995
 996         display_power(chip, true);
 997         if (hda->need_i915_power)
 998                 snd_hdac_i915_set_bclk(bus);
 999
1000         /* Read STATESTS before controller reset */
1001         status = azx_readw(chip, STATESTS);
1002
1003         azx_init_pci(chip);
1004         hda_intel_init_chip(chip, true);
1005
1006         if (status && from_rt) {
1007                 list_for_each_codec(codec, &chip->bus)
1008                         if (status & (1 << codec->addr))
1009                                 schedule_delayed_work(&codec->jackpoll_work,
1010                                                       codec->jackpoll_interval);
1011         }
1012
1013         /* power down again for link-controlled chips */
1014         if (!hda->need_i915_power)
1015                 display_power(chip, false);
1016 }
1017
1018 #ifdef CONFIG_PM_SLEEP
1019 static int azx_suspend(struct device *dev)
1020 {
1021         struct snd_card *card = dev_get_drvdata(dev);
1022         struct azx *chip;
1023         struct hdac_bus *bus;
1024
1025         if (!azx_is_pm_ready(card))
1026                 return 0;
1027
1028         chip = card->private_data;
1029         bus = azx_bus(chip);
1030         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1031         __azx_runtime_suspend(chip);
1032         if (bus->irq >= 0) {
1033                 free_irq(bus->irq, chip);
1034                 bus->irq = -1;
1035         }
1036
1037         if (chip->msi)
1038                 pci_disable_msi(chip->pci);
1039
1040         trace_azx_suspend(chip);
1041         return 0;
1042 }
1043
1044 static int azx_resume(struct device *dev)
1045 {
1046         struct snd_card *card = dev_get_drvdata(dev);
1047         struct azx *chip;
1048
1049         if (!azx_is_pm_ready(card))
1050                 return 0;
1051
1052         chip = card->private_data;
1053         if (chip->msi)
1054                 if (pci_enable_msi(chip->pci) < 0)
1055                         chip->msi = 0;
1056         if (azx_acquire_irq(chip, 1) < 0)
1057                 return -EIO;
1058         __azx_runtime_resume(chip, false);
1059         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1060
1061         trace_azx_resume(chip);
1062         return 0;
1063 }
1064
1065 /* put codec down to D3 at hibernation for Intel SKL+;
1066  * otherwise BIOS may still access the codec and screw up the driver
1067  */
1068 static int azx_freeze_noirq(struct device *dev)
1069 {
1070         struct snd_card *card = dev_get_drvdata(dev);
1071         struct azx *chip = card->private_data;
1072         struct pci_dev *pci = to_pci_dev(dev);
1073
1074         if (chip->driver_type == AZX_DRIVER_SKL)
1075                 pci_set_power_state(pci, PCI_D3hot);
1076
1077         return 0;
1078 }
1079
1080 static int azx_thaw_noirq(struct device *dev)
1081 {
1082         struct snd_card *card = dev_get_drvdata(dev);
1083         struct azx *chip = card->private_data;
1084         struct pci_dev *pci = to_pci_dev(dev);
1085
1086         if (chip->driver_type == AZX_DRIVER_SKL)
1087                 pci_set_power_state(pci, PCI_D0);
1088
1089         return 0;
1090 }
1091 #endif /* CONFIG_PM_SLEEP */
1092
1093 static int azx_runtime_suspend(struct device *dev)
1094 {
1095         struct snd_card *card = dev_get_drvdata(dev);
1096         struct azx *chip;
1097
1098         if (!azx_is_pm_ready(card))
1099                 return 0;
1100         chip = card->private_data;
1101         if (!azx_has_pm_runtime(chip))
1102                 return 0;
1103
1104         /* enable controller wake up event */
1105         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1106                   STATESTS_INT_MASK);
1107
1108         __azx_runtime_suspend(chip);
1109         trace_azx_runtime_suspend(chip);
1110         return 0;
1111 }
1112
1113 static int azx_runtime_resume(struct device *dev)
1114 {
1115         struct snd_card *card = dev_get_drvdata(dev);
1116         struct azx *chip;
1117
1118         if (!azx_is_pm_ready(card))
1119                 return 0;
1120         chip = card->private_data;
1121         if (!azx_has_pm_runtime(chip))
1122                 return 0;
1123         __azx_runtime_resume(chip, true);
1124
1125         /* disable controller Wake Up event*/
1126         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1127                         ~STATESTS_INT_MASK);
1128
1129         trace_azx_runtime_resume(chip);
1130         return 0;
1131 }
1132
1133 static int azx_runtime_idle(struct device *dev)
1134 {
1135         struct snd_card *card = dev_get_drvdata(dev);
1136         struct azx *chip;
1137         struct hda_intel *hda;
1138
1139         if (!card)
1140                 return 0;
1141
1142         chip = card->private_data;
1143         hda = container_of(chip, struct hda_intel, chip);
1144         if (chip->disabled || hda->init_failed)
1145                 return 0;
1146
1147         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1148             azx_bus(chip)->codec_powered || !chip->running)
1149                 return -EBUSY;
1150
1151         /* ELD notification gets broken when HD-audio bus is off */
1152         if (needs_eld_notify_link(hda))
1153                 return -EBUSY;
1154
1155         return 0;
1156 }
1157
1158 static const struct dev_pm_ops azx_pm = {
1159         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1160 #ifdef CONFIG_PM_SLEEP
1161         .freeze_noirq = azx_freeze_noirq,
1162         .thaw_noirq = azx_thaw_noirq,
1163 #endif
1164         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1165 };
1166
1167 #define AZX_PM_OPS      &azx_pm
1168 #else
1169 #define azx_add_card_list(chip) /* NOP */
1170 #define azx_del_card_list(chip) /* NOP */
1171 #define AZX_PM_OPS      NULL
1172 #endif /* CONFIG_PM */
1173
1174
1175 static int azx_probe_continue(struct azx *chip);
1176
1177 #ifdef SUPPORT_VGA_SWITCHEROO
1178 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1179
1180 static void azx_vs_set_state(struct pci_dev *pci,
1181                              enum vga_switcheroo_state state)
1182 {
1183         struct snd_card *card = pci_get_drvdata(pci);
1184         struct azx *chip = card->private_data;
1185         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1186         struct hda_codec *codec;
1187         bool disabled;
1188
1189         wait_for_completion(&hda->probe_wait);
1190         if (hda->init_failed)
1191                 return;
1192
1193         disabled = (state == VGA_SWITCHEROO_OFF);
1194         if (chip->disabled == disabled)
1195                 return;
1196
1197         if (!hda->probe_continued) {
1198                 chip->disabled = disabled;
1199                 if (!disabled) {
1200                         dev_info(chip->card->dev,
1201                                  "Start delayed initialization\n");
1202                         if (azx_probe_continue(chip) < 0) {
1203                                 dev_err(chip->card->dev, "initialization error\n");
1204                                 hda->init_failed = true;
1205                         }
1206                 }
1207         } else {
1208                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1209                          disabled ? "Disabling" : "Enabling");
1210                 if (disabled) {
1211                         list_for_each_codec(codec, &chip->bus) {
1212                                 pm_runtime_suspend(hda_codec_dev(codec));
1213                                 pm_runtime_disable(hda_codec_dev(codec));
1214                         }
1215                         pm_runtime_suspend(card->dev);
1216                         pm_runtime_disable(card->dev);
1217                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1218                          * however we have no ACPI handle, so pci/acpi can't put us there,
1219                          * put ourselves there */
1220                         pci->current_state = PCI_D3cold;
1221                         chip->disabled = true;
1222                         if (snd_hda_lock_devices(&chip->bus))
1223                                 dev_warn(chip->card->dev,
1224                                          "Cannot lock devices!\n");
1225                 } else {
1226                         snd_hda_unlock_devices(&chip->bus);
1227                         chip->disabled = false;
1228                         pm_runtime_enable(card->dev);
1229                         list_for_each_codec(codec, &chip->bus) {
1230                                 pm_runtime_enable(hda_codec_dev(codec));
1231                                 pm_runtime_resume(hda_codec_dev(codec));
1232                         }
1233                 }
1234         }
1235 }
1236
1237 static bool azx_vs_can_switch(struct pci_dev *pci)
1238 {
1239         struct snd_card *card = pci_get_drvdata(pci);
1240         struct azx *chip = card->private_data;
1241         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1242
1243         wait_for_completion(&hda->probe_wait);
1244         if (hda->init_failed)
1245                 return false;
1246         if (chip->disabled || !hda->probe_continued)
1247                 return true;
1248         if (snd_hda_lock_devices(&chip->bus))
1249                 return false;
1250         snd_hda_unlock_devices(&chip->bus);
1251         return true;
1252 }
1253
1254 /*
1255  * The discrete GPU cannot power down unless the HDA controller runtime
1256  * suspends, so activate runtime PM on codecs even if power_save == 0.
1257  */
1258 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1259 {
1260         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1261         struct hda_codec *codec;
1262
1263         if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1264                 list_for_each_codec(codec, &chip->bus)
1265                         codec->auto_runtime_pm = 1;
1266                 /* reset the power save setup */
1267                 if (chip->running)
1268                         set_default_power_save(chip);
1269         }
1270 }
1271
1272 static void azx_vs_gpu_bound(struct pci_dev *pci,
1273                              enum vga_switcheroo_client_id client_id)
1274 {
1275         struct snd_card *card = pci_get_drvdata(pci);
1276         struct azx *chip = card->private_data;
1277         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1278
1279         if (client_id == VGA_SWITCHEROO_DIS)
1280                 hda->need_eld_notify_link = 0;
1281         setup_vga_switcheroo_runtime_pm(chip);
1282 }
1283
1284 static void init_vga_switcheroo(struct azx *chip)
1285 {
1286         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1287         struct pci_dev *p = get_bound_vga(chip->pci);
1288         if (p) {
1289                 dev_info(chip->card->dev,
1290                          "Handle vga_switcheroo audio client\n");
1291                 hda->use_vga_switcheroo = 1;
1292                 hda->need_eld_notify_link = 1; /* cleared in gpu_bound op */
1293                 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1294                 pci_dev_put(p);
1295         }
1296 }
1297
1298 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1299         .set_gpu_state = azx_vs_set_state,
1300         .can_switch = azx_vs_can_switch,
1301         .gpu_bound = azx_vs_gpu_bound,
1302 };
1303
1304 static int register_vga_switcheroo(struct azx *chip)
1305 {
1306         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1307         struct pci_dev *p;
1308         int err;
1309
1310         if (!hda->use_vga_switcheroo)
1311                 return 0;
1312
1313         p = get_bound_vga(chip->pci);
1314         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1315         pci_dev_put(p);
1316
1317         if (err < 0)
1318                 return err;
1319         hda->vga_switcheroo_registered = 1;
1320
1321         return 0;
1322 }
1323 #else
1324 #define init_vga_switcheroo(chip)               /* NOP */
1325 #define register_vga_switcheroo(chip)           0
1326 #define check_hdmi_disabled(pci)        false
1327 #define setup_vga_switcheroo_runtime_pm(chip)   /* NOP */
1328 #endif /* SUPPORT_VGA_SWITCHER */
1329
1330 /*
1331  * destructor
1332  */
1333 static int azx_free(struct azx *chip)
1334 {
1335         struct pci_dev *pci = chip->pci;
1336         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1337         struct hdac_bus *bus = azx_bus(chip);
1338
1339         if (azx_has_pm_runtime(chip) && chip->running)
1340                 pm_runtime_get_noresume(&pci->dev);
1341         chip->running = 0;
1342
1343         azx_del_card_list(chip);
1344
1345         hda->init_failed = 1; /* to be sure */
1346         complete_all(&hda->probe_wait);
1347
1348         if (use_vga_switcheroo(hda)) {
1349                 if (chip->disabled && hda->probe_continued)
1350                         snd_hda_unlock_devices(&chip->bus);
1351                 if (hda->vga_switcheroo_registered)
1352                         vga_switcheroo_unregister_client(chip->pci);
1353         }
1354
1355         if (bus->chip_init) {
1356                 azx_clear_irq_pending(chip);
1357                 azx_stop_all_streams(chip);
1358                 azx_stop_chip(chip);
1359         }
1360
1361         if (bus->irq >= 0)
1362                 free_irq(bus->irq, (void*)chip);
1363         if (chip->msi)
1364                 pci_disable_msi(chip->pci);
1365         iounmap(bus->remap_addr);
1366
1367         azx_free_stream_pages(chip);
1368         azx_free_streams(chip);
1369         snd_hdac_bus_exit(bus);
1370
1371         if (chip->region_requested)
1372                 pci_release_regions(chip->pci);
1373
1374         pci_disable_device(chip->pci);
1375 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1376         release_firmware(chip->fw);
1377 #endif
1378         display_power(chip, false);
1379
1380         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1381                 snd_hdac_i915_exit(bus);
1382         kfree(hda);
1383
1384         return 0;
1385 }
1386
1387 static int azx_dev_disconnect(struct snd_device *device)
1388 {
1389         struct azx *chip = device->device_data;
1390
1391         chip->bus.shutdown = 1;
1392         return 0;
1393 }
1394
1395 static int azx_dev_free(struct snd_device *device)
1396 {
1397         return azx_free(device->device_data);
1398 }
1399
1400 #ifdef SUPPORT_VGA_SWITCHEROO
1401 /*
1402  * Check of disabled HDMI controller by vga_switcheroo
1403  */
1404 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1405 {
1406         struct pci_dev *p;
1407
1408         /* check only discrete GPU */
1409         switch (pci->vendor) {
1410         case PCI_VENDOR_ID_ATI:
1411         case PCI_VENDOR_ID_AMD:
1412         case PCI_VENDOR_ID_NVIDIA:
1413                 if (pci->devfn == 1) {
1414                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1415                                                         pci->bus->number, 0);
1416                         if (p) {
1417                                 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1418                                         return p;
1419                                 pci_dev_put(p);
1420                         }
1421                 }
1422                 break;
1423         }
1424         return NULL;
1425 }
1426
1427 static bool check_hdmi_disabled(struct pci_dev *pci)
1428 {
1429         bool vga_inactive = false;
1430         struct pci_dev *p = get_bound_vga(pci);
1431
1432         if (p) {
1433                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1434                         vga_inactive = true;
1435                 pci_dev_put(p);
1436         }
1437         return vga_inactive;
1438 }
1439 #endif /* SUPPORT_VGA_SWITCHEROO */
1440
1441 /*
1442  * white/black-listing for position_fix
1443  */
1444 static struct snd_pci_quirk position_fix_list[] = {
1445         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1446         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1447         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1448         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1449         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1450         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1451         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1452         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1453         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1454         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1455         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1456         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1457         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1458         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1459         {}
1460 };
1461
1462 static int check_position_fix(struct azx *chip, int fix)
1463 {
1464         const struct snd_pci_quirk *q;
1465
1466         switch (fix) {
1467         case POS_FIX_AUTO:
1468         case POS_FIX_LPIB:
1469         case POS_FIX_POSBUF:
1470         case POS_FIX_VIACOMBO:
1471         case POS_FIX_COMBO:
1472         case POS_FIX_SKL:
1473         case POS_FIX_FIFO:
1474                 return fix;
1475         }
1476
1477         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1478         if (q) {
1479                 dev_info(chip->card->dev,
1480                          "position_fix set to %d for device %04x:%04x\n",
1481                          q->value, q->subvendor, q->subdevice);
1482                 return q->value;
1483         }
1484
1485         /* Check VIA/ATI HD Audio Controller exist */
1486         if (chip->driver_type == AZX_DRIVER_VIA) {
1487                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1488                 return POS_FIX_VIACOMBO;
1489         }
1490         if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1491                 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1492                 return POS_FIX_FIFO;
1493         }
1494         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1495                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1496                 return POS_FIX_LPIB;
1497         }
1498         if (chip->driver_type == AZX_DRIVER_SKL) {
1499                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1500                 return POS_FIX_SKL;
1501         }
1502         return POS_FIX_AUTO;
1503 }
1504
1505 static void assign_position_fix(struct azx *chip, int fix)
1506 {
1507         static azx_get_pos_callback_t callbacks[] = {
1508                 [POS_FIX_AUTO] = NULL,
1509                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1510                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1511                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1512                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1513                 [POS_FIX_SKL] = azx_get_pos_skl,
1514                 [POS_FIX_FIFO] = azx_get_pos_fifo,
1515         };
1516
1517         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1518
1519         /* combo mode uses LPIB only for playback */
1520         if (fix == POS_FIX_COMBO)
1521                 chip->get_position[1] = NULL;
1522
1523         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1524             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1525                 chip->get_delay[0] = chip->get_delay[1] =
1526                         azx_get_delay_from_lpib;
1527         }
1528
1529         if (fix == POS_FIX_FIFO)
1530                 chip->get_delay[0] = chip->get_delay[1] =
1531                         azx_get_delay_from_fifo;
1532 }
1533
1534 /*
1535  * black-lists for probe_mask
1536  */
1537 static struct snd_pci_quirk probe_mask_list[] = {
1538         /* Thinkpad often breaks the controller communication when accessing
1539          * to the non-working (or non-existing) modem codec slot.
1540          */
1541         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1542         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1543         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1544         /* broken BIOS */
1545         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1546         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1547         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1548         /* forced codec slots */
1549         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1550         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1551         /* WinFast VP200 H (Teradici) user reported broken communication */
1552         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1553         {}
1554 };
1555
1556 #define AZX_FORCE_CODEC_MASK    0x100
1557
1558 static void check_probe_mask(struct azx *chip, int dev)
1559 {
1560         const struct snd_pci_quirk *q;
1561
1562         chip->codec_probe_mask = probe_mask[dev];
1563         if (chip->codec_probe_mask == -1) {
1564                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1565                 if (q) {
1566                         dev_info(chip->card->dev,
1567                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1568                                  q->value, q->subvendor, q->subdevice);
1569                         chip->codec_probe_mask = q->value;
1570                 }
1571         }
1572
1573         /* check forced option */
1574         if (chip->codec_probe_mask != -1 &&
1575             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1576                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1577                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1578                          (int)azx_bus(chip)->codec_mask);
1579         }
1580 }
1581
1582 /*
1583  * white/black-list for enable_msi
1584  */
1585 static struct snd_pci_quirk msi_black_list[] = {
1586         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1587         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1588         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1589         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1590         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1591         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1592         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1593         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1594         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1595         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1596         {}
1597 };
1598
1599 static void check_msi(struct azx *chip)
1600 {
1601         const struct snd_pci_quirk *q;
1602
1603         if (enable_msi >= 0) {
1604                 chip->msi = !!enable_msi;
1605                 return;
1606         }
1607         chip->msi = 1;  /* enable MSI as default */
1608         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1609         if (q) {
1610                 dev_info(chip->card->dev,
1611                          "msi for device %04x:%04x set to %d\n",
1612                          q->subvendor, q->subdevice, q->value);
1613                 chip->msi = q->value;
1614                 return;
1615         }
1616
1617         /* NVidia chipsets seem to cause troubles with MSI */
1618         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1619                 dev_info(chip->card->dev, "Disabling MSI\n");
1620                 chip->msi = 0;
1621         }
1622 }
1623
1624 /* check the snoop mode availability */
1625 static void azx_check_snoop_available(struct azx *chip)
1626 {
1627         int snoop = hda_snoop;
1628
1629         if (snoop >= 0) {
1630                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1631                          snoop ? "snoop" : "non-snoop");
1632                 chip->snoop = snoop;
1633                 chip->uc_buffer = !snoop;
1634                 return;
1635         }
1636
1637         snoop = true;
1638         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1639             chip->driver_type == AZX_DRIVER_VIA) {
1640                 /* force to non-snoop mode for a new VIA controller
1641                  * when BIOS is set
1642                  */
1643                 u8 val;
1644                 pci_read_config_byte(chip->pci, 0x42, &val);
1645                 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1646                                       chip->pci->revision == 0x20))
1647                         snoop = false;
1648         }
1649
1650         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1651                 snoop = false;
1652
1653         chip->snoop = snoop;
1654         if (!snoop) {
1655                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1656                 /* C-Media requires non-cached pages only for CORB/RIRB */
1657                 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1658                         chip->uc_buffer = true;
1659         }
1660 }
1661
1662 static void azx_probe_work(struct work_struct *work)
1663 {
1664         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1665         azx_probe_continue(&hda->chip);
1666 }
1667
1668 static int default_bdl_pos_adj(struct azx *chip)
1669 {
1670         /* some exceptions: Atoms seem problematic with value 1 */
1671         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1672                 switch (chip->pci->device) {
1673                 case 0x0f04: /* Baytrail */
1674                 case 0x2284: /* Braswell */
1675                         return 32;
1676                 }
1677         }
1678
1679         switch (chip->driver_type) {
1680         case AZX_DRIVER_ICH:
1681         case AZX_DRIVER_PCH:
1682                 return 1;
1683         default:
1684                 return 32;
1685         }
1686 }
1687
1688 /*
1689  * constructor
1690  */
1691 static const struct hda_controller_ops pci_hda_ops;
1692
1693 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1694                       int dev, unsigned int driver_caps,
1695                       struct azx **rchip)
1696 {
1697         static struct snd_device_ops ops = {
1698                 .dev_disconnect = azx_dev_disconnect,
1699                 .dev_free = azx_dev_free,
1700         };
1701         struct hda_intel *hda;
1702         struct azx *chip;
1703         int err;
1704
1705         *rchip = NULL;
1706
1707         err = pci_enable_device(pci);
1708         if (err < 0)
1709                 return err;
1710
1711         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1712         if (!hda) {
1713                 pci_disable_device(pci);
1714                 return -ENOMEM;
1715         }
1716
1717         chip = &hda->chip;
1718         mutex_init(&chip->open_mutex);
1719         chip->card = card;
1720         chip->pci = pci;
1721         chip->ops = &pci_hda_ops;
1722         chip->driver_caps = driver_caps;
1723         chip->driver_type = driver_caps & 0xff;
1724         check_msi(chip);
1725         chip->dev_index = dev;
1726         if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1727                 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1728         INIT_LIST_HEAD(&chip->pcm_list);
1729         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1730         INIT_LIST_HEAD(&hda->list);
1731         init_vga_switcheroo(chip);
1732         init_completion(&hda->probe_wait);
1733
1734         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1735
1736         check_probe_mask(chip, dev);
1737
1738         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1739                 chip->fallback_to_single_cmd = 1;
1740         else /* explicitly set to single_cmd or not */
1741                 chip->single_cmd = single_cmd;
1742
1743         azx_check_snoop_available(chip);
1744
1745         if (bdl_pos_adj[dev] < 0)
1746                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1747         else
1748                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1749
1750         err = azx_bus_init(chip, model[dev]);
1751         if (err < 0) {
1752                 kfree(hda);
1753                 pci_disable_device(pci);
1754                 return err;
1755         }
1756
1757         /* use the non-cached pages in non-snoop mode */
1758         if (!azx_snoop(chip))
1759                 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC;
1760
1761         /* Workaround for a communication error on CFL (bko#199007) and CNL */
1762         if (IS_CFL(pci) || IS_CNL(pci))
1763                 azx_bus(chip)->polling_mode = 1;
1764
1765         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1766                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1767                 chip->bus.needs_damn_long_delay = 1;
1768         }
1769
1770         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1771         if (err < 0) {
1772                 dev_err(card->dev, "Error creating device [card]!\n");
1773                 azx_free(chip);
1774                 return err;
1775         }
1776
1777         /* continue probing in work context as may trigger request module */
1778         INIT_WORK(&hda->probe_work, azx_probe_work);
1779
1780         *rchip = chip;
1781
1782         return 0;
1783 }
1784
1785 static int azx_first_init(struct azx *chip)
1786 {
1787         int dev = chip->dev_index;
1788         struct pci_dev *pci = chip->pci;
1789         struct snd_card *card = chip->card;
1790         struct hdac_bus *bus = azx_bus(chip);
1791         int err;
1792         unsigned short gcap;
1793         unsigned int dma_bits = 64;
1794
1795 #if BITS_PER_LONG != 64
1796         /* Fix up base address on ULI M5461 */
1797         if (chip->driver_type == AZX_DRIVER_ULI) {
1798                 u16 tmp3;
1799                 pci_read_config_word(pci, 0x40, &tmp3);
1800                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1801                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1802         }
1803 #endif
1804
1805         err = pci_request_regions(pci, "ICH HD audio");
1806         if (err < 0)
1807                 return err;
1808         chip->region_requested = 1;
1809
1810         bus->addr = pci_resource_start(pci, 0);
1811         bus->remap_addr = pci_ioremap_bar(pci, 0);
1812         if (bus->remap_addr == NULL) {
1813                 dev_err(card->dev, "ioremap error\n");
1814                 return -ENXIO;
1815         }
1816
1817         if (chip->driver_type == AZX_DRIVER_SKL)
1818                 snd_hdac_bus_parse_capabilities(bus);
1819
1820         /*
1821          * Some Intel CPUs has always running timer (ART) feature and
1822          * controller may have Global time sync reporting capability, so
1823          * check both of these before declaring synchronized time reporting
1824          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1825          */
1826         chip->gts_present = false;
1827
1828 #ifdef CONFIG_X86
1829         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1830                 chip->gts_present = true;
1831 #endif
1832
1833         if (chip->msi) {
1834                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1835                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1836                         pci->no_64bit_msi = true;
1837                 }
1838                 if (pci_enable_msi(pci) < 0)
1839                         chip->msi = 0;
1840         }
1841
1842         pci_set_master(pci);
1843         synchronize_irq(bus->irq);
1844
1845         gcap = azx_readw(chip, GCAP);
1846         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1847
1848         /* AMD devices support 40 or 48bit DMA, take the safe one */
1849         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1850                 dma_bits = 40;
1851
1852         /* disable SB600 64bit support for safety */
1853         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1854                 struct pci_dev *p_smbus;
1855                 dma_bits = 40;
1856                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1857                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1858                                          NULL);
1859                 if (p_smbus) {
1860                         if (p_smbus->revision < 0x30)
1861                                 gcap &= ~AZX_GCAP_64OK;
1862                         pci_dev_put(p_smbus);
1863                 }
1864         }
1865
1866         /* NVidia hardware normally only supports up to 40 bits of DMA */
1867         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1868                 dma_bits = 40;
1869
1870         /* disable 64bit DMA address on some devices */
1871         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1872                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1873                 gcap &= ~AZX_GCAP_64OK;
1874         }
1875
1876         /* disable buffer size rounding to 128-byte multiples if supported */
1877         if (align_buffer_size >= 0)
1878                 chip->align_buffer_size = !!align_buffer_size;
1879         else {
1880                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1881                         chip->align_buffer_size = 0;
1882                 else
1883                         chip->align_buffer_size = 1;
1884         }
1885
1886         /* allow 64bit DMA address if supported by H/W */
1887         if (!(gcap & AZX_GCAP_64OK))
1888                 dma_bits = 32;
1889         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1890                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1891         } else {
1892                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1893                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1894         }
1895
1896         /* read number of streams from GCAP register instead of using
1897          * hardcoded value
1898          */
1899         chip->capture_streams = (gcap >> 8) & 0x0f;
1900         chip->playback_streams = (gcap >> 12) & 0x0f;
1901         if (!chip->playback_streams && !chip->capture_streams) {
1902                 /* gcap didn't give any info, switching to old method */
1903
1904                 switch (chip->driver_type) {
1905                 case AZX_DRIVER_ULI:
1906                         chip->playback_streams = ULI_NUM_PLAYBACK;
1907                         chip->capture_streams = ULI_NUM_CAPTURE;
1908                         break;
1909                 case AZX_DRIVER_ATIHDMI:
1910                 case AZX_DRIVER_ATIHDMI_NS:
1911                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1912                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1913                         break;
1914                 case AZX_DRIVER_GENERIC:
1915                 default:
1916                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1917                         chip->capture_streams = ICH6_NUM_CAPTURE;
1918                         break;
1919                 }
1920         }
1921         chip->capture_index_offset = 0;
1922         chip->playback_index_offset = chip->capture_streams;
1923         chip->num_streams = chip->playback_streams + chip->capture_streams;
1924
1925         /* sanity check for the SDxCTL.STRM field overflow */
1926         if (chip->num_streams > 15 &&
1927             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1928                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1929                          "forcing separate stream tags", chip->num_streams);
1930                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1931         }
1932
1933         /* initialize streams */
1934         err = azx_init_streams(chip);
1935         if (err < 0)
1936                 return err;
1937
1938         err = azx_alloc_stream_pages(chip);
1939         if (err < 0)
1940                 return err;
1941
1942         /* initialize chip */
1943         azx_init_pci(chip);
1944
1945         snd_hdac_i915_set_bclk(bus);
1946
1947         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1948
1949         /* codec detection */
1950         if (!azx_bus(chip)->codec_mask) {
1951                 dev_err(card->dev, "no codecs found!\n");
1952                 return -ENODEV;
1953         }
1954
1955         if (azx_acquire_irq(chip, 0) < 0)
1956                 return -EBUSY;
1957
1958         strcpy(card->driver, "HDA-Intel");
1959         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1960                 sizeof(card->shortname));
1961         snprintf(card->longname, sizeof(card->longname),
1962                  "%s at 0x%lx irq %i",
1963                  card->shortname, bus->addr, bus->irq);
1964
1965         return 0;
1966 }
1967
1968 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1969 /* callback from request_firmware_nowait() */
1970 static void azx_firmware_cb(const struct firmware *fw, void *context)
1971 {
1972         struct snd_card *card = context;
1973         struct azx *chip = card->private_data;
1974         struct pci_dev *pci = chip->pci;
1975
1976         if (!fw) {
1977                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1978                 goto error;
1979         }
1980
1981         chip->fw = fw;
1982         if (!chip->disabled) {
1983                 /* continue probing */
1984                 if (azx_probe_continue(chip))
1985                         goto error;
1986         }
1987         return; /* OK */
1988
1989  error:
1990         snd_card_free(card);
1991         pci_set_drvdata(pci, NULL);
1992 }
1993 #endif
1994
1995 static int disable_msi_reset_irq(struct azx *chip)
1996 {
1997         struct hdac_bus *bus = azx_bus(chip);
1998         int err;
1999
2000         free_irq(bus->irq, chip);
2001         bus->irq = -1;
2002         pci_disable_msi(chip->pci);
2003         chip->msi = 0;
2004         err = azx_acquire_irq(chip, 1);
2005         if (err < 0)
2006                 return err;
2007
2008         return 0;
2009 }
2010
2011 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2012                              struct vm_area_struct *area)
2013 {
2014 #ifdef CONFIG_X86
2015         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2016         struct azx *chip = apcm->chip;
2017         if (chip->uc_buffer)
2018                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2019 #endif
2020 }
2021
2022 static const struct hda_controller_ops pci_hda_ops = {
2023         .disable_msi_reset_irq = disable_msi_reset_irq,
2024         .pcm_mmap_prepare = pcm_mmap_prepare,
2025         .position_check = azx_position_check,
2026 };
2027
2028 static int azx_check_dmic(struct pci_dev *pci, struct azx *chip)
2029 {
2030         struct nhlt_acpi_table *nhlt;
2031         int ret = 0;
2032
2033         if (chip->driver_type == AZX_DRIVER_SKL &&
2034             pci->class != 0x040300) {
2035                 nhlt = intel_nhlt_init(&pci->dev);
2036                 if (nhlt) {
2037                         if (intel_nhlt_get_dmic_geo(&pci->dev, nhlt)) {
2038                                 ret = -ENODEV;
2039                                 dev_info(&pci->dev, "Digital mics found on Skylake+ platform, aborting probe\n");
2040                         }
2041                         intel_nhlt_free(nhlt);
2042                 }
2043         }
2044         return ret;
2045 }
2046
2047 static int azx_probe(struct pci_dev *pci,
2048                      const struct pci_device_id *pci_id)
2049 {
2050         static int dev;
2051         struct snd_card *card;
2052         struct hda_intel *hda;
2053         struct azx *chip;
2054         bool schedule_probe;
2055         int err;
2056
2057         if (dev >= SNDRV_CARDS)
2058                 return -ENODEV;
2059         if (!enable[dev]) {
2060                 dev++;
2061                 return -ENOENT;
2062         }
2063
2064         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2065                            0, &card);
2066         if (err < 0) {
2067                 dev_err(&pci->dev, "Error creating card!\n");
2068                 return err;
2069         }
2070
2071         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2072         if (err < 0)
2073                 goto out_free;
2074         card->private_data = chip;
2075         hda = container_of(chip, struct hda_intel, chip);
2076
2077         /*
2078          * stop probe if digital microphones detected on Skylake+ platform
2079          * with the DSP enabled. This is an opt-in behavior defined at build
2080          * time or at run-time with a module parameter
2081          */
2082         if (dmic_detect) {
2083                 err = azx_check_dmic(pci, chip);
2084                 if (err < 0)
2085                         goto out_free;
2086         }
2087
2088         pci_set_drvdata(pci, card);
2089
2090         err = register_vga_switcheroo(chip);
2091         if (err < 0) {
2092                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2093                 goto out_free;
2094         }
2095
2096         if (check_hdmi_disabled(pci)) {
2097                 dev_info(card->dev, "VGA controller is disabled\n");
2098                 dev_info(card->dev, "Delaying initialization\n");
2099                 chip->disabled = true;
2100         }
2101
2102         schedule_probe = !chip->disabled;
2103
2104 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2105         if (patch[dev] && *patch[dev]) {
2106                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2107                          patch[dev]);
2108                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2109                                               &pci->dev, GFP_KERNEL, card,
2110                                               azx_firmware_cb);
2111                 if (err < 0)
2112                         goto out_free;
2113                 schedule_probe = false; /* continued in azx_firmware_cb() */
2114         }
2115 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2116
2117 #ifndef CONFIG_SND_HDA_I915
2118         if (CONTROLLER_IN_GPU(pci))
2119                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2120 #endif
2121
2122         if (schedule_probe)
2123                 schedule_work(&hda->probe_work);
2124
2125         dev++;
2126         if (chip->disabled)
2127                 complete_all(&hda->probe_wait);
2128         return 0;
2129
2130 out_free:
2131         snd_card_free(card);
2132         return err;
2133 }
2134
2135 #ifdef CONFIG_PM
2136 /* On some boards setting power_save to a non 0 value leads to clicking /
2137  * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2138  * figure out how to avoid these sounds, but that is not always feasible.
2139  * So we keep a list of devices where we disable powersaving as its known
2140  * to causes problems on these devices.
2141  */
2142 static struct snd_pci_quirk power_save_blacklist[] = {
2143         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2144         SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2145         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2146         SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2147         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2148         SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2149         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2150         SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2151         /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2152         SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2153         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2154         SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2155         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2156         /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2157         SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2158         /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2159         SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2160         /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2161         SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2162         /* https://bugs.launchpad.net/bugs/1821663 */
2163         SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2164         /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2165         SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2166         /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2167         SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2168         /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2169         SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2170         /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2171         SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2172         /* https://bugs.launchpad.net/bugs/1821663 */
2173         SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2174         {}
2175 };
2176 #endif /* CONFIG_PM */
2177
2178 static void set_default_power_save(struct azx *chip)
2179 {
2180         int val = power_save;
2181
2182 #ifdef CONFIG_PM
2183         if (pm_blacklist) {
2184                 const struct snd_pci_quirk *q;
2185
2186                 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2187                 if (q && val) {
2188                         dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2189                                  q->subvendor, q->subdevice);
2190                         val = 0;
2191                 }
2192         }
2193 #endif /* CONFIG_PM */
2194         snd_hda_set_power_save(&chip->bus, val * 1000);
2195 }
2196
2197 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2198 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2199         [AZX_DRIVER_NVIDIA] = 8,
2200         [AZX_DRIVER_TERA] = 1,
2201 };
2202
2203 static int azx_probe_continue(struct azx *chip)
2204 {
2205         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2206         struct hdac_bus *bus = azx_bus(chip);
2207         struct pci_dev *pci = chip->pci;
2208         int dev = chip->dev_index;
2209         int err;
2210
2211         to_hda_bus(bus)->bus_probing = 1;
2212         hda->probe_continued = 1;
2213
2214         /* bind with i915 if needed */
2215         if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2216                 err = snd_hdac_i915_init(bus);
2217                 if (err < 0) {
2218                         /* if the controller is bound only with HDMI/DP
2219                          * (for HSW and BDW), we need to abort the probe;
2220                          * for other chips, still continue probing as other
2221                          * codecs can be on the same link.
2222                          */
2223                         if (CONTROLLER_IN_GPU(pci)) {
2224                                 dev_err(chip->card->dev,
2225                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2226                                 goto out_free;
2227                         } else {
2228                                 /* don't bother any longer */
2229                                 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2230                         }
2231                 }
2232
2233                 /* HSW/BDW controllers need this power */
2234                 if (CONTROLLER_IN_GPU(pci))
2235                         hda->need_i915_power = 1;
2236         }
2237
2238         /* Request display power well for the HDA controller or codec. For
2239          * Haswell/Broadwell, both the display HDA controller and codec need
2240          * this power. For other platforms, like Baytrail/Braswell, only the
2241          * display codec needs the power and it can be released after probe.
2242          */
2243         display_power(chip, true);
2244
2245         err = azx_first_init(chip);
2246         if (err < 0)
2247                 goto out_free;
2248
2249 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2250         chip->beep_mode = beep_mode[dev];
2251 #endif
2252
2253         /* create codec instances */
2254         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2255         if (err < 0)
2256                 goto out_free;
2257
2258 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2259         if (chip->fw) {
2260                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2261                                          chip->fw->data);
2262                 if (err < 0)
2263                         goto out_free;
2264 #ifndef CONFIG_PM
2265                 release_firmware(chip->fw); /* no longer needed */
2266                 chip->fw = NULL;
2267 #endif
2268         }
2269 #endif
2270         if ((probe_only[dev] & 1) == 0) {
2271                 err = azx_codec_configure(chip);
2272                 if (err < 0)
2273                         goto out_free;
2274         }
2275
2276         err = snd_card_register(chip->card);
2277         if (err < 0)
2278                 goto out_free;
2279
2280         setup_vga_switcheroo_runtime_pm(chip);
2281
2282         chip->running = 1;
2283         azx_add_card_list(chip);
2284
2285         set_default_power_save(chip);
2286
2287         if (azx_has_pm_runtime(chip))
2288                 pm_runtime_put_autosuspend(&pci->dev);
2289
2290 out_free:
2291         if (err < 0 || !hda->need_i915_power)
2292                 display_power(chip, false);
2293         if (err < 0)
2294                 hda->init_failed = 1;
2295         complete_all(&hda->probe_wait);
2296         to_hda_bus(bus)->bus_probing = 0;
2297         return err;
2298 }
2299
2300 static void azx_remove(struct pci_dev *pci)
2301 {
2302         struct snd_card *card = pci_get_drvdata(pci);
2303         struct azx *chip;
2304         struct hda_intel *hda;
2305
2306         if (card) {
2307                 /* cancel the pending probing work */
2308                 chip = card->private_data;
2309                 hda = container_of(chip, struct hda_intel, chip);
2310                 /* FIXME: below is an ugly workaround.
2311                  * Both device_release_driver() and driver_probe_device()
2312                  * take *both* the device's and its parent's lock before
2313                  * calling the remove() and probe() callbacks.  The codec
2314                  * probe takes the locks of both the codec itself and its
2315                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2316                  * the PCI controller is unbound, it takes its lock, too
2317                  * ==> ouch, a deadlock!
2318                  * As a workaround, we unlock temporarily here the controller
2319                  * device during cancel_work_sync() call.
2320                  */
2321                 device_unlock(&pci->dev);
2322                 cancel_work_sync(&hda->probe_work);
2323                 device_lock(&pci->dev);
2324
2325                 snd_card_free(card);
2326         }
2327 }
2328
2329 static void azx_shutdown(struct pci_dev *pci)
2330 {
2331         struct snd_card *card = pci_get_drvdata(pci);
2332         struct azx *chip;
2333
2334         if (!card)
2335                 return;
2336         chip = card->private_data;
2337         if (chip && chip->running)
2338                 azx_stop_chip(chip);
2339 }
2340
2341 /* PCI IDs */
2342 static const struct pci_device_id azx_ids[] = {
2343         /* CPT */
2344         { PCI_DEVICE(0x8086, 0x1c20),
2345           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2346         /* PBG */
2347         { PCI_DEVICE(0x8086, 0x1d20),
2348           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2349         /* Panther Point */
2350         { PCI_DEVICE(0x8086, 0x1e20),
2351           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2352         /* Lynx Point */
2353         { PCI_DEVICE(0x8086, 0x8c20),
2354           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2355         /* 9 Series */
2356         { PCI_DEVICE(0x8086, 0x8ca0),
2357           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2358         /* Wellsburg */
2359         { PCI_DEVICE(0x8086, 0x8d20),
2360           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2361         { PCI_DEVICE(0x8086, 0x8d21),
2362           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2363         /* Lewisburg */
2364         { PCI_DEVICE(0x8086, 0xa1f0),
2365           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2366         { PCI_DEVICE(0x8086, 0xa270),
2367           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2368         /* Lynx Point-LP */
2369         { PCI_DEVICE(0x8086, 0x9c20),
2370           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2371         /* Lynx Point-LP */
2372         { PCI_DEVICE(0x8086, 0x9c21),
2373           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2374         /* Wildcat Point-LP */
2375         { PCI_DEVICE(0x8086, 0x9ca0),
2376           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2377         /* Sunrise Point */
2378         { PCI_DEVICE(0x8086, 0xa170),
2379           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2380         /* Sunrise Point-LP */
2381         { PCI_DEVICE(0x8086, 0x9d70),
2382           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2383         /* Kabylake */
2384         { PCI_DEVICE(0x8086, 0xa171),
2385           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2386         /* Kabylake-LP */
2387         { PCI_DEVICE(0x8086, 0x9d71),
2388           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2389         /* Kabylake-H */
2390         { PCI_DEVICE(0x8086, 0xa2f0),
2391           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2392         /* Coffelake */
2393         { PCI_DEVICE(0x8086, 0xa348),
2394           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2395         /* Cannonlake */
2396         { PCI_DEVICE(0x8086, 0x9dc8),
2397           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2398         /* CometLake-LP */
2399         { PCI_DEVICE(0x8086, 0x02C8),
2400           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2401         /* CometLake-H */
2402         { PCI_DEVICE(0x8086, 0x06C8),
2403           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2404         /* Icelake */
2405         { PCI_DEVICE(0x8086, 0x34c8),
2406           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2407         /* Elkhart Lake */
2408         { PCI_DEVICE(0x8086, 0x4b55),
2409           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2410         /* Broxton-P(Apollolake) */
2411         { PCI_DEVICE(0x8086, 0x5a98),
2412           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2413         /* Broxton-T */
2414         { PCI_DEVICE(0x8086, 0x1a98),
2415           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2416         /* Gemini-Lake */
2417         { PCI_DEVICE(0x8086, 0x3198),
2418           .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2419         /* Haswell */
2420         { PCI_DEVICE(0x8086, 0x0a0c),
2421           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2422         { PCI_DEVICE(0x8086, 0x0c0c),
2423           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2424         { PCI_DEVICE(0x8086, 0x0d0c),
2425           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2426         /* Broadwell */
2427         { PCI_DEVICE(0x8086, 0x160c),
2428           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2429         /* 5 Series/3400 */
2430         { PCI_DEVICE(0x8086, 0x3b56),
2431           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2432         /* Poulsbo */
2433         { PCI_DEVICE(0x8086, 0x811b),
2434           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2435         /* Oaktrail */
2436         { PCI_DEVICE(0x8086, 0x080a),
2437           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2438         /* BayTrail */
2439         { PCI_DEVICE(0x8086, 0x0f04),
2440           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2441         /* Braswell */
2442         { PCI_DEVICE(0x8086, 0x2284),
2443           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2444         /* ICH6 */
2445         { PCI_DEVICE(0x8086, 0x2668),
2446           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2447         /* ICH7 */
2448         { PCI_DEVICE(0x8086, 0x27d8),
2449           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2450         /* ESB2 */
2451         { PCI_DEVICE(0x8086, 0x269a),
2452           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2453         /* ICH8 */
2454         { PCI_DEVICE(0x8086, 0x284b),
2455           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2456         /* ICH9 */
2457         { PCI_DEVICE(0x8086, 0x293e),
2458           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2459         /* ICH9 */
2460         { PCI_DEVICE(0x8086, 0x293f),
2461           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2462         /* ICH10 */
2463         { PCI_DEVICE(0x8086, 0x3a3e),
2464           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2465         /* ICH10 */
2466         { PCI_DEVICE(0x8086, 0x3a6e),
2467           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2468         /* Generic Intel */
2469         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2470           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2471           .class_mask = 0xffffff,
2472           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2473         /* ATI SB 450/600/700/800/900 */
2474         { PCI_DEVICE(0x1002, 0x437b),
2475           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2476         { PCI_DEVICE(0x1002, 0x4383),
2477           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2478         /* AMD Hudson */
2479         { PCI_DEVICE(0x1022, 0x780d),
2480           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2481         /* AMD, X370 & co */
2482         { PCI_DEVICE(0x1022, 0x1457),
2483           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2484         /* AMD, X570 & co */
2485         { PCI_DEVICE(0x1022, 0x1487),
2486           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2487         /* AMD Stoney */
2488         { PCI_DEVICE(0x1022, 0x157a),
2489           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2490                          AZX_DCAPS_PM_RUNTIME },
2491         /* AMD Raven */
2492         { PCI_DEVICE(0x1022, 0x15e3),
2493           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2494                          AZX_DCAPS_PM_RUNTIME },
2495         /* ATI HDMI */
2496         { PCI_DEVICE(0x1002, 0x0002),
2497           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2498         { PCI_DEVICE(0x1002, 0x1308),
2499           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2500         { PCI_DEVICE(0x1002, 0x157a),
2501           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2502         { PCI_DEVICE(0x1002, 0x15b3),
2503           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2504         { PCI_DEVICE(0x1002, 0x793b),
2505           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2506         { PCI_DEVICE(0x1002, 0x7919),
2507           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2508         { PCI_DEVICE(0x1002, 0x960f),
2509           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2510         { PCI_DEVICE(0x1002, 0x970f),
2511           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2512         { PCI_DEVICE(0x1002, 0x9840),
2513           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2514         { PCI_DEVICE(0x1002, 0xaa00),
2515           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2516         { PCI_DEVICE(0x1002, 0xaa08),
2517           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2518         { PCI_DEVICE(0x1002, 0xaa10),
2519           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2520         { PCI_DEVICE(0x1002, 0xaa18),
2521           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2522         { PCI_DEVICE(0x1002, 0xaa20),
2523           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2524         { PCI_DEVICE(0x1002, 0xaa28),
2525           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2526         { PCI_DEVICE(0x1002, 0xaa30),
2527           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2528         { PCI_DEVICE(0x1002, 0xaa38),
2529           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2530         { PCI_DEVICE(0x1002, 0xaa40),
2531           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2532         { PCI_DEVICE(0x1002, 0xaa48),
2533           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2534         { PCI_DEVICE(0x1002, 0xaa50),
2535           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2536         { PCI_DEVICE(0x1002, 0xaa58),
2537           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2538         { PCI_DEVICE(0x1002, 0xaa60),
2539           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2540         { PCI_DEVICE(0x1002, 0xaa68),
2541           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2542         { PCI_DEVICE(0x1002, 0xaa80),
2543           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2544         { PCI_DEVICE(0x1002, 0xaa88),
2545           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2546         { PCI_DEVICE(0x1002, 0xaa90),
2547           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2548         { PCI_DEVICE(0x1002, 0xaa98),
2549           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2550         { PCI_DEVICE(0x1002, 0x9902),
2551           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2552         { PCI_DEVICE(0x1002, 0xaaa0),
2553           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2554         { PCI_DEVICE(0x1002, 0xaaa8),
2555           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2556         { PCI_DEVICE(0x1002, 0xaab0),
2557           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2558         { PCI_DEVICE(0x1002, 0xaac0),
2559           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2560         { PCI_DEVICE(0x1002, 0xaac8),
2561           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2562         { PCI_DEVICE(0x1002, 0xaad8),
2563           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2564         { PCI_DEVICE(0x1002, 0xaae8),
2565           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2566         { PCI_DEVICE(0x1002, 0xaae0),
2567           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2568         { PCI_DEVICE(0x1002, 0xaaf0),
2569           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2570         /* VIA VT8251/VT8237A */
2571         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2572         /* VIA GFX VT7122/VX900 */
2573         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2574         /* VIA GFX VT6122/VX11 */
2575         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2576         /* SIS966 */
2577         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2578         /* ULI M5461 */
2579         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2580         /* NVIDIA MCP */
2581         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2582           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2583           .class_mask = 0xffffff,
2584           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2585         /* Teradici */
2586         { PCI_DEVICE(0x6549, 0x1200),
2587           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2588         { PCI_DEVICE(0x6549, 0x2200),
2589           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2590         /* Creative X-Fi (CA0110-IBG) */
2591         /* CTHDA chips */
2592         { PCI_DEVICE(0x1102, 0x0010),
2593           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2594         { PCI_DEVICE(0x1102, 0x0012),
2595           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2596 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2597         /* the following entry conflicts with snd-ctxfi driver,
2598          * as ctxfi driver mutates from HD-audio to native mode with
2599          * a special command sequence.
2600          */
2601         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2602           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2603           .class_mask = 0xffffff,
2604           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2605           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2606 #else
2607         /* this entry seems still valid -- i.e. without emu20kx chip */
2608         { PCI_DEVICE(0x1102, 0x0009),
2609           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2610           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2611 #endif
2612         /* CM8888 */
2613         { PCI_DEVICE(0x13f6, 0x5011),
2614           .driver_data = AZX_DRIVER_CMEDIA |
2615           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2616         /* Vortex86MX */
2617         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2618         /* VMware HDAudio */
2619         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2620         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2621         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2622           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2623           .class_mask = 0xffffff,
2624           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2625         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2626           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2627           .class_mask = 0xffffff,
2628           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2629         { 0, }
2630 };
2631 MODULE_DEVICE_TABLE(pci, azx_ids);
2632
2633 /* pci_driver definition */
2634 static struct pci_driver azx_driver = {
2635         .name = KBUILD_MODNAME,
2636         .id_table = azx_ids,
2637         .probe = azx_probe,
2638         .remove = azx_remove,
2639         .shutdown = azx_shutdown,
2640         .driver = {
2641                 .pm = AZX_PM_OPS,
2642         },
2643 };
2644
2645 module_pci_driver(azx_driver);