1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
5 * Routines for control of EMU10K1 chips
14 #include <linux/time.h>
15 #include <sound/core.h>
16 #include <sound/emu10k1.h>
17 #include <linux/delay.h>
18 #include <linux/export.h>
21 static inline bool check_ptr_reg(struct snd_emu10k1 *emu, unsigned int reg)
25 if (snd_BUG_ON(reg & (emu->audigy ? (0xffff0000 & ~A_PTR_ADDRESS_MASK)
26 : (0xffff0000 & ~PTR_ADDRESS_MASK))))
28 if (snd_BUG_ON(reg & 0x0000ffff & ~PTR_CHANNELNUM_MASK))
33 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn)
36 unsigned int regptr, val;
39 regptr = (reg << 16) | chn;
40 if (!check_ptr_reg(emu, regptr))
43 spin_lock_irqsave(&emu->emu_lock, flags);
44 outl(regptr, emu->port + PTR);
45 val = inl(emu->port + DATA);
46 spin_unlock_irqrestore(&emu->emu_lock, flags);
48 if (reg & 0xff000000) {
49 unsigned char size, offset;
51 size = (reg >> 24) & 0x3f;
52 offset = (reg >> 16) & 0x1f;
53 mask = (1 << size) - 1;
55 return (val >> offset) & mask;
61 EXPORT_SYMBOL(snd_emu10k1_ptr_read);
63 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data)
69 regptr = (reg << 16) | chn;
70 if (!check_ptr_reg(emu, regptr))
73 if (reg & 0xff000000) {
74 unsigned char size, offset;
76 size = (reg >> 24) & 0x3f;
77 offset = (reg >> 16) & 0x1f;
78 mask = (1 << size) - 1;
79 if (snd_BUG_ON(data & ~mask))
84 spin_lock_irqsave(&emu->emu_lock, flags);
85 outl(regptr, emu->port + PTR);
86 data |= inl(emu->port + DATA) & ~mask;
88 spin_lock_irqsave(&emu->emu_lock, flags);
89 outl(regptr, emu->port + PTR);
91 outl(data, emu->port + DATA);
92 spin_unlock_irqrestore(&emu->emu_lock, flags);
95 EXPORT_SYMBOL(snd_emu10k1_ptr_write);
97 void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...)
103 if (snd_BUG_ON(!emu))
105 if (snd_BUG_ON(chn & ~PTR_CHANNELNUM_MASK))
107 addr_mask = ~((emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK) >> 16);
110 spin_lock_irqsave(&emu->emu_lock, flags);
113 u32 reg = va_arg(va, u32);
114 if (reg == REGLIST_END)
116 data = va_arg(va, u32);
117 if (snd_BUG_ON(reg & addr_mask)) // Only raw registers supported here
119 outl((reg << 16) | chn, emu->port + PTR);
120 outl(data, emu->port + DATA);
122 spin_unlock_irqrestore(&emu->emu_lock, flags);
126 EXPORT_SYMBOL(snd_emu10k1_ptr_write_multiple);
128 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu,
133 unsigned int regptr, val;
135 regptr = (reg << 16) | chn;
137 spin_lock_irqsave(&emu->emu_lock, flags);
138 outl(regptr, emu->port + PTR2);
139 val = inl(emu->port + DATA2);
140 spin_unlock_irqrestore(&emu->emu_lock, flags);
144 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu,
152 regptr = (reg << 16) | chn;
154 spin_lock_irqsave(&emu->emu_lock, flags);
155 outl(regptr, emu->port + PTR2);
156 outl(data, emu->port + DATA2);
157 spin_unlock_irqrestore(&emu->emu_lock, flags);
160 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu,
163 unsigned int reset, set;
164 unsigned int reg, tmp;
168 /* This function is not re-entrant, so protect against it. */
169 spin_lock(&emu->spi_lock);
170 if (emu->card_capabilities->ca0108_chip)
173 /* For other chip types the SPI register
174 * is currently unknown. */
179 /* Only 16bit values allowed */
184 tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
185 reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */
186 set = reset | 0x10000; /* Set xxx1xxxx */
187 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
188 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */
189 snd_emu10k1_ptr20_write(emu, reg, 0, set | data);
191 /* Wait for status bit to return to 0 */
192 for (n = 0; n < 100; n++) {
194 tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
195 if (!(tmp & 0x10000)) {
205 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
206 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */
209 spin_unlock(&emu->spi_lock);
213 /* The ADC does not support i2c read, so only write is implemented */
214 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu,
224 if ((reg > 0x7f) || (value > 0x1ff)) {
225 dev_err(emu->card->dev, "i2c_write: invalid values.\n");
229 /* This function is not re-entrant, so protect against it. */
230 spin_lock(&emu->i2c_lock);
232 tmp = reg << 25 | value << 16;
234 /* This controls the I2C connected to the WM8775 ADC Codec */
235 snd_emu10k1_ptr20_write(emu, P17V_I2C_1, 0, tmp);
236 tmp = snd_emu10k1_ptr20_read(emu, P17V_I2C_1, 0); /* write post */
238 for (retry = 0; retry < 10; retry++) {
239 /* Send the data to i2c */
241 tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD);
242 snd_emu10k1_ptr20_write(emu, P17V_I2C_ADDR, 0, tmp);
244 /* Wait till the transaction ends */
247 status = snd_emu10k1_ptr20_read(emu, P17V_I2C_ADDR, 0);
249 if ((status & I2C_A_ADC_START) == 0)
252 if (timeout > 1000) {
253 dev_warn(emu->card->dev,
254 "emu10k1:I2C:timeout status=0x%x\n",
259 //Read back and see if the transaction is successful
260 if ((status & I2C_A_ADC_ABORT) == 0)
265 dev_err(emu->card->dev, "Writing to ADC failed!\n");
266 dev_err(emu->card->dev, "status=0x%x, reg=%d, value=%d\n",
272 spin_unlock(&emu->i2c_lock);
276 static void snd_emu1010_fpga_write_locked(struct snd_emu10k1 *emu, u32 reg, u32 value)
278 if (snd_BUG_ON(reg > 0x3f))
280 reg += 0x40; /* 0x40 upwards are registers. */
281 if (snd_BUG_ON(value > 0x3f)) /* 0 to 0x3f are values */
283 outw(reg, emu->port + A_GPIO);
285 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
287 outw(value, emu->port + A_GPIO);
289 outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
292 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value)
296 spin_lock_irqsave(&emu->emu_lock, flags);
297 snd_emu1010_fpga_write_locked(emu, reg, value);
298 spin_unlock_irqrestore(&emu->emu_lock, flags);
301 static void snd_emu1010_fpga_read_locked(struct snd_emu10k1 *emu, u32 reg, u32 *value)
303 // The higest input pin is used as the designated interrupt trigger,
304 // so it needs to be masked out.
305 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f;
306 if (snd_BUG_ON(reg > 0x3f))
308 reg += 0x40; /* 0x40 upwards are registers. */
309 outw(reg, emu->port + A_GPIO);
311 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
313 *value = ((inw(emu->port + A_GPIO) >> 8) & mask);
316 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value)
320 spin_lock_irqsave(&emu->emu_lock, flags);
321 snd_emu1010_fpga_read_locked(emu, reg, value);
322 spin_unlock_irqrestore(&emu->emu_lock, flags);
325 /* Each Destination has one and only one Source,
326 * but one Source can feed any number of Destinations simultaneously.
328 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src)
332 if (snd_BUG_ON(dst & ~0x71f))
334 if (snd_BUG_ON(src & ~0x71f))
336 spin_lock_irqsave(&emu->emu_lock, flags);
337 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8);
338 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f);
339 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8);
340 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f);
341 spin_unlock_irqrestore(&emu->emu_lock, flags);
344 u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst)
349 if (snd_BUG_ON(dst & ~0x71f))
351 spin_lock_irqsave(&emu->emu_lock, flags);
352 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8);
353 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f);
354 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCHI, &hi);
355 snd_emu1010_fpga_read_locked(emu, EMU_HANA_SRCLO, &lo);
356 spin_unlock_irqrestore(&emu->emu_lock, flags);
357 return (hi << 8) | lo;
360 void snd_emu1010_update_clock(struct snd_emu10k1 *emu)
364 switch (emu->emu1010.wclock) {
365 case EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X:
366 leds = EMU_HANA_DOCK_LEDS_2_44K;
368 case EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X:
369 leds = EMU_HANA_DOCK_LEDS_2_48K;
372 leds = EMU_HANA_DOCK_LEDS_2_EXT;
376 // FIXME: this should probably represent the AND of all currently
377 // used sources' lock status. But we don't know how to get that ...
378 leds |= EMU_HANA_DOCK_LEDS_2_LOCK;
380 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, leds);
383 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb)
388 spin_lock_irqsave(&emu->emu_lock, flags);
389 enable = inl(emu->port + INTE) | intrenb;
390 outl(enable, emu->port + INTE);
391 spin_unlock_irqrestore(&emu->emu_lock, flags);
394 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb)
399 spin_lock_irqsave(&emu->emu_lock, flags);
400 enable = inl(emu->port + INTE) & ~intrenb;
401 outl(enable, emu->port + INTE);
402 spin_unlock_irqrestore(&emu->emu_lock, flags);
405 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum)
410 spin_lock_irqsave(&emu->emu_lock, flags);
411 if (voicenum >= 32) {
412 outl(CLIEH << 16, emu->port + PTR);
413 val = inl(emu->port + DATA);
414 val |= 1 << (voicenum - 32);
416 outl(CLIEL << 16, emu->port + PTR);
417 val = inl(emu->port + DATA);
418 val |= 1 << voicenum;
420 outl(val, emu->port + DATA);
421 spin_unlock_irqrestore(&emu->emu_lock, flags);
424 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum)
429 spin_lock_irqsave(&emu->emu_lock, flags);
430 if (voicenum >= 32) {
431 outl(CLIEH << 16, emu->port + PTR);
432 val = inl(emu->port + DATA);
433 val &= ~(1 << (voicenum - 32));
435 outl(CLIEL << 16, emu->port + PTR);
436 val = inl(emu->port + DATA);
437 val &= ~(1 << voicenum);
439 outl(val, emu->port + DATA);
440 spin_unlock_irqrestore(&emu->emu_lock, flags);
443 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum)
447 spin_lock_irqsave(&emu->emu_lock, flags);
448 if (voicenum >= 32) {
449 outl(CLIPH << 16, emu->port + PTR);
450 voicenum = 1 << (voicenum - 32);
452 outl(CLIPL << 16, emu->port + PTR);
453 voicenum = 1 << voicenum;
455 outl(voicenum, emu->port + DATA);
456 spin_unlock_irqrestore(&emu->emu_lock, flags);
459 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum)
464 spin_lock_irqsave(&emu->emu_lock, flags);
465 if (voicenum >= 32) {
466 outl(HLIEH << 16, emu->port + PTR);
467 val = inl(emu->port + DATA);
468 val |= 1 << (voicenum - 32);
470 outl(HLIEL << 16, emu->port + PTR);
471 val = inl(emu->port + DATA);
472 val |= 1 << voicenum;
474 outl(val, emu->port + DATA);
475 spin_unlock_irqrestore(&emu->emu_lock, flags);
478 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum)
483 spin_lock_irqsave(&emu->emu_lock, flags);
484 if (voicenum >= 32) {
485 outl(HLIEH << 16, emu->port + PTR);
486 val = inl(emu->port + DATA);
487 val &= ~(1 << (voicenum - 32));
489 outl(HLIEL << 16, emu->port + PTR);
490 val = inl(emu->port + DATA);
491 val &= ~(1 << voicenum);
493 outl(val, emu->port + DATA);
494 spin_unlock_irqrestore(&emu->emu_lock, flags);
497 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum)
501 spin_lock_irqsave(&emu->emu_lock, flags);
502 if (voicenum >= 32) {
503 outl(HLIPH << 16, emu->port + PTR);
504 voicenum = 1 << (voicenum - 32);
506 outl(HLIPL << 16, emu->port + PTR);
507 voicenum = 1 << voicenum;
509 outl(voicenum, emu->port + DATA);
510 spin_unlock_irqrestore(&emu->emu_lock, flags);
514 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum)
519 spin_lock_irqsave(&emu->emu_lock, flags);
520 if (voicenum >= 32) {
521 outl(SOLEH << 16, emu->port + PTR);
522 sol = inl(emu->port + DATA);
523 sol |= 1 << (voicenum - 32);
525 outl(SOLEL << 16, emu->port + PTR);
526 sol = inl(emu->port + DATA);
527 sol |= 1 << voicenum;
529 outl(sol, emu->port + DATA);
530 spin_unlock_irqrestore(&emu->emu_lock, flags);
533 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum)
538 spin_lock_irqsave(&emu->emu_lock, flags);
539 if (voicenum >= 32) {
540 outl(SOLEH << 16, emu->port + PTR);
541 sol = inl(emu->port + DATA);
542 sol &= ~(1 << (voicenum - 32));
544 outl(SOLEL << 16, emu->port + PTR);
545 sol = inl(emu->port + DATA);
546 sol &= ~(1 << voicenum);
548 outl(sol, emu->port + DATA);
549 spin_unlock_irqrestore(&emu->emu_lock, flags);
553 void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices)
557 spin_lock_irqsave(&emu->emu_lock, flags);
558 outl(SOLEL << 16, emu->port + PTR);
559 outl(inl(emu->port + DATA) | (u32)voices, emu->port + DATA);
560 outl(SOLEH << 16, emu->port + PTR);
561 outl(inl(emu->port + DATA) | (u32)(voices >> 32), emu->port + DATA);
562 spin_unlock_irqrestore(&emu->emu_lock, flags);
565 void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices)
569 spin_lock_irqsave(&emu->emu_lock, flags);
570 outl(SOLEL << 16, emu->port + PTR);
571 outl(inl(emu->port + DATA) & (u32)~voices, emu->port + DATA);
572 outl(SOLEH << 16, emu->port + PTR);
573 outl(inl(emu->port + DATA) & (u32)(~voices >> 32), emu->port + DATA);
574 spin_unlock_irqrestore(&emu->emu_lock, flags);
577 int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices)
583 spin_lock_irqsave(&emu->emu_lock, flags);
585 outl(SOLEL << 16, emu->port + PTR);
586 soll = inl(emu->port + DATA);
587 outl(SOLEH << 16, emu->port + PTR);
588 solh = inl(emu->port + DATA);
590 soll &= (u32)~voices;
591 solh &= (u32)(~voices >> 32);
593 for (int tries = 0; tries < 1000; tries++) {
594 const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2);
595 // First we wait for the third quarter of the sample cycle ...
596 u32 wc = inl(emu->port + WC);
597 u32 cc = REG_VAL_GET(WC_CURRENTCHANNEL, wc);
598 if (cc >= quart * 2 && cc < quart * 3) {
599 // ... and release the low voices, while the high ones are serviced.
600 outl(SOLEL << 16, emu->port + PTR);
601 outl(soll, emu->port + DATA);
602 // Then we wait for the first quarter of the next sample cycle ...
603 for (; tries < 1000; tries++) {
604 cc = REG_VAL_GET(WC_CURRENTCHANNEL, inl(emu->port + WC));
607 // We will block for 10+ us with interrupts disabled. This is
608 // not nice at all, but necessary for reasonable reliability.
613 // ... and release the high voices, while the low ones are serviced.
614 outl(SOLEH << 16, emu->port + PTR);
615 outl(solh, emu->port + DATA);
616 // Finally we verify that nothing interfered in fact.
617 if (REG_VAL_GET(WC_SAMPLECOUNTER, inl(emu->port + WC)) ==
618 ((REG_VAL_GET(WC_SAMPLECOUNTER, wc) + 1) & REG_MASK0(WC_SAMPLECOUNTER))) {
625 // Don't block for too long
626 spin_unlock_irqrestore(&emu->emu_lock, flags);
628 spin_lock_irqsave(&emu->emu_lock, flags);
631 spin_unlock_irqrestore(&emu->emu_lock, flags);
635 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait)
637 volatile unsigned count;
638 unsigned int newtime = 0, curtime;
640 curtime = inl(emu->port + WC) >> 6;
643 while (count++ < 16384) {
644 newtime = inl(emu->port + WC) >> 6;
645 if (newtime != curtime)
654 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
656 struct snd_emu10k1 *emu = ac97->private_data;
660 spin_lock_irqsave(&emu->emu_lock, flags);
661 outb(reg, emu->port + AC97ADDRESS);
662 val = inw(emu->port + AC97DATA);
663 spin_unlock_irqrestore(&emu->emu_lock, flags);
667 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data)
669 struct snd_emu10k1 *emu = ac97->private_data;
672 spin_lock_irqsave(&emu->emu_lock, flags);
673 outb(reg, emu->port + AC97ADDRESS);
674 outw(data, emu->port + AC97DATA);
675 spin_unlock_irqrestore(&emu->emu_lock, flags);