sound/pci/cmipci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
   4  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
   5  */
   6
   7 /* Does not work. Warning may block system in capture mode */
   8 /* #define USE_VAR48KRATE */
   9
  10 #include <linux/io.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/slab.h>
  16 #include <linux/gameport.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <sound/core.h>
  20 #include <sound/info.h>
  21 #include <sound/control.h>
  22 #include <sound/pcm.h>
  23 #include <sound/rawmidi.h>
  24 #include <sound/mpu401.h>
  25 #include <sound/opl3.h>
  26 #include <sound/sb.h>
  27 #include <sound/asoundef.h>
  28 #include <sound/initval.h>
  29
  30 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  31 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  32 MODULE_LICENSE("GPL");
  33 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
  34                 "{C-Media,CMI8738B},"
  35                 "{C-Media,CMI8338A},"
  36                 "{C-Media,CMI8338B}}");
  37
  38 #if IS_REACHABLE(CONFIG_GAMEPORT)
  39 #define SUPPORT_JOYSTICK 1
  40 #endif
  41
  42 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  43 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  44 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  45 static long mpu_port[SNDRV_CARDS];
  46 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  47 static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  48 #ifdef SUPPORT_JOYSTICK
  49 static int joystick_port[SNDRV_CARDS];
  50 #endif
  51
  52 module_param_array(index, int, NULL, 0444);
  53 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  54 module_param_array(id, charp, NULL, 0444);
  55 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  56 module_param_array(enable, bool, NULL, 0444);
  57 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  58 module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
  59 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  60 module_param_hw_array(fm_port, long, ioport, NULL, 0444);
  61 MODULE_PARM_DESC(fm_port, "FM port.");
  62 module_param_array(soft_ac3, bool, NULL, 0444);
  63 MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
  64 #ifdef SUPPORT_JOYSTICK
  65 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  66 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  67 #endif
  68
  69 /*
  70  * CM8x38 registers definition
  71  */
  72
  73 #define CM_REG_FUNCTRL0         0x00
  74 #define CM_RST_CH1              0x00080000
  75 #define CM_RST_CH0              0x00040000
  76 #define CM_CHEN1                0x00020000      /* ch1: enable */
  77 #define CM_CHEN0                0x00010000      /* ch0: enable */
  78 #define CM_PAUSE1               0x00000008      /* ch1: pause */
  79 #define CM_PAUSE0               0x00000004      /* ch0: pause */
  80 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
  81 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
  82
  83 #define CM_REG_FUNCTRL1         0x04
  84 #define CM_DSFC_MASK            0x0000E000      /* channel 1 (DAC?) sampling frequency */
  85 #define CM_DSFC_SHIFT           13
  86 #define CM_ASFC_MASK            0x00001C00      /* channel 0 (ADC?) sampling frequency */
  87 #define CM_ASFC_SHIFT           10
  88 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
  89 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
  90 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/IN -> OUT loopback */
  91 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
  92 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
  93 #define CM_BREQ                 0x00000010      /* bus master enabled */
  94 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
  95 #define CM_UART_EN              0x00000004      /* legacy UART */
  96 #define CM_JYSTK_EN             0x00000002      /* legacy joystick */
  97 #define CM_ZVPORT               0x00000001      /* ZVPORT */
  98
  99 #define CM_REG_CHFORMAT         0x08
 100
 101 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
 102 #define CM_FMOFFSET2            0x40000000      /* initial FM PCM offset 2 when Fmute=1 */
 103 #define CM_CHB3D                0x20000000      /* 4 channels */
 104
 105 #define CM_CHIP_MASK1           0x1f000000
 106 #define CM_CHIP_037             0x01000000
 107 #define CM_SETLAT48             0x00800000      /* set latency timer 48h */
 108 #define CM_EDGEIRQ              0x00400000      /* emulated edge trigger legacy IRQ */
 109 #define CM_SPD24SEL39           0x00200000      /* 24-bit spdif: model 039 */
 110 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
 111 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
 112 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
 113 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
 114
 115 #define CM_ADCBITLEN_MASK       0x0000C000
 116 #define CM_ADCBITLEN_16         0x00000000
 117 #define CM_ADCBITLEN_15         0x00004000
 118 #define CM_ADCBITLEN_14         0x00008000
 119 #define CM_ADCBITLEN_13         0x0000C000
 120
 121 #define CM_ADCDACLEN_MASK       0x00003000      /* model 037 */
 122 #define CM_ADCDACLEN_060        0x00000000
 123 #define CM_ADCDACLEN_066        0x00001000
 124 #define CM_ADCDACLEN_130        0x00002000
 125 #define CM_ADCDACLEN_280        0x00003000
 126
 127 #define CM_ADCDLEN_MASK         0x00003000      /* model 039 */
 128 #define CM_ADCDLEN_ORIGINAL     0x00000000
 129 #define CM_ADCDLEN_EXTRA        0x00001000
 130 #define CM_ADCDLEN_24K          0x00002000
 131 #define CM_ADCDLEN_WEIGHT       0x00003000
 132
 133 #define CM_CH1_SRATE_176K       0x00000800
 134 #define CM_CH1_SRATE_96K        0x00000800      /* model 055? */
 135 #define CM_CH1_SRATE_88K        0x00000400
 136 #define CM_CH0_SRATE_176K       0x00000200
 137 #define CM_CH0_SRATE_96K        0x00000200      /* model 055? */
 138 #define CM_CH0_SRATE_88K        0x00000100
 139 #define CM_CH0_SRATE_128K       0x00000300
 140 #define CM_CH0_SRATE_MASK       0x00000300
 141
 142 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
 143 #define CM_DBLSPDS              0x00000040      /* double SPDIF sample rate 88.2/96 */
 144 #define CM_POLVALID             0x00000020      /* inverse SPDIF/IN valid bit */
 145 #define CM_SPDLOCKED            0x00000010
 146
 147 #define CM_CH1FMT_MASK          0x0000000C      /* bit 3: 16 bits, bit 2: stereo */
 148 #define CM_CH1FMT_SHIFT         2
 149 #define CM_CH0FMT_MASK          0x00000003      /* bit 1: 16 bits, bit 0: stereo */
 150 #define CM_CH0FMT_SHIFT         0
 151
 152 #define CM_REG_INT_HLDCLR       0x0C
 153 #define CM_CHIP_MASK2           0xff000000
 154 #define CM_CHIP_8768            0x20000000
 155 #define CM_CHIP_055             0x08000000
 156 #define CM_CHIP_039             0x04000000
 157 #define CM_CHIP_039_6CH         0x01000000
 158 #define CM_UNKNOWN_INT_EN       0x00080000      /* ? */
 159 #define CM_TDMA_INT_EN          0x00040000
 160 #define CM_CH1_INT_EN           0x00020000
 161 #define CM_CH0_INT_EN           0x00010000
 162
 163 #define CM_REG_INT_STATUS       0x10
 164 #define CM_INTR                 0x80000000
 165 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
 166 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
 167 #define CM_UARTINT              0x00010000
 168 #define CM_LTDMAINT             0x00008000
 169 #define CM_HTDMAINT             0x00004000
 170 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
 171 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
 172 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
 173 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
 174 #define CM_CH1BUSY              0x00000008
 175 #define CM_CH0BUSY              0x00000004
 176 #define CM_CHINT1               0x00000002
 177 #define CM_CHINT0               0x00000001
 178
 179 #define CM_REG_LEGACY_CTRL      0x14
 180 #define CM_NXCHG                0x80000000      /* don't map base reg dword->sample */
 181 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
 182 #define CM_VMPU_330             0x00000000
 183 #define CM_VMPU_320             0x20000000
 184 #define CM_VMPU_310             0x40000000
 185 #define CM_VMPU_300             0x60000000
 186 #define CM_ENWR8237             0x10000000      /* enable bus master to write 8237 base reg */
 187 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
 188 #define CM_VSBSEL_220           0x00000000
 189 #define CM_VSBSEL_240           0x04000000
 190 #define CM_VSBSEL_260           0x08000000
 191 #define CM_VSBSEL_280           0x0C000000
 192 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
 193 #define CM_FMSEL_388            0x00000000
 194 #define CM_FMSEL_3C8            0x01000000
 195 #define CM_FMSEL_3E0            0x02000000
 196 #define CM_FMSEL_3E8            0x03000000
 197 #define CM_ENSPDOUT             0x00800000      /* enable XSPDIF/OUT to I/O interface */
 198 #define CM_SPDCOPYRHT           0x00400000      /* spdif in/out copyright bit */
 199 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
 200 #define CM_INVIDWEN             0x00100000      /* internal vendor ID write enable, model 039? */
 201 #define CM_SETRETRY             0x00100000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
 202 #define CM_C_EEACCESS           0x00080000      /* direct programming eeprom regs */
 203 #define CM_C_EECS               0x00040000
 204 #define CM_C_EEDI46             0x00020000
 205 #define CM_C_EECK46             0x00010000
 206 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
 207 #define CM_CENTR2LIN            0x00004000      /* line-in as center out */
 208 #define CM_BASE2LIN             0x00002000      /* line-in as bass out */
 209 #define CM_EXBASEN              0x00001000      /* external bass input enable */
 210
 211 #define CM_REG_MISC_CTRL        0x18
 212 #define CM_PWD                  0x80000000      /* power down */
 213 #define CM_RESET                0x40000000
 214 #define CM_SFIL_MASK            0x30000000      /* filter control at front end DAC, model 037? */
 215 #define CM_VMGAIN               0x10000000      /* analog master amp +6dB, model 039? */
 216 #define CM_TXVX                 0x08000000      /* model 037? */
 217 #define CM_N4SPK3D              0x04000000      /* copy front to rear */
 218 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
 219 #define CM_SPDIF48K             0x01000000      /* write */
 220 #define CM_SPATUS48K            0x01000000      /* read */
 221 #define CM_ENDBDAC              0x00800000      /* enable double dac */
 222 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
 223 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
 224 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-OUT -> int. IN */
 225 #define CM_FM_EN                0x00080000      /* enable legacy FM */
 226 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
 227 #define CM_ENWRASID             0x00010000      /* choose writable internal SUBID (audio) */
 228 #define CM_VIDWPDSB             0x00010000      /* model 037? */
 229 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
 230 #define CM_MASK_EN              0x00004000      /* activate channel mask on legacy DMA */
 231 #define CM_ENWRMSID             0x00002000      /* choose writable internal SUBID (modem) */
 232 #define CM_VIDWPPRT             0x00002000      /* model 037? */
 233 #define CM_SFILENB              0x00001000      /* filter stepping at front end DAC, model 037? */
 234 #define CM_MMODE_MASK           0x00000E00      /* model DAA interface mode */
 235 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
 236 #define CM_ENCENTER             0x00000080
 237 #define CM_FLINKON              0x00000040      /* force modem link detection on, model 037 */
 238 #define CM_MUTECH1              0x00000040      /* mute PCI ch1 to DAC */
 239 #define CM_FLINKOFF             0x00000020      /* force modem link detection off, model 037 */
 240 #define CM_MIDSMP               0x00000010      /* 1/2 interpolation at front end DAC */
 241 #define CM_UPDDMA_MASK          0x0000000C      /* TDMA position update notification */
 242 #define CM_UPDDMA_2048          0x00000000
 243 #define CM_UPDDMA_1024          0x00000004
 244 #define CM_UPDDMA_512           0x00000008
 245 #define CM_UPDDMA_256           0x0000000C
 246 #define CM_TWAIT_MASK           0x00000003      /* model 037 */
 247 #define CM_TWAIT1               0x00000002      /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
 248 #define CM_TWAIT0               0x00000001      /* i/o cycle, 0: 4, 1: 6 PCICLKs */
 249
 250 #define CM_REG_TDMA_POSITION    0x1C
 251 #define CM_TDMA_CNT_MASK        0xFFFF0000      /* current byte/word count */
 252 #define CM_TDMA_ADR_MASK        0x0000FFFF      /* current address */
 253
 254         /* byte */
 255 #define CM_REG_MIXER0           0x20
 256 #define CM_REG_SBVR             0x20            /* write: sb16 version */
 257 #define CM_REG_DEV              0x20            /* read: hardware device version */
 258
 259 #define CM_REG_MIXER21          0x21
 260 #define CM_UNKNOWN_21_MASK      0x78            /* ? */
 261 #define CM_X_ADPCM              0x04            /* SB16 ADPCM enable */
 262 #define CM_PROINV               0x02            /* SBPro left/right channel switching */
 263 #define CM_X_SB16               0x01            /* SB16 compatible */
 264
 265 #define CM_REG_SB16_DATA        0x22
 266 #define CM_REG_SB16_ADDR        0x23
 267
 268 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
 269 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
 270 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
 271 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
 272
 273 #define CM_REG_MIXER1           0x24
 274 #define CM_FMMUTE               0x80    /* mute FM */
 275 #define CM_FMMUTE_SHIFT         7
 276 #define CM_WSMUTE               0x40    /* mute PCM */
 277 #define CM_WSMUTE_SHIFT         6
 278 #define CM_REAR2LIN             0x20    /* lin-in -> rear line out */
 279 #define CM_REAR2LIN_SHIFT       5
 280 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
 281 #define CM_REAR2FRONT_SHIFT     4
 282 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
 283 #define CM_WAVEINL_SHIFT        3
 284 #define CM_WAVEINR              0x04    /* digical wave rec. right */
 285 #define CM_WAVEINR_SHIFT        2
 286 #define CM_X3DEN                0x02    /* 3D surround enable */
 287 #define CM_X3DEN_SHIFT          1
 288 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
 289 #define CM_CDPLAY_SHIFT         0
 290
 291 #define CM_REG_MIXER2           0x25
 292 #define CM_RAUXREN              0x80    /* AUX right capture */
 293 #define CM_RAUXREN_SHIFT        7
 294 #define CM_RAUXLEN              0x40    /* AUX left capture */
 295 #define CM_RAUXLEN_SHIFT        6
 296 #define CM_VAUXRM               0x20    /* AUX right mute */
 297 #define CM_VAUXRM_SHIFT         5
 298 #define CM_VAUXLM               0x10    /* AUX left mute */
 299 #define CM_VAUXLM_SHIFT         4
 300 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
 301 #define CM_VADMIC_SHIFT         1
 302 #define CM_MICGAINZ             0x01    /* mic boost */
 303 #define CM_MICGAINZ_SHIFT       0
 304
 305 #define CM_REG_MIXER3           0x24
 306 #define CM_REG_AUX_VOL          0x26
 307 #define CM_VAUXL_MASK           0xf0
 308 #define CM_VAUXR_MASK           0x0f
 309
 310 #define CM_REG_MISC             0x27
 311 #define CM_UNKNOWN_27_MASK      0xd8    /* ? */
 312 #define CM_XGPO1                0x20
 313 // #define CM_XGPBIO            0x04
 314 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
 315 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
 316 #define CM_SPDVALID             0x02    /* spdif input valid check */
 317 #define CM_DMAUTO               0x01    /* SB16 DMA auto detect */
 318
 319 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
 320 /*
 321  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
 322  * or identical with AC97 codec?
 323  */
 324 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
 325
 326 /*
 327  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
 328  */
 329 #define CM_REG_MPU_PCI          0x40
 330
 331 /*
 332  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
 333  */
 334 #define CM_REG_FM_PCI           0x50
 335
 336 /*
 337  * access from SB-mixer port
 338  */
 339 #define CM_REG_EXTENT_IND       0xf0
 340 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
 341 #define CM_VPHONE_SHIFT         5
 342 #define CM_VPHOM                0x10    /* Phone mute control */
 343 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
 344 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
 345 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
 346 #define CM_VADMIC3              0x01    /* Mic record boost */
 347
 348 /*
 349  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
 350  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
 351  * unit (readonly?).
 352  */
 353 #define CM_REG_PLL              0xf8
 354
 355 /*
 356  * extended registers
 357  */
 358 #define CM_REG_CH0_FRAME1       0x80    /* write: base address */
 359 #define CM_REG_CH0_FRAME2       0x84    /* read: current address */
 360 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
 361 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
 362
 363 #define CM_REG_EXT_MISC         0x90
 364 #define CM_ADC48K44K            0x10000000      /* ADC parameters group, 0: 44k, 1: 48k */
 365 #define CM_CHB3D8C              0x00200000      /* 7.1 channels support */
 366 #define CM_SPD32FMT             0x00100000      /* SPDIF/IN 32k sample rate */
 367 #define CM_ADC2SPDIF            0x00080000      /* ADC output to SPDIF/OUT */
 368 #define CM_SHAREADC             0x00040000      /* DAC in ADC as Center/LFE */
 369 #define CM_REALTCMP             0x00020000      /* monitor the CMPL/CMPR of ADC */
 370 #define CM_INVLRCK              0x00010000      /* invert ZVPORT's LRCK */
 371 #define CM_UNKNOWN_90_MASK      0x0000FFFF      /* ? */
 372
 373 /*
 374  * size of i/o region
 375  */
 376 #define CM_EXTENT_CODEC   0x100
 377 #define CM_EXTENT_MIDI    0x2
 378 #define CM_EXTENT_SYNTH   0x4
 379
 380
 381 /*
 382  * channels for playback / capture
 383  */
 384 #define CM_CH_PLAY      0
 385 #define CM_CH_CAPT      1
 386
 387 /*
 388  * flags to check device open/close
 389  */
 390 #define CM_OPEN_NONE    0
 391 #define CM_OPEN_CH_MASK 0x01
 392 #define CM_OPEN_DAC     0x10
 393 #define CM_OPEN_ADC     0x20
 394 #define CM_OPEN_SPDIF   0x40
 395 #define CM_OPEN_MCHAN   0x80
 396 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
 397 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
 398 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
 399 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
 400 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
 401 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
 402
 403
 404 #if CM_CH_PLAY == 1
 405 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
 406 #define CM_PLAYBACK_SPDF        CM_SPDF_1
 407 #define CM_CAPTURE_SPDF         CM_SPDF_0
 408 #else
 409 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
 410 #define CM_PLAYBACK_SPDF        CM_SPDF_0
 411 #define CM_CAPTURE_SPDF         CM_SPDF_1
 412 #endif
 413
 414
 415 /*
 416  * driver data
 417  */
 418
 419 struct cmipci_pcm {
 420         struct snd_pcm_substream *substream;
 421         u8 running;             /* dac/adc running? */
 422         u8 fmt;                 /* format bits */
 423         u8 is_dac;
 424         u8 needs_silencing;
 425         unsigned int dma_size;  /* in frames */
 426         unsigned int shift;
 427         unsigned int ch;        /* channel (0/1) */
 428         unsigned int offset;    /* physical address of the buffer */
 429 };
 430
 431 /* mixer elements toggled/resumed during ac3 playback */
 432 struct cmipci_mixer_auto_switches {
 433         const char *name;       /* switch to toggle */
 434         int toggle_on;          /* value to change when ac3 mode */
 435 };
 436 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
 437         {"PCM Playback Switch", 0},
 438         {"IEC958 Output Switch", 1},
 439         {"IEC958 Mix Analog", 0},
 440         // {"IEC958 Out To DAC", 1}, // no longer used
 441         {"IEC958 Loop", 0},
 442 };
 443 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
 444
 445 struct cmipci {
 446         struct snd_card *card;
 447
 448         struct pci_dev *pci;
 449         unsigned int device;    /* device ID */
 450         int irq;
 451
 452         unsigned long iobase;
 453         unsigned int ctrl;      /* FUNCTRL0 current value */
 454
 455         struct snd_pcm *pcm;            /* DAC/ADC PCM */
 456         struct snd_pcm *pcm2;   /* 2nd DAC */
 457         struct snd_pcm *pcm_spdif;      /* SPDIF */
 458
 459         int chip_version;
 460         int max_channels;
 461         unsigned int can_ac3_sw: 1;
 462         unsigned int can_ac3_hw: 1;
 463         unsigned int can_multi_ch: 1;
 464         unsigned int can_96k: 1;        /* samplerate above 48k */
 465         unsigned int do_soft_ac3: 1;
 466
 467         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
 468         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
 469         int spdif_counter;      /* for software AC3 */
 470
 471         unsigned int dig_status;
 472         unsigned int dig_pcm_status;
 473
 474         struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
 475
 476         int opened[2];  /* open mode */
 477         struct mutex open_mutex;
 478
 479         unsigned int mixer_insensitive: 1;
 480         struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
 481         int mixer_res_status[CM_SAVED_MIXERS];
 482
 483         struct cmipci_pcm channel[2];   /* ch0 - DAC, ch1 - ADC or 2nd DAC */
 484
 485         /* external MIDI */
 486         struct snd_rawmidi *rmidi;
 487
 488 #ifdef SUPPORT_JOYSTICK
 489         struct gameport *gameport;
 490 #endif
 491
 492         spinlock_t reg_lock;
 493
 494 #ifdef CONFIG_PM_SLEEP
 495         unsigned int saved_regs[0x20];
 496         unsigned char saved_mixers[0x20];
 497 #endif
 498 };
 499
 500
 501 /* read/write operations for dword register */
 502 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
 503 {
 504         outl(data, cm->iobase + cmd);
 505 }
 506
 507 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
 508 {
 509         return inl(cm->iobase + cmd);
 510 }
 511
 512 /* read/write operations for word register */
 513 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
 514 {
 515         outw(data, cm->iobase + cmd);
 516 }
 517
 518 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
 519 {
 520         return inw(cm->iobase + cmd);
 521 }
 522
 523 /* read/write operations for byte register */
 524 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
 525 {
 526         outb(data, cm->iobase + cmd);
 527 }
 528
 529 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
 530 {
 531         return inb(cm->iobase + cmd);
 532 }
 533
 534 /* bit operations for dword register */
 535 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 536 {
 537         unsigned int val, oval;
 538         val = oval = inl(cm->iobase + cmd);
 539         val |= flag;
 540         if (val == oval)
 541                 return 0;
 542         outl(val, cm->iobase + cmd);
 543         return 1;
 544 }
 545
 546 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 547 {
 548         unsigned int val, oval;
 549         val = oval = inl(cm->iobase + cmd);
 550         val &= ~flag;
 551         if (val == oval)
 552                 return 0;
 553         outl(val, cm->iobase + cmd);
 554         return 1;
 555 }
 556
 557 /* bit operations for byte register */
 558 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 559 {
 560         unsigned char val, oval;
 561         val = oval = inb(cm->iobase + cmd);
 562         val |= flag;
 563         if (val == oval)
 564                 return 0;
 565         outb(val, cm->iobase + cmd);
 566         return 1;
 567 }
 568
 569 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 570 {
 571         unsigned char val, oval;
 572         val = oval = inb(cm->iobase + cmd);
 573         val &= ~flag;
 574         if (val == oval)
 575                 return 0;
 576         outb(val, cm->iobase + cmd);
 577         return 1;
 578 }
 579
 580
 581 /*
 582  * PCM interface
 583  */
 584
 585 /*
 586  * calculate frequency
 587  */
 588
 589 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
 590
 591 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
 592 {
 593         unsigned int i;
 594
 595         for (i = 0; i < ARRAY_SIZE(rates); i++) {
 596                 if (rates[i] == rate)
 597                         return i;
 598         }
 599         snd_BUG();
 600         return 0;
 601 }
 602
 603 #ifdef USE_VAR48KRATE
 604 /*
 605  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
 606  * does it this way .. maybe not.  Never get any information from C-Media about
 607  * that <werner@suse.de>.
 608  */
 609 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
 610 {
 611         unsigned int delta, tolerance;
 612         int xm, xn, xr;
 613
 614         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
 615                 rate <<= 1;
 616         *n = -1;
 617         if (*r > 0xff)
 618                 goto out;
 619         tolerance = rate*CM_TOLERANCE_RATE;
 620
 621         for (xn = (1+2); xn < (0x1f+2); xn++) {
 622                 for (xm = (1+2); xm < (0xff+2); xm++) {
 623                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
 624
 625                         if (xr < rate)
 626                                 delta = rate - xr;
 627                         else
 628                                 delta = xr - rate;
 629
 630                         /*
 631                          * If we found one, remember this,
 632                          * and try to find a closer one
 633                          */
 634                         if (delta < tolerance) {
 635                                 tolerance = delta;
 636                                 *m = xm - 2;
 637                                 *n = xn - 2;
 638                         }
 639                 }
 640         }
 641 out:
 642         return (*n > -1);
 643 }
 644
 645 /*
 646  * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
 647  * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
 648  * at the register CM_REG_FUNCTRL1 (0x04).
 649  * Problem: other ways are also possible (any information about that?)
 650  */
 651 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
 652 {
 653         unsigned int reg = CM_REG_PLL + slot;
 654         /*
 655          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
 656          * for DSFC/ASFC (000 up to 111).
 657          */
 658
 659         /* FIXME: Init (Do we've to set an other register first before programming?) */
 660
 661         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
 662         snd_cmipci_write_b(cm, reg, rate>>8);
 663         snd_cmipci_write_b(cm, reg, rate&0xff);
 664
 665         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
 666 }
 667 #endif /* USE_VAR48KRATE */
 668
 669 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
 670                                 struct snd_pcm_hw_params *hw_params)
 671 {
 672         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 673 }
 674
 675 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
 676                                           struct snd_pcm_hw_params *hw_params)
 677 {
 678         struct cmipci *cm = snd_pcm_substream_chip(substream);
 679         if (params_channels(hw_params) > 2) {
 680                 mutex_lock(&cm->open_mutex);
 681                 if (cm->opened[CM_CH_PLAY]) {
 682                         mutex_unlock(&cm->open_mutex);
 683                         return -EBUSY;
 684                 }
 685                 /* reserve the channel A */
 686                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
 687                 mutex_unlock(&cm->open_mutex);
 688         }
 689         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 690 }
 691
 692 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
 693 {
 694         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
 695         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 696         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 697         udelay(10);
 698 }
 699
 700 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
 701 {
 702         return snd_pcm_lib_free_pages(substream);
 703 }
 704
 705
 706 /*
 707  */
 708
 709 static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
 710 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
 711         .count = 3,
 712         .list = hw_channels,
 713         .mask = 0,
 714 };
 715 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
 716         .count = 4,
 717         .list = hw_channels,
 718         .mask = 0,
 719 };
 720 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
 721         .count = 5,
 722         .list = hw_channels,
 723         .mask = 0,
 724 };
 725
 726 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
 727 {
 728         if (channels > 2) {
 729                 if (!cm->can_multi_ch || !rec->ch)
 730                         return -EINVAL;
 731                 if (rec->fmt != 0x03) /* stereo 16bit only */
 732                         return -EINVAL;
 733         }
 734
 735         if (cm->can_multi_ch) {
 736                 spin_lock_irq(&cm->reg_lock);
 737                 if (channels > 2) {
 738                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 739                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 740                 } else {
 741                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 742                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 743                 }
 744                 if (channels == 8)
 745                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 746                 else
 747                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 748                 if (channels == 6) {
 749                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 750                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 751                 } else {
 752                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 753                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 754                 }
 755                 if (channels == 4)
 756                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 757                 else
 758                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 759                 spin_unlock_irq(&cm->reg_lock);
 760         }
 761         return 0;
 762 }
 763
 764
 765 /*
 766  * prepare playback/capture channel
 767  * channel to be used must have been set in rec->ch.
 768  */
 769 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
 770                                  struct snd_pcm_substream *substream)
 771 {
 772         unsigned int reg, freq, freq_ext, val;
 773         unsigned int period_size;
 774         struct snd_pcm_runtime *runtime = substream->runtime;
 775
 776         rec->fmt = 0;
 777         rec->shift = 0;
 778         if (snd_pcm_format_width(runtime->format) >= 16) {
 779                 rec->fmt |= 0x02;
 780                 if (snd_pcm_format_width(runtime->format) > 16)
 781                         rec->shift++; /* 24/32bit */
 782         }
 783         if (runtime->channels > 1)
 784                 rec->fmt |= 0x01;
 785         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
 786                 dev_dbg(cm->card->dev, "cannot set dac channels\n");
 787                 return -EINVAL;
 788         }
 789
 790         rec->offset = runtime->dma_addr;
 791         /* buffer and period sizes in frame */
 792         rec->dma_size = runtime->buffer_size << rec->shift;
 793         period_size = runtime->period_size << rec->shift;
 794         if (runtime->channels > 2) {
 795                 /* multi-channels */
 796                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
 797                 period_size = (period_size * runtime->channels) / 2;
 798         }
 799
 800         spin_lock_irq(&cm->reg_lock);
 801
 802         /* set buffer address */
 803         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 804         snd_cmipci_write(cm, reg, rec->offset);
 805         /* program sample counts */
 806         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 807         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
 808         snd_cmipci_write_w(cm, reg + 2, period_size - 1);
 809
 810         /* set adc/dac flag */
 811         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
 812         if (rec->is_dac)
 813                 cm->ctrl &= ~val;
 814         else
 815                 cm->ctrl |= val;
 816         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 817         /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
 818
 819         /* set sample rate */
 820         freq = 0;
 821         freq_ext = 0;
 822         if (runtime->rate > 48000)
 823                 switch (runtime->rate) {
 824                 case 88200:  freq_ext = CM_CH0_SRATE_88K; break;
 825                 case 96000:  freq_ext = CM_CH0_SRATE_96K; break;
 826                 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
 827                 default:     snd_BUG(); break;
 828                 }
 829         else
 830                 freq = snd_cmipci_rate_freq(runtime->rate);
 831         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
 832         if (rec->ch) {
 833                 val &= ~CM_DSFC_MASK;
 834                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
 835         } else {
 836                 val &= ~CM_ASFC_MASK;
 837                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
 838         }
 839         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
 840         dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
 841
 842         /* set format */
 843         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
 844         if (rec->ch) {
 845                 val &= ~CM_CH1FMT_MASK;
 846                 val |= rec->fmt << CM_CH1FMT_SHIFT;
 847         } else {
 848                 val &= ~CM_CH0FMT_MASK;
 849                 val |= rec->fmt << CM_CH0FMT_SHIFT;
 850         }
 851         if (cm->can_96k) {
 852                 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
 853                 val |= freq_ext << (rec->ch * 2);
 854         }
 855         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
 856         dev_dbg(cm->card->dev, "chformat = %08x\n", val);
 857
 858         if (!rec->is_dac && cm->chip_version) {
 859                 if (runtime->rate > 44100)
 860                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 861                 else
 862                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 863         }
 864
 865         rec->running = 0;
 866         spin_unlock_irq(&cm->reg_lock);
 867
 868         return 0;
 869 }
 870
 871 /*
 872  * PCM trigger/stop
 873  */
 874 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
 875                                   int cmd)
 876 {
 877         unsigned int inthld, chen, reset, pause;
 878         int result = 0;
 879
 880         inthld = CM_CH0_INT_EN << rec->ch;
 881         chen = CM_CHEN0 << rec->ch;
 882         reset = CM_RST_CH0 << rec->ch;
 883         pause = CM_PAUSE0 << rec->ch;
 884
 885         spin_lock(&cm->reg_lock);
 886         switch (cmd) {
 887         case SNDRV_PCM_TRIGGER_START:
 888                 rec->running = 1;
 889                 /* set interrupt */
 890                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
 891                 cm->ctrl |= chen;
 892                 /* enable channel */
 893                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 894                 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
 895                 break;
 896         case SNDRV_PCM_TRIGGER_STOP:
 897                 rec->running = 0;
 898                 /* disable interrupt */
 899                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
 900                 /* reset */
 901                 cm->ctrl &= ~chen;
 902                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 903                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 904                 rec->needs_silencing = rec->is_dac;
 905                 break;
 906         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 907         case SNDRV_PCM_TRIGGER_SUSPEND:
 908                 cm->ctrl |= pause;
 909                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 910                 break;
 911         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 912         case SNDRV_PCM_TRIGGER_RESUME:
 913                 cm->ctrl &= ~pause;
 914                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 915                 break;
 916         default:
 917                 result = -EINVAL;
 918                 break;
 919         }
 920         spin_unlock(&cm->reg_lock);
 921         return result;
 922 }
 923
 924 /*
 925  * return the current pointer
 926  */
 927 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
 928                                                 struct snd_pcm_substream *substream)
 929 {
 930         size_t ptr;
 931         unsigned int reg, rem, tries;
 932
 933         if (!rec->running)
 934                 return 0;
 935 #if 1 // this seems better..
 936         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 937         for (tries = 0; tries < 3; tries++) {
 938                 rem = snd_cmipci_read_w(cm, reg);
 939                 if (rem < rec->dma_size)
 940                         goto ok;
 941         }
 942         dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
 943         return SNDRV_PCM_POS_XRUN;
 944 ok:
 945         ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
 946 #else
 947         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 948         ptr = snd_cmipci_read(cm, reg) - rec->offset;
 949         ptr = bytes_to_frames(substream->runtime, ptr);
 950 #endif
 951         if (substream->runtime->channels > 2)
 952                 ptr = (ptr * 2) / substream->runtime->channels;
 953         return ptr;
 954 }
 955
 956 /*
 957  * playback
 958  */
 959
 960 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
 961                                        int cmd)
 962 {
 963         struct cmipci *cm = snd_pcm_substream_chip(substream);
 964         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
 965 }
 966
 967 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
 968 {
 969         struct cmipci *cm = snd_pcm_substream_chip(substream);
 970         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
 971 }
 972
 973
 974
 975 /*
 976  * capture
 977  */
 978
 979 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
 980                                      int cmd)
 981 {
 982         struct cmipci *cm = snd_pcm_substream_chip(substream);
 983         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
 984 }
 985
 986 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
 987 {
 988         struct cmipci *cm = snd_pcm_substream_chip(substream);
 989         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
 990 }
 991
 992
 993 /*
 994  * hw preparation for spdif
 995  */
 996
 997 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
 998                                          struct snd_ctl_elem_info *uinfo)
 999 {
1000         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1001         uinfo->count = 1;
1002         return 0;
1003 }
1004
1005 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1006                                         struct snd_ctl_elem_value *ucontrol)
1007 {
1008         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1009         int i;
1010
1011         spin_lock_irq(&chip->reg_lock);
1012         for (i = 0; i < 4; i++)
1013                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1014         spin_unlock_irq(&chip->reg_lock);
1015         return 0;
1016 }
1017
1018 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1019                                          struct snd_ctl_elem_value *ucontrol)
1020 {
1021         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1022         int i, change;
1023         unsigned int val;
1024
1025         val = 0;
1026         spin_lock_irq(&chip->reg_lock);
1027         for (i = 0; i < 4; i++)
1028                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1029         change = val != chip->dig_status;
1030         chip->dig_status = val;
1031         spin_unlock_irq(&chip->reg_lock);
1032         return change;
1033 }
1034
1035 static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1036 {
1037         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1038         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1039         .info =         snd_cmipci_spdif_default_info,
1040         .get =          snd_cmipci_spdif_default_get,
1041         .put =          snd_cmipci_spdif_default_put
1042 };
1043
1044 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1045                                       struct snd_ctl_elem_info *uinfo)
1046 {
1047         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1048         uinfo->count = 1;
1049         return 0;
1050 }
1051
1052 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1053                                      struct snd_ctl_elem_value *ucontrol)
1054 {
1055         ucontrol->value.iec958.status[0] = 0xff;
1056         ucontrol->value.iec958.status[1] = 0xff;
1057         ucontrol->value.iec958.status[2] = 0xff;
1058         ucontrol->value.iec958.status[3] = 0xff;
1059         return 0;
1060 }
1061
1062 static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1063 {
1064         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1065         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1066         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1067         .info =         snd_cmipci_spdif_mask_info,
1068         .get =          snd_cmipci_spdif_mask_get,
1069 };
1070
1071 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1072                                         struct snd_ctl_elem_info *uinfo)
1073 {
1074         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1075         uinfo->count = 1;
1076         return 0;
1077 }
1078
1079 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1080                                        struct snd_ctl_elem_value *ucontrol)
1081 {
1082         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1083         int i;
1084
1085         spin_lock_irq(&chip->reg_lock);
1086         for (i = 0; i < 4; i++)
1087                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1088         spin_unlock_irq(&chip->reg_lock);
1089         return 0;
1090 }
1091
1092 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1093                                        struct snd_ctl_elem_value *ucontrol)
1094 {
1095         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1096         int i, change;
1097         unsigned int val;
1098
1099         val = 0;
1100         spin_lock_irq(&chip->reg_lock);
1101         for (i = 0; i < 4; i++)
1102                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1103         change = val != chip->dig_pcm_status;
1104         chip->dig_pcm_status = val;
1105         spin_unlock_irq(&chip->reg_lock);
1106         return change;
1107 }
1108
1109 static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1110 {
1111         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1112         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1113         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1114         .info =         snd_cmipci_spdif_stream_info,
1115         .get =          snd_cmipci_spdif_stream_get,
1116         .put =          snd_cmipci_spdif_stream_put
1117 };
1118
1119 /*
1120  */
1121
1122 /* save mixer setting and mute for AC3 playback */
1123 static int save_mixer_state(struct cmipci *cm)
1124 {
1125         if (! cm->mixer_insensitive) {
1126                 struct snd_ctl_elem_value *val;
1127                 unsigned int i;
1128
1129                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1130                 if (!val)
1131                         return -ENOMEM;
1132                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1133                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1134                         if (ctl) {
1135                                 int event;
1136                                 memset(val, 0, sizeof(*val));
1137                                 ctl->get(ctl, val);
1138                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1139                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1140                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1141                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1142                                         ctl->put(ctl, val); /* toggle */
1143                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1144                                 }
1145                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1146                                 snd_ctl_notify(cm->card, event, &ctl->id);
1147                         }
1148                 }
1149                 kfree(val);
1150                 cm->mixer_insensitive = 1;
1151         }
1152         return 0;
1153 }
1154
1155
1156 /* restore the previously saved mixer status */
1157 static void restore_mixer_state(struct cmipci *cm)
1158 {
1159         if (cm->mixer_insensitive) {
1160                 struct snd_ctl_elem_value *val;
1161                 unsigned int i;
1162
1163                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1164                 if (!val)
1165                         return;
1166                 cm->mixer_insensitive = 0; /* at first clear this;
1167                                               otherwise the changes will be ignored */
1168                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1169                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1170                         if (ctl) {
1171                                 int event;
1172
1173                                 memset(val, 0, sizeof(*val));
1174                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1175                                 ctl->get(ctl, val);
1176                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1177                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1178                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1179                                         ctl->put(ctl, val);
1180                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1181                                 }
1182                                 snd_ctl_notify(cm->card, event, &ctl->id);
1183                         }
1184                 }
1185                 kfree(val);
1186         }
1187 }
1188
1189 /* spinlock held! */
1190 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1191 {
1192         if (do_ac3) {
1193                 /* AC3EN for 037 */
1194                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1195                 /* AC3EN for 039 */
1196                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1197
1198                 if (cm->can_ac3_hw) {
1199                         /* SPD24SEL for 037, 0x02 */
1200                         /* SPD24SEL for 039, 0x20, but cannot be set */
1201                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1202                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1203                 } else { /* can_ac3_sw */
1204                         /* SPD32SEL for 037 & 039, 0x20 */
1205                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1206                         /* set 176K sample rate to fix 033 HW bug */
1207                         if (cm->chip_version == 33) {
1208                                 if (rate >= 48000) {
1209                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1210                                 } else {
1211                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1212                                 }
1213                         }
1214                 }
1215
1216         } else {
1217                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1218                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1219
1220                 if (cm->can_ac3_hw) {
1221                         /* chip model >= 37 */
1222                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1223                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1224                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1225                         } else {
1226                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1227                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1228                         }
1229                 } else {
1230                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1231                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1232                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1233                 }
1234         }
1235 }
1236
1237 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1238 {
1239         int rate, err;
1240
1241         rate = subs->runtime->rate;
1242
1243         if (up && do_ac3)
1244                 if ((err = save_mixer_state(cm)) < 0)
1245                         return err;
1246
1247         spin_lock_irq(&cm->reg_lock);
1248         cm->spdif_playback_avail = up;
1249         if (up) {
1250                 /* they are controlled via "IEC958 Output Switch" */
1251                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1252                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1253                 if (cm->spdif_playback_enabled)
1254                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1255                 setup_ac3(cm, subs, do_ac3, rate);
1256
1257                 if (rate == 48000 || rate == 96000)
1258                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1259                 else
1260                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1261                 if (rate > 48000)
1262                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1263                 else
1264                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1265         } else {
1266                 /* they are controlled via "IEC958 Output Switch" */
1267                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1268                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1269                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1270                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1271                 setup_ac3(cm, subs, 0, 0);
1272         }
1273         spin_unlock_irq(&cm->reg_lock);
1274         return 0;
1275 }
1276
1277
1278 /*
1279  * preparation
1280  */
1281
1282 /* playback - enable spdif only on the certain condition */
1283 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1284 {
1285         struct cmipci *cm = snd_pcm_substream_chip(substream);
1286         int rate = substream->runtime->rate;
1287         int err, do_spdif, do_ac3 = 0;
1288
1289         do_spdif = (rate >= 44100 && rate <= 96000 &&
1290                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1291                     substream->runtime->channels == 2);
1292         if (do_spdif && cm->can_ac3_hw)
1293                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1294         if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1295                 return err;
1296         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1297 }
1298
1299 /* playback  (via device #2) - enable spdif always */
1300 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1301 {
1302         struct cmipci *cm = snd_pcm_substream_chip(substream);
1303         int err, do_ac3;
1304
1305         if (cm->can_ac3_hw)
1306                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1307         else
1308                 do_ac3 = 1; /* doesn't matter */
1309         if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1310                 return err;
1311         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1312 }
1313
1314 /*
1315  * Apparently, the samples last played on channel A stay in some buffer, even
1316  * after the channel is reset, and get added to the data for the rear DACs when
1317  * playing a multichannel stream on channel B.  This is likely to generate
1318  * wraparounds and thus distortions.
1319  * To avoid this, we play at least one zero sample after the actual stream has
1320  * stopped.
1321  */
1322 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1323 {
1324         struct snd_pcm_runtime *runtime = rec->substream->runtime;
1325         unsigned int reg, val;
1326
1327         if (rec->needs_silencing && runtime && runtime->dma_area) {
1328                 /* set up a small silence buffer */
1329                 memset(runtime->dma_area, 0, PAGE_SIZE);
1330                 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1331                 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1332                 snd_cmipci_write(cm, reg, val);
1333
1334                 /* configure for 16 bits, 2 channels, 8 kHz */
1335                 if (runtime->channels > 2)
1336                         set_dac_channels(cm, rec, 2);
1337                 spin_lock_irq(&cm->reg_lock);
1338                 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1339                 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1340                 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1341                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1342                 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1343                 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1344                 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1345                 if (cm->can_96k)
1346                         val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1347                 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1348
1349                 /* start stream (we don't need interrupts) */
1350                 cm->ctrl |= CM_CHEN0 << rec->ch;
1351                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1352                 spin_unlock_irq(&cm->reg_lock);
1353
1354                 msleep(1);
1355
1356                 /* stop and reset stream */
1357                 spin_lock_irq(&cm->reg_lock);
1358                 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1359                 val = CM_RST_CH0 << rec->ch;
1360                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1361                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1362                 spin_unlock_irq(&cm->reg_lock);
1363
1364                 rec->needs_silencing = 0;
1365         }
1366 }
1367
1368 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1369 {
1370         struct cmipci *cm = snd_pcm_substream_chip(substream);
1371         setup_spdif_playback(cm, substream, 0, 0);
1372         restore_mixer_state(cm);
1373         snd_cmipci_silence_hack(cm, &cm->channel[0]);
1374         return snd_cmipci_hw_free(substream);
1375 }
1376
1377 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1378 {
1379         struct cmipci *cm = snd_pcm_substream_chip(substream);
1380         snd_cmipci_silence_hack(cm, &cm->channel[1]);
1381         return snd_cmipci_hw_free(substream);
1382 }
1383
1384 /* capture */
1385 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1386 {
1387         struct cmipci *cm = snd_pcm_substream_chip(substream);
1388         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1389 }
1390
1391 /* capture with spdif (via device #2) */
1392 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1393 {
1394         struct cmipci *cm = snd_pcm_substream_chip(substream);
1395
1396         spin_lock_irq(&cm->reg_lock);
1397         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1398         if (cm->can_96k) {
1399                 if (substream->runtime->rate > 48000)
1400                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1401                 else
1402                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1403         }
1404         if (snd_pcm_format_width(substream->runtime->format) > 16)
1405                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1406         else
1407                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1408
1409         spin_unlock_irq(&cm->reg_lock);
1410
1411         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1412 }
1413
1414 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1415 {
1416         struct cmipci *cm = snd_pcm_substream_chip(subs);
1417
1418         spin_lock_irq(&cm->reg_lock);
1419         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1420         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1421         spin_unlock_irq(&cm->reg_lock);
1422
1423         return snd_cmipci_hw_free(subs);
1424 }
1425
1426
1427 /*
1428  * interrupt handler
1429  */
1430 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1431 {
1432         struct cmipci *cm = dev_id;
1433         unsigned int status, mask = 0;
1434
1435         /* fastpath out, to ease interrupt sharing */
1436         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1437         if (!(status & CM_INTR))
1438                 return IRQ_NONE;
1439
1440         /* acknowledge interrupt */
1441         spin_lock(&cm->reg_lock);
1442         if (status & CM_CHINT0)
1443                 mask |= CM_CH0_INT_EN;
1444         if (status & CM_CHINT1)
1445                 mask |= CM_CH1_INT_EN;
1446         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1447         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1448         spin_unlock(&cm->reg_lock);
1449
1450         if (cm->rmidi && (status & CM_UARTINT))
1451                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1452
1453         if (cm->pcm) {
1454                 if ((status & CM_CHINT0) && cm->channel[0].running)
1455                         snd_pcm_period_elapsed(cm->channel[0].substream);
1456                 if ((status & CM_CHINT1) && cm->channel[1].running)
1457                         snd_pcm_period_elapsed(cm->channel[1].substream);
1458         }
1459         return IRQ_HANDLED;
1460 }
1461
1462 /*
1463  * h/w infos
1464  */
1465
1466 /* playback on channel A */
1467 static const struct snd_pcm_hardware snd_cmipci_playback =
1468 {
1469         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1470                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1471                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1472         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1473         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1474         .rate_min =             5512,
1475         .rate_max =             48000,
1476         .channels_min =         1,
1477         .channels_max =         2,
1478         .buffer_bytes_max =     (128*1024),
1479         .period_bytes_min =     64,
1480         .period_bytes_max =     (128*1024),
1481         .periods_min =          2,
1482         .periods_max =          1024,
1483         .fifo_size =            0,
1484 };
1485
1486 /* capture on channel B */
1487 static const struct snd_pcm_hardware snd_cmipci_capture =
1488 {
1489         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1490                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1491                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1492         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1493         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1494         .rate_min =             5512,
1495         .rate_max =             48000,
1496         .channels_min =         1,
1497         .channels_max =         2,
1498         .buffer_bytes_max =     (128*1024),
1499         .period_bytes_min =     64,
1500         .period_bytes_max =     (128*1024),
1501         .periods_min =          2,
1502         .periods_max =          1024,
1503         .fifo_size =            0,
1504 };
1505
1506 /* playback on channel B - stereo 16bit only? */
1507 static const struct snd_pcm_hardware snd_cmipci_playback2 =
1508 {
1509         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1510                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1511                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1512         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1513         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1514         .rate_min =             5512,
1515         .rate_max =             48000,
1516         .channels_min =         2,
1517         .channels_max =         2,
1518         .buffer_bytes_max =     (128*1024),
1519         .period_bytes_min =     64,
1520         .period_bytes_max =     (128*1024),
1521         .periods_min =          2,
1522         .periods_max =          1024,
1523         .fifo_size =            0,
1524 };
1525
1526 /* spdif playback on channel A */
1527 static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1528 {
1529         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1530                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1531                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1532         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1533         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1534         .rate_min =             44100,
1535         .rate_max =             48000,
1536         .channels_min =         2,
1537         .channels_max =         2,
1538         .buffer_bytes_max =     (128*1024),
1539         .period_bytes_min =     64,
1540         .period_bytes_max =     (128*1024),
1541         .periods_min =          2,
1542         .periods_max =          1024,
1543         .fifo_size =            0,
1544 };
1545
1546 /* spdif playback on channel A (32bit, IEC958 subframes) */
1547 static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1548 {
1549         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1550                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1551                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1552         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1553         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1554         .rate_min =             44100,
1555         .rate_max =             48000,
1556         .channels_min =         2,
1557         .channels_max =         2,
1558         .buffer_bytes_max =     (128*1024),
1559         .period_bytes_min =     64,
1560         .period_bytes_max =     (128*1024),
1561         .periods_min =          2,
1562         .periods_max =          1024,
1563         .fifo_size =            0,
1564 };
1565
1566 /* spdif capture on channel B */
1567 static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1568 {
1569         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1570                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1571                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1572         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
1573                                 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1574         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1575         .rate_min =             44100,
1576         .rate_max =             48000,
1577         .channels_min =         2,
1578         .channels_max =         2,
1579         .buffer_bytes_max =     (128*1024),
1580         .period_bytes_min =     64,
1581         .period_bytes_max =     (128*1024),
1582         .periods_min =          2,
1583         .periods_max =          1024,
1584         .fifo_size =            0,
1585 };
1586
1587 static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1588                         32000, 44100, 48000, 88200, 96000, 128000 };
1589 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1590                 .count = ARRAY_SIZE(rate_constraints),
1591                 .list = rate_constraints,
1592                 .mask = 0,
1593 };
1594
1595 /*
1596  * check device open/close
1597  */
1598 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1599 {
1600         int ch = mode & CM_OPEN_CH_MASK;
1601
1602         /* FIXME: a file should wait until the device becomes free
1603          * when it's opened on blocking mode.  however, since the current
1604          * pcm framework doesn't pass file pointer before actually opened,
1605          * we can't know whether blocking mode or not in open callback..
1606          */
1607         mutex_lock(&cm->open_mutex);
1608         if (cm->opened[ch]) {
1609                 mutex_unlock(&cm->open_mutex);
1610                 return -EBUSY;
1611         }
1612         cm->opened[ch] = mode;
1613         cm->channel[ch].substream = subs;
1614         if (! (mode & CM_OPEN_DAC)) {
1615                 /* disable dual DAC mode */
1616                 cm->channel[ch].is_dac = 0;
1617                 spin_lock_irq(&cm->reg_lock);
1618                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1619                 spin_unlock_irq(&cm->reg_lock);
1620         }
1621         mutex_unlock(&cm->open_mutex);
1622         return 0;
1623 }
1624
1625 static void close_device_check(struct cmipci *cm, int mode)
1626 {
1627         int ch = mode & CM_OPEN_CH_MASK;
1628
1629         mutex_lock(&cm->open_mutex);
1630         if (cm->opened[ch] == mode) {
1631                 if (cm->channel[ch].substream) {
1632                         snd_cmipci_ch_reset(cm, ch);
1633                         cm->channel[ch].running = 0;
1634                         cm->channel[ch].substream = NULL;
1635                 }
1636                 cm->opened[ch] = 0;
1637                 if (! cm->channel[ch].is_dac) {
1638                         /* enable dual DAC mode again */
1639                         cm->channel[ch].is_dac = 1;
1640                         spin_lock_irq(&cm->reg_lock);
1641                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1642                         spin_unlock_irq(&cm->reg_lock);
1643                 }
1644         }
1645         mutex_unlock(&cm->open_mutex);
1646 }
1647
1648 /*
1649  */
1650
1651 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1652 {
1653         struct cmipci *cm = snd_pcm_substream_chip(substream);
1654         struct snd_pcm_runtime *runtime = substream->runtime;
1655         int err;
1656
1657         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1658                 return err;
1659         runtime->hw = snd_cmipci_playback;
1660         if (cm->chip_version == 68) {
1661                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1662                                      SNDRV_PCM_RATE_96000;
1663                 runtime->hw.rate_max = 96000;
1664         } else if (cm->chip_version == 55) {
1665                 err = snd_pcm_hw_constraint_list(runtime, 0,
1666                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1667                 if (err < 0)
1668                         return err;
1669                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1670                 runtime->hw.rate_max = 128000;
1671         }
1672         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1673         cm->dig_pcm_status = cm->dig_status;
1674         return 0;
1675 }
1676
1677 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1678 {
1679         struct cmipci *cm = snd_pcm_substream_chip(substream);
1680         struct snd_pcm_runtime *runtime = substream->runtime;
1681         int err;
1682
1683         if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1684                 return err;
1685         runtime->hw = snd_cmipci_capture;
1686         if (cm->chip_version == 68) {   // 8768 only supports 44k/48k recording
1687                 runtime->hw.rate_min = 41000;
1688                 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1689         } else if (cm->chip_version == 55) {
1690                 err = snd_pcm_hw_constraint_list(runtime, 0,
1691                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1692                 if (err < 0)
1693                         return err;
1694                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1695                 runtime->hw.rate_max = 128000;
1696         }
1697         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1698         return 0;
1699 }
1700
1701 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1702 {
1703         struct cmipci *cm = snd_pcm_substream_chip(substream);
1704         struct snd_pcm_runtime *runtime = substream->runtime;
1705         int err;
1706
1707         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1708                 return err;
1709         runtime->hw = snd_cmipci_playback2;
1710         mutex_lock(&cm->open_mutex);
1711         if (! cm->opened[CM_CH_PLAY]) {
1712                 if (cm->can_multi_ch) {
1713                         runtime->hw.channels_max = cm->max_channels;
1714                         if (cm->max_channels == 4)
1715                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1716                         else if (cm->max_channels == 6)
1717                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1718                         else if (cm->max_channels == 8)
1719                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1720                 }
1721         }
1722         mutex_unlock(&cm->open_mutex);
1723         if (cm->chip_version == 68) {
1724                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1725                                      SNDRV_PCM_RATE_96000;
1726                 runtime->hw.rate_max = 96000;
1727         } else if (cm->chip_version == 55) {
1728                 err = snd_pcm_hw_constraint_list(runtime, 0,
1729                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1730                 if (err < 0)
1731                         return err;
1732                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1733                 runtime->hw.rate_max = 128000;
1734         }
1735         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1736         return 0;
1737 }
1738
1739 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1740 {
1741         struct cmipci *cm = snd_pcm_substream_chip(substream);
1742         struct snd_pcm_runtime *runtime = substream->runtime;
1743         int err;
1744
1745         if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1746                 return err;
1747         if (cm->can_ac3_hw) {
1748                 runtime->hw = snd_cmipci_playback_spdif;
1749                 if (cm->chip_version >= 37) {
1750                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1751                         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1752                 }
1753                 if (cm->can_96k) {
1754                         runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1755                                              SNDRV_PCM_RATE_96000;
1756                         runtime->hw.rate_max = 96000;
1757                 }
1758         } else {
1759                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1760         }
1761         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1762         cm->dig_pcm_status = cm->dig_status;
1763         return 0;
1764 }
1765
1766 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1767 {
1768         struct cmipci *cm = snd_pcm_substream_chip(substream);
1769         struct snd_pcm_runtime *runtime = substream->runtime;
1770         int err;
1771
1772         if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1773                 return err;
1774         runtime->hw = snd_cmipci_capture_spdif;
1775         if (cm->can_96k && !(cm->chip_version == 68)) {
1776                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1777                                      SNDRV_PCM_RATE_96000;
1778                 runtime->hw.rate_max = 96000;
1779         }
1780         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1781         return 0;
1782 }
1783
1784
1785 /*
1786  */
1787
1788 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1789 {
1790         struct cmipci *cm = snd_pcm_substream_chip(substream);
1791         close_device_check(cm, CM_OPEN_PLAYBACK);
1792         return 0;
1793 }
1794
1795 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1796 {
1797         struct cmipci *cm = snd_pcm_substream_chip(substream);
1798         close_device_check(cm, CM_OPEN_CAPTURE);
1799         return 0;
1800 }
1801
1802 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1803 {
1804         struct cmipci *cm = snd_pcm_substream_chip(substream);
1805         close_device_check(cm, CM_OPEN_PLAYBACK2);
1806         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1807         return 0;
1808 }
1809
1810 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1811 {
1812         struct cmipci *cm = snd_pcm_substream_chip(substream);
1813         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1814         return 0;
1815 }
1816
1817 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1818 {
1819         struct cmipci *cm = snd_pcm_substream_chip(substream);
1820         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1821         return 0;
1822 }
1823
1824
1825 /*
1826  */
1827
1828 static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1829         .open =         snd_cmipci_playback_open,
1830         .close =        snd_cmipci_playback_close,
1831         .ioctl =        snd_pcm_lib_ioctl,
1832         .hw_params =    snd_cmipci_hw_params,
1833         .hw_free =      snd_cmipci_playback_hw_free,
1834         .prepare =      snd_cmipci_playback_prepare,
1835         .trigger =      snd_cmipci_playback_trigger,
1836         .pointer =      snd_cmipci_playback_pointer,
1837 };
1838
1839 static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1840         .open =         snd_cmipci_capture_open,
1841         .close =        snd_cmipci_capture_close,
1842         .ioctl =        snd_pcm_lib_ioctl,
1843         .hw_params =    snd_cmipci_hw_params,
1844         .hw_free =      snd_cmipci_hw_free,
1845         .prepare =      snd_cmipci_capture_prepare,
1846         .trigger =      snd_cmipci_capture_trigger,
1847         .pointer =      snd_cmipci_capture_pointer,
1848 };
1849
1850 static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1851         .open =         snd_cmipci_playback2_open,
1852         .close =        snd_cmipci_playback2_close,
1853         .ioctl =        snd_pcm_lib_ioctl,
1854         .hw_params =    snd_cmipci_playback2_hw_params,
1855         .hw_free =      snd_cmipci_playback2_hw_free,
1856         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1857         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1858         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1859 };
1860
1861 static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1862         .open =         snd_cmipci_playback_spdif_open,
1863         .close =        snd_cmipci_playback_spdif_close,
1864         .ioctl =        snd_pcm_lib_ioctl,
1865         .hw_params =    snd_cmipci_hw_params,
1866         .hw_free =      snd_cmipci_playback_hw_free,
1867         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1868         .trigger =      snd_cmipci_playback_trigger,
1869         .pointer =      snd_cmipci_playback_pointer,
1870 };
1871
1872 static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1873         .open =         snd_cmipci_capture_spdif_open,
1874         .close =        snd_cmipci_capture_spdif_close,
1875         .ioctl =        snd_pcm_lib_ioctl,
1876         .hw_params =    snd_cmipci_hw_params,
1877         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1878         .prepare =      snd_cmipci_capture_spdif_prepare,
1879         .trigger =      snd_cmipci_capture_trigger,
1880         .pointer =      snd_cmipci_capture_pointer,
1881 };
1882
1883
1884 /*
1885  */
1886
1887 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1888 {
1889         struct snd_pcm *pcm;
1890         int err;
1891
1892         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1893         if (err < 0)
1894                 return err;
1895
1896         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1897         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1898
1899         pcm->private_data = cm;
1900         pcm->info_flags = 0;
1901         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1902         cm->pcm = pcm;
1903
1904         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1905                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1906
1907         return 0;
1908 }
1909
1910 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1911 {
1912         struct snd_pcm *pcm;
1913         int err;
1914
1915         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1916         if (err < 0)
1917                 return err;
1918
1919         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1920
1921         pcm->private_data = cm;
1922         pcm->info_flags = 0;
1923         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1924         cm->pcm2 = pcm;
1925
1926         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1927                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1928
1929         return 0;
1930 }
1931
1932 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1933 {
1934         struct snd_pcm *pcm;
1935         int err;
1936
1937         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1938         if (err < 0)
1939                 return err;
1940
1941         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1942         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1943
1944         pcm->private_data = cm;
1945         pcm->info_flags = 0;
1946         strcpy(pcm->name, "C-Media PCI IEC958");
1947         cm->pcm_spdif = pcm;
1948
1949         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1950                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1951
1952         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1953                                      snd_pcm_alt_chmaps, cm->max_channels, 0,
1954                                      NULL);
1955         if (err < 0)
1956                 return err;
1957
1958         return 0;
1959 }
1960
1961 /*
1962  * mixer interface:
1963  * - CM8338/8738 has a compatible mixer interface with SB16, but
1964  *   lack of some elements like tone control, i/o gain and AGC.
1965  * - Access to native registers:
1966  *   - A 3D switch
1967  *   - Output mute switches
1968  */
1969
1970 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1971 {
1972         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1973         outb(data, s->iobase + CM_REG_SB16_DATA);
1974 }
1975
1976 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1977 {
1978         unsigned char v;
1979
1980         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1981         v = inb(s->iobase + CM_REG_SB16_DATA);
1982         return v;
1983 }
1984
1985 /*
1986  * general mixer element
1987  */
1988 struct cmipci_sb_reg {
1989         unsigned int left_reg, right_reg;
1990         unsigned int left_shift, right_shift;
1991         unsigned int mask;
1992         unsigned int invert: 1;
1993         unsigned int stereo: 1;
1994 };
1995
1996 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1997  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1998
1999 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
2000 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2001   .info = snd_cmipci_info_volume, \
2002   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
2003   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2004 }
2005
2006 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2007 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2008 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2009 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2010
2011 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2012 {
2013         r->left_reg = val & 0xff;
2014         r->right_reg = (val >> 8) & 0xff;
2015         r->left_shift = (val >> 16) & 0x07;
2016         r->right_shift = (val >> 19) & 0x07;
2017         r->invert = (val >> 22) & 1;
2018         r->stereo = (val >> 23) & 1;
2019         r->mask = (val >> 24) & 0xff;
2020 }
2021
2022 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2023                                   struct snd_ctl_elem_info *uinfo)
2024 {
2025         struct cmipci_sb_reg reg;
2026
2027         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2028         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2029         uinfo->count = reg.stereo + 1;
2030         uinfo->value.integer.min = 0;
2031         uinfo->value.integer.max = reg.mask;
2032         return 0;
2033 }
2034
2035 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2036                                  struct snd_ctl_elem_value *ucontrol)
2037 {
2038         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2039         struct cmipci_sb_reg reg;
2040         int val;
2041
2042         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2043         spin_lock_irq(&cm->reg_lock);
2044         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2045         if (reg.invert)
2046                 val = reg.mask - val;
2047         ucontrol->value.integer.value[0] = val;
2048         if (reg.stereo) {
2049                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2050                 if (reg.invert)
2051                         val = reg.mask - val;
2052                 ucontrol->value.integer.value[1] = val;
2053         }
2054         spin_unlock_irq(&cm->reg_lock);
2055         return 0;
2056 }
2057
2058 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2059                                  struct snd_ctl_elem_value *ucontrol)
2060 {
2061         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2062         struct cmipci_sb_reg reg;
2063         int change;
2064         int left, right, oleft, oright;
2065
2066         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2067         left = ucontrol->value.integer.value[0] & reg.mask;
2068         if (reg.invert)
2069                 left = reg.mask - left;
2070         left <<= reg.left_shift;
2071         if (reg.stereo) {
2072                 right = ucontrol->value.integer.value[1] & reg.mask;
2073                 if (reg.invert)
2074                         right = reg.mask - right;
2075                 right <<= reg.right_shift;
2076         } else
2077                 right = 0;
2078         spin_lock_irq(&cm->reg_lock);
2079         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2080         left |= oleft & ~(reg.mask << reg.left_shift);
2081         change = left != oleft;
2082         if (reg.stereo) {
2083                 if (reg.left_reg != reg.right_reg) {
2084                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
2085                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2086                 } else
2087                         oright = left;
2088                 right |= oright & ~(reg.mask << reg.right_shift);
2089                 change |= right != oright;
2090                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2091         } else
2092                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2093         spin_unlock_irq(&cm->reg_lock);
2094         return change;
2095 }
2096
2097 /*
2098  * input route (left,right) -> (left,right)
2099  */
2100 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2101 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2102   .info = snd_cmipci_info_input_sw, \
2103   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2104   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2105 }
2106
2107 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2108                                     struct snd_ctl_elem_info *uinfo)
2109 {
2110         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2111         uinfo->count = 4;
2112         uinfo->value.integer.min = 0;
2113         uinfo->value.integer.max = 1;
2114         return 0;
2115 }
2116
2117 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2118                                    struct snd_ctl_elem_value *ucontrol)
2119 {
2120         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2121         struct cmipci_sb_reg reg;
2122         int val1, val2;
2123
2124         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2125         spin_lock_irq(&cm->reg_lock);
2126         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2127         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2128         spin_unlock_irq(&cm->reg_lock);
2129         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2130         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2131         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2132         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2133         return 0;
2134 }
2135
2136 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2137                                    struct snd_ctl_elem_value *ucontrol)
2138 {
2139         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2140         struct cmipci_sb_reg reg;
2141         int change;
2142         int val1, val2, oval1, oval2;
2143
2144         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2145         spin_lock_irq(&cm->reg_lock);
2146         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2147         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2148         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2149         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2150         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2151         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2152         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2153         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2154         change = val1 != oval1 || val2 != oval2;
2155         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2156         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2157         spin_unlock_irq(&cm->reg_lock);
2158         return change;
2159 }
2160
2161 /*
2162  * native mixer switches/volumes
2163  */
2164
2165 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2166 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2167   .info = snd_cmipci_info_native_mixer, \
2168   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2169   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2170 }
2171
2172 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2173 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2174   .info = snd_cmipci_info_native_mixer, \
2175   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2176   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2177 }
2178
2179 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2180 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2181   .info = snd_cmipci_info_native_mixer, \
2182   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2183   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2184 }
2185
2186 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2187 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2188   .info = snd_cmipci_info_native_mixer, \
2189   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2190   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2191 }
2192
2193 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2194                                         struct snd_ctl_elem_info *uinfo)
2195 {
2196         struct cmipci_sb_reg reg;
2197
2198         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2199         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2200         uinfo->count = reg.stereo + 1;
2201         uinfo->value.integer.min = 0;
2202         uinfo->value.integer.max = reg.mask;
2203         return 0;
2204
2205 }
2206
2207 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2208                                        struct snd_ctl_elem_value *ucontrol)
2209 {
2210         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2211         struct cmipci_sb_reg reg;
2212         unsigned char oreg, val;
2213
2214         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2215         spin_lock_irq(&cm->reg_lock);
2216         oreg = inb(cm->iobase + reg.left_reg);
2217         val = (oreg >> reg.left_shift) & reg.mask;
2218         if (reg.invert)
2219                 val = reg.mask - val;
2220         ucontrol->value.integer.value[0] = val;
2221         if (reg.stereo) {
2222                 val = (oreg >> reg.right_shift) & reg.mask;
2223                 if (reg.invert)
2224                         val = reg.mask - val;
2225                 ucontrol->value.integer.value[1] = val;
2226         }
2227         spin_unlock_irq(&cm->reg_lock);
2228         return 0;
2229 }
2230
2231 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2232                                        struct snd_ctl_elem_value *ucontrol)
2233 {
2234         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2235         struct cmipci_sb_reg reg;
2236         unsigned char oreg, nreg, val;
2237
2238         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2239         spin_lock_irq(&cm->reg_lock);
2240         oreg = inb(cm->iobase + reg.left_reg);
2241         val = ucontrol->value.integer.value[0] & reg.mask;
2242         if (reg.invert)
2243                 val = reg.mask - val;
2244         nreg = oreg & ~(reg.mask << reg.left_shift);
2245         nreg |= (val << reg.left_shift);
2246         if (reg.stereo) {
2247                 val = ucontrol->value.integer.value[1] & reg.mask;
2248                 if (reg.invert)
2249                         val = reg.mask - val;
2250                 nreg &= ~(reg.mask << reg.right_shift);
2251                 nreg |= (val << reg.right_shift);
2252         }
2253         outb(nreg, cm->iobase + reg.left_reg);
2254         spin_unlock_irq(&cm->reg_lock);
2255         return (nreg != oreg);
2256 }
2257
2258 /*
2259  * special case - check mixer sensitivity
2260  */
2261 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2262                                                  struct snd_ctl_elem_value *ucontrol)
2263 {
2264         //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2265         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2266 }
2267
2268 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2269                                                  struct snd_ctl_elem_value *ucontrol)
2270 {
2271         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2272         if (cm->mixer_insensitive) {
2273                 /* ignored */
2274                 return 0;
2275         }
2276         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2277 }
2278
2279
2280 static struct snd_kcontrol_new snd_cmipci_mixers[] = {
2281         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2282         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2283         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2284         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2285         { /* switch with sensitivity */
2286                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2287                 .name = "PCM Playback Switch",
2288                 .info = snd_cmipci_info_native_mixer,
2289                 .get = snd_cmipci_get_native_mixer_sensitive,
2290                 .put = snd_cmipci_put_native_mixer_sensitive,
2291                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2292         },
2293         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2294         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2295         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2296         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2297         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2298         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2299         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2300         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2301         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2302         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2303         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2304         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2305         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2306         CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2307         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2308         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2309         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2310         CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2311         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2312         CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2313         CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2314         CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2315         CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2316 };
2317
2318 /*
2319  * other switches
2320  */
2321
2322 struct cmipci_switch_args {
2323         int reg;                /* register index */
2324         unsigned int mask;      /* mask bits */
2325         unsigned int mask_on;   /* mask bits to turn on */
2326         unsigned int is_byte: 1;                /* byte access? */
2327         unsigned int ac3_sensitive: 1;  /* access forbidden during
2328                                          * non-audio operation?
2329                                          */
2330 };
2331
2332 #define snd_cmipci_uswitch_info         snd_ctl_boolean_mono_info
2333
2334 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2335                                    struct snd_ctl_elem_value *ucontrol,
2336                                    struct cmipci_switch_args *args)
2337 {
2338         unsigned int val;
2339         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2340
2341         spin_lock_irq(&cm->reg_lock);
2342         if (args->ac3_sensitive && cm->mixer_insensitive) {
2343                 ucontrol->value.integer.value[0] = 0;
2344                 spin_unlock_irq(&cm->reg_lock);
2345                 return 0;
2346         }
2347         if (args->is_byte)
2348                 val = inb(cm->iobase + args->reg);
2349         else
2350                 val = snd_cmipci_read(cm, args->reg);
2351         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2352         spin_unlock_irq(&cm->reg_lock);
2353         return 0;
2354 }
2355
2356 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2357                                   struct snd_ctl_elem_value *ucontrol)
2358 {
2359         struct cmipci_switch_args *args;
2360         args = (struct cmipci_switch_args *)kcontrol->private_value;
2361         if (snd_BUG_ON(!args))
2362                 return -EINVAL;
2363         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2364 }
2365
2366 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2367                                    struct snd_ctl_elem_value *ucontrol,
2368                                    struct cmipci_switch_args *args)
2369 {
2370         unsigned int val;
2371         int change;
2372         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2373
2374         spin_lock_irq(&cm->reg_lock);
2375         if (args->ac3_sensitive && cm->mixer_insensitive) {
2376                 /* ignored */
2377                 spin_unlock_irq(&cm->reg_lock);
2378                 return 0;
2379         }
2380         if (args->is_byte)
2381                 val = inb(cm->iobase + args->reg);
2382         else
2383                 val = snd_cmipci_read(cm, args->reg);
2384         change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2385                         args->mask_on : (args->mask & ~args->mask_on));
2386         if (change) {
2387                 val &= ~args->mask;
2388                 if (ucontrol->value.integer.value[0])
2389                         val |= args->mask_on;
2390                 else
2391                         val |= (args->mask & ~args->mask_on);
2392                 if (args->is_byte)
2393                         outb((unsigned char)val, cm->iobase + args->reg);
2394                 else
2395                         snd_cmipci_write(cm, args->reg, val);
2396         }
2397         spin_unlock_irq(&cm->reg_lock);
2398         return change;
2399 }
2400
2401 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2402                                   struct snd_ctl_elem_value *ucontrol)
2403 {
2404         struct cmipci_switch_args *args;
2405         args = (struct cmipci_switch_args *)kcontrol->private_value;
2406         if (snd_BUG_ON(!args))
2407                 return -EINVAL;
2408         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2409 }
2410
2411 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2412 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2413   .reg = xreg, \
2414   .mask = xmask, \
2415   .mask_on = xmask_on, \
2416   .is_byte = xis_byte, \
2417   .ac3_sensitive = xac3, \
2418 }
2419
2420 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2421         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2422
2423 #if 0 /* these will be controlled in pcm device */
2424 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2425 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2426 #endif
2427 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2428 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2429 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2430 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2431 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2432 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2433 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2434 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2435 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2436 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2437 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2438 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2439 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2440 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2441 #if CM_CH_PLAY == 1
2442 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2443 #else
2444 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2445 #endif
2446 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2447 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2448 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2449 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2450 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2451
2452 #define DEFINE_SWITCH(sname, stype, sarg) \
2453 { .name = sname, \
2454   .iface = stype, \
2455   .info = snd_cmipci_uswitch_info, \
2456   .get = snd_cmipci_uswitch_get, \
2457   .put = snd_cmipci_uswitch_put, \
2458   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2459 }
2460
2461 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2462 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2463
2464
2465 /*
2466  * callbacks for spdif output switch
2467  * needs toggle two registers..
2468  */
2469 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2470                                         struct snd_ctl_elem_value *ucontrol)
2471 {
2472         int changed;
2473         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2474         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2475         return changed;
2476 }
2477
2478 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2479                                         struct snd_ctl_elem_value *ucontrol)
2480 {
2481         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2482         int changed;
2483         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2484         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2485         if (changed) {
2486                 if (ucontrol->value.integer.value[0]) {
2487                         if (chip->spdif_playback_avail)
2488                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2489                 } else {
2490                         if (chip->spdif_playback_avail)
2491                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2492                 }
2493         }
2494         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2495         return changed;
2496 }
2497
2498
2499 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2500                                         struct snd_ctl_elem_info *uinfo)
2501 {
2502         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2503         static const char *const texts[3] = {
2504                 "Line-In", "Rear Output", "Bass Output"
2505         };
2506
2507         return snd_ctl_enum_info(uinfo, 1,
2508                                  cm->chip_version >= 39 ? 3 : 2, texts);
2509 }
2510
2511 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2512 {
2513         unsigned int val;
2514         if (cm->chip_version >= 39) {
2515                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2516                 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2517                         return 2;
2518         }
2519         val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2520         if (val & CM_REAR2LIN)
2521                 return 1;
2522         return 0;
2523 }
2524
2525 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2526                                        struct snd_ctl_elem_value *ucontrol)
2527 {
2528         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2529
2530         spin_lock_irq(&cm->reg_lock);
2531         ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2532         spin_unlock_irq(&cm->reg_lock);
2533         return 0;
2534 }
2535
2536 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2537                                        struct snd_ctl_elem_value *ucontrol)
2538 {
2539         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2540         int change;
2541
2542         spin_lock_irq(&cm->reg_lock);
2543         if (ucontrol->value.enumerated.item[0] == 2)
2544                 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2545         else
2546                 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2547         if (ucontrol->value.enumerated.item[0] == 1)
2548                 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2549         else
2550                 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2551         spin_unlock_irq(&cm->reg_lock);
2552         return change;
2553 }
2554
2555 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2556                                        struct snd_ctl_elem_info *uinfo)
2557 {
2558         static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2559
2560         return snd_ctl_enum_info(uinfo, 1, 2, texts);
2561 }
2562
2563 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2564                                       struct snd_ctl_elem_value *ucontrol)
2565 {
2566         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2567         /* same bit as spdi_phase */
2568         spin_lock_irq(&cm->reg_lock);
2569         ucontrol->value.enumerated.item[0] =
2570                 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2571         spin_unlock_irq(&cm->reg_lock);
2572         return 0;
2573 }
2574
2575 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2576                                       struct snd_ctl_elem_value *ucontrol)
2577 {
2578         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2579         int change;
2580
2581         spin_lock_irq(&cm->reg_lock);
2582         if (ucontrol->value.enumerated.item[0])
2583                 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2584         else
2585                 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2586         spin_unlock_irq(&cm->reg_lock);
2587         return change;
2588 }
2589
2590 /* both for CM8338/8738 */
2591 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2592         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2593         {
2594                 .name = "Line-In Mode",
2595                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2596                 .info = snd_cmipci_line_in_mode_info,
2597                 .get = snd_cmipci_line_in_mode_get,
2598                 .put = snd_cmipci_line_in_mode_put,
2599         },
2600 };
2601
2602 /* for non-multichannel chips */
2603 static struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2604 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2605
2606 /* only for CM8738 */
2607 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2608 #if 0 /* controlled in pcm device */
2609         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2610         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2611         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2612 #endif
2613         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2614         { .name = "IEC958 Output Switch",
2615           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2616           .info = snd_cmipci_uswitch_info,
2617           .get = snd_cmipci_spdout_enable_get,
2618           .put = snd_cmipci_spdout_enable_put,
2619         },
2620         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2621         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2622         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2623 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2624         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2625         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2626 };
2627
2628 /* only for model 033/037 */
2629 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2630         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2631         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2632         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2633 };
2634
2635 /* only for model 039 or later */
2636 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2637         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2638         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2639         {
2640                 .name = "Mic-In Mode",
2641                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2642                 .info = snd_cmipci_mic_in_mode_info,
2643                 .get = snd_cmipci_mic_in_mode_get,
2644                 .put = snd_cmipci_mic_in_mode_put,
2645         }
2646 };
2647
2648 /* card control switches */
2649 static struct snd_kcontrol_new snd_cmipci_modem_switch =
2650 DEFINE_CARD_SWITCH("Modem", modem);
2651
2652
2653 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2654 {
2655         struct snd_card *card;
2656         struct snd_kcontrol_new *sw;
2657         struct snd_kcontrol *kctl;
2658         unsigned int idx;
2659         int err;
2660
2661         if (snd_BUG_ON(!cm || !cm->card))
2662                 return -EINVAL;
2663
2664         card = cm->card;
2665
2666         strcpy(card->mixername, "CMedia PCI");
2667
2668         spin_lock_irq(&cm->reg_lock);
2669         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2670         spin_unlock_irq(&cm->reg_lock);
2671
2672         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2673                 if (cm->chip_version == 68) {   // 8768 has no PCM volume
2674                         if (!strcmp(snd_cmipci_mixers[idx].name,
2675                                 "PCM Playback Volume"))
2676                                 continue;
2677                 }
2678                 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2679                         return err;
2680         }
2681
2682         /* mixer switches */
2683         sw = snd_cmipci_mixer_switches;
2684         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2685                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2686                 if (err < 0)
2687                         return err;
2688         }
2689         if (! cm->can_multi_ch) {
2690                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2691                 if (err < 0)
2692                         return err;
2693         }
2694         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2695             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2696                 sw = snd_cmipci_8738_mixer_switches;
2697                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2698                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2699                         if (err < 0)
2700                                 return err;
2701                 }
2702                 if (cm->can_ac3_hw) {
2703                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2704                                 return err;
2705                         kctl->id.device = pcm_spdif_device;
2706                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2707                                 return err;
2708                         kctl->id.device = pcm_spdif_device;
2709                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2710                                 return err;
2711                         kctl->id.device = pcm_spdif_device;
2712                 }
2713                 if (cm->chip_version <= 37) {
2714                         sw = snd_cmipci_old_mixer_switches;
2715                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2716                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2717                                 if (err < 0)
2718                                         return err;
2719                         }
2720                 }
2721         }
2722         if (cm->chip_version >= 39) {
2723                 sw = snd_cmipci_extra_mixer_switches;
2724                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2725                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2726                         if (err < 0)
2727                                 return err;
2728                 }
2729         }
2730
2731         /* card switches */
2732         /*
2733          * newer chips don't have the register bits to force modem link
2734          * detection; the bit that was FLINKON now mutes CH1
2735          */
2736         if (cm->chip_version < 39) {
2737                 err = snd_ctl_add(cm->card,
2738                                   snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2739                 if (err < 0)
2740                         return err;
2741         }
2742
2743         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2744                 struct snd_ctl_elem_id elem_id;
2745                 struct snd_kcontrol *ctl;
2746                 memset(&elem_id, 0, sizeof(elem_id));
2747                 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2748                 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2749                 ctl = snd_ctl_find_id(cm->card, &elem_id);
2750                 if (ctl)
2751                         cm->mixer_res_ctl[idx] = ctl;
2752         }
2753
2754         return 0;
2755 }
2756
2757
2758 /*
2759  * proc interface
2760  */
2761
2762 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2763                                  struct snd_info_buffer *buffer)
2764 {
2765         struct cmipci *cm = entry->private_data;
2766         int i, v;
2767
2768         snd_iprintf(buffer, "%s\n", cm->card->longname);
2769         for (i = 0; i < 0x94; i++) {
2770                 if (i == 0x28)
2771                         i = 0x90;
2772                 v = inb(cm->iobase + i);
2773                 if (i % 4 == 0)
2774                         snd_iprintf(buffer, "\n%02x:", i);
2775                 snd_iprintf(buffer, " %02x", v);
2776         }
2777         snd_iprintf(buffer, "\n");
2778 }
2779
2780 static void snd_cmipci_proc_init(struct cmipci *cm)
2781 {
2782         snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2783 }
2784
2785 static const struct pci_device_id snd_cmipci_ids[] = {
2786         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2787         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2788         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2789         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2790         {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2791         {0,},
2792 };
2793
2794
2795 /*
2796  * check chip version and capabilities
2797  * driver name is modified according to the chip model
2798  */
2799 static void query_chip(struct cmipci *cm)
2800 {
2801         unsigned int detect;
2802
2803         /* check reg 0Ch, bit 24-31 */
2804         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2805         if (! detect) {
2806                 /* check reg 08h, bit 24-28 */
2807                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2808                 switch (detect) {
2809                 case 0:
2810                         cm->chip_version = 33;
2811                         if (cm->do_soft_ac3)
2812                                 cm->can_ac3_sw = 1;
2813                         else
2814                                 cm->can_ac3_hw = 1;
2815                         break;
2816                 case CM_CHIP_037:
2817                         cm->chip_version = 37;
2818                         cm->can_ac3_hw = 1;
2819                         break;
2820                 default:
2821                         cm->chip_version = 39;
2822                         cm->can_ac3_hw = 1;
2823                         break;
2824                 }
2825                 cm->max_channels = 2;
2826         } else {
2827                 if (detect & CM_CHIP_039) {
2828                         cm->chip_version = 39;
2829                         if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2830                                 cm->max_channels = 6;
2831                         else
2832                                 cm->max_channels = 4;
2833                 } else if (detect & CM_CHIP_8768) {
2834                         cm->chip_version = 68;
2835                         cm->max_channels = 8;
2836                         cm->can_96k = 1;
2837                 } else {
2838                         cm->chip_version = 55;
2839                         cm->max_channels = 6;
2840                         cm->can_96k = 1;
2841                 }
2842                 cm->can_ac3_hw = 1;
2843                 cm->can_multi_ch = 1;
2844         }
2845 }
2846
2847 #ifdef SUPPORT_JOYSTICK
2848 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2849 {
2850         static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2851         struct gameport *gp;
2852         struct resource *r = NULL;
2853         int i, io_port = 0;
2854
2855         if (joystick_port[dev] == 0)
2856                 return -ENODEV;
2857
2858         if (joystick_port[dev] == 1) { /* auto-detect */
2859                 for (i = 0; ports[i]; i++) {
2860                         io_port = ports[i];
2861                         r = request_region(io_port, 1, "CMIPCI gameport");
2862                         if (r)
2863                                 break;
2864                 }
2865         } else {
2866                 io_port = joystick_port[dev];
2867                 r = request_region(io_port, 1, "CMIPCI gameport");
2868         }
2869
2870         if (!r) {
2871                 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2872                 return -EBUSY;
2873         }
2874
2875         cm->gameport = gp = gameport_allocate_port();
2876         if (!gp) {
2877                 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2878                 release_and_free_resource(r);
2879                 return -ENOMEM;
2880         }
2881         gameport_set_name(gp, "C-Media Gameport");
2882         gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2883         gameport_set_dev_parent(gp, &cm->pci->dev);
2884         gp->io = io_port;
2885         gameport_set_port_data(gp, r);
2886
2887         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2888
2889         gameport_register_port(cm->gameport);
2890
2891         return 0;
2892 }
2893
2894 static void snd_cmipci_free_gameport(struct cmipci *cm)
2895 {
2896         if (cm->gameport) {
2897                 struct resource *r = gameport_get_port_data(cm->gameport);
2898
2899                 gameport_unregister_port(cm->gameport);
2900                 cm->gameport = NULL;
2901
2902                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2903                 release_and_free_resource(r);
2904         }
2905 }
2906 #else
2907 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2908 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2909 #endif
2910
2911 static int snd_cmipci_free(struct cmipci *cm)
2912 {
2913         if (cm->irq >= 0) {
2914                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2915                 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2916                 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2917                 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2918                 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2919                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2920                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2921
2922                 /* reset mixer */
2923                 snd_cmipci_mixer_write(cm, 0, 0);
2924
2925                 free_irq(cm->irq, cm);
2926         }
2927
2928         snd_cmipci_free_gameport(cm);
2929         pci_release_regions(cm->pci);
2930         pci_disable_device(cm->pci);
2931         kfree(cm);
2932         return 0;
2933 }
2934
2935 static int snd_cmipci_dev_free(struct snd_device *device)
2936 {
2937         struct cmipci *cm = device->device_data;
2938         return snd_cmipci_free(cm);
2939 }
2940
2941 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2942 {
2943         long iosynth;
2944         unsigned int val;
2945         struct snd_opl3 *opl3;
2946         int err;
2947
2948         if (!fm_port)
2949                 goto disable_fm;
2950
2951         if (cm->chip_version >= 39) {
2952                 /* first try FM regs in PCI port range */
2953                 iosynth = cm->iobase + CM_REG_FM_PCI;
2954                 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2955                                       OPL3_HW_OPL3, 1, &opl3);
2956         } else {
2957                 err = -EIO;
2958         }
2959         if (err < 0) {
2960                 /* then try legacy ports */
2961                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2962                 iosynth = fm_port;
2963                 switch (iosynth) {
2964                 case 0x3E8: val |= CM_FMSEL_3E8; break;
2965                 case 0x3E0: val |= CM_FMSEL_3E0; break;
2966                 case 0x3C8: val |= CM_FMSEL_3C8; break;
2967                 case 0x388: val |= CM_FMSEL_388; break;
2968                 default:
2969                         goto disable_fm;
2970                 }
2971                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2972                 /* enable FM */
2973                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2974
2975                 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2976                                     OPL3_HW_OPL3, 0, &opl3) < 0) {
2977                         dev_err(cm->card->dev,
2978                                 "no OPL device at %#lx, skipping...\n",
2979                                 iosynth);
2980                         goto disable_fm;
2981                 }
2982         }
2983         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2984                 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2985                 return err;
2986         }
2987         return 0;
2988
2989  disable_fm:
2990         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2991         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2992         return 0;
2993 }
2994
2995 static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2996                              int dev, struct cmipci **rcmipci)
2997 {
2998         struct cmipci *cm;
2999         int err;
3000         static struct snd_device_ops ops = {
3001                 .dev_free =     snd_cmipci_dev_free,
3002         };
3003         unsigned int val;
3004         long iomidi = 0;
3005         int integrated_midi = 0;
3006         char modelstr[16];
3007         int pcm_index, pcm_spdif_index;
3008         static const struct pci_device_id intel_82437vx[] = {
3009                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3010                 { },
3011         };
3012
3013         *rcmipci = NULL;
3014
3015         if ((err = pci_enable_device(pci)) < 0)
3016                 return err;
3017
3018         cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3019         if (cm == NULL) {
3020                 pci_disable_device(pci);
3021                 return -ENOMEM;
3022         }
3023
3024         spin_lock_init(&cm->reg_lock);
3025         mutex_init(&cm->open_mutex);
3026         cm->device = pci->device;
3027         cm->card = card;
3028         cm->pci = pci;
3029         cm->irq = -1;
3030         cm->channel[0].ch = 0;
3031         cm->channel[1].ch = 1;
3032         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3033
3034         if ((err = pci_request_regions(pci, card->driver)) < 0) {
3035                 kfree(cm);
3036                 pci_disable_device(pci);
3037                 return err;
3038         }
3039         cm->iobase = pci_resource_start(pci, 0);
3040
3041         if (request_irq(pci->irq, snd_cmipci_interrupt,
3042                         IRQF_SHARED, KBUILD_MODNAME, cm)) {
3043                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3044                 snd_cmipci_free(cm);
3045                 return -EBUSY;
3046         }
3047         cm->irq = pci->irq;
3048
3049         pci_set_master(cm->pci);
3050
3051         /*
3052          * check chip version, max channels and capabilities
3053          */
3054
3055         cm->chip_version = 0;
3056         cm->max_channels = 2;
3057         cm->do_soft_ac3 = soft_ac3[dev];
3058
3059         if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3060             pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3061                 query_chip(cm);
3062         /* added -MCx suffix for chip supporting multi-channels */
3063         if (cm->can_multi_ch)
3064                 sprintf(cm->card->driver + strlen(cm->card->driver),
3065                         "-MC%d", cm->max_channels);
3066         else if (cm->can_ac3_sw)
3067                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3068
3069         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3070         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3071
3072 #if CM_CH_PLAY == 1
3073         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
3074 #else
3075         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
3076 #endif
3077
3078         /* initialize codec registers */
3079         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3080         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3081         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
3082         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3083         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3084         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
3085         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3086
3087         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3088         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3089 #if CM_CH_PLAY == 1
3090         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3091 #else
3092         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3093 #endif
3094         if (cm->chip_version) {
3095                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3096                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3097         }
3098         /* Set Bus Master Request */
3099         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3100
3101         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3102         switch (pci->device) {
3103         case PCI_DEVICE_ID_CMEDIA_CM8738:
3104         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3105                 if (!pci_dev_present(intel_82437vx))
3106                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3107                 break;
3108         default:
3109                 break;
3110         }
3111
3112         if (cm->chip_version < 68) {
3113                 val = pci->device < 0x110 ? 8338 : 8738;
3114         } else {
3115                 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3116                 case 0:
3117                         val = 8769;
3118                         break;
3119                 case 2:
3120                         val = 8762;
3121                         break;
3122                 default:
3123                         switch ((pci->subsystem_vendor << 16) |
3124                                 pci->subsystem_device) {
3125                         case 0x13f69761:
3126                         case 0x584d3741:
3127                         case 0x584d3751:
3128                         case 0x584d3761:
3129                         case 0x584d3771:
3130                         case 0x72848384:
3131                                 val = 8770;
3132                                 break;
3133                         default:
3134                                 val = 8768;
3135                                 break;
3136                         }
3137                 }
3138         }
3139         sprintf(card->shortname, "C-Media CMI%d", val);
3140         if (cm->chip_version < 68)
3141                 sprintf(modelstr, " (model %d)", cm->chip_version);
3142         else
3143                 modelstr[0] = '\0';
3144         sprintf(card->longname, "%s%s at %#lx, irq %i",
3145                 card->shortname, modelstr, cm->iobase, cm->irq);
3146
3147         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3148                 snd_cmipci_free(cm);
3149                 return err;
3150         }
3151
3152         if (cm->chip_version >= 39) {
3153                 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3154                 if (val != 0x00 && val != 0xff) {
3155                         iomidi = cm->iobase + CM_REG_MPU_PCI;
3156                         integrated_midi = 1;
3157                 }
3158         }
3159         if (!integrated_midi) {
3160                 val = 0;
3161                 iomidi = mpu_port[dev];
3162                 switch (iomidi) {
3163                 case 0x320: val = CM_VMPU_320; break;
3164                 case 0x310: val = CM_VMPU_310; break;
3165                 case 0x300: val = CM_VMPU_300; break;
3166                 case 0x330: val = CM_VMPU_330; break;
3167                 default:
3168                             iomidi = 0; break;
3169                 }
3170                 if (iomidi > 0) {
3171                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3172                         /* enable UART */
3173                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3174                         if (inb(iomidi + 1) == 0xff) {
3175                                 dev_err(cm->card->dev,
3176                                         "cannot enable MPU-401 port at %#lx\n",
3177                                         iomidi);
3178                                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3179                                                      CM_UART_EN);
3180                                 iomidi = 0;
3181                         }
3182                 }
3183         }
3184
3185         if (cm->chip_version < 68) {
3186                 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3187                 if (err < 0)
3188                         return err;
3189         }
3190
3191         /* reset mixer */
3192         snd_cmipci_mixer_write(cm, 0, 0);
3193
3194         snd_cmipci_proc_init(cm);
3195
3196         /* create pcm devices */
3197         pcm_index = pcm_spdif_index = 0;
3198         if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3199                 return err;
3200         pcm_index++;
3201         if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3202                 return err;
3203         pcm_index++;
3204         if (cm->can_ac3_hw || cm->can_ac3_sw) {
3205                 pcm_spdif_index = pcm_index;
3206                 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3207                         return err;
3208         }
3209
3210         /* create mixer interface & switches */
3211         if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3212                 return err;
3213
3214         if (iomidi > 0) {
3215                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3216                                                iomidi,
3217                                                (integrated_midi ?
3218                                                 MPU401_INFO_INTEGRATED : 0) |
3219                                                MPU401_INFO_IRQ_HOOK,
3220                                                -1, &cm->rmidi)) < 0) {
3221                         dev_err(cm->card->dev,
3222                                 "no UART401 device at 0x%lx\n", iomidi);
3223                 }
3224         }
3225
3226 #ifdef USE_VAR48KRATE
3227         for (val = 0; val < ARRAY_SIZE(rates); val++)
3228                 snd_cmipci_set_pll(cm, rates[val], val);
3229
3230         /*
3231          * (Re-)Enable external switch spdo_48k
3232          */
3233         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3234 #endif /* USE_VAR48KRATE */
3235
3236         if (snd_cmipci_create_gameport(cm, dev) < 0)
3237                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3238
3239         *rcmipci = cm;
3240         return 0;
3241 }
3242
3243 /*
3244  */
3245
3246 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3247
3248 static int snd_cmipci_probe(struct pci_dev *pci,
3249                             const struct pci_device_id *pci_id)
3250 {
3251         static int dev;
3252         struct snd_card *card;
3253         struct cmipci *cm;
3254         int err;
3255
3256         if (dev >= SNDRV_CARDS)
3257                 return -ENODEV;
3258         if (! enable[dev]) {
3259                 dev++;
3260                 return -ENOENT;
3261         }
3262
3263         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3264                            0, &card);
3265         if (err < 0)
3266                 return err;
3267
3268         switch (pci->device) {
3269         case PCI_DEVICE_ID_CMEDIA_CM8738:
3270         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3271                 strcpy(card->driver, "CMI8738");
3272                 break;
3273         case PCI_DEVICE_ID_CMEDIA_CM8338A:
3274         case PCI_DEVICE_ID_CMEDIA_CM8338B:
3275                 strcpy(card->driver, "CMI8338");
3276                 break;
3277         default:
3278                 strcpy(card->driver, "CMIPCI");
3279                 break;
3280         }
3281
3282         err = snd_cmipci_create(card, pci, dev, &cm);
3283         if (err < 0)
3284                 goto free_card;
3285
3286         card->private_data = cm;
3287
3288         err = snd_card_register(card);
3289         if (err < 0)
3290                 goto free_card;
3291
3292         pci_set_drvdata(pci, card);
3293         dev++;
3294         return 0;
3295
3296 free_card:
3297         snd_card_free(card);
3298         return err;
3299 }
3300
3301 static void snd_cmipci_remove(struct pci_dev *pci)
3302 {
3303         snd_card_free(pci_get_drvdata(pci));
3304 }
3305
3306
3307 #ifdef CONFIG_PM_SLEEP
3308 /*
3309  * power management
3310  */
3311 static unsigned char saved_regs[] = {
3312         CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3313         CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3314         CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3315         CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3316         CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3317 };
3318
3319 static unsigned char saved_mixers[] = {
3320         SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3321         SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3322         SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3323         SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3324         SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3325         SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3326         CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3327         SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3328 };
3329
3330 static int snd_cmipci_suspend(struct device *dev)
3331 {
3332         struct snd_card *card = dev_get_drvdata(dev);
3333         struct cmipci *cm = card->private_data;
3334         int i;
3335
3336         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3337
3338         /* save registers */
3339         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3340                 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3341         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3342                 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3343
3344         /* disable ints */
3345         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3346         return 0;
3347 }
3348
3349 static int snd_cmipci_resume(struct device *dev)
3350 {
3351         struct snd_card *card = dev_get_drvdata(dev);
3352         struct cmipci *cm = card->private_data;
3353         int i;
3354
3355         /* reset / initialize to a sane state */
3356         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3357         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3358         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3359         snd_cmipci_mixer_write(cm, 0, 0);
3360
3361         /* restore registers */
3362         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3363                 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3364         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3365                 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3366
3367         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3368         return 0;
3369 }
3370
3371 static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3372 #define SND_CMIPCI_PM_OPS       &snd_cmipci_pm
3373 #else
3374 #define SND_CMIPCI_PM_OPS       NULL
3375 #endif /* CONFIG_PM_SLEEP */
3376
3377 static struct pci_driver cmipci_driver = {
3378         .name = KBUILD_MODNAME,
3379         .id_table = snd_cmipci_ids,
3380         .probe = snd_cmipci_probe,
3381         .remove = snd_cmipci_remove,
3382         .driver = {
3383                 .pm = SND_CMIPCI_PM_OPS,
3384         },
3385 };
3386
3387 module_pci_driver(cmipci_driver);