sound/pci/cmipci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
   4  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
   5  */
   6
   7 /* Does not work. Warning may block system in capture mode */
   8 /* #define USE_VAR48KRATE */
   9
  10 #include <linux/io.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/slab.h>
  16 #include <linux/gameport.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <sound/core.h>
  20 #include <sound/info.h>
  21 #include <sound/control.h>
  22 #include <sound/pcm.h>
  23 #include <sound/rawmidi.h>
  24 #include <sound/mpu401.h>
  25 #include <sound/opl3.h>
  26 #include <sound/sb.h>
  27 #include <sound/asoundef.h>
  28 #include <sound/initval.h>
  29
  30 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  31 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  32 MODULE_LICENSE("GPL");
  33
  34 #if IS_REACHABLE(CONFIG_GAMEPORT)
  35 #define SUPPORT_JOYSTICK 1
  36 #endif
  37
  38 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  39 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  40 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  41 static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
  42 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  43 static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  44 #ifdef SUPPORT_JOYSTICK
  45 static int joystick_port[SNDRV_CARDS];
  46 #endif
  47
  48 module_param_array(index, int, NULL, 0444);
  49 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  50 module_param_array(id, charp, NULL, 0444);
  51 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  52 module_param_array(enable, bool, NULL, 0444);
  53 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  54 module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
  55 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  56 module_param_hw_array(fm_port, long, ioport, NULL, 0444);
  57 MODULE_PARM_DESC(fm_port, "FM port.");
  58 module_param_array(soft_ac3, bool, NULL, 0444);
  59 MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
  60 #ifdef SUPPORT_JOYSTICK
  61 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  62 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  63 #endif
  64
  65 /*
  66  * CM8x38 registers definition
  67  */
  68
  69 #define CM_REG_FUNCTRL0         0x00
  70 #define CM_RST_CH1              0x00080000
  71 #define CM_RST_CH0              0x00040000
  72 #define CM_CHEN1                0x00020000      /* ch1: enable */
  73 #define CM_CHEN0                0x00010000      /* ch0: enable */
  74 #define CM_PAUSE1               0x00000008      /* ch1: pause */
  75 #define CM_PAUSE0               0x00000004      /* ch0: pause */
  76 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
  77 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
  78
  79 #define CM_REG_FUNCTRL1         0x04
  80 #define CM_DSFC_MASK            0x0000E000      /* channel 1 (DAC?) sampling frequency */
  81 #define CM_DSFC_SHIFT           13
  82 #define CM_ASFC_MASK            0x00001C00      /* channel 0 (ADC?) sampling frequency */
  83 #define CM_ASFC_SHIFT           10
  84 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
  85 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
  86 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/IN -> OUT loopback */
  87 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
  88 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
  89 #define CM_BREQ                 0x00000010      /* bus master enabled */
  90 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
  91 #define CM_UART_EN              0x00000004      /* legacy UART */
  92 #define CM_JYSTK_EN             0x00000002      /* legacy joystick */
  93 #define CM_ZVPORT               0x00000001      /* ZVPORT */
  94
  95 #define CM_REG_CHFORMAT         0x08
  96
  97 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
  98 #define CM_FMOFFSET2            0x40000000      /* initial FM PCM offset 2 when Fmute=1 */
  99 #define CM_CHB3D                0x20000000      /* 4 channels */
 100
 101 #define CM_CHIP_MASK1           0x1f000000
 102 #define CM_CHIP_037             0x01000000
 103 #define CM_SETLAT48             0x00800000      /* set latency timer 48h */
 104 #define CM_EDGEIRQ              0x00400000      /* emulated edge trigger legacy IRQ */
 105 #define CM_SPD24SEL39           0x00200000      /* 24-bit spdif: model 039 */
 106 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
 107 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
 108 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
 109 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
 110
 111 #define CM_ADCBITLEN_MASK       0x0000C000
 112 #define CM_ADCBITLEN_16         0x00000000
 113 #define CM_ADCBITLEN_15         0x00004000
 114 #define CM_ADCBITLEN_14         0x00008000
 115 #define CM_ADCBITLEN_13         0x0000C000
 116
 117 #define CM_ADCDACLEN_MASK       0x00003000      /* model 037 */
 118 #define CM_ADCDACLEN_060        0x00000000
 119 #define CM_ADCDACLEN_066        0x00001000
 120 #define CM_ADCDACLEN_130        0x00002000
 121 #define CM_ADCDACLEN_280        0x00003000
 122
 123 #define CM_ADCDLEN_MASK         0x00003000      /* model 039 */
 124 #define CM_ADCDLEN_ORIGINAL     0x00000000
 125 #define CM_ADCDLEN_EXTRA        0x00001000
 126 #define CM_ADCDLEN_24K          0x00002000
 127 #define CM_ADCDLEN_WEIGHT       0x00003000
 128
 129 #define CM_CH1_SRATE_176K       0x00000800
 130 #define CM_CH1_SRATE_96K        0x00000800      /* model 055? */
 131 #define CM_CH1_SRATE_88K        0x00000400
 132 #define CM_CH0_SRATE_176K       0x00000200
 133 #define CM_CH0_SRATE_96K        0x00000200      /* model 055? */
 134 #define CM_CH0_SRATE_88K        0x00000100
 135 #define CM_CH0_SRATE_128K       0x00000300
 136 #define CM_CH0_SRATE_MASK       0x00000300
 137
 138 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
 139 #define CM_DBLSPDS              0x00000040      /* double SPDIF sample rate 88.2/96 */
 140 #define CM_POLVALID             0x00000020      /* inverse SPDIF/IN valid bit */
 141 #define CM_SPDLOCKED            0x00000010
 142
 143 #define CM_CH1FMT_MASK          0x0000000C      /* bit 3: 16 bits, bit 2: stereo */
 144 #define CM_CH1FMT_SHIFT         2
 145 #define CM_CH0FMT_MASK          0x00000003      /* bit 1: 16 bits, bit 0: stereo */
 146 #define CM_CH0FMT_SHIFT         0
 147
 148 #define CM_REG_INT_HLDCLR       0x0C
 149 #define CM_CHIP_MASK2           0xff000000
 150 #define CM_CHIP_8768            0x20000000
 151 #define CM_CHIP_055             0x08000000
 152 #define CM_CHIP_039             0x04000000
 153 #define CM_CHIP_039_6CH         0x01000000
 154 #define CM_UNKNOWN_INT_EN       0x00080000      /* ? */
 155 #define CM_TDMA_INT_EN          0x00040000
 156 #define CM_CH1_INT_EN           0x00020000
 157 #define CM_CH0_INT_EN           0x00010000
 158
 159 #define CM_REG_INT_STATUS       0x10
 160 #define CM_INTR                 0x80000000
 161 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
 162 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
 163 #define CM_UARTINT              0x00010000
 164 #define CM_LTDMAINT             0x00008000
 165 #define CM_HTDMAINT             0x00004000
 166 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
 167 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
 168 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
 169 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
 170 #define CM_CH1BUSY              0x00000008
 171 #define CM_CH0BUSY              0x00000004
 172 #define CM_CHINT1               0x00000002
 173 #define CM_CHINT0               0x00000001
 174
 175 #define CM_REG_LEGACY_CTRL      0x14
 176 #define CM_NXCHG                0x80000000      /* don't map base reg dword->sample */
 177 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
 178 #define CM_VMPU_330             0x00000000
 179 #define CM_VMPU_320             0x20000000
 180 #define CM_VMPU_310             0x40000000
 181 #define CM_VMPU_300             0x60000000
 182 #define CM_ENWR8237             0x10000000      /* enable bus master to write 8237 base reg */
 183 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
 184 #define CM_VSBSEL_220           0x00000000
 185 #define CM_VSBSEL_240           0x04000000
 186 #define CM_VSBSEL_260           0x08000000
 187 #define CM_VSBSEL_280           0x0C000000
 188 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
 189 #define CM_FMSEL_388            0x00000000
 190 #define CM_FMSEL_3C8            0x01000000
 191 #define CM_FMSEL_3E0            0x02000000
 192 #define CM_FMSEL_3E8            0x03000000
 193 #define CM_ENSPDOUT             0x00800000      /* enable XSPDIF/OUT to I/O interface */
 194 #define CM_SPDCOPYRHT           0x00400000      /* spdif in/out copyright bit */
 195 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
 196 #define CM_INVIDWEN             0x00100000      /* internal vendor ID write enable, model 039? */
 197 #define CM_SETRETRY             0x00100000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
 198 #define CM_C_EEACCESS           0x00080000      /* direct programming eeprom regs */
 199 #define CM_C_EECS               0x00040000
 200 #define CM_C_EEDI46             0x00020000
 201 #define CM_C_EECK46             0x00010000
 202 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
 203 #define CM_CENTR2LIN            0x00004000      /* line-in as center out */
 204 #define CM_BASE2LIN             0x00002000      /* line-in as bass out */
 205 #define CM_EXBASEN              0x00001000      /* external bass input enable */
 206
 207 #define CM_REG_MISC_CTRL        0x18
 208 #define CM_PWD                  0x80000000      /* power down */
 209 #define CM_RESET                0x40000000
 210 #define CM_SFIL_MASK            0x30000000      /* filter control at front end DAC, model 037? */
 211 #define CM_VMGAIN               0x10000000      /* analog master amp +6dB, model 039? */
 212 #define CM_TXVX                 0x08000000      /* model 037? */
 213 #define CM_N4SPK3D              0x04000000      /* copy front to rear */
 214 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
 215 #define CM_SPDIF48K             0x01000000      /* write */
 216 #define CM_SPATUS48K            0x01000000      /* read */
 217 #define CM_ENDBDAC              0x00800000      /* enable double dac */
 218 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
 219 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
 220 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-OUT -> int. IN */
 221 #define CM_FM_EN                0x00080000      /* enable legacy FM */
 222 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
 223 #define CM_ENWRASID             0x00010000      /* choose writable internal SUBID (audio) */
 224 #define CM_VIDWPDSB             0x00010000      /* model 037? */
 225 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
 226 #define CM_MASK_EN              0x00004000      /* activate channel mask on legacy DMA */
 227 #define CM_ENWRMSID             0x00002000      /* choose writable internal SUBID (modem) */
 228 #define CM_VIDWPPRT             0x00002000      /* model 037? */
 229 #define CM_SFILENB              0x00001000      /* filter stepping at front end DAC, model 037? */
 230 #define CM_MMODE_MASK           0x00000E00      /* model DAA interface mode */
 231 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
 232 #define CM_ENCENTER             0x00000080
 233 #define CM_FLINKON              0x00000040      /* force modem link detection on, model 037 */
 234 #define CM_MUTECH1              0x00000040      /* mute PCI ch1 to DAC */
 235 #define CM_FLINKOFF             0x00000020      /* force modem link detection off, model 037 */
 236 #define CM_MIDSMP               0x00000010      /* 1/2 interpolation at front end DAC */
 237 #define CM_UPDDMA_MASK          0x0000000C      /* TDMA position update notification */
 238 #define CM_UPDDMA_2048          0x00000000
 239 #define CM_UPDDMA_1024          0x00000004
 240 #define CM_UPDDMA_512           0x00000008
 241 #define CM_UPDDMA_256           0x0000000C
 242 #define CM_TWAIT_MASK           0x00000003      /* model 037 */
 243 #define CM_TWAIT1               0x00000002      /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
 244 #define CM_TWAIT0               0x00000001      /* i/o cycle, 0: 4, 1: 6 PCICLKs */
 245
 246 #define CM_REG_TDMA_POSITION    0x1C
 247 #define CM_TDMA_CNT_MASK        0xFFFF0000      /* current byte/word count */
 248 #define CM_TDMA_ADR_MASK        0x0000FFFF      /* current address */
 249
 250         /* byte */
 251 #define CM_REG_MIXER0           0x20
 252 #define CM_REG_SBVR             0x20            /* write: sb16 version */
 253 #define CM_REG_DEV              0x20            /* read: hardware device version */
 254
 255 #define CM_REG_MIXER21          0x21
 256 #define CM_UNKNOWN_21_MASK      0x78            /* ? */
 257 #define CM_X_ADPCM              0x04            /* SB16 ADPCM enable */
 258 #define CM_PROINV               0x02            /* SBPro left/right channel switching */
 259 #define CM_X_SB16               0x01            /* SB16 compatible */
 260
 261 #define CM_REG_SB16_DATA        0x22
 262 #define CM_REG_SB16_ADDR        0x23
 263
 264 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
 265 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
 266 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
 267 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
 268
 269 #define CM_REG_MIXER1           0x24
 270 #define CM_FMMUTE               0x80    /* mute FM */
 271 #define CM_FMMUTE_SHIFT         7
 272 #define CM_WSMUTE               0x40    /* mute PCM */
 273 #define CM_WSMUTE_SHIFT         6
 274 #define CM_REAR2LIN             0x20    /* lin-in -> rear line out */
 275 #define CM_REAR2LIN_SHIFT       5
 276 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
 277 #define CM_REAR2FRONT_SHIFT     4
 278 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
 279 #define CM_WAVEINL_SHIFT        3
 280 #define CM_WAVEINR              0x04    /* digical wave rec. right */
 281 #define CM_WAVEINR_SHIFT        2
 282 #define CM_X3DEN                0x02    /* 3D surround enable */
 283 #define CM_X3DEN_SHIFT          1
 284 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
 285 #define CM_CDPLAY_SHIFT         0
 286
 287 #define CM_REG_MIXER2           0x25
 288 #define CM_RAUXREN              0x80    /* AUX right capture */
 289 #define CM_RAUXREN_SHIFT        7
 290 #define CM_RAUXLEN              0x40    /* AUX left capture */
 291 #define CM_RAUXLEN_SHIFT        6
 292 #define CM_VAUXRM               0x20    /* AUX right mute */
 293 #define CM_VAUXRM_SHIFT         5
 294 #define CM_VAUXLM               0x10    /* AUX left mute */
 295 #define CM_VAUXLM_SHIFT         4
 296 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
 297 #define CM_VADMIC_SHIFT         1
 298 #define CM_MICGAINZ             0x01    /* mic boost */
 299 #define CM_MICGAINZ_SHIFT       0
 300
 301 #define CM_REG_AUX_VOL          0x26
 302 #define CM_VAUXL_MASK           0xf0
 303 #define CM_VAUXR_MASK           0x0f
 304
 305 #define CM_REG_MISC             0x27
 306 #define CM_UNKNOWN_27_MASK      0xd8    /* ? */
 307 #define CM_XGPO1                0x20
 308 // #define CM_XGPBIO            0x04
 309 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
 310 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
 311 #define CM_SPDVALID             0x02    /* spdif input valid check */
 312 #define CM_DMAUTO               0x01    /* SB16 DMA auto detect */
 313
 314 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
 315 /*
 316  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
 317  * or identical with AC97 codec?
 318  */
 319 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
 320
 321 /*
 322  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
 323  */
 324 #define CM_REG_MPU_PCI          0x40
 325
 326 /*
 327  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
 328  */
 329 #define CM_REG_FM_PCI           0x50
 330
 331 /*
 332  * access from SB-mixer port
 333  */
 334 #define CM_REG_EXTENT_IND       0xf0
 335 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
 336 #define CM_VPHONE_SHIFT         5
 337 #define CM_VPHOM                0x10    /* Phone mute control */
 338 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
 339 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
 340 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
 341 #define CM_VADMIC3              0x01    /* Mic record boost */
 342
 343 /*
 344  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
 345  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
 346  * unit (readonly?).
 347  */
 348 #define CM_REG_PLL              0xf8
 349
 350 /*
 351  * extended registers
 352  */
 353 #define CM_REG_CH0_FRAME1       0x80    /* write: base address */
 354 #define CM_REG_CH0_FRAME2       0x84    /* read: current address */
 355 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
 356 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
 357
 358 #define CM_REG_EXT_MISC         0x90
 359 #define CM_ADC48K44K            0x10000000      /* ADC parameters group, 0: 44k, 1: 48k */
 360 #define CM_CHB3D8C              0x00200000      /* 7.1 channels support */
 361 #define CM_SPD32FMT             0x00100000      /* SPDIF/IN 32k sample rate */
 362 #define CM_ADC2SPDIF            0x00080000      /* ADC output to SPDIF/OUT */
 363 #define CM_SHAREADC             0x00040000      /* DAC in ADC as Center/LFE */
 364 #define CM_REALTCMP             0x00020000      /* monitor the CMPL/CMPR of ADC */
 365 #define CM_INVLRCK              0x00010000      /* invert ZVPORT's LRCK */
 366 #define CM_UNKNOWN_90_MASK      0x0000FFFF      /* ? */
 367
 368 /*
 369  * size of i/o region
 370  */
 371 #define CM_EXTENT_CODEC   0x100
 372 #define CM_EXTENT_MIDI    0x2
 373 #define CM_EXTENT_SYNTH   0x4
 374
 375
 376 /*
 377  * channels for playback / capture
 378  */
 379 #define CM_CH_PLAY      0
 380 #define CM_CH_CAPT      1
 381
 382 /*
 383  * flags to check device open/close
 384  */
 385 #define CM_OPEN_NONE    0
 386 #define CM_OPEN_CH_MASK 0x01
 387 #define CM_OPEN_DAC     0x10
 388 #define CM_OPEN_ADC     0x20
 389 #define CM_OPEN_SPDIF   0x40
 390 #define CM_OPEN_MCHAN   0x80
 391 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
 392 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
 393 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
 394 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
 395 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
 396 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
 397
 398
 399 #if CM_CH_PLAY == 1
 400 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
 401 #define CM_PLAYBACK_SPDF        CM_SPDF_1
 402 #define CM_CAPTURE_SPDF         CM_SPDF_0
 403 #else
 404 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
 405 #define CM_PLAYBACK_SPDF        CM_SPDF_0
 406 #define CM_CAPTURE_SPDF         CM_SPDF_1
 407 #endif
 408
 409
 410 /*
 411  * driver data
 412  */
 413
 414 struct cmipci_pcm {
 415         struct snd_pcm_substream *substream;
 416         u8 running;             /* dac/adc running? */
 417         u8 fmt;                 /* format bits */
 418         u8 is_dac;
 419         u8 needs_silencing;
 420         unsigned int dma_size;  /* in frames */
 421         unsigned int shift;
 422         unsigned int ch;        /* channel (0/1) */
 423         unsigned int offset;    /* physical address of the buffer */
 424 };
 425
 426 /* mixer elements toggled/resumed during ac3 playback */
 427 struct cmipci_mixer_auto_switches {
 428         const char *name;       /* switch to toggle */
 429         int toggle_on;          /* value to change when ac3 mode */
 430 };
 431 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
 432         {"PCM Playback Switch", 0},
 433         {"IEC958 Output Switch", 1},
 434         {"IEC958 Mix Analog", 0},
 435         // {"IEC958 Out To DAC", 1}, // no longer used
 436         {"IEC958 Loop", 0},
 437 };
 438 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
 439
 440 struct cmipci {
 441         struct snd_card *card;
 442
 443         struct pci_dev *pci;
 444         unsigned int device;    /* device ID */
 445         int irq;
 446
 447         unsigned long iobase;
 448         unsigned int ctrl;      /* FUNCTRL0 current value */
 449
 450         struct snd_pcm *pcm;            /* DAC/ADC PCM */
 451         struct snd_pcm *pcm2;   /* 2nd DAC */
 452         struct snd_pcm *pcm_spdif;      /* SPDIF */
 453
 454         int chip_version;
 455         int max_channels;
 456         unsigned int can_ac3_sw: 1;
 457         unsigned int can_ac3_hw: 1;
 458         unsigned int can_multi_ch: 1;
 459         unsigned int can_96k: 1;        /* samplerate above 48k */
 460         unsigned int do_soft_ac3: 1;
 461
 462         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
 463         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
 464         int spdif_counter;      /* for software AC3 */
 465
 466         unsigned int dig_status;
 467         unsigned int dig_pcm_status;
 468
 469         struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
 470
 471         int opened[2];  /* open mode */
 472         struct mutex open_mutex;
 473
 474         unsigned int mixer_insensitive: 1;
 475         struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
 476         int mixer_res_status[CM_SAVED_MIXERS];
 477
 478         struct cmipci_pcm channel[2];   /* ch0 - DAC, ch1 - ADC or 2nd DAC */
 479
 480         /* external MIDI */
 481         struct snd_rawmidi *rmidi;
 482
 483 #ifdef SUPPORT_JOYSTICK
 484         struct gameport *gameport;
 485 #endif
 486
 487         spinlock_t reg_lock;
 488
 489 #ifdef CONFIG_PM_SLEEP
 490         unsigned int saved_regs[0x20];
 491         unsigned char saved_mixers[0x20];
 492 #endif
 493 };
 494
 495
 496 /* read/write operations for dword register */
 497 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
 498 {
 499         outl(data, cm->iobase + cmd);
 500 }
 501
 502 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
 503 {
 504         return inl(cm->iobase + cmd);
 505 }
 506
 507 /* read/write operations for word register */
 508 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
 509 {
 510         outw(data, cm->iobase + cmd);
 511 }
 512
 513 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
 514 {
 515         return inw(cm->iobase + cmd);
 516 }
 517
 518 /* read/write operations for byte register */
 519 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
 520 {
 521         outb(data, cm->iobase + cmd);
 522 }
 523
 524 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
 525 {
 526         return inb(cm->iobase + cmd);
 527 }
 528
 529 /* bit operations for dword register */
 530 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 531 {
 532         unsigned int val, oval;
 533         val = oval = inl(cm->iobase + cmd);
 534         val |= flag;
 535         if (val == oval)
 536                 return 0;
 537         outl(val, cm->iobase + cmd);
 538         return 1;
 539 }
 540
 541 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 542 {
 543         unsigned int val, oval;
 544         val = oval = inl(cm->iobase + cmd);
 545         val &= ~flag;
 546         if (val == oval)
 547                 return 0;
 548         outl(val, cm->iobase + cmd);
 549         return 1;
 550 }
 551
 552 /* bit operations for byte register */
 553 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 554 {
 555         unsigned char val, oval;
 556         val = oval = inb(cm->iobase + cmd);
 557         val |= flag;
 558         if (val == oval)
 559                 return 0;
 560         outb(val, cm->iobase + cmd);
 561         return 1;
 562 }
 563
 564 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 565 {
 566         unsigned char val, oval;
 567         val = oval = inb(cm->iobase + cmd);
 568         val &= ~flag;
 569         if (val == oval)
 570                 return 0;
 571         outb(val, cm->iobase + cmd);
 572         return 1;
 573 }
 574
 575
 576 /*
 577  * PCM interface
 578  */
 579
 580 /*
 581  * calculate frequency
 582  */
 583
 584 static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
 585
 586 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
 587 {
 588         unsigned int i;
 589
 590         for (i = 0; i < ARRAY_SIZE(rates); i++) {
 591                 if (rates[i] == rate)
 592                         return i;
 593         }
 594         snd_BUG();
 595         return 0;
 596 }
 597
 598 #ifdef USE_VAR48KRATE
 599 /*
 600  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
 601  * does it this way .. maybe not.  Never get any information from C-Media about
 602  * that <werner@suse.de>.
 603  */
 604 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
 605 {
 606         unsigned int delta, tolerance;
 607         int xm, xn, xr;
 608
 609         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
 610                 rate <<= 1;
 611         *n = -1;
 612         if (*r > 0xff)
 613                 goto out;
 614         tolerance = rate*CM_TOLERANCE_RATE;
 615
 616         for (xn = (1+2); xn < (0x1f+2); xn++) {
 617                 for (xm = (1+2); xm < (0xff+2); xm++) {
 618                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
 619
 620                         if (xr < rate)
 621                                 delta = rate - xr;
 622                         else
 623                                 delta = xr - rate;
 624
 625                         /*
 626                          * If we found one, remember this,
 627                          * and try to find a closer one
 628                          */
 629                         if (delta < tolerance) {
 630                                 tolerance = delta;
 631                                 *m = xm - 2;
 632                                 *n = xn - 2;
 633                         }
 634                 }
 635         }
 636 out:
 637         return (*n > -1);
 638 }
 639
 640 /*
 641  * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
 642  * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
 643  * at the register CM_REG_FUNCTRL1 (0x04).
 644  * Problem: other ways are also possible (any information about that?)
 645  */
 646 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
 647 {
 648         unsigned int reg = CM_REG_PLL + slot;
 649         /*
 650          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
 651          * for DSFC/ASFC (000 up to 111).
 652          */
 653
 654         /* FIXME: Init (Do we've to set an other register first before programming?) */
 655
 656         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
 657         snd_cmipci_write_b(cm, reg, rate>>8);
 658         snd_cmipci_write_b(cm, reg, rate&0xff);
 659
 660         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
 661 }
 662 #endif /* USE_VAR48KRATE */
 663
 664 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
 665                                           struct snd_pcm_hw_params *hw_params)
 666 {
 667         struct cmipci *cm = snd_pcm_substream_chip(substream);
 668         if (params_channels(hw_params) > 2) {
 669                 mutex_lock(&cm->open_mutex);
 670                 if (cm->opened[CM_CH_PLAY]) {
 671                         mutex_unlock(&cm->open_mutex);
 672                         return -EBUSY;
 673                 }
 674                 /* reserve the channel A */
 675                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
 676                 mutex_unlock(&cm->open_mutex);
 677         }
 678         return 0;
 679 }
 680
 681 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
 682 {
 683         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
 684         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 685         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 686         udelay(10);
 687 }
 688
 689
 690 /*
 691  */
 692
 693 static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
 694 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
 695         .count = 3,
 696         .list = hw_channels,
 697         .mask = 0,
 698 };
 699 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
 700         .count = 4,
 701         .list = hw_channels,
 702         .mask = 0,
 703 };
 704 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
 705         .count = 5,
 706         .list = hw_channels,
 707         .mask = 0,
 708 };
 709
 710 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
 711 {
 712         if (channels > 2) {
 713                 if (!cm->can_multi_ch || !rec->ch)
 714                         return -EINVAL;
 715                 if (rec->fmt != 0x03) /* stereo 16bit only */
 716                         return -EINVAL;
 717         }
 718
 719         if (cm->can_multi_ch) {
 720                 spin_lock_irq(&cm->reg_lock);
 721                 if (channels > 2) {
 722                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 723                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 724                 } else {
 725                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 726                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 727                 }
 728                 if (channels == 8)
 729                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 730                 else
 731                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 732                 if (channels == 6) {
 733                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 734                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 735                 } else {
 736                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 737                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 738                 }
 739                 if (channels == 4)
 740                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 741                 else
 742                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 743                 spin_unlock_irq(&cm->reg_lock);
 744         }
 745         return 0;
 746 }
 747
 748
 749 /*
 750  * prepare playback/capture channel
 751  * channel to be used must have been set in rec->ch.
 752  */
 753 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
 754                                  struct snd_pcm_substream *substream)
 755 {
 756         unsigned int reg, freq, freq_ext, val;
 757         unsigned int period_size;
 758         struct snd_pcm_runtime *runtime = substream->runtime;
 759
 760         rec->fmt = 0;
 761         rec->shift = 0;
 762         if (snd_pcm_format_width(runtime->format) >= 16) {
 763                 rec->fmt |= 0x02;
 764                 if (snd_pcm_format_width(runtime->format) > 16)
 765                         rec->shift++; /* 24/32bit */
 766         }
 767         if (runtime->channels > 1)
 768                 rec->fmt |= 0x01;
 769         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
 770                 dev_dbg(cm->card->dev, "cannot set dac channels\n");
 771                 return -EINVAL;
 772         }
 773
 774         rec->offset = runtime->dma_addr;
 775         /* buffer and period sizes in frame */
 776         rec->dma_size = runtime->buffer_size << rec->shift;
 777         period_size = runtime->period_size << rec->shift;
 778         if (runtime->channels > 2) {
 779                 /* multi-channels */
 780                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
 781                 period_size = (period_size * runtime->channels) / 2;
 782         }
 783
 784         spin_lock_irq(&cm->reg_lock);
 785
 786         /* set buffer address */
 787         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 788         snd_cmipci_write(cm, reg, rec->offset);
 789         /* program sample counts */
 790         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 791         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
 792         snd_cmipci_write_w(cm, reg + 2, period_size - 1);
 793
 794         /* set adc/dac flag */
 795         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
 796         if (rec->is_dac)
 797                 cm->ctrl &= ~val;
 798         else
 799                 cm->ctrl |= val;
 800         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 801         /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
 802
 803         /* set sample rate */
 804         freq = 0;
 805         freq_ext = 0;
 806         if (runtime->rate > 48000)
 807                 switch (runtime->rate) {
 808                 case 88200:  freq_ext = CM_CH0_SRATE_88K; break;
 809                 case 96000:  freq_ext = CM_CH0_SRATE_96K; break;
 810                 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
 811                 default:     snd_BUG(); break;
 812                 }
 813         else
 814                 freq = snd_cmipci_rate_freq(runtime->rate);
 815         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
 816         if (rec->ch) {
 817                 val &= ~CM_DSFC_MASK;
 818                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
 819         } else {
 820                 val &= ~CM_ASFC_MASK;
 821                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
 822         }
 823         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
 824         dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
 825
 826         /* set format */
 827         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
 828         if (rec->ch) {
 829                 val &= ~CM_CH1FMT_MASK;
 830                 val |= rec->fmt << CM_CH1FMT_SHIFT;
 831         } else {
 832                 val &= ~CM_CH0FMT_MASK;
 833                 val |= rec->fmt << CM_CH0FMT_SHIFT;
 834         }
 835         if (cm->can_96k) {
 836                 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
 837                 val |= freq_ext << (rec->ch * 2);
 838         }
 839         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
 840         dev_dbg(cm->card->dev, "chformat = %08x\n", val);
 841
 842         if (!rec->is_dac && cm->chip_version) {
 843                 if (runtime->rate > 44100)
 844                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 845                 else
 846                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 847         }
 848
 849         rec->running = 0;
 850         spin_unlock_irq(&cm->reg_lock);
 851
 852         return 0;
 853 }
 854
 855 /*
 856  * PCM trigger/stop
 857  */
 858 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
 859                                   int cmd)
 860 {
 861         unsigned int inthld, chen, reset, pause;
 862         int result = 0;
 863
 864         inthld = CM_CH0_INT_EN << rec->ch;
 865         chen = CM_CHEN0 << rec->ch;
 866         reset = CM_RST_CH0 << rec->ch;
 867         pause = CM_PAUSE0 << rec->ch;
 868
 869         spin_lock(&cm->reg_lock);
 870         switch (cmd) {
 871         case SNDRV_PCM_TRIGGER_START:
 872                 rec->running = 1;
 873                 /* set interrupt */
 874                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
 875                 cm->ctrl |= chen;
 876                 /* enable channel */
 877                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 878                 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
 879                 break;
 880         case SNDRV_PCM_TRIGGER_STOP:
 881                 rec->running = 0;
 882                 /* disable interrupt */
 883                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
 884                 /* reset */
 885                 cm->ctrl &= ~chen;
 886                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 887                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 888                 rec->needs_silencing = rec->is_dac;
 889                 break;
 890         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 891         case SNDRV_PCM_TRIGGER_SUSPEND:
 892                 cm->ctrl |= pause;
 893                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 894                 break;
 895         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 896         case SNDRV_PCM_TRIGGER_RESUME:
 897                 cm->ctrl &= ~pause;
 898                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 899                 break;
 900         default:
 901                 result = -EINVAL;
 902                 break;
 903         }
 904         spin_unlock(&cm->reg_lock);
 905         return result;
 906 }
 907
 908 /*
 909  * return the current pointer
 910  */
 911 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
 912                                                 struct snd_pcm_substream *substream)
 913 {
 914         size_t ptr;
 915         unsigned int reg, rem, tries;
 916
 917         if (!rec->running)
 918                 return 0;
 919 #if 1 // this seems better..
 920         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 921         for (tries = 0; tries < 3; tries++) {
 922                 rem = snd_cmipci_read_w(cm, reg);
 923                 if (rem < rec->dma_size)
 924                         goto ok;
 925         }
 926         dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
 927         return SNDRV_PCM_POS_XRUN;
 928 ok:
 929         ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
 930 #else
 931         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 932         ptr = snd_cmipci_read(cm, reg) - rec->offset;
 933         ptr = bytes_to_frames(substream->runtime, ptr);
 934 #endif
 935         if (substream->runtime->channels > 2)
 936                 ptr = (ptr * 2) / substream->runtime->channels;
 937         return ptr;
 938 }
 939
 940 /*
 941  * playback
 942  */
 943
 944 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
 945                                        int cmd)
 946 {
 947         struct cmipci *cm = snd_pcm_substream_chip(substream);
 948         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
 949 }
 950
 951 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
 952 {
 953         struct cmipci *cm = snd_pcm_substream_chip(substream);
 954         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
 955 }
 956
 957
 958
 959 /*
 960  * capture
 961  */
 962
 963 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
 964                                      int cmd)
 965 {
 966         struct cmipci *cm = snd_pcm_substream_chip(substream);
 967         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
 968 }
 969
 970 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
 971 {
 972         struct cmipci *cm = snd_pcm_substream_chip(substream);
 973         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
 974 }
 975
 976
 977 /*
 978  * hw preparation for spdif
 979  */
 980
 981 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
 982                                          struct snd_ctl_elem_info *uinfo)
 983 {
 984         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 985         uinfo->count = 1;
 986         return 0;
 987 }
 988
 989 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
 990                                         struct snd_ctl_elem_value *ucontrol)
 991 {
 992         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
 993         int i;
 994
 995         spin_lock_irq(&chip->reg_lock);
 996         for (i = 0; i < 4; i++)
 997                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
 998         spin_unlock_irq(&chip->reg_lock);
 999         return 0;
1000 }
1001
1002 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1003                                          struct snd_ctl_elem_value *ucontrol)
1004 {
1005         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1006         int i, change;
1007         unsigned int val;
1008
1009         val = 0;
1010         spin_lock_irq(&chip->reg_lock);
1011         for (i = 0; i < 4; i++)
1012                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1013         change = val != chip->dig_status;
1014         chip->dig_status = val;
1015         spin_unlock_irq(&chip->reg_lock);
1016         return change;
1017 }
1018
1019 static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1020 {
1021         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1022         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1023         .info =         snd_cmipci_spdif_default_info,
1024         .get =          snd_cmipci_spdif_default_get,
1025         .put =          snd_cmipci_spdif_default_put
1026 };
1027
1028 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1029                                       struct snd_ctl_elem_info *uinfo)
1030 {
1031         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1032         uinfo->count = 1;
1033         return 0;
1034 }
1035
1036 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1037                                      struct snd_ctl_elem_value *ucontrol)
1038 {
1039         ucontrol->value.iec958.status[0] = 0xff;
1040         ucontrol->value.iec958.status[1] = 0xff;
1041         ucontrol->value.iec958.status[2] = 0xff;
1042         ucontrol->value.iec958.status[3] = 0xff;
1043         return 0;
1044 }
1045
1046 static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1047 {
1048         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1049         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1050         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1051         .info =         snd_cmipci_spdif_mask_info,
1052         .get =          snd_cmipci_spdif_mask_get,
1053 };
1054
1055 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1056                                         struct snd_ctl_elem_info *uinfo)
1057 {
1058         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1059         uinfo->count = 1;
1060         return 0;
1061 }
1062
1063 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1064                                        struct snd_ctl_elem_value *ucontrol)
1065 {
1066         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1067         int i;
1068
1069         spin_lock_irq(&chip->reg_lock);
1070         for (i = 0; i < 4; i++)
1071                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1072         spin_unlock_irq(&chip->reg_lock);
1073         return 0;
1074 }
1075
1076 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1077                                        struct snd_ctl_elem_value *ucontrol)
1078 {
1079         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1080         int i, change;
1081         unsigned int val;
1082
1083         val = 0;
1084         spin_lock_irq(&chip->reg_lock);
1085         for (i = 0; i < 4; i++)
1086                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1087         change = val != chip->dig_pcm_status;
1088         chip->dig_pcm_status = val;
1089         spin_unlock_irq(&chip->reg_lock);
1090         return change;
1091 }
1092
1093 static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1094 {
1095         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1096         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1097         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1098         .info =         snd_cmipci_spdif_stream_info,
1099         .get =          snd_cmipci_spdif_stream_get,
1100         .put =          snd_cmipci_spdif_stream_put
1101 };
1102
1103 /*
1104  */
1105
1106 /* save mixer setting and mute for AC3 playback */
1107 static int save_mixer_state(struct cmipci *cm)
1108 {
1109         if (! cm->mixer_insensitive) {
1110                 struct snd_ctl_elem_value *val;
1111                 unsigned int i;
1112
1113                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1114                 if (!val)
1115                         return -ENOMEM;
1116                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1117                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1118                         if (ctl) {
1119                                 int event;
1120                                 memset(val, 0, sizeof(*val));
1121                                 ctl->get(ctl, val);
1122                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1123                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1124                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1125                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1126                                         ctl->put(ctl, val); /* toggle */
1127                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1128                                 }
1129                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1130                                 snd_ctl_notify(cm->card, event, &ctl->id);
1131                         }
1132                 }
1133                 kfree(val);
1134                 cm->mixer_insensitive = 1;
1135         }
1136         return 0;
1137 }
1138
1139
1140 /* restore the previously saved mixer status */
1141 static void restore_mixer_state(struct cmipci *cm)
1142 {
1143         if (cm->mixer_insensitive) {
1144                 struct snd_ctl_elem_value *val;
1145                 unsigned int i;
1146
1147                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1148                 if (!val)
1149                         return;
1150                 cm->mixer_insensitive = 0; /* at first clear this;
1151                                               otherwise the changes will be ignored */
1152                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1153                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1154                         if (ctl) {
1155                                 int event;
1156
1157                                 memset(val, 0, sizeof(*val));
1158                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1159                                 ctl->get(ctl, val);
1160                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1161                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1162                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1163                                         ctl->put(ctl, val);
1164                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1165                                 }
1166                                 snd_ctl_notify(cm->card, event, &ctl->id);
1167                         }
1168                 }
1169                 kfree(val);
1170         }
1171 }
1172
1173 /* spinlock held! */
1174 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1175 {
1176         if (do_ac3) {
1177                 /* AC3EN for 037 */
1178                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1179                 /* AC3EN for 039 */
1180                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1181
1182                 if (cm->can_ac3_hw) {
1183                         /* SPD24SEL for 037, 0x02 */
1184                         /* SPD24SEL for 039, 0x20, but cannot be set */
1185                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1186                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1187                 } else { /* can_ac3_sw */
1188                         /* SPD32SEL for 037 & 039, 0x20 */
1189                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1190                         /* set 176K sample rate to fix 033 HW bug */
1191                         if (cm->chip_version == 33) {
1192                                 if (rate >= 48000) {
1193                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1194                                 } else {
1195                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1196                                 }
1197                         }
1198                 }
1199
1200         } else {
1201                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1202                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1203
1204                 if (cm->can_ac3_hw) {
1205                         /* chip model >= 37 */
1206                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1207                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1208                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1209                         } else {
1210                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1211                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1212                         }
1213                 } else {
1214                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1215                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1216                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1217                 }
1218         }
1219 }
1220
1221 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1222 {
1223         int rate, err;
1224
1225         rate = subs->runtime->rate;
1226
1227         if (up && do_ac3) {
1228                 err = save_mixer_state(cm);
1229                 if (err < 0)
1230                         return err;
1231         }
1232
1233         spin_lock_irq(&cm->reg_lock);
1234         cm->spdif_playback_avail = up;
1235         if (up) {
1236                 /* they are controlled via "IEC958 Output Switch" */
1237                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1238                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1239                 if (cm->spdif_playback_enabled)
1240                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1241                 setup_ac3(cm, subs, do_ac3, rate);
1242
1243                 if (rate == 48000 || rate == 96000)
1244                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1245                 else
1246                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1247                 if (rate > 48000)
1248                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1249                 else
1250                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1251         } else {
1252                 /* they are controlled via "IEC958 Output Switch" */
1253                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1254                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1255                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1256                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1257                 setup_ac3(cm, subs, 0, 0);
1258         }
1259         spin_unlock_irq(&cm->reg_lock);
1260         return 0;
1261 }
1262
1263
1264 /*
1265  * preparation
1266  */
1267
1268 /* playback - enable spdif only on the certain condition */
1269 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1270 {
1271         struct cmipci *cm = snd_pcm_substream_chip(substream);
1272         int rate = substream->runtime->rate;
1273         int err, do_spdif, do_ac3 = 0;
1274
1275         do_spdif = (rate >= 44100 && rate <= 96000 &&
1276                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1277                     substream->runtime->channels == 2);
1278         if (do_spdif && cm->can_ac3_hw)
1279                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1280         err = setup_spdif_playback(cm, substream, do_spdif, do_ac3);
1281         if (err < 0)
1282                 return err;
1283         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1284 }
1285
1286 /* playback  (via device #2) - enable spdif always */
1287 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1288 {
1289         struct cmipci *cm = snd_pcm_substream_chip(substream);
1290         int err, do_ac3;
1291
1292         if (cm->can_ac3_hw)
1293                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1294         else
1295                 do_ac3 = 1; /* doesn't matter */
1296         err = setup_spdif_playback(cm, substream, 1, do_ac3);
1297         if (err < 0)
1298                 return err;
1299         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1300 }
1301
1302 /*
1303  * Apparently, the samples last played on channel A stay in some buffer, even
1304  * after the channel is reset, and get added to the data for the rear DACs when
1305  * playing a multichannel stream on channel B.  This is likely to generate
1306  * wraparounds and thus distortions.
1307  * To avoid this, we play at least one zero sample after the actual stream has
1308  * stopped.
1309  */
1310 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1311 {
1312         struct snd_pcm_runtime *runtime = rec->substream->runtime;
1313         unsigned int reg, val;
1314
1315         if (rec->needs_silencing && runtime && runtime->dma_area) {
1316                 /* set up a small silence buffer */
1317                 memset(runtime->dma_area, 0, PAGE_SIZE);
1318                 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1319                 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1320                 snd_cmipci_write(cm, reg, val);
1321
1322                 /* configure for 16 bits, 2 channels, 8 kHz */
1323                 if (runtime->channels > 2)
1324                         set_dac_channels(cm, rec, 2);
1325                 spin_lock_irq(&cm->reg_lock);
1326                 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1327                 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1328                 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1329                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1330                 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1331                 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1332                 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1333                 if (cm->can_96k)
1334                         val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1335                 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1336
1337                 /* start stream (we don't need interrupts) */
1338                 cm->ctrl |= CM_CHEN0 << rec->ch;
1339                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1340                 spin_unlock_irq(&cm->reg_lock);
1341
1342                 msleep(1);
1343
1344                 /* stop and reset stream */
1345                 spin_lock_irq(&cm->reg_lock);
1346                 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1347                 val = CM_RST_CH0 << rec->ch;
1348                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1349                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1350                 spin_unlock_irq(&cm->reg_lock);
1351
1352                 rec->needs_silencing = 0;
1353         }
1354 }
1355
1356 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1357 {
1358         struct cmipci *cm = snd_pcm_substream_chip(substream);
1359         setup_spdif_playback(cm, substream, 0, 0);
1360         restore_mixer_state(cm);
1361         snd_cmipci_silence_hack(cm, &cm->channel[0]);
1362         return 0;
1363 }
1364
1365 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1366 {
1367         struct cmipci *cm = snd_pcm_substream_chip(substream);
1368         snd_cmipci_silence_hack(cm, &cm->channel[1]);
1369         return 0;
1370 }
1371
1372 /* capture */
1373 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1374 {
1375         struct cmipci *cm = snd_pcm_substream_chip(substream);
1376         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1377 }
1378
1379 /* capture with spdif (via device #2) */
1380 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1381 {
1382         struct cmipci *cm = snd_pcm_substream_chip(substream);
1383
1384         spin_lock_irq(&cm->reg_lock);
1385         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1386         if (cm->can_96k) {
1387                 if (substream->runtime->rate > 48000)
1388                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1389                 else
1390                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1391         }
1392         if (snd_pcm_format_width(substream->runtime->format) > 16)
1393                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1394         else
1395                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1396
1397         spin_unlock_irq(&cm->reg_lock);
1398
1399         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1400 }
1401
1402 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1403 {
1404         struct cmipci *cm = snd_pcm_substream_chip(subs);
1405
1406         spin_lock_irq(&cm->reg_lock);
1407         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1408         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1409         spin_unlock_irq(&cm->reg_lock);
1410
1411         return 0;
1412 }
1413
1414
1415 /*
1416  * interrupt handler
1417  */
1418 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1419 {
1420         struct cmipci *cm = dev_id;
1421         unsigned int status, mask = 0;
1422
1423         /* fastpath out, to ease interrupt sharing */
1424         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1425         if (!(status & CM_INTR))
1426                 return IRQ_NONE;
1427
1428         /* acknowledge interrupt */
1429         spin_lock(&cm->reg_lock);
1430         if (status & CM_CHINT0)
1431                 mask |= CM_CH0_INT_EN;
1432         if (status & CM_CHINT1)
1433                 mask |= CM_CH1_INT_EN;
1434         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1435         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1436         spin_unlock(&cm->reg_lock);
1437
1438         if (cm->rmidi && (status & CM_UARTINT))
1439                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1440
1441         if (cm->pcm) {
1442                 if ((status & CM_CHINT0) && cm->channel[0].running)
1443                         snd_pcm_period_elapsed(cm->channel[0].substream);
1444                 if ((status & CM_CHINT1) && cm->channel[1].running)
1445                         snd_pcm_period_elapsed(cm->channel[1].substream);
1446         }
1447         return IRQ_HANDLED;
1448 }
1449
1450 /*
1451  * h/w infos
1452  */
1453
1454 /* playback on channel A */
1455 static const struct snd_pcm_hardware snd_cmipci_playback =
1456 {
1457         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1458                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1459                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1460         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1461         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1462         .rate_min =             5512,
1463         .rate_max =             48000,
1464         .channels_min =         1,
1465         .channels_max =         2,
1466         .buffer_bytes_max =     (128*1024),
1467         .period_bytes_min =     64,
1468         .period_bytes_max =     (128*1024),
1469         .periods_min =          2,
1470         .periods_max =          1024,
1471         .fifo_size =            0,
1472 };
1473
1474 /* capture on channel B */
1475 static const struct snd_pcm_hardware snd_cmipci_capture =
1476 {
1477         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1478                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1479                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1480         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1481         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1482         .rate_min =             5512,
1483         .rate_max =             48000,
1484         .channels_min =         1,
1485         .channels_max =         2,
1486         .buffer_bytes_max =     (128*1024),
1487         .period_bytes_min =     64,
1488         .period_bytes_max =     (128*1024),
1489         .periods_min =          2,
1490         .periods_max =          1024,
1491         .fifo_size =            0,
1492 };
1493
1494 /* playback on channel B - stereo 16bit only? */
1495 static const struct snd_pcm_hardware snd_cmipci_playback2 =
1496 {
1497         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1498                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1499                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1500         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1501         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1502         .rate_min =             5512,
1503         .rate_max =             48000,
1504         .channels_min =         2,
1505         .channels_max =         2,
1506         .buffer_bytes_max =     (128*1024),
1507         .period_bytes_min =     64,
1508         .period_bytes_max =     (128*1024),
1509         .periods_min =          2,
1510         .periods_max =          1024,
1511         .fifo_size =            0,
1512 };
1513
1514 /* spdif playback on channel A */
1515 static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1516 {
1517         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1518                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1519                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1520         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1521         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1522         .rate_min =             44100,
1523         .rate_max =             48000,
1524         .channels_min =         2,
1525         .channels_max =         2,
1526         .buffer_bytes_max =     (128*1024),
1527         .period_bytes_min =     64,
1528         .period_bytes_max =     (128*1024),
1529         .periods_min =          2,
1530         .periods_max =          1024,
1531         .fifo_size =            0,
1532 };
1533
1534 /* spdif playback on channel A (32bit, IEC958 subframes) */
1535 static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1536 {
1537         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1538                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1539                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1540         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1541         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1542         .rate_min =             44100,
1543         .rate_max =             48000,
1544         .channels_min =         2,
1545         .channels_max =         2,
1546         .buffer_bytes_max =     (128*1024),
1547         .period_bytes_min =     64,
1548         .period_bytes_max =     (128*1024),
1549         .periods_min =          2,
1550         .periods_max =          1024,
1551         .fifo_size =            0,
1552 };
1553
1554 /* spdif capture on channel B */
1555 static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1556 {
1557         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1558                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1559                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1560         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
1561                                 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1562         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1563         .rate_min =             44100,
1564         .rate_max =             48000,
1565         .channels_min =         2,
1566         .channels_max =         2,
1567         .buffer_bytes_max =     (128*1024),
1568         .period_bytes_min =     64,
1569         .period_bytes_max =     (128*1024),
1570         .periods_min =          2,
1571         .periods_max =          1024,
1572         .fifo_size =            0,
1573 };
1574
1575 static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1576                         32000, 44100, 48000, 88200, 96000, 128000 };
1577 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1578                 .count = ARRAY_SIZE(rate_constraints),
1579                 .list = rate_constraints,
1580                 .mask = 0,
1581 };
1582
1583 /*
1584  * check device open/close
1585  */
1586 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1587 {
1588         int ch = mode & CM_OPEN_CH_MASK;
1589
1590         /* FIXME: a file should wait until the device becomes free
1591          * when it's opened on blocking mode.  however, since the current
1592          * pcm framework doesn't pass file pointer before actually opened,
1593          * we can't know whether blocking mode or not in open callback..
1594          */
1595         mutex_lock(&cm->open_mutex);
1596         if (cm->opened[ch]) {
1597                 mutex_unlock(&cm->open_mutex);
1598                 return -EBUSY;
1599         }
1600         cm->opened[ch] = mode;
1601         cm->channel[ch].substream = subs;
1602         if (! (mode & CM_OPEN_DAC)) {
1603                 /* disable dual DAC mode */
1604                 cm->channel[ch].is_dac = 0;
1605                 spin_lock_irq(&cm->reg_lock);
1606                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1607                 spin_unlock_irq(&cm->reg_lock);
1608         }
1609         mutex_unlock(&cm->open_mutex);
1610         return 0;
1611 }
1612
1613 static void close_device_check(struct cmipci *cm, int mode)
1614 {
1615         int ch = mode & CM_OPEN_CH_MASK;
1616
1617         mutex_lock(&cm->open_mutex);
1618         if (cm->opened[ch] == mode) {
1619                 if (cm->channel[ch].substream) {
1620                         snd_cmipci_ch_reset(cm, ch);
1621                         cm->channel[ch].running = 0;
1622                         cm->channel[ch].substream = NULL;
1623                 }
1624                 cm->opened[ch] = 0;
1625                 if (! cm->channel[ch].is_dac) {
1626                         /* enable dual DAC mode again */
1627                         cm->channel[ch].is_dac = 1;
1628                         spin_lock_irq(&cm->reg_lock);
1629                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1630                         spin_unlock_irq(&cm->reg_lock);
1631                 }
1632         }
1633         mutex_unlock(&cm->open_mutex);
1634 }
1635
1636 /*
1637  */
1638
1639 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1640 {
1641         struct cmipci *cm = snd_pcm_substream_chip(substream);
1642         struct snd_pcm_runtime *runtime = substream->runtime;
1643         int err;
1644
1645         err = open_device_check(cm, CM_OPEN_PLAYBACK, substream);
1646         if (err < 0)
1647                 return err;
1648         runtime->hw = snd_cmipci_playback;
1649         if (cm->chip_version == 68) {
1650                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1651                                      SNDRV_PCM_RATE_96000;
1652                 runtime->hw.rate_max = 96000;
1653         } else if (cm->chip_version == 55) {
1654                 err = snd_pcm_hw_constraint_list(runtime, 0,
1655                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1656                 if (err < 0)
1657                         return err;
1658                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1659                 runtime->hw.rate_max = 128000;
1660         }
1661         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1662         cm->dig_pcm_status = cm->dig_status;
1663         return 0;
1664 }
1665
1666 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1667 {
1668         struct cmipci *cm = snd_pcm_substream_chip(substream);
1669         struct snd_pcm_runtime *runtime = substream->runtime;
1670         int err;
1671
1672         err = open_device_check(cm, CM_OPEN_CAPTURE, substream);
1673         if (err < 0)
1674                 return err;
1675         runtime->hw = snd_cmipci_capture;
1676         if (cm->chip_version == 68) {   // 8768 only supports 44k/48k recording
1677                 runtime->hw.rate_min = 41000;
1678                 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1679         } else if (cm->chip_version == 55) {
1680                 err = snd_pcm_hw_constraint_list(runtime, 0,
1681                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1682                 if (err < 0)
1683                         return err;
1684                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1685                 runtime->hw.rate_max = 128000;
1686         }
1687         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1688         return 0;
1689 }
1690
1691 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1692 {
1693         struct cmipci *cm = snd_pcm_substream_chip(substream);
1694         struct snd_pcm_runtime *runtime = substream->runtime;
1695         int err;
1696
1697         /* use channel B */
1698         err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream);
1699         if (err < 0)
1700                 return err;
1701         runtime->hw = snd_cmipci_playback2;
1702         mutex_lock(&cm->open_mutex);
1703         if (! cm->opened[CM_CH_PLAY]) {
1704                 if (cm->can_multi_ch) {
1705                         runtime->hw.channels_max = cm->max_channels;
1706                         if (cm->max_channels == 4)
1707                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1708                         else if (cm->max_channels == 6)
1709                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1710                         else if (cm->max_channels == 8)
1711                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1712                 }
1713         }
1714         mutex_unlock(&cm->open_mutex);
1715         if (cm->chip_version == 68) {
1716                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1717                                      SNDRV_PCM_RATE_96000;
1718                 runtime->hw.rate_max = 96000;
1719         } else if (cm->chip_version == 55) {
1720                 err = snd_pcm_hw_constraint_list(runtime, 0,
1721                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1722                 if (err < 0)
1723                         return err;
1724                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1725                 runtime->hw.rate_max = 128000;
1726         }
1727         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1728         return 0;
1729 }
1730
1731 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1732 {
1733         struct cmipci *cm = snd_pcm_substream_chip(substream);
1734         struct snd_pcm_runtime *runtime = substream->runtime;
1735         int err;
1736
1737         /* use channel A */
1738         err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream);
1739         if (err < 0)
1740                 return err;
1741         if (cm->can_ac3_hw) {
1742                 runtime->hw = snd_cmipci_playback_spdif;
1743                 if (cm->chip_version >= 37) {
1744                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1745                         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1746                 }
1747                 if (cm->can_96k) {
1748                         runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1749                                              SNDRV_PCM_RATE_96000;
1750                         runtime->hw.rate_max = 96000;
1751                 }
1752         } else {
1753                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1754         }
1755         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1756         cm->dig_pcm_status = cm->dig_status;
1757         return 0;
1758 }
1759
1760 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1761 {
1762         struct cmipci *cm = snd_pcm_substream_chip(substream);
1763         struct snd_pcm_runtime *runtime = substream->runtime;
1764         int err;
1765
1766         /* use channel B */
1767         err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream);
1768         if (err < 0)
1769                 return err;
1770         runtime->hw = snd_cmipci_capture_spdif;
1771         if (cm->can_96k && !(cm->chip_version == 68)) {
1772                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1773                                      SNDRV_PCM_RATE_96000;
1774                 runtime->hw.rate_max = 96000;
1775         }
1776         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1777         return 0;
1778 }
1779
1780
1781 /*
1782  */
1783
1784 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1785 {
1786         struct cmipci *cm = snd_pcm_substream_chip(substream);
1787         close_device_check(cm, CM_OPEN_PLAYBACK);
1788         return 0;
1789 }
1790
1791 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1792 {
1793         struct cmipci *cm = snd_pcm_substream_chip(substream);
1794         close_device_check(cm, CM_OPEN_CAPTURE);
1795         return 0;
1796 }
1797
1798 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1799 {
1800         struct cmipci *cm = snd_pcm_substream_chip(substream);
1801         close_device_check(cm, CM_OPEN_PLAYBACK2);
1802         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1803         return 0;
1804 }
1805
1806 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1807 {
1808         struct cmipci *cm = snd_pcm_substream_chip(substream);
1809         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1810         return 0;
1811 }
1812
1813 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1814 {
1815         struct cmipci *cm = snd_pcm_substream_chip(substream);
1816         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1817         return 0;
1818 }
1819
1820
1821 /*
1822  */
1823
1824 static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1825         .open =         snd_cmipci_playback_open,
1826         .close =        snd_cmipci_playback_close,
1827         .hw_free =      snd_cmipci_playback_hw_free,
1828         .prepare =      snd_cmipci_playback_prepare,
1829         .trigger =      snd_cmipci_playback_trigger,
1830         .pointer =      snd_cmipci_playback_pointer,
1831 };
1832
1833 static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1834         .open =         snd_cmipci_capture_open,
1835         .close =        snd_cmipci_capture_close,
1836         .prepare =      snd_cmipci_capture_prepare,
1837         .trigger =      snd_cmipci_capture_trigger,
1838         .pointer =      snd_cmipci_capture_pointer,
1839 };
1840
1841 static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1842         .open =         snd_cmipci_playback2_open,
1843         .close =        snd_cmipci_playback2_close,
1844         .hw_params =    snd_cmipci_playback2_hw_params,
1845         .hw_free =      snd_cmipci_playback2_hw_free,
1846         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1847         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1848         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1849 };
1850
1851 static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1852         .open =         snd_cmipci_playback_spdif_open,
1853         .close =        snd_cmipci_playback_spdif_close,
1854         .hw_free =      snd_cmipci_playback_hw_free,
1855         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1856         .trigger =      snd_cmipci_playback_trigger,
1857         .pointer =      snd_cmipci_playback_pointer,
1858 };
1859
1860 static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1861         .open =         snd_cmipci_capture_spdif_open,
1862         .close =        snd_cmipci_capture_spdif_close,
1863         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1864         .prepare =      snd_cmipci_capture_spdif_prepare,
1865         .trigger =      snd_cmipci_capture_trigger,
1866         .pointer =      snd_cmipci_capture_pointer,
1867 };
1868
1869
1870 /*
1871  */
1872
1873 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1874 {
1875         struct snd_pcm *pcm;
1876         int err;
1877
1878         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1879         if (err < 0)
1880                 return err;
1881
1882         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1883         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1884
1885         pcm->private_data = cm;
1886         pcm->info_flags = 0;
1887         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1888         cm->pcm = pcm;
1889
1890         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1891                                        &cm->pci->dev, 64*1024, 128*1024);
1892
1893         return 0;
1894 }
1895
1896 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1897 {
1898         struct snd_pcm *pcm;
1899         int err;
1900
1901         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1902         if (err < 0)
1903                 return err;
1904
1905         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1906
1907         pcm->private_data = cm;
1908         pcm->info_flags = 0;
1909         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1910         cm->pcm2 = pcm;
1911
1912         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1913                                        &cm->pci->dev, 64*1024, 128*1024);
1914
1915         return 0;
1916 }
1917
1918 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1919 {
1920         struct snd_pcm *pcm;
1921         int err;
1922
1923         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1924         if (err < 0)
1925                 return err;
1926
1927         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1928         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1929
1930         pcm->private_data = cm;
1931         pcm->info_flags = 0;
1932         strcpy(pcm->name, "C-Media PCI IEC958");
1933         cm->pcm_spdif = pcm;
1934
1935         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1936                                        &cm->pci->dev, 64*1024, 128*1024);
1937
1938         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1939                                      snd_pcm_alt_chmaps, cm->max_channels, 0,
1940                                      NULL);
1941         if (err < 0)
1942                 return err;
1943
1944         return 0;
1945 }
1946
1947 /*
1948  * mixer interface:
1949  * - CM8338/8738 has a compatible mixer interface with SB16, but
1950  *   lack of some elements like tone control, i/o gain and AGC.
1951  * - Access to native registers:
1952  *   - A 3D switch
1953  *   - Output mute switches
1954  */
1955
1956 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1957 {
1958         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1959         outb(data, s->iobase + CM_REG_SB16_DATA);
1960 }
1961
1962 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1963 {
1964         unsigned char v;
1965
1966         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1967         v = inb(s->iobase + CM_REG_SB16_DATA);
1968         return v;
1969 }
1970
1971 /*
1972  * general mixer element
1973  */
1974 struct cmipci_sb_reg {
1975         unsigned int left_reg, right_reg;
1976         unsigned int left_shift, right_shift;
1977         unsigned int mask;
1978         unsigned int invert: 1;
1979         unsigned int stereo: 1;
1980 };
1981
1982 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1983  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1984
1985 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1986 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1987   .info = snd_cmipci_info_volume, \
1988   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1989   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1990 }
1991
1992 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1993 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1994 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1995 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1996
1997 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1998 {
1999         r->left_reg = val & 0xff;
2000         r->right_reg = (val >> 8) & 0xff;
2001         r->left_shift = (val >> 16) & 0x07;
2002         r->right_shift = (val >> 19) & 0x07;
2003         r->invert = (val >> 22) & 1;
2004         r->stereo = (val >> 23) & 1;
2005         r->mask = (val >> 24) & 0xff;
2006 }
2007
2008 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2009                                   struct snd_ctl_elem_info *uinfo)
2010 {
2011         struct cmipci_sb_reg reg;
2012
2013         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2014         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2015         uinfo->count = reg.stereo + 1;
2016         uinfo->value.integer.min = 0;
2017         uinfo->value.integer.max = reg.mask;
2018         return 0;
2019 }
2020
2021 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2022                                  struct snd_ctl_elem_value *ucontrol)
2023 {
2024         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2025         struct cmipci_sb_reg reg;
2026         int val;
2027
2028         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2029         spin_lock_irq(&cm->reg_lock);
2030         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2031         if (reg.invert)
2032                 val = reg.mask - val;
2033         ucontrol->value.integer.value[0] = val;
2034         if (reg.stereo) {
2035                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2036                 if (reg.invert)
2037                         val = reg.mask - val;
2038                 ucontrol->value.integer.value[1] = val;
2039         }
2040         spin_unlock_irq(&cm->reg_lock);
2041         return 0;
2042 }
2043
2044 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2045                                  struct snd_ctl_elem_value *ucontrol)
2046 {
2047         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2048         struct cmipci_sb_reg reg;
2049         int change;
2050         int left, right, oleft, oright;
2051
2052         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2053         left = ucontrol->value.integer.value[0] & reg.mask;
2054         if (reg.invert)
2055                 left = reg.mask - left;
2056         left <<= reg.left_shift;
2057         if (reg.stereo) {
2058                 right = ucontrol->value.integer.value[1] & reg.mask;
2059                 if (reg.invert)
2060                         right = reg.mask - right;
2061                 right <<= reg.right_shift;
2062         } else
2063                 right = 0;
2064         spin_lock_irq(&cm->reg_lock);
2065         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2066         left |= oleft & ~(reg.mask << reg.left_shift);
2067         change = left != oleft;
2068         if (reg.stereo) {
2069                 if (reg.left_reg != reg.right_reg) {
2070                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
2071                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2072                 } else
2073                         oright = left;
2074                 right |= oright & ~(reg.mask << reg.right_shift);
2075                 change |= right != oright;
2076                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2077         } else
2078                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2079         spin_unlock_irq(&cm->reg_lock);
2080         return change;
2081 }
2082
2083 /*
2084  * input route (left,right) -> (left,right)
2085  */
2086 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2087 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2088   .info = snd_cmipci_info_input_sw, \
2089   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2090   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2091 }
2092
2093 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2094                                     struct snd_ctl_elem_info *uinfo)
2095 {
2096         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2097         uinfo->count = 4;
2098         uinfo->value.integer.min = 0;
2099         uinfo->value.integer.max = 1;
2100         return 0;
2101 }
2102
2103 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2104                                    struct snd_ctl_elem_value *ucontrol)
2105 {
2106         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2107         struct cmipci_sb_reg reg;
2108         int val1, val2;
2109
2110         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2111         spin_lock_irq(&cm->reg_lock);
2112         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2113         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2114         spin_unlock_irq(&cm->reg_lock);
2115         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2116         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2117         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2118         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2119         return 0;
2120 }
2121
2122 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2123                                    struct snd_ctl_elem_value *ucontrol)
2124 {
2125         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2126         struct cmipci_sb_reg reg;
2127         int change;
2128         int val1, val2, oval1, oval2;
2129
2130         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2131         spin_lock_irq(&cm->reg_lock);
2132         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2133         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2134         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2135         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2136         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2137         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2138         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2139         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2140         change = val1 != oval1 || val2 != oval2;
2141         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2142         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2143         spin_unlock_irq(&cm->reg_lock);
2144         return change;
2145 }
2146
2147 /*
2148  * native mixer switches/volumes
2149  */
2150
2151 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2152 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2153   .info = snd_cmipci_info_native_mixer, \
2154   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2155   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2156 }
2157
2158 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2159 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2160   .info = snd_cmipci_info_native_mixer, \
2161   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2162   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2163 }
2164
2165 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2166 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2167   .info = snd_cmipci_info_native_mixer, \
2168   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2169   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2170 }
2171
2172 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2173 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2174   .info = snd_cmipci_info_native_mixer, \
2175   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2176   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2177 }
2178
2179 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2180                                         struct snd_ctl_elem_info *uinfo)
2181 {
2182         struct cmipci_sb_reg reg;
2183
2184         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2185         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2186         uinfo->count = reg.stereo + 1;
2187         uinfo->value.integer.min = 0;
2188         uinfo->value.integer.max = reg.mask;
2189         return 0;
2190
2191 }
2192
2193 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2194                                        struct snd_ctl_elem_value *ucontrol)
2195 {
2196         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2197         struct cmipci_sb_reg reg;
2198         unsigned char oreg, val;
2199
2200         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2201         spin_lock_irq(&cm->reg_lock);
2202         oreg = inb(cm->iobase + reg.left_reg);
2203         val = (oreg >> reg.left_shift) & reg.mask;
2204         if (reg.invert)
2205                 val = reg.mask - val;
2206         ucontrol->value.integer.value[0] = val;
2207         if (reg.stereo) {
2208                 val = (oreg >> reg.right_shift) & reg.mask;
2209                 if (reg.invert)
2210                         val = reg.mask - val;
2211                 ucontrol->value.integer.value[1] = val;
2212         }
2213         spin_unlock_irq(&cm->reg_lock);
2214         return 0;
2215 }
2216
2217 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2218                                        struct snd_ctl_elem_value *ucontrol)
2219 {
2220         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2221         struct cmipci_sb_reg reg;
2222         unsigned char oreg, nreg, val;
2223
2224         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2225         spin_lock_irq(&cm->reg_lock);
2226         oreg = inb(cm->iobase + reg.left_reg);
2227         val = ucontrol->value.integer.value[0] & reg.mask;
2228         if (reg.invert)
2229                 val = reg.mask - val;
2230         nreg = oreg & ~(reg.mask << reg.left_shift);
2231         nreg |= (val << reg.left_shift);
2232         if (reg.stereo) {
2233                 val = ucontrol->value.integer.value[1] & reg.mask;
2234                 if (reg.invert)
2235                         val = reg.mask - val;
2236                 nreg &= ~(reg.mask << reg.right_shift);
2237                 nreg |= (val << reg.right_shift);
2238         }
2239         outb(nreg, cm->iobase + reg.left_reg);
2240         spin_unlock_irq(&cm->reg_lock);
2241         return (nreg != oreg);
2242 }
2243
2244 /*
2245  * special case - check mixer sensitivity
2246  */
2247 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2248                                                  struct snd_ctl_elem_value *ucontrol)
2249 {
2250         //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2251         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2252 }
2253
2254 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2255                                                  struct snd_ctl_elem_value *ucontrol)
2256 {
2257         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2258         if (cm->mixer_insensitive) {
2259                 /* ignored */
2260                 return 0;
2261         }
2262         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2263 }
2264
2265
2266 static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2267         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2268         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2269         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2270         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2271         { /* switch with sensitivity */
2272                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2273                 .name = "PCM Playback Switch",
2274                 .info = snd_cmipci_info_native_mixer,
2275                 .get = snd_cmipci_get_native_mixer_sensitive,
2276                 .put = snd_cmipci_put_native_mixer_sensitive,
2277                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2278         },
2279         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2280         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2281         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2282         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2283         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2284         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2285         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2286         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2287         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2288         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2289         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2290         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2291         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2292         CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2293         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2294         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2295         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2296         CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2297         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2298         CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2299         CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2300         CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2301         CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2302 };
2303
2304 /*
2305  * other switches
2306  */
2307
2308 struct cmipci_switch_args {
2309         int reg;                /* register index */
2310         unsigned int mask;      /* mask bits */
2311         unsigned int mask_on;   /* mask bits to turn on */
2312         unsigned int is_byte: 1;                /* byte access? */
2313         unsigned int ac3_sensitive: 1;  /* access forbidden during
2314                                          * non-audio operation?
2315                                          */
2316 };
2317
2318 #define snd_cmipci_uswitch_info         snd_ctl_boolean_mono_info
2319
2320 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2321                                    struct snd_ctl_elem_value *ucontrol,
2322                                    struct cmipci_switch_args *args)
2323 {
2324         unsigned int val;
2325         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2326
2327         spin_lock_irq(&cm->reg_lock);
2328         if (args->ac3_sensitive && cm->mixer_insensitive) {
2329                 ucontrol->value.integer.value[0] = 0;
2330                 spin_unlock_irq(&cm->reg_lock);
2331                 return 0;
2332         }
2333         if (args->is_byte)
2334                 val = inb(cm->iobase + args->reg);
2335         else
2336                 val = snd_cmipci_read(cm, args->reg);
2337         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2338         spin_unlock_irq(&cm->reg_lock);
2339         return 0;
2340 }
2341
2342 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2343                                   struct snd_ctl_elem_value *ucontrol)
2344 {
2345         struct cmipci_switch_args *args;
2346         args = (struct cmipci_switch_args *)kcontrol->private_value;
2347         if (snd_BUG_ON(!args))
2348                 return -EINVAL;
2349         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2350 }
2351
2352 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2353                                    struct snd_ctl_elem_value *ucontrol,
2354                                    struct cmipci_switch_args *args)
2355 {
2356         unsigned int val;
2357         int change;
2358         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2359
2360         spin_lock_irq(&cm->reg_lock);
2361         if (args->ac3_sensitive && cm->mixer_insensitive) {
2362                 /* ignored */
2363                 spin_unlock_irq(&cm->reg_lock);
2364                 return 0;
2365         }
2366         if (args->is_byte)
2367                 val = inb(cm->iobase + args->reg);
2368         else
2369                 val = snd_cmipci_read(cm, args->reg);
2370         change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2371                         args->mask_on : (args->mask & ~args->mask_on));
2372         if (change) {
2373                 val &= ~args->mask;
2374                 if (ucontrol->value.integer.value[0])
2375                         val |= args->mask_on;
2376                 else
2377                         val |= (args->mask & ~args->mask_on);
2378                 if (args->is_byte)
2379                         outb((unsigned char)val, cm->iobase + args->reg);
2380                 else
2381                         snd_cmipci_write(cm, args->reg, val);
2382         }
2383         spin_unlock_irq(&cm->reg_lock);
2384         return change;
2385 }
2386
2387 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2388                                   struct snd_ctl_elem_value *ucontrol)
2389 {
2390         struct cmipci_switch_args *args;
2391         args = (struct cmipci_switch_args *)kcontrol->private_value;
2392         if (snd_BUG_ON(!args))
2393                 return -EINVAL;
2394         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2395 }
2396
2397 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2398 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2399   .reg = xreg, \
2400   .mask = xmask, \
2401   .mask_on = xmask_on, \
2402   .is_byte = xis_byte, \
2403   .ac3_sensitive = xac3, \
2404 }
2405
2406 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2407         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2408
2409 #if 0 /* these will be controlled in pcm device */
2410 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2411 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2412 #endif
2413 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2414 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2415 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2416 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2417 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2418 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2419 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2420 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2421 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2422 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2423 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2424 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2425 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2426 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2427 #if CM_CH_PLAY == 1
2428 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2429 #else
2430 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2431 #endif
2432 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2433 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2434 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2435 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2436 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2437
2438 #define DEFINE_SWITCH(sname, stype, sarg) \
2439 { .name = sname, \
2440   .iface = stype, \
2441   .info = snd_cmipci_uswitch_info, \
2442   .get = snd_cmipci_uswitch_get, \
2443   .put = snd_cmipci_uswitch_put, \
2444   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2445 }
2446
2447 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2448 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2449
2450
2451 /*
2452  * callbacks for spdif output switch
2453  * needs toggle two registers..
2454  */
2455 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2456                                         struct snd_ctl_elem_value *ucontrol)
2457 {
2458         int changed;
2459         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2460         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2461         return changed;
2462 }
2463
2464 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2465                                         struct snd_ctl_elem_value *ucontrol)
2466 {
2467         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2468         int changed;
2469         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2470         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2471         if (changed) {
2472                 if (ucontrol->value.integer.value[0]) {
2473                         if (chip->spdif_playback_avail)
2474                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2475                 } else {
2476                         if (chip->spdif_playback_avail)
2477                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2478                 }
2479         }
2480         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2481         return changed;
2482 }
2483
2484
2485 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2486                                         struct snd_ctl_elem_info *uinfo)
2487 {
2488         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2489         static const char *const texts[3] = {
2490                 "Line-In", "Rear Output", "Bass Output"
2491         };
2492
2493         return snd_ctl_enum_info(uinfo, 1,
2494                                  cm->chip_version >= 39 ? 3 : 2, texts);
2495 }
2496
2497 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2498 {
2499         unsigned int val;
2500         if (cm->chip_version >= 39) {
2501                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2502                 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2503                         return 2;
2504         }
2505         val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2506         if (val & CM_REAR2LIN)
2507                 return 1;
2508         return 0;
2509 }
2510
2511 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2512                                        struct snd_ctl_elem_value *ucontrol)
2513 {
2514         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2515
2516         spin_lock_irq(&cm->reg_lock);
2517         ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2518         spin_unlock_irq(&cm->reg_lock);
2519         return 0;
2520 }
2521
2522 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2523                                        struct snd_ctl_elem_value *ucontrol)
2524 {
2525         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2526         int change;
2527
2528         spin_lock_irq(&cm->reg_lock);
2529         if (ucontrol->value.enumerated.item[0] == 2)
2530                 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2531         else
2532                 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2533         if (ucontrol->value.enumerated.item[0] == 1)
2534                 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2535         else
2536                 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2537         spin_unlock_irq(&cm->reg_lock);
2538         return change;
2539 }
2540
2541 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2542                                        struct snd_ctl_elem_info *uinfo)
2543 {
2544         static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2545
2546         return snd_ctl_enum_info(uinfo, 1, 2, texts);
2547 }
2548
2549 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2550                                       struct snd_ctl_elem_value *ucontrol)
2551 {
2552         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2553         /* same bit as spdi_phase */
2554         spin_lock_irq(&cm->reg_lock);
2555         ucontrol->value.enumerated.item[0] =
2556                 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2557         spin_unlock_irq(&cm->reg_lock);
2558         return 0;
2559 }
2560
2561 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2562                                       struct snd_ctl_elem_value *ucontrol)
2563 {
2564         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2565         int change;
2566
2567         spin_lock_irq(&cm->reg_lock);
2568         if (ucontrol->value.enumerated.item[0])
2569                 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2570         else
2571                 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2572         spin_unlock_irq(&cm->reg_lock);
2573         return change;
2574 }
2575
2576 /* both for CM8338/8738 */
2577 static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2578         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2579         {
2580                 .name = "Line-In Mode",
2581                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2582                 .info = snd_cmipci_line_in_mode_info,
2583                 .get = snd_cmipci_line_in_mode_get,
2584                 .put = snd_cmipci_line_in_mode_put,
2585         },
2586 };
2587
2588 /* for non-multichannel chips */
2589 static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2590 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2591
2592 /* only for CM8738 */
2593 static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2594 #if 0 /* controlled in pcm device */
2595         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2596         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2597         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2598 #endif
2599         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2600         { .name = "IEC958 Output Switch",
2601           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2602           .info = snd_cmipci_uswitch_info,
2603           .get = snd_cmipci_spdout_enable_get,
2604           .put = snd_cmipci_spdout_enable_put,
2605         },
2606         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2607         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2608         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2609 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2610         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2611         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2612 };
2613
2614 /* only for model 033/037 */
2615 static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2616         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2617         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2618         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2619 };
2620
2621 /* only for model 039 or later */
2622 static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2623         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2624         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2625         {
2626                 .name = "Mic-In Mode",
2627                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2628                 .info = snd_cmipci_mic_in_mode_info,
2629                 .get = snd_cmipci_mic_in_mode_get,
2630                 .put = snd_cmipci_mic_in_mode_put,
2631         }
2632 };
2633
2634 /* card control switches */
2635 static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2636 DEFINE_CARD_SWITCH("Modem", modem);
2637
2638
2639 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2640 {
2641         struct snd_card *card;
2642         const struct snd_kcontrol_new *sw;
2643         struct snd_kcontrol *kctl;
2644         unsigned int idx;
2645         int err;
2646
2647         if (snd_BUG_ON(!cm || !cm->card))
2648                 return -EINVAL;
2649
2650         card = cm->card;
2651
2652         strcpy(card->mixername, "CMedia PCI");
2653
2654         spin_lock_irq(&cm->reg_lock);
2655         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2656         spin_unlock_irq(&cm->reg_lock);
2657
2658         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2659                 if (cm->chip_version == 68) {   // 8768 has no PCM volume
2660                         if (!strcmp(snd_cmipci_mixers[idx].name,
2661                                 "PCM Playback Volume"))
2662                                 continue;
2663                 }
2664                 err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm));
2665                 if (err < 0)
2666                         return err;
2667         }
2668
2669         /* mixer switches */
2670         sw = snd_cmipci_mixer_switches;
2671         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2672                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2673                 if (err < 0)
2674                         return err;
2675         }
2676         if (! cm->can_multi_ch) {
2677                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2678                 if (err < 0)
2679                         return err;
2680         }
2681         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2682             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2683                 sw = snd_cmipci_8738_mixer_switches;
2684                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2685                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2686                         if (err < 0)
2687                                 return err;
2688                 }
2689                 if (cm->can_ac3_hw) {
2690                         kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm);
2691                         err = snd_ctl_add(card, kctl);
2692                         if (err < 0)
2693                                 return err;
2694                         kctl->id.device = pcm_spdif_device;
2695                         kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm);
2696                         err = snd_ctl_add(card, kctl);
2697                         if (err < 0)
2698                                 return err;
2699                         kctl->id.device = pcm_spdif_device;
2700                         kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm);
2701                         err = snd_ctl_add(card, kctl);
2702                         if (err < 0)
2703                                 return err;
2704                         kctl->id.device = pcm_spdif_device;
2705                 }
2706                 if (cm->chip_version <= 37) {
2707                         sw = snd_cmipci_old_mixer_switches;
2708                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2709                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2710                                 if (err < 0)
2711                                         return err;
2712                         }
2713                 }
2714         }
2715         if (cm->chip_version >= 39) {
2716                 sw = snd_cmipci_extra_mixer_switches;
2717                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2718                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2719                         if (err < 0)
2720                                 return err;
2721                 }
2722         }
2723
2724         /* card switches */
2725         /*
2726          * newer chips don't have the register bits to force modem link
2727          * detection; the bit that was FLINKON now mutes CH1
2728          */
2729         if (cm->chip_version < 39) {
2730                 err = snd_ctl_add(cm->card,
2731                                   snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2732                 if (err < 0)
2733                         return err;
2734         }
2735
2736         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2737                 struct snd_ctl_elem_id elem_id;
2738                 struct snd_kcontrol *ctl;
2739                 memset(&elem_id, 0, sizeof(elem_id));
2740                 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2741                 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2742                 ctl = snd_ctl_find_id(cm->card, &elem_id);
2743                 if (ctl)
2744                         cm->mixer_res_ctl[idx] = ctl;
2745         }
2746
2747         return 0;
2748 }
2749
2750
2751 /*
2752  * proc interface
2753  */
2754
2755 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2756                                  struct snd_info_buffer *buffer)
2757 {
2758         struct cmipci *cm = entry->private_data;
2759         int i, v;
2760
2761         snd_iprintf(buffer, "%s\n", cm->card->longname);
2762         for (i = 0; i < 0x94; i++) {
2763                 if (i == 0x28)
2764                         i = 0x90;
2765                 v = inb(cm->iobase + i);
2766                 if (i % 4 == 0)
2767                         snd_iprintf(buffer, "\n%02x:", i);
2768                 snd_iprintf(buffer, " %02x", v);
2769         }
2770         snd_iprintf(buffer, "\n");
2771 }
2772
2773 static void snd_cmipci_proc_init(struct cmipci *cm)
2774 {
2775         snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2776 }
2777
2778 static const struct pci_device_id snd_cmipci_ids[] = {
2779         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2780         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2781         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2782         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2783         {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2784         {0,},
2785 };
2786
2787
2788 /*
2789  * check chip version and capabilities
2790  * driver name is modified according to the chip model
2791  */
2792 static void query_chip(struct cmipci *cm)
2793 {
2794         unsigned int detect;
2795
2796         /* check reg 0Ch, bit 24-31 */
2797         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2798         if (! detect) {
2799                 /* check reg 08h, bit 24-28 */
2800                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2801                 switch (detect) {
2802                 case 0:
2803                         cm->chip_version = 33;
2804                         if (cm->do_soft_ac3)
2805                                 cm->can_ac3_sw = 1;
2806                         else
2807                                 cm->can_ac3_hw = 1;
2808                         break;
2809                 case CM_CHIP_037:
2810                         cm->chip_version = 37;
2811                         cm->can_ac3_hw = 1;
2812                         break;
2813                 default:
2814                         cm->chip_version = 39;
2815                         cm->can_ac3_hw = 1;
2816                         break;
2817                 }
2818                 cm->max_channels = 2;
2819         } else {
2820                 if (detect & CM_CHIP_039) {
2821                         cm->chip_version = 39;
2822                         if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2823                                 cm->max_channels = 6;
2824                         else
2825                                 cm->max_channels = 4;
2826                 } else if (detect & CM_CHIP_8768) {
2827                         cm->chip_version = 68;
2828                         cm->max_channels = 8;
2829                         cm->can_96k = 1;
2830                 } else {
2831                         cm->chip_version = 55;
2832                         cm->max_channels = 6;
2833                         cm->can_96k = 1;
2834                 }
2835                 cm->can_ac3_hw = 1;
2836                 cm->can_multi_ch = 1;
2837         }
2838 }
2839
2840 #ifdef SUPPORT_JOYSTICK
2841 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2842 {
2843         static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2844         struct gameport *gp;
2845         struct resource *r = NULL;
2846         int i, io_port = 0;
2847
2848         if (joystick_port[dev] == 0)
2849                 return -ENODEV;
2850
2851         if (joystick_port[dev] == 1) { /* auto-detect */
2852                 for (i = 0; ports[i]; i++) {
2853                         io_port = ports[i];
2854                         r = devm_request_region(&cm->pci->dev, io_port, 1,
2855                                                 "CMIPCI gameport");
2856                         if (r)
2857                                 break;
2858                 }
2859         } else {
2860                 io_port = joystick_port[dev];
2861                 r = devm_request_region(&cm->pci->dev, io_port, 1,
2862                                         "CMIPCI gameport");
2863         }
2864
2865         if (!r) {
2866                 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2867                 return -EBUSY;
2868         }
2869
2870         cm->gameport = gp = gameport_allocate_port();
2871         if (!gp) {
2872                 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2873                 return -ENOMEM;
2874         }
2875         gameport_set_name(gp, "C-Media Gameport");
2876         gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2877         gameport_set_dev_parent(gp, &cm->pci->dev);
2878         gp->io = io_port;
2879
2880         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2881
2882         gameport_register_port(cm->gameport);
2883
2884         return 0;
2885 }
2886
2887 static void snd_cmipci_free_gameport(struct cmipci *cm)
2888 {
2889         if (cm->gameport) {
2890                 gameport_unregister_port(cm->gameport);
2891                 cm->gameport = NULL;
2892
2893                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2894         }
2895 }
2896 #else
2897 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2898 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2899 #endif
2900
2901 static void snd_cmipci_free(struct snd_card *card)
2902 {
2903         struct cmipci *cm = card->private_data;
2904
2905         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2906         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2907         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2908         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2909         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2910         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2911         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2912
2913         /* reset mixer */
2914         snd_cmipci_mixer_write(cm, 0, 0);
2915
2916         snd_cmipci_free_gameport(cm);
2917 }
2918
2919 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2920 {
2921         long iosynth;
2922         unsigned int val;
2923         struct snd_opl3 *opl3;
2924         int err;
2925
2926         if (!fm_port)
2927                 goto disable_fm;
2928
2929         if (cm->chip_version >= 39) {
2930                 /* first try FM regs in PCI port range */
2931                 iosynth = cm->iobase + CM_REG_FM_PCI;
2932                 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2933                                       OPL3_HW_OPL3, 1, &opl3);
2934         } else {
2935                 err = -EIO;
2936         }
2937         if (err < 0) {
2938                 /* then try legacy ports */
2939                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2940                 iosynth = fm_port;
2941                 switch (iosynth) {
2942                 case 0x3E8: val |= CM_FMSEL_3E8; break;
2943                 case 0x3E0: val |= CM_FMSEL_3E0; break;
2944                 case 0x3C8: val |= CM_FMSEL_3C8; break;
2945                 case 0x388: val |= CM_FMSEL_388; break;
2946                 default:
2947                         goto disable_fm;
2948                 }
2949                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2950                 /* enable FM */
2951                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2952
2953                 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2954                                     OPL3_HW_OPL3, 0, &opl3) < 0) {
2955                         dev_err(cm->card->dev,
2956                                 "no OPL device at %#lx, skipping...\n",
2957                                 iosynth);
2958                         goto disable_fm;
2959                 }
2960         }
2961         err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2962         if (err < 0) {
2963                 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2964                 return err;
2965         }
2966         return 0;
2967
2968  disable_fm:
2969         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2970         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2971         return 0;
2972 }
2973
2974 static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2975                              int dev)
2976 {
2977         struct cmipci *cm = card->private_data;
2978         int err;
2979         unsigned int val;
2980         long iomidi = 0;
2981         int integrated_midi = 0;
2982         char modelstr[16];
2983         int pcm_index, pcm_spdif_index;
2984         static const struct pci_device_id intel_82437vx[] = {
2985                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2986                 { },
2987         };
2988
2989         err = pcim_enable_device(pci);
2990         if (err < 0)
2991                 return err;
2992
2993         spin_lock_init(&cm->reg_lock);
2994         mutex_init(&cm->open_mutex);
2995         cm->device = pci->device;
2996         cm->card = card;
2997         cm->pci = pci;
2998         cm->irq = -1;
2999         cm->channel[0].ch = 0;
3000         cm->channel[1].ch = 1;
3001         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3002
3003         err = pci_request_regions(pci, card->driver);
3004         if (err < 0)
3005                 return err;
3006         cm->iobase = pci_resource_start(pci, 0);
3007
3008         if (devm_request_irq(&pci->dev, pci->irq, snd_cmipci_interrupt,
3009                              IRQF_SHARED, KBUILD_MODNAME, cm)) {
3010                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3011                 return -EBUSY;
3012         }
3013         cm->irq = pci->irq;
3014         card->sync_irq = cm->irq;
3015         card->private_free = snd_cmipci_free;
3016
3017         pci_set_master(cm->pci);
3018
3019         /*
3020          * check chip version, max channels and capabilities
3021          */
3022
3023         cm->chip_version = 0;
3024         cm->max_channels = 2;
3025         cm->do_soft_ac3 = soft_ac3[dev];
3026
3027         if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3028             pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3029                 query_chip(cm);
3030         /* added -MCx suffix for chip supporting multi-channels */
3031         if (cm->can_multi_ch)
3032                 sprintf(cm->card->driver + strlen(cm->card->driver),
3033                         "-MC%d", cm->max_channels);
3034         else if (cm->can_ac3_sw)
3035                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3036
3037         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3038         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3039
3040 #if CM_CH_PLAY == 1
3041         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
3042 #else
3043         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
3044 #endif
3045
3046         /* initialize codec registers */
3047         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3048         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3049         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
3050         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3051         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3052         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
3053         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3054
3055         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3056         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3057 #if CM_CH_PLAY == 1
3058         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3059 #else
3060         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3061 #endif
3062         if (cm->chip_version) {
3063                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3064                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3065         }
3066         /* Set Bus Master Request */
3067         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3068
3069         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3070         switch (pci->device) {
3071         case PCI_DEVICE_ID_CMEDIA_CM8738:
3072         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3073                 if (!pci_dev_present(intel_82437vx))
3074                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3075                 break;
3076         default:
3077                 break;
3078         }
3079
3080         if (cm->chip_version < 68) {
3081                 val = pci->device < 0x110 ? 8338 : 8738;
3082         } else {
3083                 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3084                 case 0:
3085                         val = 8769;
3086                         break;
3087                 case 2:
3088                         val = 8762;
3089                         break;
3090                 default:
3091                         switch ((pci->subsystem_vendor << 16) |
3092                                 pci->subsystem_device) {
3093                         case 0x13f69761:
3094                         case 0x584d3741:
3095                         case 0x584d3751:
3096                         case 0x584d3761:
3097                         case 0x584d3771:
3098                         case 0x72848384:
3099                                 val = 8770;
3100                                 break;
3101                         default:
3102                                 val = 8768;
3103                                 break;
3104                         }
3105                 }
3106         }
3107         sprintf(card->shortname, "C-Media CMI%d", val);
3108         if (cm->chip_version < 68)
3109                 sprintf(modelstr, " (model %d)", cm->chip_version);
3110         else
3111                 modelstr[0] = '\0';
3112         sprintf(card->longname, "%s%s at %#lx, irq %i",
3113                 card->shortname, modelstr, cm->iobase, cm->irq);
3114
3115         if (cm->chip_version >= 39) {
3116                 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3117                 if (val != 0x00 && val != 0xff) {
3118                         if (mpu_port[dev])
3119                                 iomidi = cm->iobase + CM_REG_MPU_PCI;
3120                         integrated_midi = 1;
3121                 }
3122         }
3123         if (!integrated_midi) {
3124                 val = 0;
3125                 iomidi = mpu_port[dev];
3126                 switch (iomidi) {
3127                 case 0x320: val = CM_VMPU_320; break;
3128                 case 0x310: val = CM_VMPU_310; break;
3129                 case 0x300: val = CM_VMPU_300; break;
3130                 case 0x330: val = CM_VMPU_330; break;
3131                 default:
3132                             iomidi = 0; break;
3133                 }
3134                 if (iomidi > 0) {
3135                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3136                         /* enable UART */
3137                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3138                         if (inb(iomidi + 1) == 0xff) {
3139                                 dev_err(cm->card->dev,
3140                                         "cannot enable MPU-401 port at %#lx\n",
3141                                         iomidi);
3142                                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3143                                                      CM_UART_EN);
3144                                 iomidi = 0;
3145                         }
3146                 }
3147         }
3148
3149         if (cm->chip_version < 68) {
3150                 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3151                 if (err < 0)
3152                         return err;
3153         }
3154
3155         /* reset mixer */
3156         snd_cmipci_mixer_write(cm, 0, 0);
3157
3158         snd_cmipci_proc_init(cm);
3159
3160         /* create pcm devices */
3161         pcm_index = pcm_spdif_index = 0;
3162         err = snd_cmipci_pcm_new(cm, pcm_index);
3163         if (err < 0)
3164                 return err;
3165         pcm_index++;
3166         err = snd_cmipci_pcm2_new(cm, pcm_index);
3167         if (err < 0)
3168                 return err;
3169         pcm_index++;
3170         if (cm->can_ac3_hw || cm->can_ac3_sw) {
3171                 pcm_spdif_index = pcm_index;
3172                 err = snd_cmipci_pcm_spdif_new(cm, pcm_index);
3173                 if (err < 0)
3174                         return err;
3175         }
3176
3177         /* create mixer interface & switches */
3178         err = snd_cmipci_mixer_new(cm, pcm_spdif_index);
3179         if (err < 0)
3180                 return err;
3181
3182         if (iomidi > 0) {
3183                 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3184                                           iomidi,
3185                                           (integrated_midi ?
3186                                            MPU401_INFO_INTEGRATED : 0) |
3187                                           MPU401_INFO_IRQ_HOOK,
3188                                           -1, &cm->rmidi);
3189                 if (err < 0)
3190                         dev_err(cm->card->dev,
3191                                 "no UART401 device at 0x%lx\n", iomidi);
3192         }
3193
3194 #ifdef USE_VAR48KRATE
3195         for (val = 0; val < ARRAY_SIZE(rates); val++)
3196                 snd_cmipci_set_pll(cm, rates[val], val);
3197
3198         /*
3199          * (Re-)Enable external switch spdo_48k
3200          */
3201         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3202 #endif /* USE_VAR48KRATE */
3203
3204         if (snd_cmipci_create_gameport(cm, dev) < 0)
3205                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3206
3207         return 0;
3208 }
3209
3210 /*
3211  */
3212
3213 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3214
3215 static int snd_cmipci_probe(struct pci_dev *pci,
3216                             const struct pci_device_id *pci_id)
3217 {
3218         static int dev;
3219         struct snd_card *card;
3220         int err;
3221
3222         if (dev >= SNDRV_CARDS)
3223                 return -ENODEV;
3224         if (! enable[dev]) {
3225                 dev++;
3226                 return -ENOENT;
3227         }
3228
3229         err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3230                                 sizeof(struct cmipci), &card);
3231         if (err < 0)
3232                 return err;
3233
3234         switch (pci->device) {
3235         case PCI_DEVICE_ID_CMEDIA_CM8738:
3236         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3237                 strcpy(card->driver, "CMI8738");
3238                 break;
3239         case PCI_DEVICE_ID_CMEDIA_CM8338A:
3240         case PCI_DEVICE_ID_CMEDIA_CM8338B:
3241                 strcpy(card->driver, "CMI8338");
3242                 break;
3243         default:
3244                 strcpy(card->driver, "CMIPCI");
3245                 break;
3246         }
3247
3248         err = snd_cmipci_create(card, pci, dev);
3249         if (err < 0)
3250                 goto error;
3251
3252         err = snd_card_register(card);
3253         if (err < 0)
3254                 goto error;
3255
3256         pci_set_drvdata(pci, card);
3257         dev++;
3258         return 0;
3259
3260  error:
3261         snd_card_free(card);
3262         return err;
3263 }
3264
3265 #ifdef CONFIG_PM_SLEEP
3266 /*
3267  * power management
3268  */
3269 static const unsigned char saved_regs[] = {
3270         CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3271         CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
3272         CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3273         CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3274         CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3275 };
3276
3277 static const unsigned char saved_mixers[] = {
3278         SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3279         SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3280         SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3281         SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3282         SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3283         SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3284         CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3285         SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3286 };
3287
3288 static int snd_cmipci_suspend(struct device *dev)
3289 {
3290         struct snd_card *card = dev_get_drvdata(dev);
3291         struct cmipci *cm = card->private_data;
3292         int i;
3293
3294         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3295
3296         /* save registers */
3297         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3298                 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3299         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3300                 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3301
3302         /* disable ints */
3303         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3304         return 0;
3305 }
3306
3307 static int snd_cmipci_resume(struct device *dev)
3308 {
3309         struct snd_card *card = dev_get_drvdata(dev);
3310         struct cmipci *cm = card->private_data;
3311         int i;
3312
3313         /* reset / initialize to a sane state */
3314         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3315         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3316         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3317         snd_cmipci_mixer_write(cm, 0, 0);
3318
3319         /* restore registers */
3320         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3321                 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3322         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3323                 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3324
3325         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3326         return 0;
3327 }
3328
3329 static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3330 #define SND_CMIPCI_PM_OPS       &snd_cmipci_pm
3331 #else
3332 #define SND_CMIPCI_PM_OPS       NULL
3333 #endif /* CONFIG_PM_SLEEP */
3334
3335 static struct pci_driver cmipci_driver = {
3336         .name = KBUILD_MODNAME,
3337         .id_table = snd_cmipci_ids,
3338         .probe = snd_cmipci_probe,
3339         .driver = {
3340                 .pm = SND_CMIPCI_PM_OPS,
3341         },
3342 };
3343
3344 module_pci_driver(cmipci_driver);