1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio stream operations
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <linux/clocksource.h>
10 #include <sound/compress_driver.h>
11 #include <sound/core.h>
12 #include <sound/pcm.h>
13 #include <sound/hdaudio.h>
14 #include <sound/hda_register.h>
18 * the hdac_stream library is intended to be used with the following
19 * transitions. The states are not formally defined in the code but loosely
20 * inspired by boolean variables. Note that the 'prepared' field is not used
21 * in this library but by the callers during the hw_params/prepare transitions
30 * stream_assign() | | stream_release()
37 * stream_setup() | | stream_cleanup()
43 * stream_start() | | stream_stop()
51 * snd_hdac_get_stream_stripe_ctl - get stripe control value
52 * @bus: HD-audio core bus
53 * @substream: PCM substream
55 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
56 struct snd_pcm_substream *substream)
58 struct snd_pcm_runtime *runtime = substream->runtime;
59 unsigned int channels = runtime->channels,
61 bits_per_sample = runtime->sample_bits,
62 max_sdo_lines, value, sdo_line;
64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
65 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
67 /* following is from HD audio spec */
68 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
70 value = (channels * bits_per_sample *
71 (rate / 48000)) / sdo_line;
73 value = (channels * bits_per_sample) / sdo_line;
75 if (value >= bus->sdo_limit)
79 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
85 * snd_hdac_stream_init - initialize each stream (aka device)
86 * @bus: HD-audio core bus
87 * @azx_dev: HD-audio core stream object to initialize
88 * @idx: stream index number
89 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
90 * @tag: the tag id to assign
92 * Assign the starting bdl address to each stream (device) and initialize.
94 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
95 int idx, int direction, int tag)
98 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
100 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
101 azx_dev->sd_int_sta_mask = 1 << idx;
102 azx_dev->index = idx;
103 azx_dev->direction = direction;
104 azx_dev->stream_tag = tag;
105 snd_hdac_dsp_lock_init(azx_dev);
106 list_add_tail(&azx_dev->list, &bus->stream_list);
109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +
110 AZX_SPB_INTERVAL * idx +
113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +
114 AZX_SPB_INTERVAL * idx +
119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
120 AZX_DRSM_INTERVAL * idx;
122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
125 * snd_hdac_stream_start - start a stream
126 * @azx_dev: HD-audio core stream to start
128 * Start a stream, set start_wallclk and set the running flag.
130 void snd_hdac_stream_start(struct hdac_stream *azx_dev)
132 struct hdac_bus *bus = azx_dev->bus;
135 trace_snd_hdac_stream_start(bus, azx_dev);
137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
140 snd_hdac_chip_updatel(bus, INTCTL,
142 1 << azx_dev->index);
143 /* set stripe control */
144 if (azx_dev->stripe) {
145 if (azx_dev->substream)
146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
149 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
152 /* set DMA start and interrupt mask */
153 snd_hdac_stream_updateb(azx_dev, SD_CTL,
154 0, SD_CTL_DMA_START | SD_INT_MASK);
155 azx_dev->running = true;
157 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
160 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers
161 * @azx_dev: HD-audio core stream to stop
163 static void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
165 snd_hdac_stream_updateb(azx_dev, SD_CTL,
166 SD_CTL_DMA_START | SD_INT_MASK, 0);
167 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
169 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
170 azx_dev->running = false;
174 * snd_hdac_stream_stop - stop a stream
175 * @azx_dev: HD-audio core stream to stop
177 * Stop a stream DMA and disable stream interrupt
179 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
181 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
183 snd_hdac_stream_clear(azx_dev);
185 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
187 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
190 * snd_hdac_stop_streams - stop all streams
191 * @bus: HD-audio core bus
193 void snd_hdac_stop_streams(struct hdac_bus *bus)
195 struct hdac_stream *stream;
197 list_for_each_entry(stream, &bus->stream_list, list)
198 snd_hdac_stream_stop(stream);
200 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
203 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
204 * @bus: HD-audio core bus
206 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
209 if (bus->chip_init) {
210 snd_hdac_stop_streams(bus);
211 snd_hdac_bus_stop_chip(bus);
214 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
217 * snd_hdac_stream_reset - reset a stream
218 * @azx_dev: HD-audio core stream to reset
220 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
225 snd_hdac_stream_clear(azx_dev);
227 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
229 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
231 /* wait for hardware to report that the stream entered reset */
232 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300);
234 if (azx_dev->bus->dma_stop_delay && dma_run_state)
235 udelay(azx_dev->bus->dma_stop_delay);
237 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0);
239 /* wait for hardware to report that the stream is out of reset */
240 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300);
242 /* reset first position - may not be synced with hw at this time */
244 *azx_dev->posbuf = 0;
246 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
249 * snd_hdac_stream_setup - set up the SD for streaming
250 * @azx_dev: HD-audio core stream to set up
252 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
254 struct hdac_bus *bus = azx_dev->bus;
255 struct snd_pcm_runtime *runtime;
258 if (azx_dev->substream)
259 runtime = azx_dev->substream->runtime;
262 /* make sure the run bit is zero for SD */
263 snd_hdac_stream_clear(azx_dev);
264 /* program the stream_tag */
265 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
266 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
267 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
269 val |= SD_CTL_TRAFFIC_PRIO;
270 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
272 /* program the length of samples in cyclic buffer */
273 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
275 /* program the stream format */
276 /* this value needs to be the same as the one programmed */
277 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
279 /* program the stream LVI (last valid index) of the BDL */
280 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
282 /* program the BDL address */
283 /* lower BDL address */
284 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
285 /* upper BDL address */
286 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
287 upper_32_bits(azx_dev->bdl.addr));
289 /* enable the position buffer */
290 if (bus->use_posbuf && bus->posbuf.addr) {
291 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
292 snd_hdac_chip_writel(bus, DPLBASE,
293 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
296 /* set the interrupt enable bits in the descriptor control register */
297 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
299 azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
301 /* when LPIB delay correction gives a small negative value,
302 * we ignore it; currently set the threshold statically to
305 if (runtime && runtime->period_size > 64)
306 azx_dev->delay_negative_threshold =
307 -frames_to_bytes(runtime, 64);
309 azx_dev->delay_negative_threshold = 0;
311 /* wallclk has 24Mhz clock source */
313 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
314 runtime->rate) * 1000);
318 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
321 * snd_hdac_stream_cleanup - cleanup a stream
322 * @azx_dev: HD-audio core stream to clean up
324 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
326 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
327 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
328 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
329 azx_dev->bufsize = 0;
330 azx_dev->period_bytes = 0;
331 azx_dev->format_val = 0;
333 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
336 * snd_hdac_stream_assign - assign a stream for the PCM
337 * @bus: HD-audio core bus
338 * @substream: PCM substream to assign
340 * Look for an unused stream for the given PCM substream, assign it
341 * and return the stream object. If no stream is free, returns NULL.
342 * The function tries to keep using the same stream object when it's used
343 * beforehand. Also, when bus->reverse_assign flag is set, the last free
344 * or matching entry is returned. This is needed for some strange codecs.
346 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
347 struct snd_pcm_substream *substream)
349 struct hdac_stream *azx_dev;
350 struct hdac_stream *res = NULL;
352 /* make a non-zero unique key for the substream */
353 int key = (substream->pcm->device << 16) | (substream->number << 2) |
354 (substream->stream + 1);
356 spin_lock_irq(&bus->reg_lock);
357 list_for_each_entry(azx_dev, &bus->stream_list, list) {
358 if (azx_dev->direction != substream->stream)
362 if (azx_dev->assigned_key == key) {
366 if (!res || bus->reverse_assign)
372 res->assigned_key = key;
373 res->substream = substream;
375 spin_unlock_irq(&bus->reg_lock);
378 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
381 * snd_hdac_stream_release_locked - release the assigned stream
382 * @azx_dev: HD-audio core stream to release
384 * Release the stream that has been assigned by snd_hdac_stream_assign().
385 * The bus->reg_lock needs to be taken at a higher level
387 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev)
390 azx_dev->running = 0;
391 azx_dev->substream = NULL;
393 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked);
396 * snd_hdac_stream_release - release the assigned stream
397 * @azx_dev: HD-audio core stream to release
399 * Release the stream that has been assigned by snd_hdac_stream_assign().
401 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
403 struct hdac_bus *bus = azx_dev->bus;
405 spin_lock_irq(&bus->reg_lock);
406 snd_hdac_stream_release_locked(azx_dev);
407 spin_unlock_irq(&bus->reg_lock);
409 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
412 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
415 * @bus: HD-audio core bus
416 * @dir: direction for the stream to be found
417 * @stream_tag: stream tag for stream to be found
419 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
420 int dir, int stream_tag)
422 struct hdac_stream *s;
424 list_for_each_entry(s, &bus->stream_list, list) {
425 if (s->direction == dir && s->stream_tag == stream_tag)
431 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
436 static int setup_bdle(struct hdac_bus *bus,
437 struct snd_dma_buffer *dmab,
438 struct hdac_stream *azx_dev, __le32 **bdlp,
439 int ofs, int size, int with_ioc)
447 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
450 addr = snd_sgbuf_get_addr(dmab, ofs);
451 /* program the address field of the BDL entry */
452 bdl[0] = cpu_to_le32((u32)addr);
453 bdl[1] = cpu_to_le32(upper_32_bits(addr));
454 /* program the size field of the BDL entry */
455 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
456 /* one BDLE cannot cross 4K boundary on CTHDA chips */
457 if (bus->align_bdle_4k) {
458 u32 remain = 0x1000 - (ofs & 0xfff);
463 bdl[2] = cpu_to_le32(chunk);
464 /* program the IOC to enable interrupt
465 * only when the whole fragment is processed
468 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
478 * snd_hdac_stream_setup_periods - set up BDL entries
479 * @azx_dev: HD-audio core stream to set up
481 * Set up the buffer descriptor table of the given stream based on the
482 * period and buffer sizes of the assigned PCM substream.
484 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
486 struct hdac_bus *bus = azx_dev->bus;
487 struct snd_pcm_substream *substream = azx_dev->substream;
488 struct snd_compr_stream *cstream = azx_dev->cstream;
489 struct snd_pcm_runtime *runtime = NULL;
490 struct snd_dma_buffer *dmab;
492 int i, ofs, periods, period_bytes;
493 int pos_adj, pos_align;
496 runtime = substream->runtime;
497 dmab = snd_pcm_get_dma_buf(substream);
498 } else if (cstream) {
499 dmab = snd_pcm_get_dma_buf(cstream);
501 WARN(1, "No substream or cstream assigned\n");
505 /* reset BDL address */
506 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
507 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
509 period_bytes = azx_dev->period_bytes;
510 periods = azx_dev->bufsize / period_bytes;
512 /* program the initial BDL entries */
513 bdl = (__le32 *)azx_dev->bdl.area;
517 pos_adj = bus->bdl_pos_adj;
518 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {
520 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
524 pos_adj = roundup(pos_adj, pos_align);
525 pos_adj = frames_to_bytes(runtime, pos_adj);
526 if (pos_adj >= period_bytes) {
527 dev_warn(bus->dev, "Too big adjustment %d\n",
531 ofs = setup_bdle(bus, dmab, azx_dev,
532 &bdl, ofs, pos_adj, true);
539 for (i = 0; i < periods; i++) {
540 if (i == periods - 1 && pos_adj)
541 ofs = setup_bdle(bus, dmab, azx_dev,
542 &bdl, ofs, period_bytes - pos_adj, 0);
544 ofs = setup_bdle(bus, dmab, azx_dev,
545 &bdl, ofs, period_bytes,
546 !azx_dev->no_period_wakeup);
553 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
554 azx_dev->bufsize, period_bytes);
557 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
560 * snd_hdac_stream_set_params - set stream parameters
561 * @azx_dev: HD-audio core stream for which parameters are to be set
562 * @format_val: format value parameter
564 * Setup the HD-audio core stream parameters from substream of the stream
565 * and passed format value
567 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
568 unsigned int format_val)
570 struct snd_pcm_substream *substream = azx_dev->substream;
571 struct snd_compr_stream *cstream = azx_dev->cstream;
572 unsigned int bufsize, period_bytes;
573 unsigned int no_period_wakeup;
577 bufsize = snd_pcm_lib_buffer_bytes(substream);
578 period_bytes = snd_pcm_lib_period_bytes(substream);
579 no_period_wakeup = substream->runtime->no_period_wakeup;
580 } else if (cstream) {
581 bufsize = cstream->runtime->buffer_size;
582 period_bytes = cstream->runtime->fragment_size;
583 no_period_wakeup = 0;
588 if (bufsize != azx_dev->bufsize ||
589 period_bytes != azx_dev->period_bytes ||
590 format_val != azx_dev->format_val ||
591 no_period_wakeup != azx_dev->no_period_wakeup) {
592 azx_dev->bufsize = bufsize;
593 azx_dev->period_bytes = period_bytes;
594 azx_dev->format_val = format_val;
595 azx_dev->no_period_wakeup = no_period_wakeup;
596 err = snd_hdac_stream_setup_periods(azx_dev);
602 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
604 static u64 azx_cc_read(const struct cyclecounter *cc)
606 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
608 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
611 static void azx_timecounter_init(struct hdac_stream *azx_dev,
612 bool force, u64 last)
614 struct timecounter *tc = &azx_dev->tc;
615 struct cyclecounter *cc = &azx_dev->cc;
618 cc->read = azx_cc_read;
619 cc->mask = CLOCKSOURCE_MASK(32);
622 * Calculate the optimal mult/shift values. The counter wraps
623 * around after ~178.9 seconds.
625 clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000,
628 nsec = 0; /* audio time is elapsed time since trigger */
629 timecounter_init(tc, cc, nsec);
632 * force timecounter to use predefined value,
633 * used for synchronized starts
635 tc->cycle_last = last;
640 * snd_hdac_stream_timecounter_init - initialize time counter
641 * @azx_dev: HD-audio core stream (master stream)
642 * @streams: bit flags of streams to set up
644 * Initializes the time counter of streams marked by the bit flags (each
645 * bit corresponds to the stream index).
646 * The trigger timestamp of PCM substream assigned to the given stream is
647 * updated accordingly, too.
649 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
650 unsigned int streams)
652 struct hdac_bus *bus = azx_dev->bus;
653 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
654 struct hdac_stream *s;
659 list_for_each_entry(s, &bus->stream_list, list) {
660 if (streams & (1 << i)) {
661 azx_timecounter_init(s, inited, cycle_last);
664 cycle_last = s->tc.cycle_last;
670 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
671 runtime->trigger_tstamp_latched = true;
673 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
676 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
677 * @azx_dev: HD-audio core stream (master stream)
678 * @set: true = set, false = clear
679 * @streams: bit flags of streams to sync
680 * @reg: the stream sync register address
682 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
683 unsigned int streams, unsigned int reg)
685 struct hdac_bus *bus = azx_dev->bus;
690 val = _snd_hdac_chip_readl(bus, reg);
695 _snd_hdac_chip_writel(bus, reg, val);
697 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
700 * snd_hdac_stream_sync - sync with start/stop trigger operation
701 * @azx_dev: HD-audio core stream (master stream)
702 * @start: true = start, false = stop
703 * @streams: bit flags of streams to sync
705 * For @start = true, wait until all FIFOs get ready.
706 * For @start = false, wait until all RUN bits are cleared.
708 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
709 unsigned int streams)
711 struct hdac_bus *bus = azx_dev->bus;
712 int i, nwait, timeout;
713 struct hdac_stream *s;
715 for (timeout = 5000; timeout; timeout--) {
718 list_for_each_entry(s, &bus->stream_list, list) {
719 if (!(streams & (1 << i++)))
723 /* check FIFO gets ready */
724 if (!(snd_hdac_stream_readb(s, SD_STS) &
728 /* check RUN bit is cleared */
729 if (snd_hdac_stream_readb(s, SD_CTL) &
733 * Perform stream reset if DMA RUN
734 * bit not cleared within given timeout
737 snd_hdac_stream_reset(s);
746 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
749 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream
750 * @bus: HD-audio core bus
751 * @enable: flag to enable/disable SPIB
752 * @index: stream index for which SPIB need to be enabled
754 void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus,
755 bool enable, int index)
760 dev_err(bus->dev, "Address of SPB capability is NULL\n");
764 mask |= (1 << index);
767 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
769 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
771 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable);
774 * snd_hdac_stream_set_spib - sets the spib value of a stream
775 * @bus: HD-audio core bus
776 * @azx_dev: hdac_stream
777 * @value: spib value to set
779 int snd_hdac_stream_set_spib(struct hdac_bus *bus,
780 struct hdac_stream *azx_dev, u32 value)
783 dev_err(bus->dev, "Address of SPB capability is NULL\n");
787 writel(value, azx_dev->spib_addr);
791 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);
794 * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream
795 * @bus: HD-audio core bus
796 * @azx_dev: hdac_stream
798 * Return maxfifo for the stream
800 int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
801 struct hdac_stream *azx_dev)
804 dev_err(bus->dev, "Address of SPB capability is NULL\n");
808 return readl(azx_dev->fifo_addr);
810 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo);
813 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream
814 * @bus: HD-audio core bus
815 * @enable: flag to enable/disable DRSM
816 * @index: stream index for which DRSM need to be enabled
818 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
819 bool enable, int index)
824 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
828 mask |= (1 << index);
831 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
833 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
835 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);
838 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream
839 * @azx_dev: HD-audio core stream to await RSM for
841 * Returns 0 on success and -ETIMEDOUT upon a timeout.
843 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev)
845 struct hdac_bus *bus = azx_dev->bus;
849 mask = 1 << azx_dev->index;
851 ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus,
852 bus->drsmcap + AZX_REG_DRSM_CTL);
854 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret);
857 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);
860 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream
861 * @bus: HD-audio core bus
862 * @azx_dev: hdac_stream
863 * @value: dpib value to set
865 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
866 struct hdac_stream *azx_dev, u32 value)
869 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
873 writel(value, azx_dev->dpibr_addr);
877 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);
880 * snd_hdac_stream_set_lpib - sets the lpib value of a stream
881 * @azx_dev: hdac_stream
882 * @value: lpib value to set
884 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value)
886 snd_hdac_stream_writel(azx_dev, SD_LPIB, value);
890 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);
892 #ifdef CONFIG_SND_HDA_DSP_LOADER
894 * snd_hdac_dsp_prepare - prepare for DSP loading
895 * @azx_dev: HD-audio core stream used for DSP loading
896 * @format: HD-audio stream format
897 * @byte_size: data chunk byte size
898 * @bufp: allocated buffer
900 * Allocate the buffer for the given size and set up the given stream for
901 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
903 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
904 unsigned int byte_size, struct snd_dma_buffer *bufp)
906 struct hdac_bus *bus = azx_dev->bus;
910 snd_hdac_dsp_lock(azx_dev);
911 spin_lock_irq(&bus->reg_lock);
912 if (azx_dev->running || azx_dev->locked) {
913 spin_unlock_irq(&bus->reg_lock);
917 azx_dev->locked = true;
918 spin_unlock_irq(&bus->reg_lock);
920 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
925 azx_dev->substream = NULL;
926 azx_dev->bufsize = byte_size;
927 azx_dev->period_bytes = byte_size;
928 azx_dev->format_val = format;
930 snd_hdac_stream_reset(azx_dev);
932 /* reset BDL address */
933 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
934 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
937 bdl = (__le32 *)azx_dev->bdl.area;
938 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
942 snd_hdac_stream_setup(azx_dev);
943 snd_hdac_dsp_unlock(azx_dev);
944 return azx_dev->stream_tag;
947 snd_dma_free_pages(bufp);
949 spin_lock_irq(&bus->reg_lock);
950 azx_dev->locked = false;
951 spin_unlock_irq(&bus->reg_lock);
953 snd_hdac_dsp_unlock(azx_dev);
956 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
959 * snd_hdac_dsp_trigger - start / stop DSP loading
960 * @azx_dev: HD-audio core stream used for DSP loading
961 * @start: trigger start or stop
963 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
966 snd_hdac_stream_start(azx_dev);
968 snd_hdac_stream_stop(azx_dev);
970 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
973 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
974 * @azx_dev: HD-audio core stream used for DSP loading
975 * @dmab: buffer used by DSP loading
977 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
978 struct snd_dma_buffer *dmab)
980 struct hdac_bus *bus = azx_dev->bus;
982 if (!dmab->area || !azx_dev->locked)
985 snd_hdac_dsp_lock(azx_dev);
986 /* reset BDL address */
987 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
988 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
989 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
990 azx_dev->bufsize = 0;
991 azx_dev->period_bytes = 0;
992 azx_dev->format_val = 0;
994 snd_dma_free_pages(dmab);
997 spin_lock_irq(&bus->reg_lock);
998 azx_dev->locked = false;
999 spin_unlock_irq(&bus->reg_lock);
1000 snd_hdac_dsp_unlock(azx_dev);
1002 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1003 #endif /* CONFIG_SND_HDA_DSP_LOADER */