sound/hda/hdac_stream.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * HD-audio stream operations
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/delay.h>
   8 #include <linux/export.h>
   9 #include <linux/clocksource.h>
  10 #include <sound/core.h>
  11 #include <sound/pcm.h>
  12 #include <sound/hdaudio.h>
  13 #include <sound/hda_register.h>
  14 #include "trace.h"
  15
  16 /**
  17  * snd_hdac_get_stream_stripe_ctl - get stripe control value
  18  * @bus: HD-audio core bus
  19  * @substream: PCM substream
  20  */
  21 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
  22                                    struct snd_pcm_substream *substream)
  23 {
  24         struct snd_pcm_runtime *runtime = substream->runtime;
  25         unsigned int channels = runtime->channels,
  26                      rate = runtime->rate,
  27                      bits_per_sample = runtime->sample_bits,
  28                      max_sdo_lines, value, sdo_line;
  29
  30         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
  31         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
  32
  33         /* following is from HD audio spec */
  34         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
  35                 if (rate > 48000)
  36                         value = (channels * bits_per_sample *
  37                                         (rate / 48000)) / sdo_line;
  38                 else
  39                         value = (channels * bits_per_sample) / sdo_line;
  40
  41                 if (value >= bus->sdo_limit)
  42                         break;
  43         }
  44
  45         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
  46         return sdo_line >> 1;
  47 }
  48 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
  49
  50 /**
  51  * snd_hdac_stream_init - initialize each stream (aka device)
  52  * @bus: HD-audio core bus
  53  * @azx_dev: HD-audio core stream object to initialize
  54  * @idx: stream index number
  55  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
  56  * @tag: the tag id to assign
  57  *
  58  * Assign the starting bdl address to each stream (device) and initialize.
  59  */
  60 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
  61                           int idx, int direction, int tag)
  62 {
  63         azx_dev->bus = bus;
  64         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  65         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
  66         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
  67         azx_dev->sd_int_sta_mask = 1 << idx;
  68         azx_dev->index = idx;
  69         azx_dev->direction = direction;
  70         azx_dev->stream_tag = tag;
  71         snd_hdac_dsp_lock_init(azx_dev);
  72         list_add_tail(&azx_dev->list, &bus->stream_list);
  73 }
  74 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
  75
  76 /**
  77  * snd_hdac_stream_start - start a stream
  78  * @azx_dev: HD-audio core stream to start
  79  * @fresh_start: false = wallclock timestamp relative to period wallclock
  80  *
  81  * Start a stream, set start_wallclk and set the running flag.
  82  */
  83 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
  84 {
  85         struct hdac_bus *bus = azx_dev->bus;
  86         int stripe_ctl;
  87
  88         trace_snd_hdac_stream_start(bus, azx_dev);
  89
  90         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
  91         if (!fresh_start)
  92                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
  93
  94         /* enable SIE */
  95         snd_hdac_chip_updatel(bus, INTCTL,
  96                               1 << azx_dev->index,
  97                               1 << azx_dev->index);
  98         /* set stripe control */
  99         if (azx_dev->stripe) {
 100                 if (azx_dev->substream)
 101                         stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
 102                 else
 103                         stripe_ctl = 0;
 104                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
 105                                         stripe_ctl);
 106         }
 107         /* set DMA start and interrupt mask */
 108         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 109                                 0, SD_CTL_DMA_START | SD_INT_MASK);
 110         azx_dev->running = true;
 111 }
 112 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
 113
 114 /**
 115  * snd_hdac_stream_clear - stop a stream DMA
 116  * @azx_dev: HD-audio core stream to stop
 117  */
 118 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
 119 {
 120         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 121                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
 122         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 123         if (azx_dev->stripe)
 124                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
 125         azx_dev->running = false;
 126 }
 127 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
 128
 129 /**
 130  * snd_hdac_stream_stop - stop a stream
 131  * @azx_dev: HD-audio core stream to stop
 132  *
 133  * Stop a stream DMA and disable stream interrupt
 134  */
 135 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
 136 {
 137         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
 138
 139         snd_hdac_stream_clear(azx_dev);
 140         /* disable SIE */
 141         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
 142 }
 143 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
 144
 145 /**
 146  * snd_hdac_stream_reset - reset a stream
 147  * @azx_dev: HD-audio core stream to reset
 148  */
 149 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
 150 {
 151         unsigned char val;
 152         int timeout;
 153         int dma_run_state;
 154
 155         snd_hdac_stream_clear(azx_dev);
 156
 157         dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
 158
 159         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
 160         udelay(3);
 161         timeout = 300;
 162         do {
 163                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 164                         SD_CTL_STREAM_RESET;
 165                 if (val)
 166                         break;
 167         } while (--timeout);
 168
 169         if (azx_dev->bus->dma_stop_delay && dma_run_state)
 170                 udelay(azx_dev->bus->dma_stop_delay);
 171
 172         val &= ~SD_CTL_STREAM_RESET;
 173         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
 174         udelay(3);
 175
 176         timeout = 300;
 177         /* waiting for hardware to report that the stream is out of reset */
 178         do {
 179                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 180                         SD_CTL_STREAM_RESET;
 181                 if (!val)
 182                         break;
 183         } while (--timeout);
 184
 185         /* reset first position - may not be synced with hw at this time */
 186         if (azx_dev->posbuf)
 187                 *azx_dev->posbuf = 0;
 188 }
 189 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
 190
 191 /**
 192  * snd_hdac_stream_setup -  set up the SD for streaming
 193  * @azx_dev: HD-audio core stream to set up
 194  */
 195 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
 196 {
 197         struct hdac_bus *bus = azx_dev->bus;
 198         struct snd_pcm_runtime *runtime;
 199         unsigned int val;
 200
 201         if (azx_dev->substream)
 202                 runtime = azx_dev->substream->runtime;
 203         else
 204                 runtime = NULL;
 205         /* make sure the run bit is zero for SD */
 206         snd_hdac_stream_clear(azx_dev);
 207         /* program the stream_tag */
 208         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
 209         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
 210                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
 211         if (!bus->snoop)
 212                 val |= SD_CTL_TRAFFIC_PRIO;
 213         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
 214
 215         /* program the length of samples in cyclic buffer */
 216         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 217
 218         /* program the stream format */
 219         /* this value needs to be the same as the one programmed */
 220         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 221
 222         /* program the stream LVI (last valid index) of the BDL */
 223         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 224
 225         /* program the BDL address */
 226         /* lower BDL address */
 227         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
 228         /* upper BDL address */
 229         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
 230                                upper_32_bits(azx_dev->bdl.addr));
 231
 232         /* enable the position buffer */
 233         if (bus->use_posbuf && bus->posbuf.addr) {
 234                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
 235                         snd_hdac_chip_writel(bus, DPLBASE,
 236                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
 237         }
 238
 239         /* set the interrupt enable bits in the descriptor control register */
 240         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
 241
 242         azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
 243
 244         /* when LPIB delay correction gives a small negative value,
 245          * we ignore it; currently set the threshold statically to
 246          * 64 frames
 247          */
 248         if (runtime && runtime->period_size > 64)
 249                 azx_dev->delay_negative_threshold =
 250                         -frames_to_bytes(runtime, 64);
 251         else
 252                 azx_dev->delay_negative_threshold = 0;
 253
 254         /* wallclk has 24Mhz clock source */
 255         if (runtime)
 256                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
 257                                     runtime->rate) * 1000);
 258
 259         return 0;
 260 }
 261 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
 262
 263 /**
 264  * snd_hdac_stream_cleanup - cleanup a stream
 265  * @azx_dev: HD-audio core stream to clean up
 266  */
 267 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
 268 {
 269         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 270         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 271         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 272         azx_dev->bufsize = 0;
 273         azx_dev->period_bytes = 0;
 274         azx_dev->format_val = 0;
 275 }
 276 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
 277
 278 /**
 279  * snd_hdac_stream_assign - assign a stream for the PCM
 280  * @bus: HD-audio core bus
 281  * @substream: PCM substream to assign
 282  *
 283  * Look for an unused stream for the given PCM substream, assign it
 284  * and return the stream object.  If no stream is free, returns NULL.
 285  * The function tries to keep using the same stream object when it's used
 286  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
 287  * or matching entry is returned.  This is needed for some strange codecs.
 288  */
 289 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
 290                                            struct snd_pcm_substream *substream)
 291 {
 292         struct hdac_stream *azx_dev;
 293         struct hdac_stream *res = NULL;
 294
 295         /* make a non-zero unique key for the substream */
 296         int key = (substream->pcm->device << 16) | (substream->number << 2) |
 297                 (substream->stream + 1);
 298
 299         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 300                 if (azx_dev->direction != substream->stream)
 301                         continue;
 302                 if (azx_dev->opened)
 303                         continue;
 304                 if (azx_dev->assigned_key == key) {
 305                         res = azx_dev;
 306                         break;
 307                 }
 308                 if (!res || bus->reverse_assign)
 309                         res = azx_dev;
 310         }
 311         if (res) {
 312                 spin_lock_irq(&bus->reg_lock);
 313                 res->opened = 1;
 314                 res->running = 0;
 315                 res->assigned_key = key;
 316                 res->substream = substream;
 317                 spin_unlock_irq(&bus->reg_lock);
 318         }
 319         return res;
 320 }
 321 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
 322
 323 /**
 324  * snd_hdac_stream_release - release the assigned stream
 325  * @azx_dev: HD-audio core stream to release
 326  *
 327  * Release the stream that has been assigned by snd_hdac_stream_assign().
 328  */
 329 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
 330 {
 331         struct hdac_bus *bus = azx_dev->bus;
 332
 333         spin_lock_irq(&bus->reg_lock);
 334         azx_dev->opened = 0;
 335         azx_dev->running = 0;
 336         azx_dev->substream = NULL;
 337         spin_unlock_irq(&bus->reg_lock);
 338 }
 339 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
 340
 341 /**
 342  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
 343  * direction
 344  *
 345  * @bus: HD-audio core bus
 346  * @dir: direction for the stream to be found
 347  * @stream_tag: stream tag for stream to be found
 348  */
 349 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
 350                                         int dir, int stream_tag)
 351 {
 352         struct hdac_stream *s;
 353
 354         list_for_each_entry(s, &bus->stream_list, list) {
 355                 if (s->direction == dir && s->stream_tag == stream_tag)
 356                         return s;
 357         }
 358
 359         return NULL;
 360 }
 361 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
 362
 363 /*
 364  * set up a BDL entry
 365  */
 366 static int setup_bdle(struct hdac_bus *bus,
 367                       struct snd_dma_buffer *dmab,
 368                       struct hdac_stream *azx_dev, __le32 **bdlp,
 369                       int ofs, int size, int with_ioc)
 370 {
 371         __le32 *bdl = *bdlp;
 372
 373         while (size > 0) {
 374                 dma_addr_t addr;
 375                 int chunk;
 376
 377                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
 378                         return -EINVAL;
 379
 380                 addr = snd_sgbuf_get_addr(dmab, ofs);
 381                 /* program the address field of the BDL entry */
 382                 bdl[0] = cpu_to_le32((u32)addr);
 383                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 384                 /* program the size field of the BDL entry */
 385                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
 386                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
 387                 if (bus->align_bdle_4k) {
 388                         u32 remain = 0x1000 - (ofs & 0xfff);
 389
 390                         if (chunk > remain)
 391                                 chunk = remain;
 392                 }
 393                 bdl[2] = cpu_to_le32(chunk);
 394                 /* program the IOC to enable interrupt
 395                  * only when the whole fragment is processed
 396                  */
 397                 size -= chunk;
 398                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 399                 bdl += 4;
 400                 azx_dev->frags++;
 401                 ofs += chunk;
 402         }
 403         *bdlp = bdl;
 404         return ofs;
 405 }
 406
 407 /**
 408  * snd_hdac_stream_setup_periods - set up BDL entries
 409  * @azx_dev: HD-audio core stream to set up
 410  *
 411  * Set up the buffer descriptor table of the given stream based on the
 412  * period and buffer sizes of the assigned PCM substream.
 413  */
 414 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 415 {
 416         struct hdac_bus *bus = azx_dev->bus;
 417         struct snd_pcm_substream *substream = azx_dev->substream;
 418         struct snd_pcm_runtime *runtime = substream->runtime;
 419         __le32 *bdl;
 420         int i, ofs, periods, period_bytes;
 421         int pos_adj, pos_align;
 422
 423         /* reset BDL address */
 424         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 425         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 426
 427         period_bytes = azx_dev->period_bytes;
 428         periods = azx_dev->bufsize / period_bytes;
 429
 430         /* program the initial BDL entries */
 431         bdl = (__le32 *)azx_dev->bdl.area;
 432         ofs = 0;
 433         azx_dev->frags = 0;
 434
 435         pos_adj = bus->bdl_pos_adj;
 436         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
 437                 pos_align = pos_adj;
 438                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
 439                 if (!pos_adj)
 440                         pos_adj = pos_align;
 441                 else
 442                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
 443                                 pos_align;
 444                 pos_adj = frames_to_bytes(runtime, pos_adj);
 445                 if (pos_adj >= period_bytes) {
 446                         dev_warn(bus->dev, "Too big adjustment %d\n",
 447                                  pos_adj);
 448                         pos_adj = 0;
 449                 } else {
 450                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 451                                          azx_dev,
 452                                          &bdl, ofs, pos_adj, true);
 453                         if (ofs < 0)
 454                                 goto error;
 455                 }
 456         } else
 457                 pos_adj = 0;
 458
 459         for (i = 0; i < periods; i++) {
 460                 if (i == periods - 1 && pos_adj)
 461                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 462                                          azx_dev, &bdl, ofs,
 463                                          period_bytes - pos_adj, 0);
 464                 else
 465                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 466                                          azx_dev, &bdl, ofs,
 467                                          period_bytes,
 468                                          !azx_dev->no_period_wakeup);
 469                 if (ofs < 0)
 470                         goto error;
 471         }
 472         return 0;
 473
 474  error:
 475         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
 476                 azx_dev->bufsize, period_bytes);
 477         return -EINVAL;
 478 }
 479 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
 480
 481 /**
 482  * snd_hdac_stream_set_params - set stream parameters
 483  * @azx_dev: HD-audio core stream for which parameters are to be set
 484  * @format_val: format value parameter
 485  *
 486  * Setup the HD-audio core stream parameters from substream of the stream
 487  * and passed format value
 488  */
 489 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
 490                                  unsigned int format_val)
 491 {
 492
 493         unsigned int bufsize, period_bytes;
 494         struct snd_pcm_substream *substream = azx_dev->substream;
 495         struct snd_pcm_runtime *runtime;
 496         int err;
 497
 498         if (!substream)
 499                 return -EINVAL;
 500         runtime = substream->runtime;
 501         bufsize = snd_pcm_lib_buffer_bytes(substream);
 502         period_bytes = snd_pcm_lib_period_bytes(substream);
 503
 504         if (bufsize != azx_dev->bufsize ||
 505             period_bytes != azx_dev->period_bytes ||
 506             format_val != azx_dev->format_val ||
 507             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
 508                 azx_dev->bufsize = bufsize;
 509                 azx_dev->period_bytes = period_bytes;
 510                 azx_dev->format_val = format_val;
 511                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
 512                 err = snd_hdac_stream_setup_periods(azx_dev);
 513                 if (err < 0)
 514                         return err;
 515         }
 516         return 0;
 517 }
 518 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
 519
 520 static u64 azx_cc_read(const struct cyclecounter *cc)
 521 {
 522         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
 523
 524         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
 525 }
 526
 527 static void azx_timecounter_init(struct hdac_stream *azx_dev,
 528                                  bool force, u64 last)
 529 {
 530         struct timecounter *tc = &azx_dev->tc;
 531         struct cyclecounter *cc = &azx_dev->cc;
 532         u64 nsec;
 533
 534         cc->read = azx_cc_read;
 535         cc->mask = CLOCKSOURCE_MASK(32);
 536
 537         /*
 538          * Converting from 24 MHz to ns means applying a 125/3 factor.
 539          * To avoid any saturation issues in intermediate operations,
 540          * the 125 factor is applied first. The division is applied
 541          * last after reading the timecounter value.
 542          * Applying the 1/3 factor as part of the multiplication
 543          * requires at least 20 bits for a decent precision, however
 544          * overflows occur after about 4 hours or less, not a option.
 545          */
 546
 547         cc->mult = 125; /* saturation after 195 years */
 548         cc->shift = 0;
 549
 550         nsec = 0; /* audio time is elapsed time since trigger */
 551         timecounter_init(tc, cc, nsec);
 552         if (force) {
 553                 /*
 554                  * force timecounter to use predefined value,
 555                  * used for synchronized starts
 556                  */
 557                 tc->cycle_last = last;
 558         }
 559 }
 560
 561 /**
 562  * snd_hdac_stream_timecounter_init - initialize time counter
 563  * @azx_dev: HD-audio core stream (master stream)
 564  * @streams: bit flags of streams to set up
 565  *
 566  * Initializes the time counter of streams marked by the bit flags (each
 567  * bit corresponds to the stream index).
 568  * The trigger timestamp of PCM substream assigned to the given stream is
 569  * updated accordingly, too.
 570  */
 571 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
 572                                       unsigned int streams)
 573 {
 574         struct hdac_bus *bus = azx_dev->bus;
 575         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
 576         struct hdac_stream *s;
 577         bool inited = false;
 578         u64 cycle_last = 0;
 579         int i = 0;
 580
 581         list_for_each_entry(s, &bus->stream_list, list) {
 582                 if (streams & (1 << i)) {
 583                         azx_timecounter_init(s, inited, cycle_last);
 584                         if (!inited) {
 585                                 inited = true;
 586                                 cycle_last = s->tc.cycle_last;
 587                         }
 588                 }
 589                 i++;
 590         }
 591
 592         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
 593         runtime->trigger_tstamp_latched = true;
 594 }
 595 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
 596
 597 /**
 598  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
 599  * @azx_dev: HD-audio core stream (master stream)
 600  * @set: true = set, false = clear
 601  * @streams: bit flags of streams to sync
 602  * @reg: the stream sync register address
 603  */
 604 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
 605                                   unsigned int streams, unsigned int reg)
 606 {
 607         struct hdac_bus *bus = azx_dev->bus;
 608         unsigned int val;
 609
 610         if (!reg)
 611                 reg = AZX_REG_SSYNC;
 612         val = _snd_hdac_chip_readl(bus, reg);
 613         if (set)
 614                 val |= streams;
 615         else
 616                 val &= ~streams;
 617         _snd_hdac_chip_writel(bus, reg, val);
 618 }
 619 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
 620
 621 /**
 622  * snd_hdac_stream_sync - sync with start/strop trigger operation
 623  * @azx_dev: HD-audio core stream (master stream)
 624  * @start: true = start, false = stop
 625  * @streams: bit flags of streams to sync
 626  *
 627  * For @start = true, wait until all FIFOs get ready.
 628  * For @start = false, wait until all RUN bits are cleared.
 629  */
 630 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
 631                           unsigned int streams)
 632 {
 633         struct hdac_bus *bus = azx_dev->bus;
 634         int i, nwait, timeout;
 635         struct hdac_stream *s;
 636
 637         for (timeout = 5000; timeout; timeout--) {
 638                 nwait = 0;
 639                 i = 0;
 640                 list_for_each_entry(s, &bus->stream_list, list) {
 641                         if (!(streams & (1 << i++)))
 642                                 continue;
 643
 644                         if (start) {
 645                                 /* check FIFO gets ready */
 646                                 if (!(snd_hdac_stream_readb(s, SD_STS) &
 647                                       SD_STS_FIFO_READY))
 648                                         nwait++;
 649                         } else {
 650                                 /* check RUN bit is cleared */
 651                                 if (snd_hdac_stream_readb(s, SD_CTL) &
 652                                     SD_CTL_DMA_START) {
 653                                         nwait++;
 654                                         /*
 655                                          * Perform stream reset if DMA RUN
 656                                          * bit not cleared within given timeout
 657                                          */
 658                                         if (timeout == 1)
 659                                                 snd_hdac_stream_reset(s);
 660                                 }
 661                         }
 662                 }
 663                 if (!nwait)
 664                         break;
 665                 cpu_relax();
 666         }
 667 }
 668 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
 669
 670 #ifdef CONFIG_SND_HDA_DSP_LOADER
 671 /**
 672  * snd_hdac_dsp_prepare - prepare for DSP loading
 673  * @azx_dev: HD-audio core stream used for DSP loading
 674  * @format: HD-audio stream format
 675  * @byte_size: data chunk byte size
 676  * @bufp: allocated buffer
 677  *
 678  * Allocate the buffer for the given size and set up the given stream for
 679  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
 680  */
 681 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
 682                          unsigned int byte_size, struct snd_dma_buffer *bufp)
 683 {
 684         struct hdac_bus *bus = azx_dev->bus;
 685         __le32 *bdl;
 686         int err;
 687
 688         snd_hdac_dsp_lock(azx_dev);
 689         spin_lock_irq(&bus->reg_lock);
 690         if (azx_dev->running || azx_dev->locked) {
 691                 spin_unlock_irq(&bus->reg_lock);
 692                 err = -EBUSY;
 693                 goto unlock;
 694         }
 695         azx_dev->locked = true;
 696         spin_unlock_irq(&bus->reg_lock);
 697
 698         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
 699                                   byte_size, bufp);
 700         if (err < 0)
 701                 goto err_alloc;
 702
 703         azx_dev->substream = NULL;
 704         azx_dev->bufsize = byte_size;
 705         azx_dev->period_bytes = byte_size;
 706         azx_dev->format_val = format;
 707
 708         snd_hdac_stream_reset(azx_dev);
 709
 710         /* reset BDL address */
 711         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 712         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 713
 714         azx_dev->frags = 0;
 715         bdl = (__le32 *)azx_dev->bdl.area;
 716         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
 717         if (err < 0)
 718                 goto error;
 719
 720         snd_hdac_stream_setup(azx_dev);
 721         snd_hdac_dsp_unlock(azx_dev);
 722         return azx_dev->stream_tag;
 723
 724  error:
 725         snd_dma_free_pages(bufp);
 726  err_alloc:
 727         spin_lock_irq(&bus->reg_lock);
 728         azx_dev->locked = false;
 729         spin_unlock_irq(&bus->reg_lock);
 730  unlock:
 731         snd_hdac_dsp_unlock(azx_dev);
 732         return err;
 733 }
 734 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
 735
 736 /**
 737  * snd_hdac_dsp_trigger - start / stop DSP loading
 738  * @azx_dev: HD-audio core stream used for DSP loading
 739  * @start: trigger start or stop
 740  */
 741 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
 742 {
 743         if (start)
 744                 snd_hdac_stream_start(azx_dev, true);
 745         else
 746                 snd_hdac_stream_stop(azx_dev);
 747 }
 748 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
 749
 750 /**
 751  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
 752  * @azx_dev: HD-audio core stream used for DSP loading
 753  * @dmab: buffer used by DSP loading
 754  */
 755 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
 756                           struct snd_dma_buffer *dmab)
 757 {
 758         struct hdac_bus *bus = azx_dev->bus;
 759
 760         if (!dmab->area || !azx_dev->locked)
 761                 return;
 762
 763         snd_hdac_dsp_lock(azx_dev);
 764         /* reset BDL address */
 765         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 766         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 767         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 768         azx_dev->bufsize = 0;
 769         azx_dev->period_bytes = 0;
 770         azx_dev->format_val = 0;
 771
 772         snd_dma_free_pages(dmab);
 773         dmab->area = NULL;
 774
 775         spin_lock_irq(&bus->reg_lock);
 776         azx_dev->locked = false;
 777         spin_unlock_irq(&bus->reg_lock);
 778         snd_hdac_dsp_unlock(azx_dev);
 779 }
 780 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
 781 #endif /* CONFIG_SND_HDA_DSP_LOADER */