1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio controller helpers
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <sound/core.h>
10 #include <sound/hdaudio.h>
11 #include <sound/hda_register.h>
13 /* clear CORB read pointer properly */
14 static void azx_clear_corbrp(struct hdac_bus *bus)
18 for (timeout = 1000; timeout > 0; timeout--) {
19 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
24 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
25 snd_hdac_chip_readw(bus, CORBRP));
27 snd_hdac_chip_writew(bus, CORBRP, 0);
28 for (timeout = 1000; timeout > 0; timeout--) {
29 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
34 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
35 snd_hdac_chip_readw(bus, CORBRP));
39 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
40 * @bus: HD-audio core bus
42 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
44 WARN_ON_ONCE(!bus->rb.area);
46 spin_lock_irq(&bus->reg_lock);
48 bus->corb.addr = bus->rb.addr;
49 bus->corb.buf = (__le32 *)bus->rb.area;
50 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
51 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
53 /* set the corb size to 256 entries (ULI requires explicitly) */
54 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
55 /* set the corb write pointer to 0 */
56 snd_hdac_chip_writew(bus, CORBWP, 0);
58 /* reset the corb hw read pointer */
59 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
60 if (!bus->corbrp_self_clear)
61 azx_clear_corbrp(bus);
64 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
67 bus->rirb.addr = bus->rb.addr + 2048;
68 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
69 bus->rirb.wp = bus->rirb.rp = 0;
70 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
71 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
72 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
74 /* set the rirb size to 256 entries (ULI requires explicitly) */
75 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
76 /* reset the rirb hw write pointer */
77 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
78 /* set N=1, get RIRB response interrupt for new entry */
79 snd_hdac_chip_writew(bus, RINTCNT, 1);
80 /* enable rirb dma and response irq */
81 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
82 /* Accept unsolicited responses */
83 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
84 spin_unlock_irq(&bus->reg_lock);
86 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
88 /* wait for cmd dmas till they are stopped */
89 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
91 unsigned long timeout;
93 timeout = jiffies + msecs_to_jiffies(100);
94 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
95 && time_before(jiffies, timeout))
98 timeout = jiffies + msecs_to_jiffies(100);
99 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
100 && time_before(jiffies, timeout))
105 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
106 * @bus: HD-audio core bus
108 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
110 spin_lock_irq(&bus->reg_lock);
111 /* disable ringbuffer DMAs */
112 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
113 snd_hdac_chip_writeb(bus, CORBCTL, 0);
114 spin_unlock_irq(&bus->reg_lock);
116 hdac_wait_for_cmd_dmas(bus);
118 spin_lock_irq(&bus->reg_lock);
119 /* disable unsolicited responses */
120 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
121 spin_unlock_irq(&bus->reg_lock);
123 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
125 static unsigned int azx_command_addr(u32 cmd)
127 unsigned int addr = cmd >> 28;
129 if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
135 * snd_hdac_bus_send_cmd - send a command verb via CORB
136 * @bus: HD-audio core bus
137 * @val: encoded verb value to send
139 * Returns zero for success or a negative error code.
141 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
143 unsigned int addr = azx_command_addr(val);
146 spin_lock_irq(&bus->reg_lock);
148 bus->last_cmd[azx_command_addr(val)] = val;
150 /* add command to corb */
151 wp = snd_hdac_chip_readw(bus, CORBWP);
153 /* something wrong, controller likely turned to D3 */
154 spin_unlock_irq(&bus->reg_lock);
158 wp %= AZX_MAX_CORB_ENTRIES;
160 rp = snd_hdac_chip_readw(bus, CORBRP);
162 /* oops, it's full */
163 spin_unlock_irq(&bus->reg_lock);
167 bus->rirb.cmds[addr]++;
168 bus->corb.buf[wp] = cpu_to_le32(val);
169 snd_hdac_chip_writew(bus, CORBWP, wp);
171 spin_unlock_irq(&bus->reg_lock);
175 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
177 #define AZX_RIRB_EX_UNSOL_EV (1<<4)
180 * snd_hdac_bus_update_rirb - retrieve RIRB entries
181 * @bus: HD-audio core bus
183 * Usually called from interrupt handler.
184 * The caller needs bus->reg_lock spinlock before calling this.
186 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
192 wp = snd_hdac_chip_readw(bus, RIRBWP);
194 /* something wrong, controller likely turned to D3 */
198 if (wp == bus->rirb.wp)
202 while (bus->rirb.rp != wp) {
204 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
206 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
207 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
208 res = le32_to_cpu(bus->rirb.buf[rp]);
210 if (addr >= HDA_MAX_CODECS) {
212 "spurious response %#x:%#x, rp = %d, wp = %d",
213 res, res_ex, bus->rirb.rp, wp);
215 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
216 snd_hdac_bus_queue_event(bus, res, res_ex);
217 else if (bus->rirb.cmds[addr]) {
218 bus->rirb.res[addr] = res;
219 bus->rirb.cmds[addr]--;
220 if (!bus->rirb.cmds[addr] &&
221 waitqueue_active(&bus->rirb_wq))
222 wake_up(&bus->rirb_wq);
224 dev_err_ratelimited(bus->dev,
225 "spurious response %#x:%#x, last cmd=%#08x\n",
226 res, res_ex, bus->last_cmd[addr]);
230 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
233 * snd_hdac_bus_get_response - receive a response via RIRB
234 * @bus: HD-audio core bus
235 * @addr: codec address
236 * @res: pointer to store the value, NULL when not needed
238 * Returns zero if a value is read, or a negative error code.
240 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
243 unsigned long timeout;
244 unsigned long loopcounter;
245 wait_queue_entry_t wait;
248 init_wait_entry(&wait, 0);
249 timeout = jiffies + msecs_to_jiffies(1000);
251 for (loopcounter = 0;; loopcounter++) {
252 spin_lock_irq(&bus->reg_lock);
253 if (!bus->polling_mode)
254 prepare_to_wait(&bus->rirb_wq, &wait,
255 TASK_UNINTERRUPTIBLE);
256 if (bus->polling_mode)
257 snd_hdac_bus_update_rirb(bus);
258 if (!bus->rirb.cmds[addr]) {
260 *res = bus->rirb.res[addr]; /* the last value */
261 if (!bus->polling_mode)
262 finish_wait(&bus->rirb_wq, &wait);
263 spin_unlock_irq(&bus->reg_lock);
266 spin_unlock_irq(&bus->reg_lock);
267 if (time_after(jiffies, timeout))
269 #define LOOP_COUNT_MAX 3000
270 if (!bus->polling_mode) {
271 schedule_timeout(msecs_to_jiffies(2));
272 } else if (bus->needs_damn_long_delay ||
273 loopcounter > LOOP_COUNT_MAX) {
274 if (loopcounter > LOOP_COUNT_MAX && !warned) {
275 dev_dbg_ratelimited(bus->dev,
276 "too slow response, last cmd=%#08x\n",
277 bus->last_cmd[addr]);
280 msleep(2); /* temporary workaround */
287 if (!bus->polling_mode)
288 finish_wait(&bus->rirb_wq, &wait);
292 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
294 #define HDAC_MAX_CAPS 10
296 * snd_hdac_bus_parse_capabilities - parse capability structure
297 * @bus: the pointer to bus object
299 * Returns 0 if successful, or a negative error code.
301 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
303 unsigned int cur_cap;
305 unsigned int counter = 0;
307 offset = snd_hdac_chip_readw(bus, LLCH);
309 /* Lets walk the linked capabilities list */
311 cur_cap = _snd_hdac_chip_readl(bus, offset);
313 dev_dbg(bus->dev, "Capability version: 0x%x\n",
314 (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
316 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
317 (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
320 dev_dbg(bus->dev, "Invalid capability reg read\n");
324 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
326 dev_dbg(bus->dev, "Found ML capability\n");
327 bus->mlcap = bus->remap_addr + offset;
331 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
332 bus->gtscap = bus->remap_addr + offset;
336 /* PP capability found, the Audio DSP is present */
337 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
338 bus->ppcap = bus->remap_addr + offset;
342 /* SPIB capability found, handler function */
343 dev_dbg(bus->dev, "Found SPB capability\n");
344 bus->spbcap = bus->remap_addr + offset;
347 case AZX_DRSM_CAP_ID:
348 /* DMA resume capability found, handler function */
349 dev_dbg(bus->dev, "Found DRSM capability\n");
350 bus->drsmcap = bus->remap_addr + offset;
354 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
361 if (counter > HDAC_MAX_CAPS) {
362 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
366 /* read the offset of next capability */
367 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
373 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
380 * snd_hdac_bus_enter_link_reset - enter link reset
381 * @bus: HD-audio core bus
383 * Enter to the link reset state.
385 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
387 unsigned long timeout;
389 /* reset controller */
390 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
392 timeout = jiffies + msecs_to_jiffies(100);
393 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
394 time_before(jiffies, timeout))
395 usleep_range(500, 1000);
397 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
400 * snd_hdac_bus_exit_link_reset - exit link reset
401 * @bus: HD-audio core bus
403 * Exit from the link reset state.
405 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
407 unsigned long timeout;
409 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
411 timeout = jiffies + msecs_to_jiffies(100);
412 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
413 usleep_range(500, 1000);
415 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
417 /* reset codec link */
418 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
424 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
426 /* reset controller */
427 snd_hdac_bus_enter_link_reset(bus);
429 /* delay for >= 100us for codec PLL to settle per spec
430 * Rev 0.9 section 5.5.1
432 usleep_range(500, 1000);
434 /* Bring controller out of reset */
435 snd_hdac_bus_exit_link_reset(bus);
437 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
438 usleep_range(1000, 1200);
441 /* check to see if controller is ready */
442 if (!snd_hdac_chip_readb(bus, GCTL)) {
443 dev_dbg(bus->dev, "controller not ready!\n");
448 if (!bus->codec_mask) {
449 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
450 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
455 EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link);
457 /* enable interrupts */
458 static void azx_int_enable(struct hdac_bus *bus)
460 /* enable controller CIE and GIE */
461 snd_hdac_chip_updatel(bus, INTCTL,
462 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN,
463 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
466 /* disable interrupts */
467 static void azx_int_disable(struct hdac_bus *bus)
469 struct hdac_stream *azx_dev;
471 /* disable interrupts in stream descriptor */
472 list_for_each_entry(azx_dev, &bus->stream_list, list)
473 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
475 /* disable SIE for all streams */
476 snd_hdac_chip_writeb(bus, INTCTL, 0);
478 /* disable controller CIE and GIE */
479 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
482 /* clear interrupts */
483 static void azx_int_clear(struct hdac_bus *bus)
485 struct hdac_stream *azx_dev;
487 /* clear stream status */
488 list_for_each_entry(azx_dev, &bus->stream_list, list)
489 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
492 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
494 /* clear rirb status */
495 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
497 /* clear int status */
498 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
502 * snd_hdac_bus_init_chip - reset and start the controller registers
503 * @bus: HD-audio core bus
504 * @full_reset: Do full reset
506 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
511 /* reset controller */
512 snd_hdac_bus_reset_link(bus, full_reset);
514 /* clear interrupts */
517 /* initialize the codec command I/O */
518 snd_hdac_bus_init_cmd_io(bus);
520 /* enable interrupts after CORB/RIRB buffers are initialized above */
523 /* program the position buffer */
524 if (bus->use_posbuf && bus->posbuf.addr) {
525 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
526 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
529 bus->chip_init = true;
532 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
535 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
536 * @bus: HD-audio core bus
538 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
543 /* disable interrupts */
544 azx_int_disable(bus);
547 /* disable CORB/RIRB */
548 snd_hdac_bus_stop_cmd_io(bus);
550 /* disable position buffer */
551 if (bus->posbuf.addr) {
552 snd_hdac_chip_writel(bus, DPLBASE, 0);
553 snd_hdac_chip_writel(bus, DPUBASE, 0);
556 bus->chip_init = false;
558 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
561 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
562 * @bus: HD-audio core bus
563 * @status: INTSTS register value
564 * @ack: callback to be called for woken streams
566 * Returns the bits of handled streams, or zero if no stream is handled.
568 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
569 void (*ack)(struct hdac_bus *,
570 struct hdac_stream *))
572 struct hdac_stream *azx_dev;
576 list_for_each_entry(azx_dev, &bus->stream_list, list) {
577 if (status & azx_dev->sd_int_sta_mask) {
578 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
579 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
580 handled |= 1 << azx_dev->index;
581 if (!azx_dev->substream || !azx_dev->running ||
582 !(sd_status & SD_INT_COMPLETE))
590 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
593 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
594 * @bus: HD-audio core bus
596 * Call this after assigning the all streams.
597 * Returns zero for success, or a negative error code.
599 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
601 struct hdac_stream *s;
603 int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
606 list_for_each_entry(s, &bus->stream_list, list) {
607 /* allocate memory for the BDL for each stream */
608 err = snd_dma_alloc_pages(dma_type, bus->dev,
615 if (WARN_ON(!num_streams))
617 /* allocate memory for the position buffer */
618 err = snd_dma_alloc_pages(dma_type, bus->dev,
619 num_streams * 8, &bus->posbuf);
622 list_for_each_entry(s, &bus->stream_list, list)
623 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
625 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
626 return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
628 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
631 * snd_hdac_bus_free_stream_pages - release BDL and other buffers
632 * @bus: HD-audio core bus
634 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
636 struct hdac_stream *s;
638 list_for_each_entry(s, &bus->stream_list, list) {
640 snd_dma_free_pages(&s->bdl);
644 snd_dma_free_pages(&bus->rb);
645 if (bus->posbuf.area)
646 snd_dma_free_pages(&bus->posbuf);
648 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);