sound/firewire/motu/motu-protocol-v3.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * motu-protocol-v3.c - a part of driver for MOTU FireWire series
   4  *
   5  * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
   6  */
   7
   8 #include <linux/delay.h>
   9 #include "motu.h"
  10
  11 #define V3_CLOCK_STATUS_OFFSET          0x0b14
  12 #define  V3_FETCH_PCM_FRAMES            0x02000000
  13 #define  V3_CLOCK_RATE_MASK             0x0000ff00
  14 #define  V3_CLOCK_RATE_SHIFT            8
  15 #define  V3_CLOCK_SOURCE_MASK           0x000000ff
  16
  17 #define V3_OPT_IFACE_MODE_OFFSET        0x0c94
  18 #define  V3_ENABLE_OPT_IN_IFACE_A       0x00000001
  19 #define  V3_ENABLE_OPT_IN_IFACE_B       0x00000002
  20 #define  V3_ENABLE_OPT_OUT_IFACE_A      0x00000100
  21 #define  V3_ENABLE_OPT_OUT_IFACE_B      0x00000200
  22 #define  V3_NO_ADAT_OPT_IN_IFACE_A      0x00010000
  23 #define  V3_NO_ADAT_OPT_IN_IFACE_B      0x00100000
  24 #define  V3_NO_ADAT_OPT_OUT_IFACE_A     0x00040000
  25 #define  V3_NO_ADAT_OPT_OUT_IFACE_B     0x00400000
  26
  27 #define V3_MSG_FLAG_CLK_CHANGED         0x00000002
  28 #define V3_CLK_WAIT_MSEC                4000
  29
  30 int snd_motu_protocol_v3_get_clock_rate(struct snd_motu *motu,
  31                                         unsigned int *rate)
  32 {
  33         __be32 reg;
  34         u32 data;
  35         int err;
  36
  37         err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, &reg,
  38                                         sizeof(reg));
  39         if (err < 0)
  40                 return err;
  41         data = be32_to_cpu(reg);
  42
  43         data = (data & V3_CLOCK_RATE_MASK) >> V3_CLOCK_RATE_SHIFT;
  44         if (data >= ARRAY_SIZE(snd_motu_clock_rates))
  45                 return -EIO;
  46
  47         *rate = snd_motu_clock_rates[data];
  48
  49         return 0;
  50 }
  51
  52 int snd_motu_protocol_v3_set_clock_rate(struct snd_motu *motu,
  53                                         unsigned int rate)
  54 {
  55         __be32 reg;
  56         u32 data;
  57         bool need_to_wait;
  58         int i, err;
  59
  60         for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
  61                 if (snd_motu_clock_rates[i] == rate)
  62                         break;
  63         }
  64         if (i == ARRAY_SIZE(snd_motu_clock_rates))
  65                 return -EINVAL;
  66
  67         err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, &reg,
  68                                         sizeof(reg));
  69         if (err < 0)
  70                 return err;
  71         data = be32_to_cpu(reg);
  72
  73         data &= ~(V3_CLOCK_RATE_MASK | V3_FETCH_PCM_FRAMES);
  74         data |= i << V3_CLOCK_RATE_SHIFT;
  75
  76         need_to_wait = data != be32_to_cpu(reg);
  77
  78         reg = cpu_to_be32(data);
  79         err = snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, &reg,
  80                                          sizeof(reg));
  81         if (err < 0)
  82                 return err;
  83
  84         if (need_to_wait) {
  85                 int result;
  86
  87                 motu->msg = 0;
  88                 result = wait_event_interruptible_timeout(motu->hwdep_wait,
  89                                         motu->msg & V3_MSG_FLAG_CLK_CHANGED,
  90                                         msecs_to_jiffies(V3_CLK_WAIT_MSEC));
  91                 if (result < 0)
  92                         return result;
  93                 if (result == 0)
  94                         return -ETIMEDOUT;
  95         }
  96
  97         return 0;
  98 }
  99
 100 int snd_motu_protocol_v3_get_clock_source(struct snd_motu *motu,
 101                                           enum snd_motu_clock_source *src)
 102 {
 103         __be32 reg;
 104         u32 data;
 105         int err;
 106
 107         err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, &reg,
 108                                         sizeof(reg));
 109         if (err < 0)
 110                 return err;
 111         data = be32_to_cpu(reg) & V3_CLOCK_SOURCE_MASK;
 112
 113         switch (data) {
 114         case 0x00:
 115                 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
 116                 break;
 117         case 0x01:
 118                 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
 119                 break;
 120         case 0x02:
 121                 *src = SND_MOTU_CLOCK_SOURCE_SPH;
 122                 break;
 123         case 0x10:
 124                 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
 125                 break;
 126         case 0x18:
 127         case 0x19:
 128         {
 129                 __be32 reg;
 130                 u32 options;
 131
 132                 err = snd_motu_transaction_read(motu,
 133                                 V3_OPT_IFACE_MODE_OFFSET, &reg, sizeof(reg));
 134                 if (err < 0)
 135                         return err;
 136                 options = be32_to_cpu(reg);
 137
 138                 if (data == 0x18) {
 139                         if (options & V3_NO_ADAT_OPT_IN_IFACE_A)
 140                                 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_A;
 141                         else
 142                                 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_A;
 143                 } else {
 144                         if (options & V3_NO_ADAT_OPT_IN_IFACE_B)
 145                                 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT_B;
 146                         else
 147                                 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT_B;
 148                 }
 149                 break;
 150         }
 151         default:
 152                 *src = SND_MOTU_CLOCK_SOURCE_UNKNOWN;
 153                 break;
 154         }
 155
 156         return 0;
 157 }
 158
 159 int snd_motu_protocol_v3_switch_fetching_mode(struct snd_motu *motu,
 160                                               bool enable)
 161 {
 162         __be32 reg;
 163         u32 data;
 164         int err;
 165
 166         err = snd_motu_transaction_read(motu, V3_CLOCK_STATUS_OFFSET, &reg,
 167                                         sizeof(reg));
 168         if (err < 0)
 169                 return 0;
 170         data = be32_to_cpu(reg);
 171
 172         if (enable)
 173                 data |= V3_FETCH_PCM_FRAMES;
 174         else
 175                 data &= ~V3_FETCH_PCM_FRAMES;
 176
 177         reg = cpu_to_be32(data);
 178         return snd_motu_transaction_write(motu, V3_CLOCK_STATUS_OFFSET, &reg,
 179                                           sizeof(reg));
 180 }
 181
 182 static int detect_packet_formats_828mk3(struct snd_motu *motu, u32 data)
 183 {
 184         if (data & V3_ENABLE_OPT_IN_IFACE_A) {
 185                 if (data & V3_NO_ADAT_OPT_IN_IFACE_A) {
 186                         motu->tx_packet_formats.pcm_chunks[0] += 4;
 187                         motu->tx_packet_formats.pcm_chunks[1] += 4;
 188                 } else {
 189                         motu->tx_packet_formats.pcm_chunks[0] += 8;
 190                         motu->tx_packet_formats.pcm_chunks[1] += 4;
 191                 }
 192         }
 193
 194         if (data & V3_ENABLE_OPT_IN_IFACE_B) {
 195                 if (data & V3_NO_ADAT_OPT_IN_IFACE_B) {
 196                         motu->tx_packet_formats.pcm_chunks[0] += 4;
 197                         motu->tx_packet_formats.pcm_chunks[1] += 4;
 198                 } else {
 199                         motu->tx_packet_formats.pcm_chunks[0] += 8;
 200                         motu->tx_packet_formats.pcm_chunks[1] += 4;
 201                 }
 202         }
 203
 204         if (data & V3_ENABLE_OPT_OUT_IFACE_A) {
 205                 if (data & V3_NO_ADAT_OPT_OUT_IFACE_A) {
 206                         motu->rx_packet_formats.pcm_chunks[0] += 4;
 207                         motu->rx_packet_formats.pcm_chunks[1] += 4;
 208                 } else {
 209                         motu->rx_packet_formats.pcm_chunks[0] += 8;
 210                         motu->rx_packet_formats.pcm_chunks[1] += 4;
 211                 }
 212         }
 213
 214         if (data & V3_ENABLE_OPT_OUT_IFACE_B) {
 215                 if (data & V3_NO_ADAT_OPT_OUT_IFACE_B) {
 216                         motu->rx_packet_formats.pcm_chunks[0] += 4;
 217                         motu->rx_packet_formats.pcm_chunks[1] += 4;
 218                 } else {
 219                         motu->rx_packet_formats.pcm_chunks[0] += 8;
 220                         motu->rx_packet_formats.pcm_chunks[1] += 4;
 221                 }
 222         }
 223
 224         return 0;
 225 }
 226
 227 int snd_motu_protocol_v3_cache_packet_formats(struct snd_motu *motu)
 228 {
 229         __be32 reg;
 230         u32 data;
 231         int err;
 232
 233         motu->tx_packet_formats.pcm_byte_offset = 10;
 234         motu->rx_packet_formats.pcm_byte_offset = 10;
 235
 236         motu->tx_packet_formats.msg_chunks = 2;
 237         motu->rx_packet_formats.msg_chunks = 2;
 238
 239         err = snd_motu_transaction_read(motu, V3_OPT_IFACE_MODE_OFFSET, &reg,
 240                                         sizeof(reg));
 241         if (err < 0)
 242                 return err;
 243         data = be32_to_cpu(reg);
 244
 245         memcpy(motu->tx_packet_formats.pcm_chunks,
 246                motu->spec->tx_fixed_pcm_chunks,
 247                sizeof(motu->tx_packet_formats.pcm_chunks));
 248         memcpy(motu->rx_packet_formats.pcm_chunks,
 249                motu->spec->rx_fixed_pcm_chunks,
 250                sizeof(motu->rx_packet_formats.pcm_chunks));
 251
 252         if (motu->spec == &snd_motu_spec_828mk3_fw || motu->spec == &snd_motu_spec_828mk3_hybrid)
 253                 return detect_packet_formats_828mk3(motu, data);
 254         else
 255                 return 0;
 256 }
 257
 258
 259 const struct snd_motu_spec snd_motu_spec_828mk3_fw = {
 260         .name = "828mk3",
 261         .protocol_version = SND_MOTU_PROTOCOL_V3,
 262         .flags = SND_MOTU_SPEC_RX_MIDI_3RD_Q |
 263                  SND_MOTU_SPEC_TX_MIDI_3RD_Q,
 264         .tx_fixed_pcm_chunks = {18, 18, 14},
 265         .rx_fixed_pcm_chunks = {14, 14, 10},
 266 };
 267
 268 const struct snd_motu_spec snd_motu_spec_828mk3_hybrid = {
 269         .name = "828mk3",
 270         .protocol_version = SND_MOTU_PROTOCOL_V3,
 271         .flags = SND_MOTU_SPEC_RX_MIDI_3RD_Q |
 272                  SND_MOTU_SPEC_TX_MIDI_3RD_Q,
 273         .tx_fixed_pcm_chunks = {18, 18, 14},
 274         .rx_fixed_pcm_chunks = {14, 14, 14},    // Additional 4 dummy chunks at higher rate.
 275 };
 276
 277 const struct snd_motu_spec snd_motu_spec_ultralite_mk3 = {
 278         .name = "UltraLiteMk3",
 279         .protocol_version = SND_MOTU_PROTOCOL_V3,
 280         .flags = SND_MOTU_SPEC_RX_MIDI_3RD_Q |
 281                  SND_MOTU_SPEC_TX_MIDI_3RD_Q,
 282         .tx_fixed_pcm_chunks = {18, 14, 10},
 283         .rx_fixed_pcm_chunks = {14, 14, 14},
 284 };
 285
 286 const struct snd_motu_spec snd_motu_spec_audio_express = {
 287         .name = "AudioExpress",
 288         .protocol_version = SND_MOTU_PROTOCOL_V3,
 289         .flags = SND_MOTU_SPEC_RX_MIDI_2ND_Q |
 290                  SND_MOTU_SPEC_TX_MIDI_3RD_Q,
 291         .tx_fixed_pcm_chunks = {10, 10, 0},
 292         .rx_fixed_pcm_chunks = {10, 10, 0},
 293 };
 294
 295 const struct snd_motu_spec snd_motu_spec_4pre = {
 296         .name = "4pre",
 297         .protocol_version = SND_MOTU_PROTOCOL_V3,
 298         .tx_fixed_pcm_chunks = {10, 10, 0},
 299         .rx_fixed_pcm_chunks = {10, 10, 0},
 300 };