sound/firewire/motu/motu-protocol-v1.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 // motu-protocol-v1.c - a part of driver for MOTU FireWire series
   4 //
   5 // Copyright (c) 2021 Takashi Sakamoto <o-takashi@sakamocchi.jp>
   6 //
   7 // Licensed under the terms of the GNU General Public License, version 2.
   8
   9 #include "motu.h"
  10
  11 #include <linux/delay.h>
  12
  13 // Status register for MOTU 828 (0x'ffff'f000'0b00).
  14 //
  15 // 0xffff0000: ISOC_COMM_CONTROL_MASK in motu-stream.c.
  16 // 0x00008000: mode of optical input interface.
  17 //   0x00008000: for S/PDIF signal.
  18 //   0x00000000: disabled or for ADAT signal.
  19 // 0x00004000: mode of optical output interface.
  20 //   0x00004000: for S/PDIF signal.
  21 //   0x00000000: disabled or for ADAT signal.
  22 // 0x00003f40: monitor input mode.
  23 //   0x00000800: analog-1/2
  24 //   0x00001a00: analog-3/4
  25 //   0x00002c00: analog-5/6
  26 //   0x00003e00: analog-7/8
  27 //   0x00000000: analog-1
  28 //   0x00000900: analog-2
  29 //   0x00001200: analog-3
  30 //   0x00001b00: analog-4
  31 //   0x00002400: analog-5
  32 //   0x00002d00: analog-6
  33 //   0x00003600: analog-7
  34 //   0x00003f00: analog-8
  35 //   0x00000040: disabled
  36 // 0x00000004: rate of sampling clock.
  37 //   0x00000004: 48.0 kHz
  38 //   0x00000000: 44.1 kHz
  39 // 0x00000023: source of sampling clock.
  40 //   0x00000002: S/PDIF on optical/coaxial interface.
  41 //   0x00000021: ADAT on optical interface
  42 //   0x00000001: ADAT on Dsub 9pin
  43 //   0x00000000: internal or SMPTE
  44
  45 #define CLK_828_STATUS_OFFSET                           0x0b00
  46 #define  CLK_828_STATUS_MASK                            0x0000ffff
  47 #define  CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF      0x00008000
  48 #define  CLK_828_STATUS_FLAG_OPT_OUT_IFACE_IS_SPDIF     0x00004000
  49 #define  CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES           0x00000080
  50 #define  CLK_828_STATUS_FLAG_SRC_IS_NOT_FROM_ADAT_DSUB  0x00000020
  51 #define  CLK_828_STATUS_FLAG_OUTPUT_MUTE                0x00000008
  52 #define  CLK_828_STATUS_FLAG_RATE_48000                 0x00000004
  53 #define  CLK_828_STATUS_FLAG_SRC_SPDIF_ON_OPT_OR_COAX   0x00000002
  54 #define  CLK_828_STATUS_FLAG_SRC_ADAT_ON_OPT_OR_DSUB    0x00000001
  55
  56 // Status register for MOTU 896 (0x'ffff'f000'0b14).
  57 //
  58 // 0x20000000: fetch PCM frames from communication IC to DAC.
  59 // 0x08000000: speed of word clock signal output on BNC interface.
  60 //   0x00000000: follow to system clock.
  61 //   0x08000000: half of system clock.
  62 // 0x01000000: Route main output to headphone output.
  63 // 0x00ffff00: input to monitor.
  64 //   0x00000000: none
  65 //   0x00004800: analog-1/2
  66 //   0x00005a00: analog-3/4
  67 //   0x00006c00: analog-5/6
  68 //   0x00007e00: analog-7/8
  69 //   0x00104800: AES/EBU-1/2
  70 //   0x00004000: analog-1
  71 //   0x00004900: analog-2
  72 //   0x00005200: analog-3
  73 //   0x00005b00: analog-4
  74 //   0x00006400: analog-5
  75 //   0x00006d00: analog-6
  76 //   0x00007600: analog-7
  77 //   0x00007f00: analog-8
  78 //   0x00104000: AES/EBU-1
  79 //   0x00104900: AES/EBU-2
  80 // 0x00000060: sample rate conversin for AES/EBU input/output.
  81 //   0x00000000: None
  82 //   0x00000020: input signal is converted to system rate
  83 //   0x00000040: output is slave to input, ignoring system rate
  84 //   0x00000060: output is double rate than system rate
  85 // 0x00000018: nominal rate of sampling clock.
  86 //   0x00000000: 44.1 kHz
  87 //   0x00000008: 48.0 kHz
  88 //   0x00000010: 88.2 kHz
  89 //   0x00000018: 96.0 kHz
  90 // 0x00000007: source of sampling clock.
  91 //   0x00000000: internal
  92 //   0x00000001: ADAT on optical interface
  93 //   0x00000002: AES/EBU on XLR
  94 //   0x00000004: word clock on BNC
  95 //   0x00000005: ADAT on Dsub 9pin
  96
  97 #define CLK_896_STATUS_OFFSET                   0x0b14
  98 #define  CLK_896_STATUS_FLAG_FETCH_ENABLE       0x20000000
  99 #define  CLK_896_STATUS_FLAG_MAIN_TO_HP         0x01000000
 100 #define  CLK_896_STATUS_MASK_SRC                0x00000007
 101 #define   CLK_896_STATUS_FLAG_SRC_INTERNAL      0x00000000
 102 #define   CLK_896_STATUS_FLAG_SRC_ADAT_ON_OPT   0x00000001
 103 #define   CLK_896_STATUS_FLAG_SRC_AESEBU        0x00000002
 104 #define   CLK_896_STATUS_FLAG_SRC_WORD          0x00000004
 105 #define   CLK_896_STATUS_FLAG_SRC_ADAT_ON_DSUB  0x00000005
 106 #define  CLK_896_STATUS_MASK_RATE               0x00000018
 107 #define   CLK_896_STATUS_FLAG_RATE_44100        0x00000000
 108 #define   CLK_896_STATUS_FLAG_RATE_48000        0x00000008
 109 #define   CLK_896_STATUS_FLAG_RATE_88200        0x00000010
 110 #define   CLK_896_STATUS_FLAG_RATE_96000        0x00000018
 111
 112 static void parse_clock_rate_828(u32 data, unsigned int *rate)
 113 {
 114         if (data & CLK_828_STATUS_FLAG_RATE_48000)
 115                 *rate = 48000;
 116         else
 117                 *rate = 44100;
 118 }
 119
 120 static int get_clock_rate_828(struct snd_motu *motu, unsigned int *rate)
 121 {
 122         __be32 reg;
 123         int err;
 124
 125         err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, &reg, sizeof(reg));
 126         if (err < 0)
 127                 return err;
 128         parse_clock_rate_828(be32_to_cpu(reg), rate);
 129
 130         return 0;
 131 }
 132
 133 static int parse_clock_rate_896(u32 data, unsigned int *rate)
 134 {
 135         switch (data & CLK_896_STATUS_MASK_RATE) {
 136         case CLK_896_STATUS_FLAG_RATE_44100:
 137                 *rate = 44100;
 138                 break;
 139         case CLK_896_STATUS_FLAG_RATE_48000:
 140                 *rate = 48000;
 141                 break;
 142         case CLK_896_STATUS_FLAG_RATE_88200:
 143                 *rate = 88200;
 144                 break;
 145         case CLK_896_STATUS_FLAG_RATE_96000:
 146                 *rate = 96000;
 147                 break;
 148         default:
 149                 return -ENXIO;
 150         }
 151
 152         return 0;
 153 }
 154
 155 static int get_clock_rate_896(struct snd_motu *motu, unsigned int *rate)
 156 {
 157         __be32 reg;
 158         int err;
 159
 160         err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, &reg, sizeof(reg));
 161         if (err < 0)
 162                 return err;
 163         return parse_clock_rate_896(be32_to_cpu(reg), rate);
 164 }
 165
 166 int snd_motu_protocol_v1_get_clock_rate(struct snd_motu *motu, unsigned int *rate)
 167 {
 168         if (motu->spec == &snd_motu_spec_828)
 169                 return get_clock_rate_828(motu, rate);
 170         else if (motu->spec == &snd_motu_spec_896)
 171                 return get_clock_rate_896(motu, rate);
 172         else
 173                 return -ENXIO;
 174 }
 175
 176 static int set_clock_rate_828(struct snd_motu *motu, unsigned int rate)
 177 {
 178         __be32 reg;
 179         u32 data;
 180         int err;
 181
 182         err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, &reg, sizeof(reg));
 183         if (err < 0)
 184                 return err;
 185         data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
 186
 187         data &= ~CLK_828_STATUS_FLAG_RATE_48000;
 188         if (rate == 48000)
 189                 data |= CLK_828_STATUS_FLAG_RATE_48000;
 190
 191         reg = cpu_to_be32(data);
 192         return snd_motu_transaction_write(motu, CLK_828_STATUS_OFFSET, &reg, sizeof(reg));
 193 }
 194
 195 static int set_clock_rate_896(struct snd_motu *motu, unsigned int rate)
 196 {
 197         unsigned int flag;
 198         __be32 reg;
 199         u32 data;
 200         int err;
 201
 202         err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, &reg, sizeof(reg));
 203         if (err < 0)
 204                 return err;
 205         data = be32_to_cpu(reg);
 206
 207         switch (rate) {
 208         case 44100:
 209                 flag = CLK_896_STATUS_FLAG_RATE_44100;
 210                 break;
 211         case 48000:
 212                 flag = CLK_896_STATUS_FLAG_RATE_48000;
 213                 break;
 214         case 88200:
 215                 flag = CLK_896_STATUS_FLAG_RATE_88200;
 216                 break;
 217         case 96000:
 218                 flag = CLK_896_STATUS_FLAG_RATE_96000;
 219                 break;
 220         default:
 221                 return -EINVAL;
 222         }
 223
 224         data &= ~CLK_896_STATUS_MASK_RATE;
 225         data |= flag;
 226
 227         reg = cpu_to_be32(data);
 228         return snd_motu_transaction_write(motu, CLK_896_STATUS_OFFSET, &reg, sizeof(reg));
 229 }
 230
 231 int snd_motu_protocol_v1_set_clock_rate(struct snd_motu *motu, unsigned int rate)
 232 {
 233         if (motu->spec == &snd_motu_spec_828)
 234                 return set_clock_rate_828(motu, rate);
 235         else if (motu->spec == &snd_motu_spec_896)
 236                 return set_clock_rate_896(motu, rate);
 237         else
 238                 return -ENXIO;
 239 }
 240
 241 static int get_clock_source_828(struct snd_motu *motu, enum snd_motu_clock_source *src)
 242 {
 243         __be32 reg;
 244         u32 data;
 245         int err;
 246
 247         err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, &reg, sizeof(reg));
 248         if (err < 0)
 249                 return err;
 250         data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
 251
 252         if (data & CLK_828_STATUS_FLAG_SRC_ADAT_ON_OPT_OR_DSUB) {
 253                 if (data & CLK_828_STATUS_FLAG_SRC_IS_NOT_FROM_ADAT_DSUB)
 254                         *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
 255                 else
 256                         *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
 257         } else if (data & CLK_828_STATUS_FLAG_SRC_SPDIF_ON_OPT_OR_COAX) {
 258                 if (data & CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF)
 259                         *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
 260                 else
 261                         *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
 262         } else {
 263                 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int get_clock_source_896(struct snd_motu *motu, enum snd_motu_clock_source *src)
 270 {
 271         __be32 reg;
 272         u32 data;
 273         int err;
 274
 275         err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, &reg, sizeof(reg));
 276         if (err < 0)
 277                 return err;
 278         data = be32_to_cpu(reg);
 279
 280         switch (data & CLK_896_STATUS_MASK_SRC) {
 281         case CLK_896_STATUS_FLAG_SRC_INTERNAL:
 282                 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
 283                 break;
 284         case CLK_896_STATUS_FLAG_SRC_ADAT_ON_OPT:
 285                 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
 286                 break;
 287         case CLK_896_STATUS_FLAG_SRC_AESEBU:
 288                 *src = SND_MOTU_CLOCK_SOURCE_AESEBU_ON_XLR;
 289                 break;
 290         case CLK_896_STATUS_FLAG_SRC_WORD:
 291                 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
 292                 break;
 293         case CLK_896_STATUS_FLAG_SRC_ADAT_ON_DSUB:
 294                 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
 295                 break;
 296         default:
 297                 return -ENXIO;
 298         }
 299
 300         return 0;
 301 }
 302
 303 int snd_motu_protocol_v1_get_clock_source(struct snd_motu *motu, enum snd_motu_clock_source *src)
 304 {
 305         if (motu->spec == &snd_motu_spec_828)
 306                 return get_clock_source_828(motu, src);
 307         else if (motu->spec == &snd_motu_spec_896)
 308                 return get_clock_source_896(motu, src);
 309         else
 310                 return -ENXIO;
 311 }
 312
 313 static int switch_fetching_mode_828(struct snd_motu *motu, bool enable)
 314 {
 315         __be32 reg;
 316         u32 data;
 317         int err;
 318
 319         err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, &reg, sizeof(reg));
 320         if (err < 0)
 321                 return err;
 322         data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
 323
 324         data &= ~(CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES | CLK_828_STATUS_FLAG_OUTPUT_MUTE);
 325         if (enable) {
 326                 // This transaction should be initiated after the device receives batch of packets
 327                 // since the device voluntarily mutes outputs. As a workaround, yield processor over
 328                 // 100 msec.
 329                 msleep(100);
 330                 data |= CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES | CLK_828_STATUS_FLAG_OUTPUT_MUTE;
 331         }
 332
 333         reg = cpu_to_be32(data);
 334         return snd_motu_transaction_write(motu, CLK_828_STATUS_OFFSET, &reg, sizeof(reg));
 335 }
 336
 337 static int switch_fetching_mode_896(struct snd_motu *motu, bool enable)
 338 {
 339         __be32 reg;
 340         u32 data;
 341         int err;
 342
 343         err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, &reg, sizeof(reg));
 344         if (err < 0)
 345                 return err;
 346         data = be32_to_cpu(reg);
 347
 348         data &= ~(CLK_896_STATUS_FLAG_FETCH_ENABLE | CLK_896_STATUS_FLAG_MAIN_TO_HP);
 349         if (enable)
 350                 data |= (CLK_896_STATUS_FLAG_FETCH_ENABLE | CLK_896_STATUS_FLAG_MAIN_TO_HP);
 351
 352         reg = cpu_to_be32(data);
 353         return snd_motu_transaction_write(motu, CLK_896_STATUS_OFFSET, &reg, sizeof(reg));
 354 }
 355
 356 int snd_motu_protocol_v1_switch_fetching_mode(struct snd_motu *motu, bool enable)
 357 {
 358         if (motu->spec == &snd_motu_spec_828)
 359                 return switch_fetching_mode_828(motu, enable);
 360         else if (motu->spec == &snd_motu_spec_896)
 361                 return switch_fetching_mode_896(motu, enable);
 362         else
 363                 return -ENXIO;
 364 }
 365
 366 static int detect_packet_formats_828(struct snd_motu *motu)
 367 {
 368         __be32 reg;
 369         u32 data;
 370         int err;
 371
 372         motu->tx_packet_formats.pcm_byte_offset = 4;
 373         motu->tx_packet_formats.msg_chunks = 2;
 374
 375         motu->rx_packet_formats.pcm_byte_offset = 4;
 376         motu->rx_packet_formats.msg_chunks = 0;
 377
 378         err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, &reg, sizeof(reg));
 379         if (err < 0)
 380                 return err;
 381         data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
 382
 383         // The number of chunks is just reduced when SPDIF is activated.
 384         if (!(data & CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF))
 385                 motu->tx_packet_formats.pcm_chunks[0] += 8;
 386
 387         if (!(data & CLK_828_STATUS_FLAG_OPT_OUT_IFACE_IS_SPDIF))
 388                 motu->rx_packet_formats.pcm_chunks[0] += 8;
 389
 390         return 0;
 391 }
 392
 393 static int detect_packet_formats_896(struct snd_motu *motu)
 394 {
 395         // 24bit PCM frames follow to source packet header without message chunk.
 396         motu->tx_packet_formats.pcm_byte_offset = 4;
 397         motu->rx_packet_formats.pcm_byte_offset = 4;
 398
 399         // No message chunk in data block.
 400         motu->tx_packet_formats.msg_chunks = 0;
 401         motu->rx_packet_formats.msg_chunks = 0;
 402
 403         // Always enable optical interface for ADAT signal since the device have no registers
 404         // to refer to current configuration.
 405         motu->tx_packet_formats.pcm_chunks[0] += 8;
 406         motu->tx_packet_formats.pcm_chunks[1] += 8;
 407
 408         motu->rx_packet_formats.pcm_chunks[0] += 8;
 409         motu->rx_packet_formats.pcm_chunks[1] += 8;
 410
 411         return 0;
 412 }
 413
 414 int snd_motu_protocol_v1_cache_packet_formats(struct snd_motu *motu)
 415 {
 416         memcpy(motu->tx_packet_formats.pcm_chunks, motu->spec->tx_fixed_pcm_chunks,
 417                sizeof(motu->tx_packet_formats.pcm_chunks));
 418         memcpy(motu->rx_packet_formats.pcm_chunks, motu->spec->rx_fixed_pcm_chunks,
 419                sizeof(motu->rx_packet_formats.pcm_chunks));
 420
 421         if (motu->spec == &snd_motu_spec_828)
 422                 return detect_packet_formats_828(motu);
 423         else if (motu->spec == &snd_motu_spec_896)
 424                 return detect_packet_formats_896(motu);
 425         else
 426                 return 0;
 427 }
 428
 429 const struct snd_motu_spec snd_motu_spec_828 = {
 430         .name = "828",
 431         .protocol_version = SND_MOTU_PROTOCOL_V1,
 432         .tx_fixed_pcm_chunks = {10, 0, 0},
 433         .rx_fixed_pcm_chunks = {10, 0, 0},
 434 };
 435
 436 const struct snd_motu_spec snd_motu_spec_896 = {
 437         .name = "896",
 438         .tx_fixed_pcm_chunks = {10, 10, 0},
 439         .rx_fixed_pcm_chunks = {10, 10, 0},
 440 };