2 * TC Applied Technologies Digital Interface Communications Engine driver
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Licensed under the terms of the GNU General Public License, version 2.
8 #include <linux/compat.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/firewire.h>
12 #include <linux/firewire-constants.h>
13 #include <linux/module.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/mutex.h>
16 #include <linux/slab.h>
17 #include <linux/spinlock.h>
18 #include <linux/wait.h>
19 #include <sound/control.h>
20 #include <sound/core.h>
21 #include <sound/firewire.h>
22 #include <sound/hwdep.h>
23 #include <sound/initval.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
27 #include "iso-resources.h"
30 #define DICE_PRIVATE_SPACE 0xffffe0000000uLL
32 /* offset from DICE_PRIVATE_SPACE; offsets and sizes in quadlets */
33 #define DICE_GLOBAL_OFFSET 0x00
34 #define DICE_GLOBAL_SIZE 0x04
35 #define DICE_TX_OFFSET 0x08
36 #define DICE_TX_SIZE 0x0c
37 #define DICE_RX_OFFSET 0x10
38 #define DICE_RX_SIZE 0x14
40 /* pointed to by DICE_GLOBAL_OFFSET */
41 #define GLOBAL_OWNER 0x000
42 #define OWNER_NO_OWNER 0xffff000000000000uLL
43 #define OWNER_NODE_SHIFT 48
44 #define GLOBAL_NOTIFICATION 0x008
45 #define NOTIFY_RX_CFG_CHG 0x00000001
46 #define NOTIFY_TX_CFG_CHG 0x00000002
47 #define NOTIFY_DUP_ISOC 0x00000004
48 #define NOTIFY_BW_ERR 0x00000008
49 #define NOTIFY_LOCK_CHG 0x00000010
50 #define NOTIFY_CLOCK_ACCEPTED 0x00000020
51 #define NOTIFY_INTERFACE_CHG 0x00000040
52 #define NOTIFY_MESSAGE 0x00100000
53 #define GLOBAL_NICK_NAME 0x00c
54 #define NICK_NAME_SIZE 64
55 #define GLOBAL_CLOCK_SELECT 0x04c
56 #define CLOCK_SOURCE_MASK 0x000000ff
57 #define CLOCK_SOURCE_AES1 0x00000000
58 #define CLOCK_SOURCE_AES2 0x00000001
59 #define CLOCK_SOURCE_AES3 0x00000002
60 #define CLOCK_SOURCE_AES4 0x00000003
61 #define CLOCK_SOURCE_AES_ANY 0x00000004
62 #define CLOCK_SOURCE_ADAT 0x00000005
63 #define CLOCK_SOURCE_TDIF 0x00000006
64 #define CLOCK_SOURCE_WC 0x00000007
65 #define CLOCK_SOURCE_ARX1 0x00000008
66 #define CLOCK_SOURCE_ARX2 0x00000009
67 #define CLOCK_SOURCE_ARX3 0x0000000a
68 #define CLOCK_SOURCE_ARX4 0x0000000b
69 #define CLOCK_SOURCE_INTERNAL 0x0000000c
70 #define CLOCK_RATE_MASK 0x0000ff00
71 #define CLOCK_RATE_32000 0x00000000
72 #define CLOCK_RATE_44100 0x00000100
73 #define CLOCK_RATE_48000 0x00000200
74 #define CLOCK_RATE_88200 0x00000300
75 #define CLOCK_RATE_96000 0x00000400
76 #define CLOCK_RATE_176400 0x00000500
77 #define CLOCK_RATE_192000 0x00000600
78 #define CLOCK_RATE_ANY_LOW 0x00000700
79 #define CLOCK_RATE_ANY_MID 0x00000800
80 #define CLOCK_RATE_ANY_HIGH 0x00000900
81 #define CLOCK_RATE_NONE 0x00000a00
82 #define CLOCK_RATE_SHIFT 8
83 #define GLOBAL_ENABLE 0x050
84 #define ENABLE 0x00000001
85 #define GLOBAL_STATUS 0x054
86 #define STATUS_SOURCE_LOCKED 0x00000001
87 #define STATUS_RATE_CONFLICT 0x00000002
88 #define STATUS_NOMINAL_RATE_MASK 0x0000ff00
89 #define GLOBAL_EXTENDED_STATUS 0x058
90 #define EXT_STATUS_AES1_LOCKED 0x00000001
91 #define EXT_STATUS_AES2_LOCKED 0x00000002
92 #define EXT_STATUS_AES3_LOCKED 0x00000004
93 #define EXT_STATUS_AES4_LOCKED 0x00000008
94 #define EXT_STATUS_ADAT_LOCKED 0x00000010
95 #define EXT_STATUS_TDIF_LOCKED 0x00000020
96 #define EXT_STATUS_ARX1_LOCKED 0x00000040
97 #define EXT_STATUS_ARX2_LOCKED 0x00000080
98 #define EXT_STATUS_ARX3_LOCKED 0x00000100
99 #define EXT_STATUS_ARX4_LOCKED 0x00000200
100 #define EXT_STATUS_WC_LOCKED 0x00000400
101 #define EXT_STATUS_AES1_SLIP 0x00010000
102 #define EXT_STATUS_AES2_SLIP 0x00020000
103 #define EXT_STATUS_AES3_SLIP 0x00040000
104 #define EXT_STATUS_AES4_SLIP 0x00080000
105 #define EXT_STATUS_ADAT_SLIP 0x00100000
106 #define EXT_STATUS_TDIF_SLIP 0x00200000
107 #define EXT_STATUS_ARX1_SLIP 0x00400000
108 #define EXT_STATUS_ARX2_SLIP 0x00800000
109 #define EXT_STATUS_ARX3_SLIP 0x01000000
110 #define EXT_STATUS_ARX4_SLIP 0x02000000
111 #define EXT_STATUS_WC_SLIP 0x04000000
112 #define GLOBAL_SAMPLE_RATE 0x05c
113 #define GLOBAL_VERSION 0x060
114 #define GLOBAL_CLOCK_CAPABILITIES 0x064
115 #define CLOCK_CAP_RATE_32000 0x00000001
116 #define CLOCK_CAP_RATE_44100 0x00000002
117 #define CLOCK_CAP_RATE_48000 0x00000004
118 #define CLOCK_CAP_RATE_88200 0x00000008
119 #define CLOCK_CAP_RATE_96000 0x00000010
120 #define CLOCK_CAP_RATE_176400 0x00000020
121 #define CLOCK_CAP_RATE_192000 0x00000040
122 #define CLOCK_CAP_SOURCE_AES1 0x00010000
123 #define CLOCK_CAP_SOURCE_AES2 0x00020000
124 #define CLOCK_CAP_SOURCE_AES3 0x00040000
125 #define CLOCK_CAP_SOURCE_AES4 0x00080000
126 #define CLOCK_CAP_SOURCE_AES_ANY 0x00100000
127 #define CLOCK_CAP_SOURCE_ADAT 0x00200000
128 #define CLOCK_CAP_SOURCE_TDIF 0x00400000
129 #define CLOCK_CAP_SOURCE_WC 0x00800000
130 #define CLOCK_CAP_SOURCE_ARX1 0x01000000
131 #define CLOCK_CAP_SOURCE_ARX2 0x02000000
132 #define CLOCK_CAP_SOURCE_ARX3 0x04000000
133 #define CLOCK_CAP_SOURCE_ARX4 0x08000000
134 #define CLOCK_CAP_SOURCE_INTERNAL 0x10000000
135 #define GLOBAL_CLOCK_SOURCE_NAMES 0x068
136 #define CLOCK_SOURCE_NAMES_SIZE 256
138 /* pointed to by DICE_TX_OFFSET */
139 #define TX_NUMBER 0x000
140 #define TX_SIZE 0x004
141 /* repeated TX_NUMBER times, offset by TX_SIZE quadlets */
142 #define TX_ISOCHRONOUS 0x008
143 #define TX_NUMBER_AUDIO 0x00c
144 #define TX_NUMBER_MIDI 0x010
145 #define TX_SPEED 0x014
146 #define TX_NAMES 0x018
147 #define TX_NAMES_SIZE 256
148 #define TX_AC3_CAPABILITIES 0x118
149 #define TX_AC3_ENABLE 0x11c
151 /* pointed to by DICE_RX_OFFSET */
152 #define RX_NUMBER 0x000
153 #define RX_SIZE 0x004
154 /* repeated RX_NUMBER times, offset by RX_SIZE quadlets */
155 #define RX_ISOCHRONOUS 0x008
156 #define RX_SEQ_START 0x00c
157 #define RX_NUMBER_AUDIO 0x010
158 #define RX_NUMBER_MIDI 0x014
159 #define RX_NAMES 0x018
160 #define RX_NAMES_SIZE 256
161 #define RX_AC3_CAPABILITIES 0x118
162 #define RX_AC3_ENABLE 0x11c
165 #define FIRMWARE_LOAD_SPACE 0xffffe0100000uLL
167 /* offset from FIRMWARE_LOAD_SPACE */
168 #define FIRMWARE_VERSION 0x000
169 #define FIRMWARE_OPCODE 0x004
170 #define OPCODE_MASK 0x00000fff
171 #define OPCODE_GET_IMAGE_DESC 0x00000000
172 #define OPCODE_DELETE_IMAGE 0x00000001
173 #define OPCODE_CREATE_IMAGE 0x00000002
174 #define OPCODE_UPLOAD 0x00000003
175 #define OPCODE_UPLOAD_STAT 0x00000004
176 #define OPCODE_RESET_IMAGE 0x00000005
177 #define OPCODE_TEST_ACTION 0x00000006
178 #define OPCODE_GET_RUNNING_IMAGE_VINFO 0x0000000a
179 #define OPCODE_EXECUTE 0x80000000
180 #define FIRMWARE_RETURN_STATUS 0x008
181 #define FIRMWARE_PROGRESS 0x00c
182 #define PROGRESS_CURR_MASK 0x00000fff
183 #define PROGRESS_MAX_MASK 0x00fff000
184 #define PROGRESS_TOUT_MASK 0x0f000000
185 #define PROGRESS_FLAG 0x80000000
186 #define FIRMWARE_CAPABILITIES 0x010
187 #define FL_CAP_AUTOERASE 0x00000001
188 #define FL_CAP_PROGRESS 0x00000002
189 #define FIRMWARE_DATA 0x02c
190 #define TEST_CMD_POKE 0x00000001
191 #define TEST_CMD_PEEK 0x00000002
192 #define CMD_GET_AVS_CNT 0x00000003
193 #define CMD_CLR_AVS_CNT 0x00000004
194 #define CMD_SET_MODE 0x00000005
195 #define CMD_SET_MIDIBP 0x00000006
196 #define CMD_GET_AVSPHASE 0x00000007
197 #define CMD_ENABLE_BNC_SYNC 0x00000008
198 #define CMD_PULSE_BNC_SYNC 0x00000009
199 #define CMD_EMUL_SLOW_CMD 0x0000000a
200 #define FIRMWARE_TEST_DELAY 0xfd8
201 #define FIRMWARE_TEST_BUF 0xfdc
205 #define EAP_PRIVATE_SPACE 0xffffe0200000uLL
207 #define EAP_CAPABILITY_OFFSET 0x000
208 #define EAP_CAPABILITY_SIZE 0x004
211 #define EAP_ROUTER_CAPS 0x000
212 #define ROUTER_EXPOSED 0x00000001
213 #define ROUTER_READ_ONLY 0x00000002
214 #define ROUTER_FLASH 0x00000004
215 #define MAX_ROUTES_MASK 0xffff0000
216 #define EAP_MIXER_CAPS 0x004
217 #define MIXER_EXPOSED 0x00000001
218 #define MIXER_READ_ONLY 0x00000002
219 #define MIXER_FLASH 0x00000004
220 #define MIXER_IN_DEV_MASK 0x000000f0
221 #define MIXER_OUT_DEV_MASK 0x00000f00
222 #define MIXER_INPUTS_MASK 0x00ff0000
223 #define MIXER_OUTPUTS_MASK 0xff000000
224 #define EAP_GENERAL_CAPS 0x008
225 #define GENERAL_STREAM_CONFIG 0x00000001
226 #define GENERAL_FLASH 0x00000002
227 #define GENERAL_PEAK 0x00000004
228 #define GENERAL_MAX_TX_STREAMS_MASK 0x000000f0
229 #define GENERAL_MAX_RX_STREAMS_MASK 0x00000f00
230 #define GENERAL_STREAM_CONFIG_FLASH 0x00001000
231 #define GENERAL_CHIP_MASK 0x00ff0000
232 #define GENERAL_CHIP_DICE_II 0x00000000
233 #define GENERAL_CHIP_DICE_MINI 0x00010000
234 #define GENERAL_CHIP_DICE_JR 0x00020000
238 struct snd_card *card;
239 struct fw_unit *unit;
242 unsigned int global_offset;
243 unsigned int rx_offset;
244 struct fw_address_handler notification_handler;
245 int owner_generation;
246 int dev_lock_count; /* > 0 driver, < 0 userspace */
247 bool dev_lock_changed;
249 wait_queue_head_t hwdep_wait;
250 u32 notification_bits;
251 struct snd_pcm_substream *pcm;
252 struct fw_iso_resources resources;
253 struct amdtp_out_stream stream;
256 MODULE_DESCRIPTION("DICE driver");
257 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
258 MODULE_LICENSE("GPL v2");
260 static const unsigned int dice_rates[] = {
270 static void dice_lock_changed(struct dice *dice)
272 dice->dev_lock_changed = true;
273 wake_up(&dice->hwdep_wait);
276 static int dice_try_lock(struct dice *dice)
280 spin_lock_irq(&dice->lock);
282 if (dice->dev_lock_count < 0) {
287 if (dice->dev_lock_count++ == 0)
288 dice_lock_changed(dice);
292 spin_unlock_irq(&dice->lock);
297 static void dice_unlock(struct dice *dice)
299 spin_lock_irq(&dice->lock);
301 if (WARN_ON(dice->dev_lock_count <= 0))
304 if (--dice->dev_lock_count == 0)
305 dice_lock_changed(dice);
308 spin_unlock_irq(&dice->lock);
311 static inline u64 global_address(struct dice *dice, unsigned int offset)
313 return DICE_PRIVATE_SPACE + dice->global_offset + offset;
317 static inline u64 rx_address(struct dice *dice, unsigned int offset)
319 return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
322 static int dice_owner_set(struct dice *dice)
324 struct fw_device *device = fw_parent_device(dice->unit);
326 int rcode, err, errors = 0;
328 buffer = kmalloc(2 * 8, GFP_KERNEL);
333 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
334 buffer[1] = cpu_to_be64(
335 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
336 dice->notification_handler.offset);
338 dice->owner_generation = device->generation;
339 smp_rmb(); /* node_id vs. generation */
340 rcode = fw_run_transaction(device->card,
341 TCODE_LOCK_COMPARE_SWAP,
343 dice->owner_generation,
345 global_address(dice, GLOBAL_OWNER),
348 if (rcode == RCODE_COMPLETE) {
349 if (buffer[0] == cpu_to_be64(OWNER_NO_OWNER)) {
352 dev_err(&dice->unit->device,
353 "device is already in use\n");
358 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
359 dev_err(&dice->unit->device,
360 "setting device owner failed: %s\n",
361 fw_rcode_string(rcode));
373 static int dice_owner_update(struct dice *dice)
375 struct fw_device *device = fw_parent_device(dice->unit);
377 int rcode, err, errors = 0;
379 if (dice->owner_generation == -1)
382 buffer = kmalloc(2 * 8, GFP_KERNEL);
387 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
388 buffer[1] = cpu_to_be64(
389 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
390 dice->notification_handler.offset);
392 dice->owner_generation = device->generation;
393 smp_rmb(); /* node_id vs. generation */
394 rcode = fw_run_transaction(device->card,
395 TCODE_LOCK_COMPARE_SWAP,
397 dice->owner_generation,
399 global_address(dice, GLOBAL_OWNER),
402 if (rcode == RCODE_COMPLETE) {
403 if (buffer[0] == cpu_to_be64(OWNER_NO_OWNER)) {
406 dev_err(&dice->unit->device,
407 "device is already in use\n");
412 if (rcode == RCODE_GENERATION) {
413 err = 0; /* try again later */
416 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
417 dev_err(&dice->unit->device,
418 "setting device owner failed: %s\n",
419 fw_rcode_string(rcode));
429 dice->owner_generation = -1;
434 static void dice_owner_clear(struct dice *dice)
436 struct fw_device *device = fw_parent_device(dice->unit);
438 int rcode, errors = 0;
440 buffer = kmalloc(2 * 8, GFP_KERNEL);
445 buffer[0] = cpu_to_be64(
446 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
447 dice->notification_handler.offset);
448 buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
450 rcode = fw_run_transaction(device->card,
451 TCODE_LOCK_COMPARE_SWAP,
453 dice->owner_generation,
455 global_address(dice, GLOBAL_OWNER),
458 if (rcode == RCODE_COMPLETE)
460 if (rcode == RCODE_GENERATION)
462 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
463 dev_err(&dice->unit->device,
464 "clearing device owner failed: %s\n",
465 fw_rcode_string(rcode));
473 dice->owner_generation = -1;
476 static int dice_enable_set(struct dice *dice)
478 struct fw_device *device = fw_parent_device(dice->unit);
480 int rcode, err, errors = 0;
482 value = cpu_to_be32(ENABLE);
484 rcode = fw_run_transaction(device->card,
485 TCODE_WRITE_QUADLET_REQUEST,
487 dice->owner_generation,
489 global_address(dice, GLOBAL_ENABLE),
491 if (rcode == RCODE_COMPLETE) {
492 dice->global_enabled = true;
496 if (rcode == RCODE_GENERATION) {
500 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
501 dev_err(&dice->unit->device,
502 "device enabling failed: %s\n",
503 fw_rcode_string(rcode));
513 static void dice_enable_clear(struct dice *dice)
515 struct fw_device *device = fw_parent_device(dice->unit);
517 int rcode, errors = 0;
521 rcode = fw_run_transaction(device->card,
522 TCODE_WRITE_QUADLET_REQUEST,
524 dice->owner_generation,
526 global_address(dice, GLOBAL_ENABLE),
528 if (rcode == RCODE_COMPLETE ||
529 rcode == RCODE_GENERATION)
531 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
532 dev_err(&dice->unit->device,
533 "device disabling failed: %s\n",
534 fw_rcode_string(rcode));
539 dice->global_enabled = false;
542 static void dice_notification(struct fw_card *card, struct fw_request *request,
543 int tcode, int destination, int source,
544 int generation, unsigned long long offset,
545 void *data, size_t length, void *callback_data)
547 struct dice *dice = callback_data;
550 if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
551 fw_send_response(card, request, RCODE_TYPE_ERROR);
554 if ((offset & 3) != 0) {
555 fw_send_response(card, request, RCODE_ADDRESS_ERROR);
558 spin_lock_irqsave(&dice->lock, flags);
559 dice->notification_bits |= be32_to_cpup(data);
560 spin_unlock_irqrestore(&dice->lock, flags);
561 fw_send_response(card, request, RCODE_COMPLETE);
562 wake_up(&dice->hwdep_wait);
565 static int dice_open(struct snd_pcm_substream *substream)
567 static const struct snd_pcm_hardware hardware = {
568 .info = SNDRV_PCM_INFO_MMAP |
569 SNDRV_PCM_INFO_MMAP_VALID |
570 SNDRV_PCM_INFO_BATCH |
571 SNDRV_PCM_INFO_INTERLEAVED |
572 SNDRV_PCM_INFO_BLOCK_TRANSFER,
573 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
574 .buffer_bytes_max = 16 * 1024 * 1024,
575 .period_bytes_min = 1,
576 .period_bytes_max = UINT_MAX,
578 .periods_max = UINT_MAX,
580 struct dice *dice = substream->private_data;
581 struct snd_pcm_runtime *runtime = substream->runtime;
582 __be32 clock_sel, number_audio, number_midi;
586 err = dice_try_lock(dice);
590 err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
591 global_address(dice, GLOBAL_CLOCK_SELECT),
595 rate = (be32_to_cpu(clock_sel) & CLOCK_RATE_MASK) >> CLOCK_RATE_SHIFT;
596 if (rate >= ARRAY_SIZE(dice_rates)) {
600 rate = dice_rates[rate];
602 err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
603 rx_address(dice, RX_NUMBER_AUDIO),
607 err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
608 rx_address(dice, RX_NUMBER_MIDI),
613 runtime->hw = hardware;
615 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
616 snd_pcm_limit_hw_rates(runtime);
618 runtime->hw.channels_min = be32_to_cpu(number_audio);
619 runtime->hw.channels_max = be32_to_cpu(number_audio);
621 amdtp_out_stream_set_rate(&dice->stream, rate);
622 amdtp_out_stream_set_pcm(&dice->stream, be32_to_cpu(number_audio));
623 amdtp_out_stream_set_midi(&dice->stream, be32_to_cpu(number_midi));
625 err = snd_pcm_hw_constraint_minmax(runtime,
626 SNDRV_PCM_HW_PARAM_PERIOD_TIME,
631 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
643 static int dice_close(struct snd_pcm_substream *substream)
645 struct dice *dice = substream->private_data;
652 static int dice_stream_start_packets(struct dice *dice)
656 if (amdtp_out_stream_running(&dice->stream))
659 err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
660 fw_parent_device(dice->unit)->max_speed);
664 err = dice_enable_set(dice);
666 amdtp_out_stream_stop(&dice->stream);
673 static int dice_stream_start(struct dice *dice)
678 if (!dice->resources.allocated) {
679 err = fw_iso_resources_allocate(&dice->resources,
680 amdtp_out_stream_get_max_payload(&dice->stream),
681 fw_parent_device(dice->unit)->max_speed);
685 channel = cpu_to_be32(dice->resources.channel);
686 err = snd_fw_transaction(dice->unit,
687 TCODE_WRITE_QUADLET_REQUEST,
688 rx_address(dice, RX_ISOCHRONOUS),
694 err = dice_stream_start_packets(dice);
701 channel = cpu_to_be32((u32)-1);
702 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
703 rx_address(dice, RX_ISOCHRONOUS), &channel, 4);
705 fw_iso_resources_free(&dice->resources);
710 static void dice_stream_stop_packets(struct dice *dice)
712 if (amdtp_out_stream_running(&dice->stream)) {
713 dice_enable_clear(dice);
714 amdtp_out_stream_stop(&dice->stream);
718 static void dice_stream_stop(struct dice *dice)
722 dice_stream_stop_packets(dice);
724 if (!dice->resources.allocated)
727 channel = cpu_to_be32((u32)-1);
728 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
729 rx_address(dice, RX_ISOCHRONOUS), &channel, 4);
731 fw_iso_resources_free(&dice->resources);
734 static int dice_hw_params(struct snd_pcm_substream *substream,
735 struct snd_pcm_hw_params *hw_params)
737 struct dice *dice = substream->private_data;
740 mutex_lock(&dice->mutex);
741 dice_stream_stop(dice);
742 mutex_unlock(&dice->mutex);
744 err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
745 params_buffer_bytes(hw_params));
749 amdtp_out_stream_set_pcm_format(&dice->stream,
750 params_format(hw_params));
758 static int dice_hw_free(struct snd_pcm_substream *substream)
760 struct dice *dice = substream->private_data;
762 mutex_lock(&dice->mutex);
763 dice_stream_stop(dice);
764 mutex_unlock(&dice->mutex);
766 return snd_pcm_lib_free_vmalloc_buffer(substream);
769 static int dice_prepare(struct snd_pcm_substream *substream)
771 struct dice *dice = substream->private_data;
774 mutex_lock(&dice->mutex);
776 if (amdtp_out_streaming_error(&dice->stream))
777 dice_stream_stop_packets(dice);
779 err = dice_stream_start(dice);
781 mutex_unlock(&dice->mutex);
785 mutex_unlock(&dice->mutex);
787 amdtp_out_stream_pcm_prepare(&dice->stream);
792 static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
794 struct dice *dice = substream->private_data;
795 struct snd_pcm_substream *pcm;
798 case SNDRV_PCM_TRIGGER_START:
801 case SNDRV_PCM_TRIGGER_STOP:
807 amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
812 static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
814 struct dice *dice = substream->private_data;
816 return amdtp_out_stream_pcm_pointer(&dice->stream);
819 static int dice_create_pcm(struct dice *dice)
821 static struct snd_pcm_ops ops = {
824 .ioctl = snd_pcm_lib_ioctl,
825 .hw_params = dice_hw_params,
826 .hw_free = dice_hw_free,
827 .prepare = dice_prepare,
828 .trigger = dice_trigger,
829 .pointer = dice_pointer,
830 .page = snd_pcm_lib_get_vmalloc_page,
831 .mmap = snd_pcm_lib_mmap_vmalloc,
836 err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
839 pcm->private_data = dice;
840 strcpy(pcm->name, dice->card->shortname);
841 dice->pcm = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
842 dice->pcm->ops = &ops;
847 static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
848 long count, loff_t *offset)
850 struct dice *dice = hwdep->private_data;
852 union snd_firewire_event event;
854 spin_lock_irq(&dice->lock);
856 while (!dice->dev_lock_changed && dice->notification_bits == 0) {
857 prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
858 spin_unlock_irq(&dice->lock);
860 finish_wait(&dice->hwdep_wait, &wait);
861 if (signal_pending(current))
863 spin_lock_irq(&dice->lock);
866 memset(&event, 0, sizeof(event));
867 if (dice->dev_lock_changed) {
868 event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
869 event.lock_status.status = dice->dev_lock_count > 0;
870 dice->dev_lock_changed = false;
872 count = min(count, (long)sizeof(event.lock_status));
874 event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
875 event.dice_notification.notification = dice->notification_bits;
876 dice->notification_bits = 0;
878 count = min(count, (long)sizeof(event.dice_notification));
881 spin_unlock_irq(&dice->lock);
883 if (copy_to_user(buf, &event, count))
889 static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
892 struct dice *dice = hwdep->private_data;
895 poll_wait(file, &dice->hwdep_wait, wait);
897 spin_lock_irq(&dice->lock);
898 if (dice->dev_lock_changed || dice->notification_bits != 0)
899 events = POLLIN | POLLRDNORM;
902 spin_unlock_irq(&dice->lock);
907 static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
909 struct fw_device *dev = fw_parent_device(dice->unit);
910 struct snd_firewire_get_info info;
912 memset(&info, 0, sizeof(info));
913 info.type = SNDRV_FIREWIRE_TYPE_DICE;
914 info.card = dev->card->index;
915 *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
916 *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
917 strlcpy(info.device_name, dev_name(&dev->device),
918 sizeof(info.device_name));
920 if (copy_to_user(arg, &info, sizeof(info)))
926 static int dice_hwdep_lock(struct dice *dice)
930 spin_lock_irq(&dice->lock);
932 if (dice->dev_lock_count == 0) {
933 dice->dev_lock_count = -1;
939 spin_unlock_irq(&dice->lock);
944 static int dice_hwdep_unlock(struct dice *dice)
948 spin_lock_irq(&dice->lock);
950 if (dice->dev_lock_count == -1) {
951 dice->dev_lock_count = 0;
957 spin_unlock_irq(&dice->lock);
962 static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
964 struct dice *dice = hwdep->private_data;
966 spin_lock_irq(&dice->lock);
967 if (dice->dev_lock_count == -1)
968 dice->dev_lock_count = 0;
969 spin_unlock_irq(&dice->lock);
974 static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
975 unsigned int cmd, unsigned long arg)
977 struct dice *dice = hwdep->private_data;
980 case SNDRV_FIREWIRE_IOCTL_GET_INFO:
981 return dice_hwdep_get_info(dice, (void __user *)arg);
982 case SNDRV_FIREWIRE_IOCTL_LOCK:
983 return dice_hwdep_lock(dice);
984 case SNDRV_FIREWIRE_IOCTL_UNLOCK:
985 return dice_hwdep_unlock(dice);
992 static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
993 unsigned int cmd, unsigned long arg)
995 return dice_hwdep_ioctl(hwdep, file, cmd,
996 (unsigned long)compat_ptr(arg));
999 #define dice_hwdep_compat_ioctl NULL
1002 static int dice_create_hwdep(struct dice *dice)
1004 static const struct snd_hwdep_ops ops = {
1005 .read = dice_hwdep_read,
1006 .release = dice_hwdep_release,
1007 .poll = dice_hwdep_poll,
1008 .ioctl = dice_hwdep_ioctl,
1009 .ioctl_compat = dice_hwdep_compat_ioctl,
1011 struct snd_hwdep *hwdep;
1014 err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
1017 strcpy(hwdep->name, "DICE");
1018 hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
1020 hwdep->private_data = dice;
1021 hwdep->exclusive = true;
1026 static void dice_card_free(struct snd_card *card)
1028 struct dice *dice = card->private_data;
1030 amdtp_out_stream_destroy(&dice->stream);
1031 fw_core_remove_address_handler(&dice->notification_handler);
1032 mutex_destroy(&dice->mutex);
1035 static int dice_init_offsets(struct dice *dice)
1038 unsigned int global_size, rx_size;
1041 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1042 DICE_PRIVATE_SPACE, &pointers, 6 * 4);
1046 dice->global_offset = be32_to_cpu(pointers[0]) * 4;
1047 global_size = be32_to_cpu(pointers[1]);
1048 dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
1049 rx_size = be32_to_cpu(pointers[5]);
1051 /* some sanity checks to ensure that we actually have a DICE */
1052 if (dice->global_offset < 10 * 4 || global_size < 0x168 / 4 ||
1053 dice->rx_offset < 10 * 4 || rx_size < 0x120 / 4) {
1054 dev_err(&dice->unit->device, "invalid register pointers\n");
1061 static void dice_card_strings(struct dice *dice)
1063 struct snd_card *card = dice->card;
1064 struct fw_device *dev = fw_parent_device(dice->unit);
1065 char vendor[32], model[32];
1069 strcpy(card->driver, "DICE");
1071 strcpy(card->shortname, "DICE");
1072 BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
1073 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1074 global_address(dice, GLOBAL_NICK_NAME),
1075 card->shortname, sizeof(card->shortname));
1077 /* DICE strings are returned in "always-wrong" endianness */
1078 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
1079 for (i = 0; i < sizeof(card->shortname); i += 4)
1080 swab32s((u32 *)&card->shortname[i]);
1081 card->shortname[sizeof(card->shortname) - 1] = '\0';
1084 strcpy(vendor, "?");
1085 fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
1087 fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
1088 snprintf(card->longname, sizeof(card->longname),
1089 "%s %s, GUID %08x%08x at %s, S%d",
1090 vendor, model, dev->config_rom[3], dev->config_rom[4],
1091 dev_name(&dice->unit->device), 100 << dev->max_speed);
1093 strcpy(card->mixername, "DICE");
1096 static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
1098 struct snd_card *card;
1103 err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
1106 snd_card_set_dev(card, &unit->device);
1108 dice = card->private_data;
1110 spin_lock_init(&dice->lock);
1111 mutex_init(&dice->mutex);
1113 init_waitqueue_head(&dice->hwdep_wait);
1115 err = dice_init_offsets(dice);
1119 dice->notification_handler.length = 4;
1120 dice->notification_handler.address_callback = dice_notification;
1121 dice->notification_handler.callback_data = dice;
1122 err = fw_core_add_address_handler(&dice->notification_handler,
1123 &fw_high_memory_region);
1127 err = fw_iso_resources_init(&dice->resources, unit);
1129 goto err_notification_handler;
1130 dice->resources.channels_mask = 0x00000000ffffffffuLL;
1132 err = amdtp_out_stream_init(&dice->stream, unit, CIP_BLOCKING);
1136 err = dice_owner_set(dice);
1140 card->private_free = dice_card_free;
1142 dice_card_strings(dice);
1144 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1145 global_address(dice, GLOBAL_CLOCK_SELECT),
1149 clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
1150 clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
1151 err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
1152 global_address(dice, GLOBAL_CLOCK_SELECT),
1157 err = dice_create_pcm(dice);
1161 err = dice_create_hwdep(dice);
1165 err = snd_card_register(card);
1169 dev_set_drvdata(&unit->device, dice);
1174 amdtp_out_stream_destroy(&dice->stream);
1176 fw_iso_resources_destroy(&dice->resources);
1177 err_notification_handler:
1178 fw_core_remove_address_handler(&dice->notification_handler);
1180 mutex_destroy(&dice->mutex);
1182 snd_card_free(card);
1186 static void dice_remove(struct fw_unit *unit)
1188 struct dice *dice = dev_get_drvdata(&unit->device);
1190 mutex_lock(&dice->mutex);
1192 amdtp_out_stream_pcm_abort(&dice->stream);
1194 snd_card_disconnect(dice->card);
1196 dice_stream_stop(dice);
1197 dice_owner_clear(dice);
1199 mutex_unlock(&dice->mutex);
1201 snd_card_free_when_closed(dice->card);
1204 static void dice_bus_reset(struct fw_unit *unit)
1206 struct dice *dice = dev_get_drvdata(&unit->device);
1208 mutex_lock(&dice->mutex);
1211 * On a bus reset, the DICE firmware disables streaming and then goes
1212 * off contemplating its own navel for hundreds of milliseconds before
1213 * it can react to any of our attempts to reenable streaming. This
1214 * means that we lose synchronization anyway, so we force our streams
1215 * to stop so that the application can restart them in an orderly
1218 amdtp_out_stream_pcm_abort(&dice->stream);
1219 dice_stream_stop_packets(dice);
1221 dice_owner_update(dice);
1223 fw_iso_resources_update(&dice->resources);
1225 mutex_unlock(&dice->mutex);
1228 #define TC_OUI 0x000166
1229 #define DICE_INTERFACE 0x000001
1231 static const struct ieee1394_device_id dice_id_table[] = {
1233 .match_flags = IEEE1394_MATCH_SPECIFIER_ID |
1234 IEEE1394_MATCH_VERSION,
1235 .specifier_id = TC_OUI,
1236 .version = DICE_INTERFACE,
1240 MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1242 static struct fw_driver dice_driver = {
1244 .owner = THIS_MODULE,
1245 .name = KBUILD_MODNAME,
1246 .bus = &fw_bus_type,
1248 .probe = dice_probe,
1249 .update = dice_bus_reset,
1250 .remove = dice_remove,
1251 .id_table = dice_id_table,
1254 static int __init alsa_dice_init(void)
1256 return driver_register(&dice_driver.driver);
1259 static void __exit alsa_dice_exit(void)
1261 driver_unregister(&dice_driver.driver);
1264 module_init(alsa_dice_init);
1265 module_exit(alsa_dice_exit);