sound/firewire/dice.c

   1 /*
   2  * TC Applied Technologies Digital Interface Communications Engine driver
   3  *
   4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   5  * Licensed under the terms of the GNU General Public License, version 2.
   6  */
   7
   8 #include <linux/compat.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/firewire.h>
  12 #include <linux/firewire-constants.h>
  13 #include <linux/module.h>
  14 #include <linux/mod_devicetable.h>
  15 #include <linux/mutex.h>
  16 #include <linux/slab.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/wait.h>
  19 #include <sound/control.h>
  20 #include <sound/core.h>
  21 #include <sound/firewire.h>
  22 #include <sound/hwdep.h>
  23 #include <sound/initval.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include "amdtp.h"
  27 #include "iso-resources.h"
  28 #include "lib.h"
  29
  30 #define DICE_PRIVATE_SPACE              0xffffe0000000uLL
  31
  32 /* offset from DICE_PRIVATE_SPACE; offsets and sizes in quadlets */
  33 #define DICE_GLOBAL_OFFSET              0x00
  34 #define DICE_GLOBAL_SIZE                0x04
  35 #define DICE_TX_OFFSET                  0x08
  36 #define DICE_TX_SIZE                    0x0c
  37 #define DICE_RX_OFFSET                  0x10
  38 #define DICE_RX_SIZE                    0x14
  39
  40 /* pointed to by DICE_GLOBAL_OFFSET */
  41 #define GLOBAL_OWNER                    0x000
  42 #define  OWNER_NO_OWNER                 0xffff000000000000uLL
  43 #define  OWNER_NODE_SHIFT               48
  44 #define GLOBAL_NOTIFICATION             0x008
  45 #define  NOTIFY_RX_CFG_CHG              0x00000001
  46 #define  NOTIFY_TX_CFG_CHG              0x00000002
  47 #define  NOTIFY_DUP_ISOC                0x00000004
  48 #define  NOTIFY_BW_ERR                  0x00000008
  49 #define  NOTIFY_LOCK_CHG                0x00000010
  50 #define  NOTIFY_CLOCK_ACCEPTED          0x00000020
  51 #define  NOTIFY_INTERFACE_CHG           0x00000040
  52 #define  NOTIFY_MESSAGE                 0x00100000
  53 #define GLOBAL_NICK_NAME                0x00c
  54 #define  NICK_NAME_SIZE                 64
  55 #define GLOBAL_CLOCK_SELECT             0x04c
  56 #define  CLOCK_SOURCE_MASK              0x000000ff
  57 #define  CLOCK_SOURCE_AES1              0x00000000
  58 #define  CLOCK_SOURCE_AES2              0x00000001
  59 #define  CLOCK_SOURCE_AES3              0x00000002
  60 #define  CLOCK_SOURCE_AES4              0x00000003
  61 #define  CLOCK_SOURCE_AES_ANY           0x00000004
  62 #define  CLOCK_SOURCE_ADAT              0x00000005
  63 #define  CLOCK_SOURCE_TDIF              0x00000006
  64 #define  CLOCK_SOURCE_WC                0x00000007
  65 #define  CLOCK_SOURCE_ARX1              0x00000008
  66 #define  CLOCK_SOURCE_ARX2              0x00000009
  67 #define  CLOCK_SOURCE_ARX3              0x0000000a
  68 #define  CLOCK_SOURCE_ARX4              0x0000000b
  69 #define  CLOCK_SOURCE_INTERNAL          0x0000000c
  70 #define  CLOCK_RATE_MASK                0x0000ff00
  71 #define  CLOCK_RATE_32000               0x00000000
  72 #define  CLOCK_RATE_44100               0x00000100
  73 #define  CLOCK_RATE_48000               0x00000200
  74 #define  CLOCK_RATE_88200               0x00000300
  75 #define  CLOCK_RATE_96000               0x00000400
  76 #define  CLOCK_RATE_176400              0x00000500
  77 #define  CLOCK_RATE_192000              0x00000600
  78 #define  CLOCK_RATE_ANY_LOW             0x00000700
  79 #define  CLOCK_RATE_ANY_MID             0x00000800
  80 #define  CLOCK_RATE_ANY_HIGH            0x00000900
  81 #define  CLOCK_RATE_NONE                0x00000a00
  82 #define  CLOCK_RATE_SHIFT               8
  83 #define GLOBAL_ENABLE                   0x050
  84 #define  ENABLE                         0x00000001
  85 #define GLOBAL_STATUS                   0x054
  86 #define  STATUS_SOURCE_LOCKED           0x00000001
  87 #define  STATUS_RATE_CONFLICT           0x00000002
  88 #define  STATUS_NOMINAL_RATE_MASK       0x0000ff00
  89 #define GLOBAL_EXTENDED_STATUS          0x058
  90 #define  EXT_STATUS_AES1_LOCKED         0x00000001
  91 #define  EXT_STATUS_AES2_LOCKED         0x00000002
  92 #define  EXT_STATUS_AES3_LOCKED         0x00000004
  93 #define  EXT_STATUS_AES4_LOCKED         0x00000008
  94 #define  EXT_STATUS_ADAT_LOCKED         0x00000010
  95 #define  EXT_STATUS_TDIF_LOCKED         0x00000020
  96 #define  EXT_STATUS_ARX1_LOCKED         0x00000040
  97 #define  EXT_STATUS_ARX2_LOCKED         0x00000080
  98 #define  EXT_STATUS_ARX3_LOCKED         0x00000100
  99 #define  EXT_STATUS_ARX4_LOCKED         0x00000200
 100 #define  EXT_STATUS_WC_LOCKED           0x00000400
 101 #define  EXT_STATUS_AES1_SLIP           0x00010000
 102 #define  EXT_STATUS_AES2_SLIP           0x00020000
 103 #define  EXT_STATUS_AES3_SLIP           0x00040000
 104 #define  EXT_STATUS_AES4_SLIP           0x00080000
 105 #define  EXT_STATUS_ADAT_SLIP           0x00100000
 106 #define  EXT_STATUS_TDIF_SLIP           0x00200000
 107 #define  EXT_STATUS_ARX1_SLIP           0x00400000
 108 #define  EXT_STATUS_ARX2_SLIP           0x00800000
 109 #define  EXT_STATUS_ARX3_SLIP           0x01000000
 110 #define  EXT_STATUS_ARX4_SLIP           0x02000000
 111 #define  EXT_STATUS_WC_SLIP             0x04000000
 112 #define GLOBAL_SAMPLE_RATE              0x05c
 113 #define GLOBAL_VERSION                  0x060
 114 #define GLOBAL_CLOCK_CAPABILITIES       0x064
 115 #define  CLOCK_CAP_RATE_32000           0x00000001
 116 #define  CLOCK_CAP_RATE_44100           0x00000002
 117 #define  CLOCK_CAP_RATE_48000           0x00000004
 118 #define  CLOCK_CAP_RATE_88200           0x00000008
 119 #define  CLOCK_CAP_RATE_96000           0x00000010
 120 #define  CLOCK_CAP_RATE_176400          0x00000020
 121 #define  CLOCK_CAP_RATE_192000          0x00000040
 122 #define  CLOCK_CAP_SOURCE_AES1          0x00010000
 123 #define  CLOCK_CAP_SOURCE_AES2          0x00020000
 124 #define  CLOCK_CAP_SOURCE_AES3          0x00040000
 125 #define  CLOCK_CAP_SOURCE_AES4          0x00080000
 126 #define  CLOCK_CAP_SOURCE_AES_ANY       0x00100000
 127 #define  CLOCK_CAP_SOURCE_ADAT          0x00200000
 128 #define  CLOCK_CAP_SOURCE_TDIF          0x00400000
 129 #define  CLOCK_CAP_SOURCE_WC            0x00800000
 130 #define  CLOCK_CAP_SOURCE_ARX1          0x01000000
 131 #define  CLOCK_CAP_SOURCE_ARX2          0x02000000
 132 #define  CLOCK_CAP_SOURCE_ARX3          0x04000000
 133 #define  CLOCK_CAP_SOURCE_ARX4          0x08000000
 134 #define  CLOCK_CAP_SOURCE_INTERNAL      0x10000000
 135 #define GLOBAL_CLOCK_SOURCE_NAMES       0x068
 136 #define  CLOCK_SOURCE_NAMES_SIZE        256
 137
 138 /* pointed to by DICE_TX_OFFSET */
 139 #define TX_NUMBER                       0x000
 140 #define TX_SIZE                         0x004
 141 /* repeated TX_NUMBER times, offset by TX_SIZE quadlets */
 142 #define TX_ISOCHRONOUS                  0x008
 143 #define TX_NUMBER_AUDIO                 0x00c
 144 #define TX_NUMBER_MIDI                  0x010
 145 #define TX_SPEED                        0x014
 146 #define TX_NAMES                        0x018
 147 #define  TX_NAMES_SIZE                  256
 148 #define TX_AC3_CAPABILITIES             0x118
 149 #define TX_AC3_ENABLE                   0x11c
 150
 151 /* pointed to by DICE_RX_OFFSET */
 152 #define RX_NUMBER                       0x000
 153 #define RX_SIZE                         0x004
 154 /* repeated RX_NUMBER times, offset by RX_SIZE quadlets */
 155 #define RX_ISOCHRONOUS                  0x008
 156 #define RX_SEQ_START                    0x00c
 157 #define RX_NUMBER_AUDIO                 0x010
 158 #define RX_NUMBER_MIDI                  0x014
 159 #define RX_NAMES                        0x018
 160 #define  RX_NAMES_SIZE                  256
 161 #define RX_AC3_CAPABILITIES             0x118
 162 #define RX_AC3_ENABLE                   0x11c
 163
 164
 165 #define FIRMWARE_LOAD_SPACE             0xffffe0100000uLL
 166
 167 /* offset from FIRMWARE_LOAD_SPACE */
 168 #define FIRMWARE_VERSION                0x000
 169 #define FIRMWARE_OPCODE                 0x004
 170 #define  OPCODE_MASK                    0x00000fff
 171 #define  OPCODE_GET_IMAGE_DESC          0x00000000
 172 #define  OPCODE_DELETE_IMAGE            0x00000001
 173 #define  OPCODE_CREATE_IMAGE            0x00000002
 174 #define  OPCODE_UPLOAD                  0x00000003
 175 #define  OPCODE_UPLOAD_STAT             0x00000004
 176 #define  OPCODE_RESET_IMAGE             0x00000005
 177 #define  OPCODE_TEST_ACTION             0x00000006
 178 #define  OPCODE_GET_RUNNING_IMAGE_VINFO 0x0000000a
 179 #define  OPCODE_EXECUTE                 0x80000000
 180 #define FIRMWARE_RETURN_STATUS          0x008
 181 #define FIRMWARE_PROGRESS               0x00c
 182 #define  PROGRESS_CURR_MASK             0x00000fff
 183 #define  PROGRESS_MAX_MASK              0x00fff000
 184 #define  PROGRESS_TOUT_MASK             0x0f000000
 185 #define  PROGRESS_FLAG                  0x80000000
 186 #define FIRMWARE_CAPABILITIES           0x010
 187 #define  FL_CAP_AUTOERASE               0x00000001
 188 #define  FL_CAP_PROGRESS                0x00000002
 189 #define FIRMWARE_DATA                   0x02c
 190 #define  TEST_CMD_POKE                  0x00000001
 191 #define  TEST_CMD_PEEK                  0x00000002
 192 #define  CMD_GET_AVS_CNT                0x00000003
 193 #define  CMD_CLR_AVS_CNT                0x00000004
 194 #define  CMD_SET_MODE                   0x00000005
 195 #define  CMD_SET_MIDIBP                 0x00000006
 196 #define  CMD_GET_AVSPHASE               0x00000007
 197 #define  CMD_ENABLE_BNC_SYNC            0x00000008
 198 #define  CMD_PULSE_BNC_SYNC             0x00000009
 199 #define  CMD_EMUL_SLOW_CMD              0x0000000a
 200 #define FIRMWARE_TEST_DELAY             0xfd8
 201 #define FIRMWARE_TEST_BUF               0xfdc
 202
 203
 204 /* EAP */
 205 #define EAP_PRIVATE_SPACE               0xffffe0200000uLL
 206
 207 #define EAP_CAPABILITY_OFFSET           0x000
 208 #define EAP_CAPABILITY_SIZE             0x004
 209 /* ... */
 210
 211 #define EAP_ROUTER_CAPS                 0x000
 212 #define  ROUTER_EXPOSED                 0x00000001
 213 #define  ROUTER_READ_ONLY               0x00000002
 214 #define  ROUTER_FLASH                   0x00000004
 215 #define  MAX_ROUTES_MASK                0xffff0000
 216 #define EAP_MIXER_CAPS                  0x004
 217 #define  MIXER_EXPOSED                  0x00000001
 218 #define  MIXER_READ_ONLY                0x00000002
 219 #define  MIXER_FLASH                    0x00000004
 220 #define  MIXER_IN_DEV_MASK              0x000000f0
 221 #define  MIXER_OUT_DEV_MASK             0x00000f00
 222 #define  MIXER_INPUTS_MASK              0x00ff0000
 223 #define  MIXER_OUTPUTS_MASK             0xff000000
 224 #define EAP_GENERAL_CAPS                0x008
 225 #define  GENERAL_STREAM_CONFIG          0x00000001
 226 #define  GENERAL_FLASH                  0x00000002
 227 #define  GENERAL_PEAK                   0x00000004
 228 #define  GENERAL_MAX_TX_STREAMS_MASK    0x000000f0
 229 #define  GENERAL_MAX_RX_STREAMS_MASK    0x00000f00
 230 #define  GENERAL_STREAM_CONFIG_FLASH    0x00001000
 231 #define  GENERAL_CHIP_MASK              0x00ff0000
 232 #define  GENERAL_CHIP_DICE_II           0x00000000
 233 #define  GENERAL_CHIP_DICE_MINI         0x00010000
 234 #define  GENERAL_CHIP_DICE_JR           0x00020000
 235
 236
 237 struct dice {
 238         struct snd_card *card;
 239         struct fw_unit *unit;
 240         spinlock_t lock;
 241         struct mutex mutex;
 242         unsigned int global_offset;
 243         unsigned int rx_offset;
 244         struct fw_address_handler notification_handler;
 245         int owner_generation;
 246         int dev_lock_count; /* > 0 driver, < 0 userspace */
 247         bool dev_lock_changed;
 248         bool global_enabled;
 249         bool stream_running;
 250         wait_queue_head_t hwdep_wait;
 251         u32 notification_bits;
 252         struct snd_pcm_substream *pcm;
 253         struct fw_iso_resources resources;
 254         struct amdtp_out_stream stream;
 255 };
 256
 257 MODULE_DESCRIPTION("DICE driver");
 258 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
 259 MODULE_LICENSE("GPL v2");
 260
 261 static const unsigned int dice_rates[] = {
 262         [0] =  32000,
 263         [1] =  44100,
 264         [2] =  48000,
 265         [3] =  88200,
 266         [4] =  96000,
 267         [5] = 176400,
 268         [6] = 192000,
 269 };
 270
 271 static void dice_lock_changed(struct dice *dice)
 272 {
 273         dice->dev_lock_changed = true;
 274         wake_up(&dice->hwdep_wait);
 275 }
 276
 277 static int dice_try_lock(struct dice *dice)
 278 {
 279         int err;
 280
 281         spin_lock_irq(&dice->lock);
 282
 283         if (dice->dev_lock_count < 0) {
 284                 err = -EBUSY;
 285                 goto out;
 286         }
 287
 288         if (dice->dev_lock_count++ == 0)
 289                 dice_lock_changed(dice);
 290         err = 0;
 291
 292 out:
 293         spin_unlock_irq(&dice->lock);
 294
 295         return err;
 296 }
 297
 298 static void dice_unlock(struct dice *dice)
 299 {
 300         spin_lock_irq(&dice->lock);
 301
 302         if (WARN_ON(dice->dev_lock_count <= 0))
 303                 goto out;
 304
 305         if (--dice->dev_lock_count == 0)
 306                 dice_lock_changed(dice);
 307
 308 out:
 309         spin_unlock_irq(&dice->lock);
 310 }
 311
 312 static inline u64 global_address(struct dice *dice, unsigned int offset)
 313 {
 314         return DICE_PRIVATE_SPACE + dice->global_offset + offset;
 315 }
 316
 317 // TODO: rx index
 318 static inline u64 rx_address(struct dice *dice, unsigned int offset)
 319 {
 320         return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
 321 }
 322
 323 static int dice_owner_set(struct dice *dice)
 324 {
 325         struct fw_device *device = fw_parent_device(dice->unit);
 326         __be64 *buffer;
 327         int rcode, err, errors = 0;
 328
 329         buffer = kmalloc(2 * 8, GFP_KERNEL);
 330         if (!buffer)
 331                 return -ENOMEM;
 332
 333         for (;;) {
 334                 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
 335                 buffer[1] = cpu_to_be64(
 336                         ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
 337                         dice->notification_handler.offset);
 338
 339                 dice->owner_generation = device->generation;
 340                 smp_rmb(); /* node_id vs. generation */
 341                 rcode = fw_run_transaction(device->card,
 342                                            TCODE_LOCK_COMPARE_SWAP,
 343                                            device->node_id,
 344                                            dice->owner_generation,
 345                                            device->max_speed,
 346                                            global_address(dice, GLOBAL_OWNER),
 347                                            buffer, 2 * 8);
 348
 349                 if (rcode == RCODE_COMPLETE) {
 350                         if (buffer[0] == cpu_to_be64(OWNER_NO_OWNER)) {
 351                                 err = 0;
 352                         } else {
 353                                 dev_err(&dice->unit->device,
 354                                         "device is already in use\n");
 355                                 err = -EBUSY;
 356                         }
 357                         break;
 358                 }
 359                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 360                         dev_err(&dice->unit->device,
 361                                 "setting device owner failed: %s\n",
 362                                 fw_rcode_string(rcode));
 363                         err = -EIO;
 364                         break;
 365                 }
 366                 msleep(20);
 367         }
 368
 369         kfree(buffer);
 370
 371         return err;
 372 }
 373
 374 static int dice_owner_update(struct dice *dice)
 375 {
 376         struct fw_device *device = fw_parent_device(dice->unit);
 377         __be64 *buffer;
 378         int rcode, err, errors = 0;
 379
 380         if (dice->owner_generation == -1)
 381                 return 0;
 382
 383         buffer = kmalloc(2 * 8, GFP_KERNEL);
 384         if (!buffer)
 385                 return -ENOMEM;
 386
 387         for (;;) {
 388                 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
 389                 buffer[1] = cpu_to_be64(
 390                         ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
 391                         dice->notification_handler.offset);
 392
 393                 dice->owner_generation = device->generation;
 394                 smp_rmb(); /* node_id vs. generation */
 395                 rcode = fw_run_transaction(device->card,
 396                                            TCODE_LOCK_COMPARE_SWAP,
 397                                            device->node_id,
 398                                            dice->owner_generation,
 399                                            device->max_speed,
 400                                            global_address(dice, GLOBAL_OWNER),
 401                                            buffer, 2 * 8);
 402
 403                 if (rcode == RCODE_COMPLETE) {
 404                         if (buffer[0] == cpu_to_be64(OWNER_NO_OWNER)) {
 405                                 err = 0;
 406                         } else {
 407                                 dev_err(&dice->unit->device,
 408                                         "device is already in use\n");
 409                                 err = -EBUSY;
 410                         }
 411                         break;
 412                 }
 413                 if (rcode == RCODE_GENERATION) {
 414                         err = 0; /* try again later */
 415                         break;
 416                 }
 417                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 418                         dev_err(&dice->unit->device,
 419                                 "setting device owner failed: %s\n",
 420                                 fw_rcode_string(rcode));
 421                         err = -EIO;
 422                         break;
 423                 }
 424                 msleep(20);
 425         }
 426
 427         kfree(buffer);
 428
 429         if (err < 0)
 430                 dice->owner_generation = -1;
 431
 432         return err;
 433 }
 434
 435 static void dice_owner_clear(struct dice *dice)
 436 {
 437         struct fw_device *device = fw_parent_device(dice->unit);
 438         __be64 *buffer;
 439         int rcode, errors = 0;
 440
 441         buffer = kmalloc(2 * 8, GFP_KERNEL);
 442         if (!buffer)
 443                 return;
 444
 445         for (;;) {
 446                 buffer[0] = cpu_to_be64(
 447                         ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
 448                         dice->notification_handler.offset);
 449                 buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
 450
 451                 rcode = fw_run_transaction(device->card,
 452                                            TCODE_LOCK_COMPARE_SWAP,
 453                                            device->node_id,
 454                                            dice->owner_generation,
 455                                            device->max_speed,
 456                                            global_address(dice, GLOBAL_OWNER),
 457                                            buffer, 2 * 8);
 458
 459                 if (rcode == RCODE_COMPLETE)
 460                         break;
 461                 if (rcode == RCODE_GENERATION)
 462                         break;
 463                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 464                         dev_err(&dice->unit->device,
 465                                 "clearing device owner failed: %s\n",
 466                                 fw_rcode_string(rcode));
 467                         break;
 468                 }
 469                 msleep(20);
 470         }
 471
 472         kfree(buffer);
 473
 474         dice->owner_generation = -1;
 475 }
 476
 477 static int dice_enable_set(struct dice *dice)
 478 {
 479         struct fw_device *device = fw_parent_device(dice->unit);
 480         __be32 value;
 481         int rcode, err, errors = 0;
 482
 483         value = cpu_to_be32(ENABLE);
 484         for (;;) {
 485                 rcode = fw_run_transaction(device->card,
 486                                            TCODE_WRITE_QUADLET_REQUEST,
 487                                            device->node_id,
 488                                            dice->owner_generation,
 489                                            device->max_speed,
 490                                            global_address(dice, GLOBAL_ENABLE),
 491                                            &value, 4);
 492                 if (rcode == RCODE_COMPLETE) {
 493                         dice->global_enabled = true;
 494                         err = 0;
 495                         break;
 496                 }
 497                 if (rcode == RCODE_GENERATION) {
 498                         err = -EAGAIN;
 499                         break;
 500                 }
 501                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 502                         dev_err(&dice->unit->device,
 503                                 "device enabling failed: %s\n",
 504                                 fw_rcode_string(rcode));
 505                         err = -EIO;
 506                         break;
 507                 }
 508                 msleep(20);
 509         }
 510
 511         return err;
 512 }
 513
 514 static void dice_enable_clear(struct dice *dice)
 515 {
 516         struct fw_device *device = fw_parent_device(dice->unit);
 517         __be32 value;
 518         int rcode, errors = 0;
 519
 520         value = 0;
 521         for (;;) {
 522                 rcode = fw_run_transaction(device->card,
 523                                            TCODE_WRITE_QUADLET_REQUEST,
 524                                            device->node_id,
 525                                            dice->owner_generation,
 526                                            device->max_speed,
 527                                            global_address(dice, GLOBAL_ENABLE),
 528                                            &value, 4);
 529                 if (rcode == RCODE_COMPLETE ||
 530                     rcode == RCODE_GENERATION)
 531                         break;
 532                 if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
 533                         dev_err(&dice->unit->device,
 534                                 "device disabling failed: %s\n",
 535                                 fw_rcode_string(rcode));
 536                         break;
 537                 }
 538                 msleep(20);
 539         }
 540         dice->global_enabled = false;
 541 }
 542
 543 static void dice_notification(struct fw_card *card, struct fw_request *request,
 544                               int tcode, int destination, int source,
 545                               int generation, unsigned long long offset,
 546                               void *data, size_t length, void *callback_data)
 547 {
 548         struct dice *dice = callback_data;
 549         unsigned long flags;
 550
 551         if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
 552                 fw_send_response(card, request, RCODE_TYPE_ERROR);
 553                 return;
 554         }
 555         if ((offset & 3) != 0) {
 556                 fw_send_response(card, request, RCODE_ADDRESS_ERROR);
 557                 return;
 558         }
 559         spin_lock_irqsave(&dice->lock, flags);
 560         dice->notification_bits |= be32_to_cpup(data);
 561         spin_unlock_irqrestore(&dice->lock, flags);
 562         fw_send_response(card, request, RCODE_COMPLETE);
 563         wake_up(&dice->hwdep_wait);
 564 }
 565
 566 static int dice_open(struct snd_pcm_substream *substream)
 567 {
 568         static const struct snd_pcm_hardware hardware = {
 569                 .info = SNDRV_PCM_INFO_MMAP |
 570                         SNDRV_PCM_INFO_MMAP_VALID |
 571                         SNDRV_PCM_INFO_BATCH |
 572                         SNDRV_PCM_INFO_INTERLEAVED |
 573                         SNDRV_PCM_INFO_BLOCK_TRANSFER,
 574                 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
 575                 .buffer_bytes_max = 16 * 1024 * 1024,
 576                 .period_bytes_min = 1,
 577                 .period_bytes_max = UINT_MAX,
 578                 .periods_min = 1,
 579                 .periods_max = UINT_MAX,
 580         };
 581         struct dice *dice = substream->private_data;
 582         struct snd_pcm_runtime *runtime = substream->runtime;
 583         __be32 clock_sel, number_audio, number_midi;
 584         unsigned int rate;
 585         int err;
 586
 587         err = dice_try_lock(dice);
 588         if (err < 0)
 589                 goto error;
 590
 591         err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
 592                                  global_address(dice, GLOBAL_CLOCK_SELECT),
 593                                  &clock_sel, 4);
 594         if (err < 0)
 595                 goto err_lock;
 596         rate = (be32_to_cpu(clock_sel) & CLOCK_RATE_MASK) >> CLOCK_RATE_SHIFT;
 597         if (rate >= ARRAY_SIZE(dice_rates)) {
 598                 err = -ENXIO;
 599                 goto err_lock;
 600         }
 601         rate = dice_rates[rate];
 602
 603         err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
 604                                  rx_address(dice, RX_NUMBER_AUDIO),
 605                                  &number_audio, 4);
 606         if (err < 0)
 607                 goto err_lock;
 608         err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
 609                                  rx_address(dice, RX_NUMBER_MIDI),
 610                                  &number_midi, 4);
 611         if (err < 0)
 612                 goto err_lock;
 613
 614         runtime->hw = hardware;
 615
 616         runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 617         snd_pcm_limit_hw_rates(runtime);
 618
 619         runtime->hw.channels_min = be32_to_cpu(number_audio);
 620         runtime->hw.channels_max = be32_to_cpu(number_audio);
 621
 622         amdtp_out_stream_set_rate(&dice->stream, rate);
 623         amdtp_out_stream_set_pcm(&dice->stream, be32_to_cpu(number_audio));
 624         amdtp_out_stream_set_midi(&dice->stream, be32_to_cpu(number_midi));
 625
 626         err = snd_pcm_hw_constraint_minmax(runtime,
 627                                            SNDRV_PCM_HW_PARAM_PERIOD_TIME,
 628                                            5000, 8192000);
 629         if (err < 0)
 630                 goto err_lock;
 631
 632         err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
 633         if (err < 0)
 634                 goto err_lock;
 635
 636         return 0;
 637
 638 err_lock:
 639         dice_unlock(dice);
 640 error:
 641         return err;
 642 }
 643
 644 static int dice_close(struct snd_pcm_substream *substream)
 645 {
 646         struct dice *dice = substream->private_data;
 647
 648         dice_unlock(dice);
 649
 650         return 0;
 651 }
 652
 653 static int dice_stream_start_packets(struct dice *dice)
 654 {
 655         int err;
 656
 657         if (dice->stream_running)
 658                 return 0;
 659
 660         err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
 661                                      fw_parent_device(dice->unit)->max_speed);
 662         if (err < 0)
 663                 return err;
 664
 665         err = dice_enable_set(dice);
 666         if (err < 0) {
 667                 amdtp_out_stream_stop(&dice->stream);
 668                 return err;
 669         }
 670
 671         dice->stream_running = true;
 672
 673         return 0;
 674 }
 675
 676 static int dice_stream_start(struct dice *dice)
 677 {
 678         __be32 channel;
 679         int err;
 680
 681         if (!dice->resources.allocated) {
 682                 err = fw_iso_resources_allocate(&dice->resources,
 683                                 amdtp_out_stream_get_max_payload(&dice->stream),
 684                                 fw_parent_device(dice->unit)->max_speed);
 685                 if (err < 0)
 686                         goto error;
 687
 688                 channel = cpu_to_be32(dice->resources.channel);
 689                 err = snd_fw_transaction(dice->unit,
 690                                          TCODE_WRITE_QUADLET_REQUEST,
 691                                          rx_address(dice, RX_ISOCHRONOUS),
 692                                          &channel, 4);
 693                 if (err < 0)
 694                         goto err_resources;
 695         }
 696
 697         err = dice_stream_start_packets(dice);
 698         if (err < 0)
 699                 goto err_rx_channel;
 700
 701         return 0;
 702
 703 err_rx_channel:
 704         channel = cpu_to_be32((u32)-1);
 705         snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
 706                            rx_address(dice, RX_ISOCHRONOUS), &channel, 4);
 707 err_resources:
 708         fw_iso_resources_free(&dice->resources);
 709 error:
 710         return err;
 711 }
 712
 713 static void dice_stream_stop_packets(struct dice *dice)
 714 {
 715         if (!dice->stream_running)
 716                 return;
 717
 718         dice_enable_clear(dice);
 719
 720         amdtp_out_stream_stop(&dice->stream);
 721
 722         dice->stream_running = false;
 723 }
 724
 725 static void dice_stream_stop(struct dice *dice)
 726 {
 727         __be32 channel;
 728
 729         dice_stream_stop_packets(dice);
 730
 731         if (!dice->resources.allocated)
 732                 return;
 733
 734         channel = cpu_to_be32((u32)-1);
 735         snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
 736                            rx_address(dice, RX_ISOCHRONOUS), &channel, 4);
 737
 738         fw_iso_resources_free(&dice->resources);
 739 }
 740
 741 static int dice_hw_params(struct snd_pcm_substream *substream,
 742                           struct snd_pcm_hw_params *hw_params)
 743 {
 744         struct dice *dice = substream->private_data;
 745         int err;
 746
 747         mutex_lock(&dice->mutex);
 748         dice_stream_stop(dice);
 749         mutex_unlock(&dice->mutex);
 750
 751         err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
 752                                                params_buffer_bytes(hw_params));
 753         if (err < 0)
 754                 goto error;
 755
 756         amdtp_out_stream_set_pcm_format(&dice->stream,
 757                                         params_format(hw_params));
 758
 759         return 0;
 760
 761 error:
 762         return err;
 763 }
 764
 765 static int dice_hw_free(struct snd_pcm_substream *substream)
 766 {
 767         struct dice *dice = substream->private_data;
 768
 769         mutex_lock(&dice->mutex);
 770         dice_stream_stop(dice);
 771         mutex_unlock(&dice->mutex);
 772
 773         return snd_pcm_lib_free_vmalloc_buffer(substream);
 774 }
 775
 776 static int dice_prepare(struct snd_pcm_substream *substream)
 777 {
 778         struct dice *dice = substream->private_data;
 779         int err;
 780
 781         mutex_lock(&dice->mutex);
 782
 783         if (amdtp_out_streaming_error(&dice->stream))
 784                 dice_stream_stop_packets(dice);
 785
 786         err = dice_stream_start(dice);
 787         if (err < 0) {
 788                 mutex_unlock(&dice->mutex);
 789                 return err;
 790         }
 791
 792         mutex_unlock(&dice->mutex);
 793
 794         amdtp_out_stream_pcm_prepare(&dice->stream);
 795
 796         return 0;
 797 }
 798
 799 static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
 800 {
 801         struct dice *dice = substream->private_data;
 802         struct snd_pcm_substream *pcm;
 803
 804         switch (cmd) {
 805         case SNDRV_PCM_TRIGGER_START:
 806                 pcm = substream;
 807                 break;
 808         case SNDRV_PCM_TRIGGER_STOP:
 809                 pcm = NULL;
 810                 break;
 811         default:
 812                 return -EINVAL;
 813         }
 814         amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
 815
 816         return 0;
 817 }
 818
 819 static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
 820 {
 821         struct dice *dice = substream->private_data;
 822
 823         return amdtp_out_stream_pcm_pointer(&dice->stream);
 824 }
 825
 826 static int dice_create_pcm(struct dice *dice)
 827 {
 828         static struct snd_pcm_ops ops = {
 829                 .open      = dice_open,
 830                 .close     = dice_close,
 831                 .ioctl     = snd_pcm_lib_ioctl,
 832                 .hw_params = dice_hw_params,
 833                 .hw_free   = dice_hw_free,
 834                 .prepare   = dice_prepare,
 835                 .trigger   = dice_trigger,
 836                 .pointer   = dice_pointer,
 837                 .page      = snd_pcm_lib_get_vmalloc_page,
 838                 .mmap      = snd_pcm_lib_mmap_vmalloc,
 839         };
 840         struct snd_pcm *pcm;
 841         int err;
 842
 843         err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
 844         if (err < 0)
 845                 return err;
 846         pcm->private_data = dice;
 847         strcpy(pcm->name, dice->card->shortname);
 848         dice->pcm = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
 849         dice->pcm->ops = &ops;
 850
 851         return 0;
 852 }
 853
 854 static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
 855                             long count, loff_t *offset)
 856 {
 857         struct dice *dice = hwdep->private_data;
 858         DEFINE_WAIT(wait);
 859         union snd_firewire_event event;
 860
 861         spin_lock_irq(&dice->lock);
 862
 863         while (!dice->dev_lock_changed && dice->notification_bits == 0) {
 864                 prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
 865                 spin_unlock_irq(&dice->lock);
 866                 schedule();
 867                 finish_wait(&dice->hwdep_wait, &wait);
 868                 if (signal_pending(current))
 869                         return -ERESTARTSYS;
 870                 spin_lock_irq(&dice->lock);
 871         }
 872
 873         memset(&event, 0, sizeof(event));
 874         if (dice->dev_lock_changed) {
 875                 event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
 876                 event.lock_status.status = dice->dev_lock_count > 0;
 877                 dice->dev_lock_changed = false;
 878
 879                 count = min(count, (long)sizeof(event.lock_status));
 880         } else {
 881                 event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
 882                 event.dice_notification.notification = dice->notification_bits;
 883                 dice->notification_bits = 0;
 884
 885                 count = min(count, (long)sizeof(event.dice_notification));
 886         }
 887
 888         spin_unlock_irq(&dice->lock);
 889
 890         if (copy_to_user(buf, &event, count))
 891                 return -EFAULT;
 892
 893         return count;
 894 }
 895
 896 static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
 897                                     poll_table *wait)
 898 {
 899         struct dice *dice = hwdep->private_data;
 900         unsigned int events;
 901
 902         poll_wait(file, &dice->hwdep_wait, wait);
 903
 904         spin_lock_irq(&dice->lock);
 905         if (dice->dev_lock_changed || dice->notification_bits != 0)
 906                 events = POLLIN | POLLRDNORM;
 907         else
 908                 events = 0;
 909         spin_unlock_irq(&dice->lock);
 910
 911         return events;
 912 }
 913
 914 static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
 915 {
 916         struct fw_device *dev = fw_parent_device(dice->unit);
 917         struct snd_firewire_get_info info;
 918
 919         memset(&info, 0, sizeof(info));
 920         info.type = SNDRV_FIREWIRE_TYPE_DICE;
 921         info.card = dev->card->index;
 922         *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
 923         *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
 924         strlcpy(info.device_name, dev_name(&dev->device),
 925                 sizeof(info.device_name));
 926
 927         if (copy_to_user(arg, &info, sizeof(info)))
 928                 return -EFAULT;
 929
 930         return 0;
 931 }
 932
 933 static int dice_hwdep_lock(struct dice *dice)
 934 {
 935         int err;
 936
 937         spin_lock_irq(&dice->lock);
 938
 939         if (dice->dev_lock_count == 0) {
 940                 dice->dev_lock_count = -1;
 941                 err = 0;
 942         } else {
 943                 err = -EBUSY;
 944         }
 945
 946         spin_unlock_irq(&dice->lock);
 947
 948         return err;
 949 }
 950
 951 static int dice_hwdep_unlock(struct dice *dice)
 952 {
 953         int err;
 954
 955         spin_lock_irq(&dice->lock);
 956
 957         if (dice->dev_lock_count == -1) {
 958                 dice->dev_lock_count = 0;
 959                 err = 0;
 960         } else {
 961                 err = -EBADFD;
 962         }
 963
 964         spin_unlock_irq(&dice->lock);
 965
 966         return err;
 967 }
 968
 969 static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
 970                             unsigned int cmd, unsigned long arg)
 971 {
 972         struct dice *dice = hwdep->private_data;
 973
 974         switch (cmd) {
 975         case SNDRV_FIREWIRE_IOCTL_GET_INFO:
 976                 return dice_hwdep_get_info(dice, (void __user *)arg);
 977         case SNDRV_FIREWIRE_IOCTL_LOCK:
 978                 return dice_hwdep_lock(dice);
 979         case SNDRV_FIREWIRE_IOCTL_UNLOCK:
 980                 return dice_hwdep_unlock(dice);
 981         default:
 982                 return -ENOIOCTLCMD;
 983         }
 984 }
 985
 986 #ifdef CONFIG_COMPAT
 987 static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
 988                                    unsigned int cmd, unsigned long arg)
 989 {
 990         return dice_hwdep_ioctl(hwdep, file, cmd,
 991                                 (unsigned long)compat_ptr(arg));
 992 }
 993 #else
 994 #define dice_hwdep_compat_ioctl NULL
 995 #endif
 996
 997 static int dice_create_hwdep(struct dice *dice)
 998 {
 999         static const struct snd_hwdep_ops ops = {
1000                 .read         = dice_hwdep_read,
1001                 .poll         = dice_hwdep_poll,
1002                 .ioctl        = dice_hwdep_ioctl,
1003                 .ioctl_compat = dice_hwdep_compat_ioctl,
1004         };
1005         struct snd_hwdep *hwdep;
1006         int err;
1007
1008         err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
1009         if (err < 0)
1010                 return err;
1011         strcpy(hwdep->name, "DICE");
1012         hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
1013         hwdep->ops = ops;
1014         hwdep->private_data = dice;
1015         hwdep->exclusive = true;
1016
1017         return 0;
1018 }
1019
1020 static void dice_card_free(struct snd_card *card)
1021 {
1022         struct dice *dice = card->private_data;
1023
1024         amdtp_out_stream_destroy(&dice->stream);
1025         fw_core_remove_address_handler(&dice->notification_handler);
1026         mutex_destroy(&dice->mutex);
1027 }
1028
1029 static int dice_init_offsets(struct dice *dice)
1030 {
1031         __be32 pointers[6];
1032         unsigned int global_size, rx_size;
1033         int err;
1034
1035         err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1036                                  DICE_PRIVATE_SPACE, &pointers, 6 * 4);
1037         if (err < 0)
1038                 return err;
1039
1040         dice->global_offset = be32_to_cpu(pointers[0]) * 4;
1041         global_size = be32_to_cpu(pointers[1]);
1042         dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
1043         rx_size = be32_to_cpu(pointers[5]);
1044
1045         /* some sanity checks to ensure that we actually have a DICE */
1046         if (dice->global_offset < 10 * 4 || global_size < 0x168 / 4 ||
1047             dice->rx_offset < 10 * 4 || rx_size < 0x120 / 4) {
1048                 dev_err(&dice->unit->device, "invalid register pointers\n");
1049                 return -ENXIO;
1050         }
1051
1052         return 0;
1053 }
1054
1055 static void dice_card_strings(struct dice *dice)
1056 {
1057         struct snd_card *card = dice->card;
1058         struct fw_device *dev = fw_parent_device(dice->unit);
1059         char vendor[32], model[32];
1060         unsigned int i;
1061         int err;
1062
1063         strcpy(card->driver, "DICE");
1064
1065         strcpy(card->shortname, "DICE");
1066         BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
1067         err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1068                                  global_address(dice, GLOBAL_NICK_NAME),
1069                                  card->shortname, sizeof(card->shortname));
1070         if (err >= 0) {
1071                 /* DICE strings are returned in "always-wrong" endianness */
1072                 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
1073                 for (i = 0; i < sizeof(card->shortname); i += 4)
1074                         swab32s((u32 *)&card->shortname[i]);
1075                 card->shortname[sizeof(card->shortname) - 1] = '\0';
1076         }
1077
1078         strcpy(vendor, "?");
1079         fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
1080         strcpy(model, "?");
1081         fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
1082         snprintf(card->longname, sizeof(card->longname),
1083                  "%s %s, GUID %08x%08x at %s, S%d",
1084                  vendor, model, dev->config_rom[3], dev->config_rom[4],
1085                  dev_name(&dice->unit->device), 100 << dev->max_speed);
1086
1087         strcpy(card->mixername, "DICE");
1088 }
1089
1090 static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
1091 {
1092         struct snd_card *card;
1093         struct dice *dice;
1094         __be32 clock_sel;
1095         int err;
1096
1097         err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
1098         if (err < 0)
1099                 return err;
1100         snd_card_set_dev(card, &unit->device);
1101
1102         dice = card->private_data;
1103         dice->card = card;
1104         spin_lock_init(&dice->lock);
1105         mutex_init(&dice->mutex);
1106         dice->unit = unit;
1107         init_waitqueue_head(&dice->hwdep_wait);
1108
1109         err = dice_init_offsets(dice);
1110         if (err < 0)
1111                 goto err_mutex;
1112
1113         dice->notification_handler.length = 4;
1114         dice->notification_handler.address_callback = dice_notification;
1115         dice->notification_handler.callback_data = dice;
1116         err = fw_core_add_address_handler(&dice->notification_handler,
1117                                           &fw_high_memory_region);
1118         if (err < 0)
1119                 goto err_mutex;
1120
1121         err = fw_iso_resources_init(&dice->resources, unit);
1122         if (err < 0)
1123                 goto err_notification_handler;
1124         dice->resources.channels_mask = 0x00000000ffffffffuLL;
1125
1126         err = amdtp_out_stream_init(&dice->stream, unit, CIP_BLOCKING);
1127         if (err < 0)
1128                 goto err_resources;
1129
1130         err = dice_owner_set(dice);
1131         if (err < 0)
1132                 goto err_stream;
1133
1134         card->private_free = dice_card_free;
1135
1136         dice_card_strings(dice);
1137
1138         err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1139                                  global_address(dice, GLOBAL_CLOCK_SELECT),
1140                                  &clock_sel, 4);
1141         if (err < 0)
1142                 goto error;
1143         clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
1144         clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
1145         err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
1146                                  global_address(dice, GLOBAL_CLOCK_SELECT),
1147                                  &clock_sel, 4);
1148         if (err < 0)
1149                 goto error;
1150
1151         err = dice_create_pcm(dice);
1152         if (err < 0)
1153                 goto error;
1154
1155         err = dice_create_hwdep(dice);
1156         if (err < 0)
1157                 goto error;
1158
1159         err = snd_card_register(card);
1160         if (err < 0)
1161                 goto error;
1162
1163         dev_set_drvdata(&unit->device, dice);
1164
1165         return 0;
1166
1167 err_stream:
1168         amdtp_out_stream_destroy(&dice->stream);
1169 err_resources:
1170         fw_iso_resources_destroy(&dice->resources);
1171 err_notification_handler:
1172         fw_core_remove_address_handler(&dice->notification_handler);
1173 err_mutex:
1174         mutex_destroy(&dice->mutex);
1175 error:
1176         snd_card_free(card);
1177         return err;
1178 }
1179
1180 static void dice_remove(struct fw_unit *unit)
1181 {
1182         struct dice *dice = dev_get_drvdata(&unit->device);
1183
1184         mutex_lock(&dice->mutex);
1185
1186         amdtp_out_stream_pcm_abort(&dice->stream);
1187
1188         snd_card_disconnect(dice->card);
1189
1190         dice_stream_stop(dice);
1191         dice_owner_clear(dice);
1192
1193         mutex_unlock(&dice->mutex);
1194
1195         snd_card_free_when_closed(dice->card);
1196 }
1197
1198 static void dice_bus_reset(struct fw_unit *unit)
1199 {
1200         struct dice *dice = dev_get_drvdata(&unit->device);
1201
1202         mutex_lock(&dice->mutex);
1203
1204         /*
1205          * On a bus reset, the DICE firmware disables streaming and then goes
1206          * off contemplating its own navel for hundreds of milliseconds before
1207          * it can react to any of our attempts to reenable streaming.  This
1208          * means that we lose synchronization anyway, so we force our streams
1209          * to stop so that the application can restart them in an orderly
1210          * manner.
1211          */
1212         amdtp_out_stream_pcm_abort(&dice->stream);
1213         dice_stream_stop_packets(dice);
1214
1215         dice_owner_update(dice);
1216
1217         fw_iso_resources_update(&dice->resources);
1218
1219         mutex_unlock(&dice->mutex);
1220 }
1221
1222 #define TC_OUI          0x000166
1223 #define DICE_INTERFACE  0x000001
1224
1225 static const struct ieee1394_device_id dice_id_table[] = {
1226         {
1227                 .match_flags  = IEEE1394_MATCH_SPECIFIER_ID |
1228                                 IEEE1394_MATCH_VERSION,
1229                 .specifier_id = TC_OUI,
1230                 .version      = DICE_INTERFACE,
1231         },
1232         { }
1233 };
1234 MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1235
1236 static struct fw_driver dice_driver = {
1237         .driver   = {
1238                 .owner  = THIS_MODULE,
1239                 .name   = KBUILD_MODNAME,
1240                 .bus    = &fw_bus_type,
1241         },
1242         .probe    = dice_probe,
1243         .update   = dice_bus_reset,
1244         .remove   = dice_remove,
1245         .id_table = dice_id_table,
1246 };
1247
1248 static int __init alsa_dice_init(void)
1249 {
1250         return driver_register(&dice_driver.driver);
1251 }
1252
1253 static void __exit alsa_dice_exit(void)
1254 {
1255         driver_unregister(&dice_driver.driver);
1256 }
1257
1258 module_init(alsa_dice_init);
1259 module_exit(alsa_dice_exit);