1 // SPDX-License-Identifier: GPL-2.0-only
3 * dice_stream.c - a part of driver for DICE based devices
5 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
6 * Copyright (c) 2014 Takashi Sakamoto <o-takashi@sakamocchi.jp>
11 #define READY_TIMEOUT_MS 200
12 #define NOTIFICATION_TIMEOUT_MS 100
19 const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT] = {
32 int snd_dice_stream_get_rate_mode(struct snd_dice *dice, unsigned int rate,
33 enum snd_dice_rate_mode *mode)
35 /* Corresponding to each entry in snd_dice_rates. */
36 static const enum snd_dice_rate_mode modes[] = {
37 [0] = SND_DICE_RATE_MODE_LOW,
38 [1] = SND_DICE_RATE_MODE_LOW,
39 [2] = SND_DICE_RATE_MODE_LOW,
40 [3] = SND_DICE_RATE_MODE_MIDDLE,
41 [4] = SND_DICE_RATE_MODE_MIDDLE,
42 [5] = SND_DICE_RATE_MODE_HIGH,
43 [6] = SND_DICE_RATE_MODE_HIGH,
47 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); i++) {
48 if (!(dice->clock_caps & BIT(i)))
50 if (snd_dice_rates[i] != rate)
60 static int select_clock(struct snd_dice *dice, unsigned int rate)
67 err = snd_dice_transaction_read_global(dice, GLOBAL_CLOCK_SELECT,
72 data = be32_to_cpu(reg);
74 data &= ~CLOCK_RATE_MASK;
75 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); ++i) {
76 if (snd_dice_rates[i] == rate)
79 if (i == ARRAY_SIZE(snd_dice_rates))
81 data |= i << CLOCK_RATE_SHIFT;
83 if (completion_done(&dice->clock_accepted))
84 reinit_completion(&dice->clock_accepted);
86 reg = cpu_to_be32(data);
87 err = snd_dice_transaction_write_global(dice, GLOBAL_CLOCK_SELECT,
92 if (wait_for_completion_timeout(&dice->clock_accepted,
93 msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0)
99 static int get_register_params(struct snd_dice *dice,
100 struct reg_params *tx_params,
101 struct reg_params *rx_params)
106 err = snd_dice_transaction_read_tx(dice, TX_NUMBER, reg, sizeof(reg));
110 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
111 tx_params->size = be32_to_cpu(reg[1]) * 4;
113 err = snd_dice_transaction_read_rx(dice, RX_NUMBER, reg, sizeof(reg));
117 min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
118 rx_params->size = be32_to_cpu(reg[1]) * 4;
123 static void release_resources(struct snd_dice *dice)
127 for (i = 0; i < MAX_STREAMS; ++i) {
128 fw_iso_resources_free(&dice->tx_resources[i]);
129 fw_iso_resources_free(&dice->rx_resources[i]);
133 static void stop_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
134 struct reg_params *params)
139 for (i = 0; i < params->count; i++) {
140 reg = cpu_to_be32((u32)-1);
141 if (dir == AMDTP_IN_STREAM) {
142 snd_dice_transaction_write_tx(dice,
143 params->size * i + TX_ISOCHRONOUS,
146 snd_dice_transaction_write_rx(dice,
147 params->size * i + RX_ISOCHRONOUS,
153 static int keep_resources(struct snd_dice *dice, struct amdtp_stream *stream,
154 struct fw_iso_resources *resources, unsigned int rate,
155 unsigned int pcm_chs, unsigned int midi_ports)
157 bool double_pcm_frames;
161 // At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
162 // one data block of AMDTP packet. Thus sampling transfer frequency is
163 // a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
164 // transferred on AMDTP packets at 96 kHz. Two successive samples of a
165 // channel are stored consecutively in the packet. This quirk is called
167 // For this quirk, blocking mode is required and PCM buffer size should
168 // be aligned to SYT_INTERVAL.
169 double_pcm_frames = (rate > 96000 && !dice->disable_double_pcm_frames);
170 if (double_pcm_frames) {
175 err = amdtp_am824_set_parameters(stream, rate, pcm_chs, midi_ports,
180 if (double_pcm_frames) {
183 for (i = 0; i < pcm_chs; i++) {
184 amdtp_am824_set_pcm_position(stream, i, i * 2);
185 amdtp_am824_set_pcm_position(stream, i + pcm_chs,
190 return fw_iso_resources_allocate(resources,
191 amdtp_stream_get_max_payload(stream),
192 fw_parent_device(dice->unit)->max_speed);
195 static int keep_dual_resources(struct snd_dice *dice, unsigned int rate,
196 enum amdtp_stream_direction dir,
197 struct reg_params *params)
199 enum snd_dice_rate_mode mode;
203 err = snd_dice_stream_get_rate_mode(dice, rate, &mode);
207 for (i = 0; i < params->count; ++i) {
209 struct amdtp_stream *stream;
210 struct fw_iso_resources *resources;
211 unsigned int pcm_cache;
212 unsigned int pcm_chs;
213 unsigned int midi_ports;
215 if (dir == AMDTP_IN_STREAM) {
216 stream = &dice->tx_stream[i];
217 resources = &dice->tx_resources[i];
219 pcm_cache = dice->tx_pcm_chs[i][mode];
220 err = snd_dice_transaction_read_tx(dice,
221 params->size * i + TX_NUMBER_AUDIO,
224 stream = &dice->rx_stream[i];
225 resources = &dice->rx_resources[i];
227 pcm_cache = dice->rx_pcm_chs[i][mode];
228 err = snd_dice_transaction_read_rx(dice,
229 params->size * i + RX_NUMBER_AUDIO,
234 pcm_chs = be32_to_cpu(reg[0]);
235 midi_ports = be32_to_cpu(reg[1]);
237 // These are important for developer of this driver.
238 if (pcm_chs != pcm_cache) {
239 dev_info(&dice->unit->device,
240 "cache mismatch: pcm: %u:%u, midi: %u\n",
241 pcm_chs, pcm_cache, midi_ports);
245 err = keep_resources(dice, stream, resources, rate, pcm_chs,
254 static void finish_session(struct snd_dice *dice, struct reg_params *tx_params,
255 struct reg_params *rx_params)
257 stop_streams(dice, AMDTP_IN_STREAM, tx_params);
258 stop_streams(dice, AMDTP_OUT_STREAM, rx_params);
260 snd_dice_transaction_clear_enable(dice);
263 int snd_dice_stream_reserve_duplex(struct snd_dice *dice, unsigned int rate,
264 unsigned int events_per_period,
265 unsigned int events_per_buffer)
267 unsigned int curr_rate;
270 // Check sampling transmission frequency.
271 err = snd_dice_transaction_get_rate(dice, &curr_rate);
277 if (dice->substreams_counter == 0 || curr_rate != rate) {
278 struct reg_params tx_params, rx_params;
280 amdtp_domain_stop(&dice->domain);
282 err = get_register_params(dice, &tx_params, &rx_params);
285 finish_session(dice, &tx_params, &rx_params);
287 release_resources(dice);
289 // Just after owning the unit (GLOBAL_OWNER), the unit can
290 // return invalid stream formats. Selecting clock parameters
291 // have an effect for the unit to refine it.
292 err = select_clock(dice, rate);
296 // After changing sampling transfer frequency, the value of
297 // register can be changed.
298 err = get_register_params(dice, &tx_params, &rx_params);
302 err = keep_dual_resources(dice, rate, AMDTP_IN_STREAM,
307 err = keep_dual_resources(dice, rate, AMDTP_OUT_STREAM,
312 err = amdtp_domain_set_events_per_period(&dice->domain,
313 events_per_period, events_per_buffer);
320 release_resources(dice);
324 static int start_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
325 unsigned int rate, struct reg_params *params)
327 unsigned int max_speed = fw_parent_device(dice->unit)->max_speed;
331 for (i = 0; i < params->count; i++) {
332 struct amdtp_stream *stream;
333 struct fw_iso_resources *resources;
336 if (dir == AMDTP_IN_STREAM) {
337 stream = dice->tx_stream + i;
338 resources = dice->tx_resources + i;
340 stream = dice->rx_stream + i;
341 resources = dice->rx_resources + i;
344 reg = cpu_to_be32(resources->channel);
345 if (dir == AMDTP_IN_STREAM) {
346 err = snd_dice_transaction_write_tx(dice,
347 params->size * i + TX_ISOCHRONOUS,
350 err = snd_dice_transaction_write_rx(dice,
351 params->size * i + RX_ISOCHRONOUS,
357 if (dir == AMDTP_IN_STREAM) {
358 reg = cpu_to_be32(max_speed);
359 err = snd_dice_transaction_write_tx(dice,
360 params->size * i + TX_SPEED,
366 err = amdtp_domain_add_stream(&dice->domain, stream,
367 resources->channel, max_speed);
376 * MEMO: After this function, there're two states of streams:
377 * - None streams are running.
378 * - All streams are running.
380 int snd_dice_stream_start_duplex(struct snd_dice *dice)
382 unsigned int generation = dice->rx_resources[0].generation;
383 struct reg_params tx_params, rx_params;
386 enum snd_dice_rate_mode mode;
389 if (dice->substreams_counter == 0)
392 err = get_register_params(dice, &tx_params, &rx_params);
396 // Check error of packet streaming.
397 for (i = 0; i < MAX_STREAMS; ++i) {
398 if (amdtp_streaming_error(&dice->tx_stream[i]) ||
399 amdtp_streaming_error(&dice->rx_stream[i])) {
400 amdtp_domain_stop(&dice->domain);
401 finish_session(dice, &tx_params, &rx_params);
406 if (generation != fw_parent_device(dice->unit)->card->generation) {
407 for (i = 0; i < MAX_STREAMS; ++i) {
408 if (i < tx_params.count)
409 fw_iso_resources_update(dice->tx_resources + i);
410 if (i < rx_params.count)
411 fw_iso_resources_update(dice->rx_resources + i);
415 // Check required streams are running or not.
416 err = snd_dice_transaction_get_rate(dice, &rate);
419 err = snd_dice_stream_get_rate_mode(dice, rate, &mode);
422 for (i = 0; i < MAX_STREAMS; ++i) {
423 if (dice->tx_pcm_chs[i][mode] > 0 &&
424 !amdtp_stream_running(&dice->tx_stream[i]))
426 if (dice->rx_pcm_chs[i][mode] > 0 &&
427 !amdtp_stream_running(&dice->rx_stream[i]))
430 if (i < MAX_STREAMS) {
431 // Start both streams.
432 err = start_streams(dice, AMDTP_IN_STREAM, rate, &tx_params);
436 err = start_streams(dice, AMDTP_OUT_STREAM, rate, &rx_params);
440 err = snd_dice_transaction_set_enable(dice);
442 dev_err(&dice->unit->device,
443 "fail to enable interface\n");
447 // MEMO: The device immediately starts packet transmission when enabled. Some
448 // devices are strictly to generate any discontinuity in the sequence of tx packet
449 // when they receives invalid sequence of presentation time in CIP header. The
450 // sequence replay for media clock recovery can suppress the behaviour.
451 err = amdtp_domain_start(&dice->domain, 0, true, false);
455 if (!amdtp_domain_wait_ready(&dice->domain, READY_TIMEOUT_MS)) {
463 amdtp_domain_stop(&dice->domain);
464 finish_session(dice, &tx_params, &rx_params);
469 * MEMO: After this function, there're two states of streams:
470 * - None streams are running.
471 * - All streams are running.
473 void snd_dice_stream_stop_duplex(struct snd_dice *dice)
475 struct reg_params tx_params, rx_params;
477 if (dice->substreams_counter == 0) {
478 if (get_register_params(dice, &tx_params, &rx_params) >= 0)
479 finish_session(dice, &tx_params, &rx_params);
481 amdtp_domain_stop(&dice->domain);
482 release_resources(dice);
486 static int init_stream(struct snd_dice *dice, enum amdtp_stream_direction dir,
489 struct amdtp_stream *stream;
490 struct fw_iso_resources *resources;
493 if (dir == AMDTP_IN_STREAM) {
494 stream = &dice->tx_stream[index];
495 resources = &dice->tx_resources[index];
497 stream = &dice->rx_stream[index];
498 resources = &dice->rx_resources[index];
501 err = fw_iso_resources_init(resources, dice->unit);
504 resources->channels_mask = 0x00000000ffffffffuLL;
506 err = amdtp_am824_init(stream, dice->unit, dir, CIP_BLOCKING);
508 amdtp_stream_destroy(stream);
509 fw_iso_resources_destroy(resources);
516 * This function should be called before starting streams or after stopping
519 static void destroy_stream(struct snd_dice *dice,
520 enum amdtp_stream_direction dir,
523 struct amdtp_stream *stream;
524 struct fw_iso_resources *resources;
526 if (dir == AMDTP_IN_STREAM) {
527 stream = &dice->tx_stream[index];
528 resources = &dice->tx_resources[index];
530 stream = &dice->rx_stream[index];
531 resources = &dice->rx_resources[index];
534 amdtp_stream_destroy(stream);
535 fw_iso_resources_destroy(resources);
538 int snd_dice_stream_init_duplex(struct snd_dice *dice)
542 for (i = 0; i < MAX_STREAMS; i++) {
543 err = init_stream(dice, AMDTP_IN_STREAM, i);
546 destroy_stream(dice, AMDTP_IN_STREAM, i);
551 for (i = 0; i < MAX_STREAMS; i++) {
552 err = init_stream(dice, AMDTP_OUT_STREAM, i);
555 destroy_stream(dice, AMDTP_OUT_STREAM, i);
556 for (i = 0; i < MAX_STREAMS; i++)
557 destroy_stream(dice, AMDTP_IN_STREAM, i);
562 err = amdtp_domain_init(&dice->domain);
564 for (i = 0; i < MAX_STREAMS; ++i) {
565 destroy_stream(dice, AMDTP_OUT_STREAM, i);
566 destroy_stream(dice, AMDTP_IN_STREAM, i);
573 void snd_dice_stream_destroy_duplex(struct snd_dice *dice)
577 for (i = 0; i < MAX_STREAMS; i++) {
578 destroy_stream(dice, AMDTP_IN_STREAM, i);
579 destroy_stream(dice, AMDTP_OUT_STREAM, i);
582 amdtp_domain_destroy(&dice->domain);
585 void snd_dice_stream_update_duplex(struct snd_dice *dice)
587 struct reg_params tx_params, rx_params;
590 * On a bus reset, the DICE firmware disables streaming and then goes
591 * off contemplating its own navel for hundreds of milliseconds before
592 * it can react to any of our attempts to reenable streaming. This
593 * means that we lose synchronization anyway, so we force our streams
594 * to stop so that the application can restart them in an orderly
597 dice->global_enabled = false;
599 if (get_register_params(dice, &tx_params, &rx_params) == 0) {
600 amdtp_domain_stop(&dice->domain);
602 stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
603 stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
607 int snd_dice_stream_detect_current_formats(struct snd_dice *dice)
610 enum snd_dice_rate_mode mode;
612 struct reg_params tx_params, rx_params;
616 /* If extended protocol is available, detect detail spec. */
617 err = snd_dice_detect_extension_formats(dice);
622 * Available stream format is restricted at current mode of sampling
625 err = snd_dice_transaction_get_rate(dice, &rate);
629 err = snd_dice_stream_get_rate_mode(dice, rate, &mode);
634 * Just after owning the unit (GLOBAL_OWNER), the unit can return
635 * invalid stream formats. Selecting clock parameters have an effect
636 * for the unit to refine it.
638 err = select_clock(dice, rate);
642 err = get_register_params(dice, &tx_params, &rx_params);
646 for (i = 0; i < tx_params.count; ++i) {
647 err = snd_dice_transaction_read_tx(dice,
648 tx_params.size * i + TX_NUMBER_AUDIO,
652 dice->tx_pcm_chs[i][mode] = be32_to_cpu(reg[0]);
653 dice->tx_midi_ports[i] = max_t(unsigned int,
654 be32_to_cpu(reg[1]), dice->tx_midi_ports[i]);
656 for (i = 0; i < rx_params.count; ++i) {
657 err = snd_dice_transaction_read_rx(dice,
658 rx_params.size * i + RX_NUMBER_AUDIO,
662 dice->rx_pcm_chs[i][mode] = be32_to_cpu(reg[0]);
663 dice->rx_midi_ports[i] = max_t(unsigned int,
664 be32_to_cpu(reg[1]), dice->rx_midi_ports[i]);
670 static void dice_lock_changed(struct snd_dice *dice)
672 dice->dev_lock_changed = true;
673 wake_up(&dice->hwdep_wait);
676 int snd_dice_stream_lock_try(struct snd_dice *dice)
680 spin_lock_irq(&dice->lock);
682 if (dice->dev_lock_count < 0) {
687 if (dice->dev_lock_count++ == 0)
688 dice_lock_changed(dice);
691 spin_unlock_irq(&dice->lock);
695 void snd_dice_stream_lock_release(struct snd_dice *dice)
697 spin_lock_irq(&dice->lock);
699 if (WARN_ON(dice->dev_lock_count <= 0))
702 if (--dice->dev_lock_count == 0)
703 dice_lock_changed(dice);
705 spin_unlock_irq(&dice->lock);