4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define DATA_TYPE uint64_t
27 #define DATA_TYPE uint32_t
31 #define DATA_TYPE uint16_t
32 #define DATA_STYPE int16_t
36 #define DATA_TYPE uint8_t
37 #define DATA_STYPE int8_t
39 #error unsupported data size
44 #define CPU_MEM_INDEX 0
45 #define MMUSUFFIX _mmu
47 #elif ACCESS_TYPE == 1
49 #define CPU_MEM_INDEX 1
50 #define MMUSUFFIX _mmu
52 #elif ACCESS_TYPE == 2
55 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
56 #elif defined (TARGET_PPC)
57 #define CPU_MEM_INDEX (msr_pr)
58 #elif defined (TARGET_SPARC)
59 #define CPU_MEM_INDEX ((env->psrs) == 0)
61 #define MMUSUFFIX _mmu
63 #elif ACCESS_TYPE == 3
66 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
67 #elif defined (TARGET_PPC)
68 #define CPU_MEM_INDEX (msr_pr)
69 #elif defined (TARGET_SPARC)
70 #define CPU_MEM_INDEX ((env->psrs) == 0)
72 #define MMUSUFFIX _cmmu
75 #error invalid ACCESS_TYPE
79 #define RES_TYPE uint64_t
85 DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
87 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
89 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
90 (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
92 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
96 asm volatile ("movl %1, %%edx\n"
101 "leal %5(%%edx, %%ebp), %%edx\n"
102 "cmpl (%%edx), %%eax\n"
111 "addl 4(%%edx), %%eax\n"
113 "movzbl (%%eax), %0\n"
115 "movzwl (%%eax), %0\n"
119 #error unsupported size
124 "i" ((CPU_TLB_SIZE - 1) << 3),
125 "i" (TARGET_PAGE_BITS - 3),
126 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
127 "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
129 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
130 : "%eax", "%ecx", "%edx", "memory", "cc");
135 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
139 asm volatile ("movl %1, %%edx\n"
144 "leal %5(%%edx, %%ebp), %%edx\n"
145 "cmpl (%%edx), %%eax\n"
156 #error unsupported size
160 "addl 4(%%edx), %%eax\n"
162 "movsbl (%%eax), %0\n"
164 "movswl (%%eax), %0\n"
166 #error unsupported size
171 "i" ((CPU_TLB_SIZE - 1) << 3),
172 "i" (TARGET_PAGE_BITS - 3),
173 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
174 "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
176 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
177 : "%eax", "%ecx", "%edx", "memory", "cc");
182 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
184 asm volatile ("movl %0, %%edx\n"
189 "leal %5(%%edx, %%ebp), %%edx\n"
190 "cmpl (%%edx), %%eax\n"
194 "movzbl %b1, %%edx\n"
196 "movzwl %w1, %%edx\n"
200 #error unsupported size
207 "addl 4(%%edx), %%eax\n"
209 "movb %b1, (%%eax)\n"
211 "movw %w1, (%%eax)\n"
215 #error unsupported size
220 /* NOTE: 'q' would be needed as constraint, but we could not use it
223 "i" ((CPU_TLB_SIZE - 1) << 3),
224 "i" (TARGET_PAGE_BITS - 3),
225 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
226 "m" (*(uint32_t *)offsetof(CPUState, tlb_write[CPU_MEM_INDEX][0].address)),
228 "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
229 : "%eax", "%ecx", "%edx", "memory", "cc");
234 /* generic load/store macros */
236 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
241 unsigned long physaddr;
245 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
246 is_user = CPU_MEM_INDEX;
247 if (__builtin_expect(env->tlb_read[is_user][index].address !=
248 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
249 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
251 physaddr = addr + env->tlb_read[is_user][index].addend;
252 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
258 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
262 unsigned long physaddr;
266 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
267 is_user = CPU_MEM_INDEX;
268 if (__builtin_expect(env->tlb_read[is_user][index].address !=
269 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
270 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
272 physaddr = addr + env->tlb_read[is_user][index].addend;
273 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
279 /* generic store macro */
281 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
285 unsigned long physaddr;
289 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
290 is_user = CPU_MEM_INDEX;
291 if (__builtin_expect(env->tlb_write[is_user][index].address !=
292 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
293 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
295 physaddr = addr + env->tlb_write[is_user][index].addend;
296 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
303 static inline double glue(ldfq, MEMSUFFIX)(target_ulong ptr)
309 u.i = glue(ldq, MEMSUFFIX)(ptr);
313 static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, double v)
320 glue(stq, MEMSUFFIX)(ptr, u.i);
322 #endif /* DATA_SIZE == 8 */
325 static inline float glue(ldfl, MEMSUFFIX)(target_ulong ptr)
331 u.i = glue(ldl, MEMSUFFIX)(ptr);
335 static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float v)
342 glue(stl, MEMSUFFIX)(ptr, u.i);
344 #endif /* DATA_SIZE == 4 */