29 unsigned int op0, psw;
32 temp = (State.regs[OP[0]] << 23) >> 23;
36 if ((psw & PSW_OV) != 0)
46 unsigned int op0, psw;
49 temp = (State.regs[OP[0]] << 23) >> 23;
53 if ((psw & PSW_CY) != 0)
63 unsigned int op0, psw;
66 temp = (State.regs[OP[0]] << 23) >> 23;
70 if ((psw & PSW_Z) != 0)
80 unsigned int op0, psw;
83 temp = (State.regs[OP[0]] << 23) >> 23;
87 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
97 unsigned int op0, psw;
100 temp = (State.regs[OP[0]] << 23) >> 23;
104 if ((psw & PSW_S) != 0)
117 temp = (State.regs[OP[0]] << 23) >> 23;
126 unsigned int op0, psw;
129 temp = (State.regs[OP[0]] << 23) >> 23;
133 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
143 unsigned int op0, psw;
146 temp = (State.regs[OP[0]] << 23) >> 23;
150 if ((((psw & PSW_Z) != 0)
151 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
161 unsigned int op0, psw;
164 temp = (State.regs[OP[0]] << 23) >> 23;
168 if ((psw & PSW_OV) == 0)
178 unsigned int op0, psw;
181 temp = (State.regs[OP[0]] << 23) >> 23;
185 if ((psw & PSW_CY) == 0)
195 unsigned int op0, psw;
198 temp = (State.regs[OP[0]] << 23) >> 23;
202 if ((psw & PSW_Z) == 0)
212 unsigned int op0, psw;
215 temp = (State.regs[OP[0]] << 23) >> 23;
219 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
229 unsigned int op0, psw;
232 temp = (State.regs[OP[0]] << 23) >> 23;
236 if ((psw & PSW_S) == 0)
246 unsigned int op0, psw;
249 temp = (State.regs[OP[0]] << 23) >> 23;
253 if ((psw & PSW_SAT) != 0)
263 unsigned int op0, psw;
266 temp = (State.regs[OP[0]] << 23) >> 23;
270 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
280 unsigned int op0, psw;
283 temp = (State.regs[OP[0]] << 23) >> 23;
287 if ((((psw & PSW_Z) != 0)
288 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
298 /* interp.c will bump this by +2, so correct for it here. */
299 State.pc = State.regs[OP[0]] - 2;
302 /* jarl disp22, reg */
306 unsigned int op0, opc;
310 temp = (temp << 10) >> 10;
316 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
318 State.regs[OP[1]] = opc + 4;
325 unsigned int op0, op1, result, z, s, cy, ov;
327 /* Compute the result. */
328 op0 = State.regs[OP[0]];
329 op1 = State.regs[OP[1]];
332 /* Compute the condition codes. */
334 s = (result & 0x80000000);
335 cy = (result < op0 || result < op1);
336 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
337 && (op0 & 0x80000000) != (result & 0x80000000));
339 /* Store the result and condition codes. */
340 State.regs[OP[1]] = result;
341 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
342 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
343 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
346 /* add sign_extend(imm5), reg */
350 unsigned int op0, op1, result, z, s, cy, ov;
353 /* Compute the result. */
354 temp = (OP[0] & 0x1f);
355 temp = (temp << 27) >> 27;
357 op1 = State.regs[OP[1]];
360 /* Compute the condition codes. */
362 s = (result & 0x80000000);
363 cy = (result < op0 || result < op1);
364 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
365 && (op0 & 0x80000000) != (result & 0x80000000));
367 /* Store the result and condition codes. */
368 State.regs[OP[1]] = result;
369 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
370 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
371 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
374 /* addi sign_extend(imm16), reg, reg */
378 unsigned int op0, op1, result, z, s, cy, ov;
381 /* Compute the result. */
382 temp = (OP[0] & 0xffff);
383 temp = (temp << 16) >> 16;
385 op1 = State.regs[OP[1]];
388 /* Compute the condition codes. */
390 s = (result & 0x80000000);
391 cy = (result < op0 || result < op1);
392 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
393 && (op0 & 0x80000000) != (result & 0x80000000));
395 /* Store the result and condition codes. */
396 State.regs[OP[2]] = result;
397 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
398 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
399 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
406 unsigned int op0, op1, result, z, s, cy, ov;
408 /* Compute the result. */
409 op0 = State.regs[OP[0]];
410 op1 = State.regs[OP[1]];
413 /* Compute the condition codes. */
415 s = (result & 0x80000000);
416 cy = (result < -op0);
417 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
418 && (op1 & 0x80000000) != (result & 0x80000000));
420 /* Store the result and condition codes. */
421 State.regs[OP[1]] = result;
422 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
423 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
424 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
427 /* subr reg1, reg2 */
431 unsigned int op0, op1, result, z, s, cy, ov;
433 /* Compute the result. */
434 op0 = State.regs[OP[0]];
435 op1 = State.regs[OP[1]];
438 /* Compute the condition codes. */
440 s = (result & 0x80000000);
441 cy = (result < -op1);
442 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
443 && (op0 & 0x80000000) != (result & 0x80000000));
445 /* Store the result and condition codes. */
446 State.regs[OP[1]] = result;
447 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
448 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
449 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
452 /* mulh reg1, reg2 */
456 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
457 * (State.regs[OP[0]] & 0xffff));
460 /* mulh sign_extend(imm5), reg2
468 value = (value << 27) >> 27;
470 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
473 /* mulhi imm16, reg1, reg2 */
479 value = value & 0xffff;
481 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
484 /* divh reg1, reg2 */
488 unsigned int op0, op1, result, z, s, cy, ov;
491 /* Compute the result. */
492 temp = State.regs[OP[0]] & 0xffff;
493 temp = (temp << 16) >> 16;
495 op1 = State.regs[OP[1]];
497 if (op0 == 0xffffffff && op1 == 0x80000000)
510 /* Compute the condition codes. */
512 s = (result & 0x80000000);
514 /* Store the result and condition codes. */
515 State.regs[OP[1]] = result;
516 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
517 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
518 | (ov ? PSW_OV : 0));
525 unsigned int op0, op1, result, z, s, cy, ov;
527 /* Compute the result. */
528 op0 = State.regs[OP[0]];
529 op1 = State.regs[OP[1]];
532 /* Compute the condition codes. */
534 s = (result & 0x80000000);
535 cy = (result < -op0);
536 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
537 && (op1 & 0x80000000) != (result & 0x80000000));
539 /* Set condition codes. */
540 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
541 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
542 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
545 /* cmp sign_extend(imm5), reg */
549 unsigned int op0, op1, result, z, s, cy, ov;
552 /* Compute the result. */
554 temp = (temp << 27) >> 27;
556 op1 = State.regs[OP[1]];
559 /* Compute the condition codes. */
561 s = (result & 0x80000000);
562 cy = (result < -op0);
563 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
564 && (op1 & 0x80000000) != (result & 0x80000000));
566 /* Set condition codes. */
567 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
568 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
569 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
576 /* Hack alert. We turn off a bit in op0 since we really only
578 unsigned int op0, psw, result;
586 result = ((psw & PSW_OV) != 0);
589 result = ((psw & PSW_CY) != 0);
592 result = ((psw & PSW_Z) != 0);
595 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
598 result = ((psw & PSW_S) != 0);
604 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
607 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
608 || ((psw & PSW_Z) != 0)) != 0);
611 result = ((psw & PSW_OV) == 0);
614 result = ((psw & PSW_CY) == 0);
617 result = ((psw & PSW_Z) == 0);
620 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
623 result = ((psw & PSW_S) == 0);
626 result = ((psw & PSW_SAT) != 0);
629 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
632 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
633 || ((psw & PSW_Z) != 0)) == 0);
637 State.regs[OP[1]] = result;
644 unsigned int op0, op1, result, z, s, cy, ov;
646 /* Compute the result. */
647 op0 = State.regs[OP[0]];
648 op1 = State.regs[OP[1]];
651 /* Compute the condition codes. */
653 s = (result & 0x80000000);
655 /* Store the condition codes. */
656 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
657 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
684 State.regs[OP[1]] = State.regs[OP[0]];
687 /* mov sign_extend(imm5), reg */
693 value = (value << 27) >> 27;
694 State.regs[OP[1]] = value;
697 /* movea sign_extend(imm16), reg, reg */
704 value = (value << 16) >> 16;
706 State.regs[OP[2]] = State.regs[OP[1]] + value;
709 /* movhi imm16, reg, reg */
715 value = (value & 0xffff) << 16;
717 State.regs[OP[2]] = State.regs[OP[1]] + value;
745 /* sar zero_extend(imm5),reg1 */
749 unsigned int op0, op1, result, z, s, cy, ov;
752 op1 = State.regs[OP[1]];
753 result = (signed)op1 >> op0;
755 /* Compute the condition codes. */
757 s = (result & 0x80000000);
758 cy = (op1 & (1 << (op0 - 1)));
760 /* Store the result and condition codes. */
761 State.regs[OP[1]] = result;
762 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
763 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
764 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
771 unsigned int op0, op1, result, z, s, cy, ov;
773 op0 = State.regs[OP[0]] & 0x1f;
774 op1 = State.regs[OP[1]];
775 result = (signed)op1 >> op0;
777 /* Compute the condition codes. */
779 s = (result & 0x80000000);
780 cy = (op1 & (1 << (op0 - 1)));
782 /* Store the result and condition codes. */
783 State.regs[OP[1]] = result;
784 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
785 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
786 | (cy ? PSW_CY : 0));
789 /* shl zero_extend(imm5),reg1 */
793 unsigned int op0, op1, result, z, s, cy, ov;
796 op1 = State.regs[OP[1]];
799 /* Compute the condition codes. */
801 s = (result & 0x80000000);
802 cy = (op1 & (1 << (32 - op0)));
804 /* Store the result and condition codes. */
805 State.regs[OP[1]] = result;
806 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
807 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
808 | (cy ? PSW_CY : 0));
815 unsigned int op0, op1, result, z, s, cy, ov;
817 op0 = State.regs[OP[0]] & 0x1f;
818 op1 = State.regs[OP[1]];
821 /* Compute the condition codes. */
823 s = (result & 0x80000000);
824 cy = (op1 & (1 << (32 - op0)));
826 /* Store the result and condition codes. */
827 State.regs[OP[1]] = result;
828 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
829 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
830 | (cy ? PSW_CY : 0));
833 /* shr zero_extend(imm5),reg1 */
837 unsigned int op0, op1, result, z, s, cy, ov;
840 op1 = State.regs[OP[1]];
843 /* Compute the condition codes. */
845 s = (result & 0x80000000);
846 cy = (op1 & (1 << (op0 - 1)));
848 /* Store the result and condition codes. */
849 State.regs[OP[1]] = result;
850 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
851 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
852 | (cy ? PSW_CY : 0));
859 unsigned int op0, op1, result, z, s, cy, ov;
861 op0 = State.regs[OP[0]] & 0x1f;
862 op1 = State.regs[OP[1]];
865 /* Compute the condition codes. */
867 s = (result & 0x80000000);
868 cy = (op1 & (1 << (op0 - 1)));
870 /* Store the result and condition codes. */
871 State.regs[OP[1]] = result;
872 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
873 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
874 | (cy ? PSW_CY : 0));
891 unsigned int op0, op1, result, z, s, cy, ov;
893 /* Compute the result. */
894 op0 = State.regs[OP[0]];
895 op1 = State.regs[OP[1]];
898 /* Compute the condition codes. */
900 s = (result & 0x80000000);
902 /* Store the result and condition codes. */
903 State.regs[OP[1]] = result;
904 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
905 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
908 /* ori zero_extend(imm16), reg, reg */
912 unsigned int op0, op1, result, z, s, cy, ov;
914 op0 = OP[0] & 0xffff;
915 op1 = State.regs[OP[1]];
918 /* Compute the condition codes. */
920 s = (result & 0x80000000);
922 /* Store the result and condition codes. */
923 State.regs[OP[2]] = result;
924 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
925 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
932 unsigned int op0, op1, result, z, s, cy, ov;
934 /* Compute the result. */
935 op0 = State.regs[OP[0]];
936 op1 = State.regs[OP[1]];
939 /* Compute the condition codes. */
941 s = (result & 0x80000000);
943 /* Store the result and condition codes. */
944 State.regs[OP[1]] = result;
945 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
946 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
949 /* andi zero_extend(imm16), reg, reg */
953 unsigned int op0, op1, result, z, s, cy, ov;
955 op0 = OP[0] & 0xffff;
956 op1 = State.regs[OP[1]];
959 /* Compute the condition codes. */
962 /* Store the result and condition codes. */
963 State.regs[OP[2]] = result;
964 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
965 State.psw |= (z ? PSW_Z : 0);
972 unsigned int op0, op1, result, z, s, cy, ov;
974 /* Compute the result. */
975 op0 = State.regs[OP[0]];
976 op1 = State.regs[OP[1]];
979 /* Compute the condition codes. */
981 s = (result & 0x80000000);
983 /* Store the result and condition codes. */
984 State.regs[OP[1]] = result;
985 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
986 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
989 /* xori zero_extend(imm16), reg, reg */
993 unsigned int op0, op1, result, z, s, cy, ov;
995 op0 = OP[0] & 0xffff;
996 op1 = State.regs[OP[1]];
999 /* Compute the condition codes. */
1001 s = (result & 0x80000000);
1003 /* Store the result and condition codes. */
1004 State.regs[OP[2]] = result;
1005 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1006 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1009 /* not reg1, reg2 */
1013 unsigned int op0, result, z, s, cy, ov;
1015 /* Compute the result. */
1016 op0 = State.regs[OP[0]];
1019 /* Compute the condition codes. */
1021 s = (result & 0x80000000);
1023 /* Store the result and condition codes. */
1024 State.regs[OP[1]] = result;
1025 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1026 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1053 State.psw |= PSW_ID;
1060 State.psw &= ~PSW_ID;
1063 /* halt, not supported */
1070 /* reti, not supported */
1077 /* trap, not supportd */
1084 /* ldsr, not supported */
1091 /* stsr, not supported */