30 /* FIXME - should be including a version of syscall.h that does not
31 pollute the name space */
32 #include "../../libgloss/v850/sys/syscall.h"
34 #include "libiberty.h"
37 #if !defined(__GO32__) && !defined(_WIN32)
39 #include <sys/times.h>
43 /* start-sanitize-v850e */
44 /* This is an array of the bit positions of registers r20 .. r31 in
45 that order in a prepare/dispose instruction. */
46 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
47 /* end-sanitize-v850e */
48 /* start-sanitize-v850eq */
49 /* This is an array of the bit positions of registers r16 .. r31 in
50 that order in a push/pop instruction. */
51 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
52 /* This is an array of the bit positions of registers r1 .. r15 in
53 that order in a push/pop instruction. */
54 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
55 /* end-sanitize-v850eq */
58 #ifndef SIZE_INSTRUCTION
59 #define SIZE_INSTRUCTION 6
63 #define SIZE_OPERANDS 16
67 #define SIZE_VALUES 11
71 #define SIZE_LOCATION 40
76 trace_input (name, type, size)
86 const char *functionname;
87 unsigned int linenumber;
89 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
94 if (STATE_TEXT_SECTION (simulator)
95 && PC >= STATE_TEXT_START (simulator)
96 && PC < STATE_TEXT_END (simulator))
98 filename = (const char *)0;
99 functionname = (const char *)0;
101 if (bfd_find_nearest_line (STATE_PROG_BFD (simulator),
102 STATE_TEXT_SECTION (simulator),
103 (struct symbol_cache_entry **)0,
104 PC - STATE_TEXT_START (simulator),
105 &filename, &functionname, &linenumber))
110 sprintf (p, "Line %5d ", linenumber);
116 sprintf (p, "Func %s ", functionname);
121 char *q = (char *) strrchr (filename, '/');
122 sprintf (p, "File %s ", (q) ? q+1 : filename);
131 trace_printf (simulator, STATE_CPU (simulator, 0),
132 "0x%.8x: %-*.*s %-*s",
134 SIZE_LOCATION, SIZE_LOCATION, buf,
135 SIZE_INSTRUCTION, name);
147 case OP_REG_REG_MOVE:
148 values[0] = State.regs[OP[0]];
152 /* start-sanitize-v850e */
154 /* end-sanitize-v850e */
157 values[0] = State.regs[OP[1]];
158 values[1] = State.regs[OP[0]];
164 values[0] = SEXT5 (OP[0]);
169 case OP_IMM_REG_MOVE:
170 values[0] = SEXT5 (OP[0]);
175 values[0] = State.pc;
176 values[1] = SEXT9 (OP[0]);
182 values[0] = OP[1] * size;
183 values[1] = State.regs[30];
188 values[0] = State.regs[OP[0]];
189 values[1] = OP[1] * size;
190 values[2] = State.regs[30];
195 values[0] = EXTEND16 (OP[2]);
196 values[1] = State.regs[OP[0]];
201 values[0] = State.regs[OP[1]];
202 values[1] = EXTEND16 (OP[2]);
203 values[2] = State.regs[OP[0]];
208 values[0] = SEXT22 (OP[0]);
209 values[1] = State.pc;
214 values[0] = EXTEND16 (OP[0]) << size;
215 values[1] = State.regs[OP[1]];
219 case OP_UIMM_REG_REG:
220 values[0] = (OP[0] & 0xffff) << size;
221 values[1] = State.regs[OP[1]];
239 values[0] = State.regs[OP[0]];
244 values[0] = State.sregs[OP[1]];
248 for (i = 0; i < num_values; i++)
249 trace_printf (simulator, STATE_CPU (simulator, 0),
250 "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
253 trace_printf (simulator, STATE_CPU (simulator, 0),
254 "%*s", SIZE_VALUES, "");
258 trace_output (result)
259 enum op_types result;
261 if (TRACE_ALU_P (STATE_CPU (simulator, 0)))
281 trace_printf (simulator, STATE_CPU (simulator, 0),
282 " :: 0x%.8lx", (unsigned long)State.regs[OP[0]]);
286 case OP_REG_REG_MOVE:
288 case OP_IMM_REG_MOVE:
291 trace_printf (simulator, STATE_CPU (simulator, 0),
292 " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
296 case OP_UIMM_REG_REG:
297 trace_printf (simulator, STATE_CPU (simulator, 0),
298 " :: 0x%.8lx", (unsigned long)State.regs[OP[2]]);
303 trace_printf (simulator, STATE_CPU (simulator, 0),
304 " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
308 trace_printf (simulator, STATE_CPU (simulator, 0),
309 " :: 0x%.8lx", (unsigned long)State.sregs[OP[1]]);
313 trace_printf (simulator, STATE_CPU (simulator, 0),
321 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
323 condition_met (unsigned code)
325 unsigned int psw = PSW;
329 case 0x0: return ((psw & PSW_OV) != 0);
330 case 0x1: return ((psw & PSW_CY) != 0);
331 case 0x2: return ((psw & PSW_Z) != 0);
332 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
333 case 0x4: return ((psw & PSW_S) != 0);
334 /*case 0x5: return 1;*/
335 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
336 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
337 case 0x8: return ((psw & PSW_OV) == 0);
338 case 0x9: return ((psw & PSW_CY) == 0);
339 case 0xa: return ((psw & PSW_Z) == 0);
340 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
341 case 0xc: return ((psw & PSW_S) == 0);
342 case 0xd: return ((psw & PSW_SAT) != 0);
343 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
344 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
349 /* start-sanitize-v850e */
352 Add32 (unsigned long a1, unsigned long a2, int * carry)
354 unsigned long result = (a1 + a2);
356 * carry = (result < a1);
362 Multiply64 (boolean sign, unsigned long op0)
373 op1 = State.regs[ OP[1] ];
377 /* Compute sign of result and adjust operands if necessary. */
379 sign = (op0 ^ op1) & 0x80000000;
381 if (((signed long) op0) < 0)
384 if (((signed long) op1) < 0)
388 /* We can split the 32x32 into four 16x16 operations. This ensures
389 that we do not lose precision on 32bit only hosts: */
390 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
391 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
392 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
393 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
395 /* We now need to add all of these results together, taking care
396 to propogate the carries from the additions: */
397 RdLo = Add32 (lo, (mid1 << 16), & carry);
399 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
400 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
404 /* Negate result if necessary. */
408 if (RdLo == 0xFFFFFFFF)
417 /* Don't store into register 0. */
419 State.regs[ OP[1] ] = RdLo;
421 State.regs[ OP[2] >> 11 ] = RdHi;
426 /* end-sanitize-v850e */
428 /* Read a null terminated string from memory, return in a buffer */
436 while (sim_core_read_1 (STATE_CPU (sd, 0),
437 PC, sim_core_read_map, addr + nr) != 0)
439 buf = NZALLOC (char, nr + 1);
440 sim_read (simulator, addr, buf, nr);
444 /* Read a null terminated argument vector from memory, return in a
447 fetch_argv (sd, addr)
453 char **buf = xmalloc (max_nr * sizeof (char*));
456 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
457 PC, sim_core_read_map, addr + nr * 4);
459 buf[nr] = fetch_str (sd, a);
461 if (nr == max_nr - 1)
464 buf = xrealloc (buf, max_nr * sizeof (char*));
476 unsigned long result;
478 result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
480 /* start-sanitize-v850eq */
483 trace_input ("sld.bu", OP_LOAD16, 1);
484 State.regs[ OP[1] ] = result;
488 /* end-sanitize-v850eq */
489 trace_input ("sld.b", OP_LOAD16, 1);
491 State.regs[ OP[1] ] = EXTEND8 (result);
492 /* start-sanitize-v850eq */
494 /* end-sanitize-v850eq */
496 trace_output (OP_LOAD16);
505 unsigned long result;
507 result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
509 /* start-sanitize-v850eq */
512 trace_input ("sld.hu", OP_LOAD16, 2);
513 State.regs[ OP[1] ] = result;
517 /* end-sanitize-v850eq */
518 trace_input ("sld.h", OP_LOAD16, 2);
520 State.regs[ OP[1] ] = EXTEND16 (result);
521 /* start-sanitize-v850eq */
523 /* end-sanitize-v850eq */
525 trace_output (OP_LOAD16);
534 trace_input ("sld.w", OP_LOAD16, 4);
536 State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
538 trace_output (OP_LOAD16);
547 trace_input ("sst.b", OP_STORE16, 1);
549 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
551 trace_output (OP_STORE16);
560 trace_input ("sst.h", OP_STORE16, 2);
562 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
564 trace_output (OP_STORE16);
573 trace_input ("sst.w", OP_STORE16, 4);
575 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
577 trace_output (OP_STORE16);
588 trace_input ("ld.b", OP_LOAD32, 1);
590 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
592 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
594 trace_output (OP_LOAD32);
605 trace_input ("ld.h", OP_LOAD32, 2);
607 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
610 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
612 trace_output (OP_LOAD32);
623 trace_input ("ld.w", OP_LOAD32, 4);
625 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
628 State.regs[ OP[1] ] = load_mem (adr, 4);
630 trace_output (OP_LOAD32);
639 trace_input ("st.b", OP_STORE32, 1);
641 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
643 trace_output (OP_STORE32);
654 trace_input ("st.h", OP_STORE32, 2);
656 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
659 store_mem (adr, 2, State.regs[ OP[1] ]);
661 trace_output (OP_STORE32);
672 trace_input ("st.w", OP_STORE32, 4);
674 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
677 store_mem (adr, 4, State.regs[ OP[1] ]);
679 trace_output (OP_STORE32);
687 trace_input ("Bcond", OP_COND_BR, 0);
688 trace_output (OP_COND_BR);
690 if (condition_met (code))
691 return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
808 /* jarl/jr disp22, reg */
812 trace_input ("jarl/jr", OP_JUMP, 0);
815 State.regs[ OP[1] ] = PC + 4;
817 trace_output (OP_JUMP);
819 return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
826 unsigned int op0, op1, result, z, s, cy, ov;
828 trace_input ("add", OP_REG_REG, 0);
830 /* Compute the result. */
832 op0 = State.regs[ OP[0] ];
833 op1 = State.regs[ OP[1] ];
837 /* Compute the condition codes. */
839 s = (result & 0x80000000);
840 cy = (result < op0 || result < op1);
841 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
842 && (op0 & 0x80000000) != (result & 0x80000000));
844 /* Store the result and condition codes. */
845 State.regs[OP[1]] = result;
846 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
847 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
848 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
849 trace_output (OP_REG_REG);
854 /* add sign_extend(imm5), reg */
858 unsigned int op0, op1, result, z, s, cy, ov;
861 trace_input ("add", OP_IMM_REG, 0);
863 /* Compute the result. */
864 temp = SEXT5 (OP[0]);
866 op1 = State.regs[OP[1]];
869 /* Compute the condition codes. */
871 s = (result & 0x80000000);
872 cy = (result < op0 || result < op1);
873 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
874 && (op0 & 0x80000000) != (result & 0x80000000));
876 /* Store the result and condition codes. */
877 State.regs[OP[1]] = result;
878 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
879 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
880 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
881 trace_output (OP_IMM_REG);
886 /* addi sign_extend(imm16), reg, reg */
890 unsigned int op0, op1, result, z, s, cy, ov;
892 trace_input ("addi", OP_IMM_REG_REG, 0);
894 /* Compute the result. */
896 op0 = EXTEND16 (OP[2]);
897 op1 = State.regs[ OP[0] ];
900 /* Compute the condition codes. */
902 s = (result & 0x80000000);
903 cy = (result < op0 || result < op1);
904 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
905 && (op0 & 0x80000000) != (result & 0x80000000));
907 /* Store the result and condition codes. */
908 State.regs[OP[1]] = result;
909 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
910 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
911 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
912 trace_output (OP_IMM_REG_REG);
921 unsigned int op0, op1, result, z, s, cy, ov;
923 trace_input ("sub", OP_REG_REG, 0);
924 /* Compute the result. */
925 op0 = State.regs[ OP[0] ];
926 op1 = State.regs[ OP[1] ];
929 /* Compute the condition codes. */
931 s = (result & 0x80000000);
933 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
934 && (op1 & 0x80000000) != (result & 0x80000000));
936 /* Store the result and condition codes. */
937 State.regs[OP[1]] = result;
938 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
939 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
940 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
941 trace_output (OP_REG_REG);
946 /* subr reg1, reg2 */
950 unsigned int op0, op1, result, z, s, cy, ov;
952 trace_input ("subr", OP_REG_REG, 0);
953 /* Compute the result. */
954 op0 = State.regs[ OP[0] ];
955 op1 = State.regs[ OP[1] ];
958 /* Compute the condition codes. */
960 s = (result & 0x80000000);
962 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
963 && (op0 & 0x80000000) != (result & 0x80000000));
965 /* Store the result and condition codes. */
966 State.regs[OP[1]] = result;
967 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
968 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
969 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
970 trace_output (OP_REG_REG);
976 /* mulh reg1, reg2 */
980 /* start-sanitize-v850e */
983 trace_input ("sxh", OP_REG, 0);
985 State.regs[ OP[0] ] = EXTEND16 (State.regs[ OP[0] ]);
987 trace_output (OP_REG);
990 /* end-sanitize-v850e */
992 trace_input ("mulh", OP_REG_REG, 0);
994 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
996 trace_output (OP_REG_REG);
1002 /* mulh sign_extend(imm5), reg2 */
1006 trace_input ("mulh", OP_IMM_REG, 0);
1008 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
1010 trace_output (OP_IMM_REG);
1015 /* mulhi imm16, reg1, reg2 */
1019 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1021 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
1023 trace_output (OP_IMM_REG_REG);
1028 /* divh reg1, reg2 */
1033 /* start-sanitize-v850e */
1038 trace_input ("switch", OP_REG, 0);
1040 adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
1041 State.pc = State.pc + 2 + (EXTEND16 (load_mem (adr, 2)) << 1);
1043 trace_output (OP_REG);
1046 /* end-sanitize-v850e */
1048 unsigned int op0, op1, result, ov, s, z;
1051 trace_input ("divh", OP_REG_REG, 0);
1053 /* Compute the result. */
1054 temp = EXTEND16 (State.regs[ OP[0] ]);
1056 op1 = State.regs[OP[1]];
1058 if (op0 == 0xffffffff && op1 == 0x80000000)
1060 result = 0x80000000;
1074 /* Compute the condition codes. */
1076 s = (result & 0x80000000);
1078 /* Store the result and condition codes. */
1079 State.regs[OP[1]] = result;
1080 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1081 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1082 | (ov ? PSW_OV : 0));
1083 trace_output (OP_REG_REG);
1093 unsigned int op0, op1, result, z, s, cy, ov;
1095 trace_input ("cmp", OP_REG_REG_CMP, 0);
1096 /* Compute the result. */
1097 op0 = State.regs[ OP[0] ];
1098 op1 = State.regs[ OP[1] ];
1101 /* Compute the condition codes. */
1103 s = (result & 0x80000000);
1105 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1106 && (op1 & 0x80000000) != (result & 0x80000000));
1108 /* Set condition codes. */
1109 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1110 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1111 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1112 trace_output (OP_REG_REG_CMP);
1117 /* cmp sign_extend(imm5), reg */
1121 unsigned int op0, op1, result, z, s, cy, ov;
1124 /* Compute the result. */
1125 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1126 temp = SEXT5 (OP[0]);
1128 op1 = State.regs[OP[1]];
1131 /* Compute the condition codes. */
1133 s = (result & 0x80000000);
1135 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1136 && (op1 & 0x80000000) != (result & 0x80000000));
1138 /* Set condition codes. */
1139 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1140 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1141 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1142 trace_output (OP_IMM_REG_CMP);
1147 /* setf cccc,reg2 */
1151 trace_input ("setf", OP_EX1, 0);
1153 State.regs[ OP[1] ] = condition_met (OP[0]);
1155 trace_output (OP_EX1);
1160 /* satadd reg,reg */
1164 unsigned int op0, op1, result, z, s, cy, ov, sat;
1166 trace_input ("satadd", OP_REG_REG, 0);
1167 /* Compute the result. */
1168 op0 = State.regs[ OP[0] ];
1169 op1 = State.regs[ OP[1] ];
1172 /* Compute the condition codes. */
1174 s = (result & 0x80000000);
1175 cy = (result < op0 || result < op1);
1176 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1177 && (op0 & 0x80000000) != (result & 0x80000000));
1180 /* Store the result and condition codes. */
1181 State.regs[OP[1]] = result;
1182 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1183 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1184 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1185 | (sat ? PSW_SAT : 0));
1187 /* Handle saturated results. */
1189 State.regs[OP[1]] = 0x80000000;
1191 State.regs[OP[1]] = 0x7fffffff;
1192 trace_output (OP_REG_REG);
1197 /* satadd sign_extend(imm5), reg */
1201 unsigned int op0, op1, result, z, s, cy, ov, sat;
1205 trace_input ("satadd", OP_IMM_REG, 0);
1207 /* Compute the result. */
1208 temp = SEXT5 (OP[0]);
1210 op1 = State.regs[OP[1]];
1213 /* Compute the condition codes. */
1215 s = (result & 0x80000000);
1216 cy = (result < op0 || result < op1);
1217 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1218 && (op0 & 0x80000000) != (result & 0x80000000));
1221 /* Store the result and condition codes. */
1222 State.regs[OP[1]] = result;
1223 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1224 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1225 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1226 | (sat ? PSW_SAT : 0));
1228 /* Handle saturated results. */
1230 State.regs[OP[1]] = 0x80000000;
1232 State.regs[OP[1]] = 0x7fffffff;
1233 trace_output (OP_IMM_REG);
1238 /* satsub reg1, reg2 */
1243 /* start-sanitize-v850e */
1246 trace_input ("sxb", OP_REG, 0);
1248 State.regs[ OP[0] ] = EXTEND8 (State.regs[ OP[0] ]);
1250 trace_output (OP_REG);
1253 /* end-sanitize-v850e */
1255 unsigned int op0, op1, result, z, s, cy, ov, sat;
1257 trace_input ("satsub", OP_REG_REG, 0);
1259 /* Compute the result. */
1260 op0 = State.regs[ OP[0] ];
1261 op1 = State.regs[ OP[1] ];
1264 /* Compute the condition codes. */
1266 s = (result & 0x80000000);
1268 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1269 && (op1 & 0x80000000) != (result & 0x80000000));
1272 /* Store the result and condition codes. */
1273 State.regs[OP[1]] = result;
1274 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1275 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1276 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1277 | (sat ? PSW_SAT : 0));
1279 /* Handle saturated results. */
1281 State.regs[OP[1]] = 0x80000000;
1283 State.regs[OP[1]] = 0x7fffffff;
1284 trace_output (OP_REG_REG);
1290 /* satsubi sign_extend(imm16), reg */
1294 unsigned int op0, op1, result, z, s, cy, ov, sat;
1297 trace_input ("satsubi", OP_IMM_REG, 0);
1299 /* Compute the result. */
1300 temp = EXTEND16 (OP[2]);
1302 op1 = State.regs[ OP[0] ];
1305 /* Compute the condition codes. */
1307 s = (result & 0x80000000);
1309 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1310 && (op1 & 0x80000000) != (result & 0x80000000));
1313 /* Store the result and condition codes. */
1314 State.regs[OP[1]] = result;
1315 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1316 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1317 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1318 | (sat ? PSW_SAT : 0));
1320 /* Handle saturated results. */
1322 State.regs[OP[1]] = 0x80000000;
1324 State.regs[OP[1]] = 0x7fffffff;
1325 trace_output (OP_IMM_REG);
1330 /* satsubr reg,reg */
1334 unsigned int op0, op1, result, z, s, cy, ov, sat;
1336 trace_input ("satsubr", OP_REG_REG, 0);
1338 /* Compute the result. */
1339 op0 = State.regs[ OP[0] ];
1340 op1 = State.regs[ OP[1] ];
1343 /* Compute the condition codes. */
1345 s = (result & 0x80000000);
1346 cy = (result < op0);
1347 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1348 && (op1 & 0x80000000) != (result & 0x80000000));
1351 /* Store the result and condition codes. */
1352 State.regs[OP[1]] = result;
1353 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1354 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1355 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1356 | (sat ? PSW_SAT : 0));
1358 /* Handle saturated results. */
1360 State.regs[OP[1]] = 0x80000000;
1362 State.regs[OP[1]] = 0x7fffffff;
1363 trace_output (OP_REG_REG);
1372 unsigned int op0, op1, result, z, s;
1374 trace_input ("tst", OP_REG_REG_CMP, 0);
1376 /* Compute the result. */
1377 op0 = State.regs[ OP[0] ];
1378 op1 = State.regs[ OP[1] ];
1381 /* Compute the condition codes. */
1383 s = (result & 0x80000000);
1385 /* Store the condition codes. */
1386 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1387 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1388 trace_output (OP_REG_REG_CMP);
1397 trace_input ("mov", OP_REG_REG_MOVE, 0);
1399 State.regs[ OP[1] ] = State.regs[ OP[0] ];
1401 trace_output (OP_REG_REG_MOVE);
1406 /* mov sign_extend(imm5), reg */
1411 /* start-sanitize-v850e */
1416 trace_input ("callt", OP_LOAD16, 1);
1421 adr = CTBP + ((OP[3] & 0x3f) << 1);
1423 PC = CTBP + load_mem (adr, 1);
1425 trace_output (OP_LOAD16);
1430 /* end-sanitize-v850e */
1432 int value = SEXT5 (OP[0]);
1434 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1436 State.regs[ OP[1] ] = value;
1438 trace_output (OP_IMM_REG_MOVE);
1444 /* mov imm32, reg1 */
1445 /* movea sign_extend(imm16), reg, reg */
1449 /* start-sanitize-v850e */
1452 trace_input ("mov", OP_IMM_REG, 4);
1454 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1456 trace_output (OP_IMM_REG);
1461 /* end-sanitize-v850e */
1463 trace_input ("movea", OP_IMM_REG_REG, 0);
1465 State.regs[ OP[1] ] = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
1467 trace_output (OP_IMM_REG_REG);
1473 /* dispose imm5, list12 [, reg1] */
1474 /* movhi imm16, reg, reg */
1478 /* start-sanitize-v850e */
1484 trace_input ("dispose", OP_PUSHPOP1, 0);
1486 SP += (OP[3] & 0x3e) << 1;
1488 /* Load the registers with lower number registers being retrieved from higher addresses. */
1490 if ((OP[3] & (1 << type1_regs[ i ])))
1492 State.regs[ 20 + i ] = load_mem (SP, 4);
1496 if ((OP[3] & 0x1f0000) != 0)
1498 PC = State.regs[ (OP[3] >> 16) & 0x1f];
1502 trace_output (OP_PUSHPOP1);
1505 /* end-sanitize-v850e */
1507 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1509 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1511 trace_output (OP_UIMM_REG_REG);
1517 /* sar zero_extend(imm5),reg1 */
1521 unsigned int op0, op1, result, z, s, cy;
1523 trace_input ("sar", OP_IMM_REG, 0);
1525 op1 = State.regs[ OP[1] ];
1526 result = (signed)op1 >> op0;
1528 /* Compute the condition codes. */
1530 s = (result & 0x80000000);
1531 cy = (op1 & (1 << (op0 - 1)));
1533 /* Store the result and condition codes. */
1534 State.regs[ OP[1] ] = result;
1535 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1536 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1537 | (cy ? PSW_CY : 0));
1538 trace_output (OP_IMM_REG);
1543 /* sar reg1, reg2 */
1547 unsigned int op0, op1, result, z, s, cy;
1549 trace_input ("sar", OP_REG_REG, 0);
1551 op0 = State.regs[ OP[0] ] & 0x1f;
1552 op1 = State.regs[ OP[1] ];
1553 result = (signed)op1 >> op0;
1555 /* Compute the condition codes. */
1557 s = (result & 0x80000000);
1558 cy = (op1 & (1 << (op0 - 1)));
1560 /* Store the result and condition codes. */
1561 State.regs[OP[1]] = result;
1562 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1563 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1564 | (cy ? PSW_CY : 0));
1565 trace_output (OP_REG_REG);
1570 /* shl zero_extend(imm5),reg1 */
1574 unsigned int op0, op1, result, z, s, cy;
1576 trace_input ("shl", OP_IMM_REG, 0);
1578 op1 = State.regs[ OP[1] ];
1579 result = op1 << op0;
1581 /* Compute the condition codes. */
1583 s = (result & 0x80000000);
1584 cy = (op1 & (1 << (32 - op0)));
1586 /* Store the result and condition codes. */
1587 State.regs[OP[1]] = result;
1588 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1589 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1590 | (cy ? PSW_CY : 0));
1591 trace_output (OP_IMM_REG);
1596 /* shl reg1, reg2 */
1600 unsigned int op0, op1, result, z, s, cy;
1602 trace_input ("shl", OP_REG_REG, 0);
1603 op0 = State.regs[ OP[0] ] & 0x1f;
1604 op1 = State.regs[ OP[1] ];
1605 result = op1 << op0;
1607 /* Compute the condition codes. */
1609 s = (result & 0x80000000);
1610 cy = (op1 & (1 << (32 - op0)));
1612 /* Store the result and condition codes. */
1613 State.regs[OP[1]] = result;
1614 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1615 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1616 | (cy ? PSW_CY : 0));
1617 trace_output (OP_REG_REG);
1622 /* shr zero_extend(imm5),reg1 */
1626 unsigned int op0, op1, result, z, s, cy;
1628 trace_input ("shr", OP_IMM_REG, 0);
1630 op1 = State.regs[ OP[1] ];
1631 result = op1 >> op0;
1633 /* Compute the condition codes. */
1635 s = (result & 0x80000000);
1636 cy = (op1 & (1 << (op0 - 1)));
1638 /* Store the result and condition codes. */
1639 State.regs[OP[1]] = result;
1640 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1641 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1642 | (cy ? PSW_CY : 0));
1643 trace_output (OP_IMM_REG);
1648 /* shr reg1, reg2 */
1652 unsigned int op0, op1, result, z, s, cy;
1654 trace_input ("shr", OP_REG_REG, 0);
1655 op0 = State.regs[ OP[0] ] & 0x1f;
1656 op1 = State.regs[ OP[1] ];
1657 result = op1 >> op0;
1659 /* Compute the condition codes. */
1661 s = (result & 0x80000000);
1662 cy = (op1 & (1 << (op0 - 1)));
1664 /* Store the result and condition codes. */
1665 State.regs[OP[1]] = result;
1666 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1667 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1668 | (cy ? PSW_CY : 0));
1669 trace_output (OP_REG_REG);
1678 unsigned int op0, op1, result, z, s;
1680 trace_input ("or", OP_REG_REG, 0);
1682 /* Compute the result. */
1683 op0 = State.regs[ OP[0] ];
1684 op1 = State.regs[ OP[1] ];
1687 /* Compute the condition codes. */
1689 s = (result & 0x80000000);
1691 /* Store the result and condition codes. */
1692 State.regs[OP[1]] = result;
1693 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1694 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1695 trace_output (OP_REG_REG);
1700 /* ori zero_extend(imm16), reg, reg */
1704 unsigned int op0, op1, result, z, s;
1706 trace_input ("ori", OP_UIMM_REG_REG, 0);
1708 op1 = State.regs[ OP[0] ];
1711 /* Compute the condition codes. */
1713 s = (result & 0x80000000);
1715 /* Store the result and condition codes. */
1716 State.regs[OP[1]] = result;
1717 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1718 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1719 trace_output (OP_UIMM_REG_REG);
1728 unsigned int op0, op1, result, z, s;
1730 trace_input ("and", OP_REG_REG, 0);
1732 /* Compute the result. */
1733 op0 = State.regs[ OP[0] ];
1734 op1 = State.regs[ OP[1] ];
1737 /* Compute the condition codes. */
1739 s = (result & 0x80000000);
1741 /* Store the result and condition codes. */
1742 State.regs[OP[1]] = result;
1743 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1744 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1745 trace_output (OP_REG_REG);
1750 /* andi zero_extend(imm16), reg, reg */
1754 unsigned int result, z;
1756 trace_input ("andi", OP_UIMM_REG_REG, 0);
1758 result = OP[2] & State.regs[ OP[0] ];
1760 /* Compute the condition codes. */
1763 /* Store the result and condition codes. */
1764 State.regs[ OP[1] ] = result;
1766 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1767 PSW |= (z ? PSW_Z : 0);
1769 trace_output (OP_UIMM_REG_REG);
1778 unsigned int op0, op1, result, z, s;
1780 trace_input ("xor", OP_REG_REG, 0);
1782 /* Compute the result. */
1783 op0 = State.regs[ OP[0] ];
1784 op1 = State.regs[ OP[1] ];
1787 /* Compute the condition codes. */
1789 s = (result & 0x80000000);
1791 /* Store the result and condition codes. */
1792 State.regs[OP[1]] = result;
1793 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1794 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1795 trace_output (OP_REG_REG);
1800 /* xori zero_extend(imm16), reg, reg */
1804 unsigned int op0, op1, result, z, s;
1806 trace_input ("xori", OP_UIMM_REG_REG, 0);
1808 op1 = State.regs[ OP[0] ];
1811 /* Compute the condition codes. */
1813 s = (result & 0x80000000);
1815 /* Store the result and condition codes. */
1816 State.regs[OP[1]] = result;
1817 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1818 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1819 trace_output (OP_UIMM_REG_REG);
1824 /* not reg1, reg2 */
1828 unsigned int op0, result, z, s;
1830 trace_input ("not", OP_REG_REG_MOVE, 0);
1831 /* Compute the result. */
1832 op0 = State.regs[ OP[0] ];
1835 /* Compute the condition codes. */
1837 s = (result & 0x80000000);
1839 /* Store the result and condition codes. */
1840 State.regs[OP[1]] = result;
1841 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1842 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1843 trace_output (OP_REG_REG_MOVE);
1852 unsigned int op0, op1, op2;
1855 trace_input ("set1", OP_BIT, 0);
1856 op0 = State.regs[ OP[0] ];
1858 temp = EXTEND16 (OP[2]);
1860 temp = load_mem (op0 + op2, 1);
1862 if ((temp & (1 << op1)) == 0)
1865 store_mem (op0 + op2, 1, temp);
1866 trace_output (OP_BIT);
1875 unsigned int op0, op1, op2;
1878 trace_input ("not1", OP_BIT, 0);
1879 op0 = State.regs[ OP[0] ];
1881 temp = EXTEND16 (OP[2]);
1883 temp = load_mem (op0 + op2, 1);
1885 if ((temp & (1 << op1)) == 0)
1888 store_mem (op0 + op2, 1, temp);
1889 trace_output (OP_BIT);
1898 unsigned int op0, op1, op2;
1901 trace_input ("clr1", OP_BIT, 0);
1902 op0 = State.regs[ OP[0] ];
1904 temp = EXTEND16 (OP[2]);
1906 temp = load_mem (op0 + op2, 1);
1908 if ((temp & (1 << op1)) == 0)
1910 temp &= ~(1 << op1);
1911 store_mem (op0 + op2, 1, temp);
1912 trace_output (OP_BIT);
1921 unsigned int op0, op1, op2;
1924 trace_input ("tst1", OP_BIT, 0);
1925 op0 = State.regs[ OP[0] ];
1927 temp = EXTEND16 (OP[2]);
1929 temp = load_mem (op0 + op2, 1);
1931 if ((temp & (1 << op1)) == 0)
1933 trace_output (OP_BIT);
1942 trace_input ("di", OP_NONE, 0);
1944 trace_output (OP_NONE);
1953 trace_input ("ei", OP_NONE, 0);
1955 trace_output (OP_NONE);
1964 trace_input ("halt", OP_NONE, 0);
1965 /* FIXME this should put processor into a mode where NMI still handled */
1966 trace_output (OP_NONE);
1967 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1968 sim_stopped, SIGTRAP);
1976 trace_input ("reti", OP_NONE, 0);
1977 trace_output (OP_NONE);
1979 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
1980 if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
1998 trace_input ("trap", OP_TRAP, 0);
1999 trace_output (OP_TRAP);
2001 /* Trap 31 is used for simulating OS I/O functions */
2005 int save_errno = errno;
2008 /* Registers passed to trap 0 */
2010 #define FUNC State.regs[6] /* function number, return value */
2011 #define PARM1 State.regs[7] /* optional parm 1 */
2012 #define PARM2 State.regs[8] /* optional parm 2 */
2013 #define PARM3 State.regs[9] /* optional parm 3 */
2015 /* Registers set by trap 0 */
2017 #define RETVAL State.regs[10] /* return value */
2018 #define RETERR State.regs[11] /* return error code */
2020 /* Turn a pointer in a register into a pointer into real memory. */
2022 #define MEMPTR(x) (map (x))
2039 char *path = fetch_str (simulator, PARM1);
2040 char **argv = fetch_argv (simulator, PARM2);
2041 char **envp = fetch_argv (simulator, PARM3);
2042 RETVAL = execve (path, argv, envp);
2055 char *path = fetch_str (simulator, PARM1);
2056 char **argv = fetch_argv (simulator, PARM2);
2057 RETVAL = execv (path, argv);
2073 RETVAL = pipe (host_fd);
2074 SW (buf, host_fd[0]);
2075 buf += sizeof(uint16);
2076 SW (buf, host_fd[1]);
2088 RETVAL = wait (&status);
2098 char *buf = zalloc (PARM3);
2099 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
2100 sim_write (simulator, PARM2, buf, PARM3);
2109 char *buf = zalloc (PARM3);
2110 sim_read (simulator, PARM2, buf, PARM3);
2112 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
2114 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
2122 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
2128 RETVAL = sim_io_close (simulator, PARM1);
2135 char *buf = fetch_str (simulator, PARM1);
2136 RETVAL = sim_io_open (simulator, buf, PARM2);
2144 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
2145 /* get signal encoded by kill */
2146 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
2147 sim_signalled, PARM1 & 0xffff);
2148 else if (PARM1 == 0xdead)
2150 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
2151 sim_exited, SIGABRT);
2153 /* PARM1 has exit status */
2154 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
2159 #if !defined(__GO32__) && !defined(_WIN32)
2161 case SYS_stat: /* added at hmsi */
2162 /* stat system call */
2164 struct stat host_stat;
2166 char *path = fetch_str (simulator, PARM1);
2168 RETVAL = stat (path, &host_stat);
2173 /* Just wild-assed guesses. */
2174 store_mem (buf, 2, host_stat.st_dev);
2175 store_mem (buf + 2, 2, host_stat.st_ino);
2176 store_mem (buf + 4, 4, host_stat.st_mode);
2177 store_mem (buf + 8, 2, host_stat.st_nlink);
2178 store_mem (buf + 10, 2, host_stat.st_uid);
2179 store_mem (buf + 12, 2, host_stat.st_gid);
2180 store_mem (buf + 14, 2, host_stat.st_rdev);
2181 store_mem (buf + 16, 4, host_stat.st_size);
2182 store_mem (buf + 20, 4, host_stat.st_atime);
2183 store_mem (buf + 28, 4, host_stat.st_mtime);
2184 store_mem (buf + 36, 4, host_stat.st_ctime);
2194 char *path = fetch_str (simulator, PARM1);
2195 RETVAL = chown (path, PARM2, PARM3);
2206 char *path = fetch_str (simulator, PARM1);
2207 RETVAL = chmod (path, PARM2);
2219 RETVAL = time (&now);
2220 store_mem (PARM1, 4, now);
2226 #if !defined(__GO32__) && !defined(_WIN32)
2231 RETVAL = times (&tms);
2232 store_mem (PARM1, 4, tms.tms_utime);
2233 store_mem (PARM1 + 4, 4, tms.tms_stime);
2234 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2235 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2241 #ifdef SYS_gettimeofday
2242 #if !defined(__GO32__) && !defined(_WIN32)
2243 case SYS_gettimeofday:
2247 RETVAL = gettimeofday (&t, &tz);
2248 store_mem (PARM1, 4, t.tv_sec);
2249 store_mem (PARM1 + 4, 4, t.tv_usec);
2250 store_mem (PARM2, 4, tz.tz_minuteswest);
2251 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2261 /* Cast the second argument to void *, to avoid type mismatch
2262 if a prototype is present. */
2263 sim_io_error (simulator, "Utime not supported");
2264 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
2279 { /* Trap 0 -> 30 */
2284 ECR |= 0x40 + OP[0];
2285 /* Flag that we are now doing exception processing. */
2286 PSW |= PSW_EP | PSW_ID;
2287 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2293 /* start-sanitize-v850e */
2294 /* tst1 reg2, [reg1] */
2300 trace_input ("tst1", OP_BIT, 1);
2302 temp = load_mem (State.regs[ OP[0] ], 1);
2305 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
2308 trace_output (OP_BIT);
2313 /* end-sanitize-v850e */
2314 /* start-sanitize-v850e */
2315 /* mulu reg1, reg2, reg3 */
2319 trace_input ("mulu", OP_REG_REG_REG, 0);
2321 Multiply64 (false, State.regs[ OP[0] ]);
2323 trace_output (OP_REG_REG_REG);
2328 /* end-sanitize-v850e */
2329 /* start-sanitize-v850e */
2331 #define BIT_CHANGE_OP( name, binop ) \
2333 unsigned int temp; \
2335 trace_input (name, OP_BIT_CHANGE, 0); \
2337 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
2338 temp = load_mem (State.regs[ OP[0] ], 1); \
2341 if ((temp & bit) == 0) \
2345 store_mem (State.regs[ OP[0] ], 1, temp); \
2347 trace_output (OP_BIT_CHANGE); \
2351 /* clr1 reg2, [reg1] */
2355 BIT_CHANGE_OP ("clr1", &= ~ );
2358 /* not1 reg2, [reg1] */
2362 BIT_CHANGE_OP ("not1", ^= );
2369 BIT_CHANGE_OP ("set1", |= );
2376 trace_input ("sasf", OP_EX1, 0);
2378 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2380 trace_output (OP_EX1);
2384 /* end-sanitize-v850e */
2385 /* start-sanitize-v850eq */
2386 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2391 unsigned long int als,
2392 unsigned long int sfi,
2393 unsigned long int * quotient_ptr,
2394 unsigned long int * remainder_ptr,
2395 boolean * overflow_ptr
2398 unsigned long ald = sfi >> (N - 1);
2399 unsigned long alo = als;
2404 unsigned int R1 = 1;
2405 unsigned int DBZ = (als == 0) ? 1 : 0;
2406 unsigned long alt = Q ? ~als : als;
2409 alo = ald + alt + Q;
2410 C = (((alt >> 31) & (ald >> 31))
2411 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2414 R1 = (alo == 0) ? 0 : (R1 & Q);
2415 if ((S ^ (alo>>31)) && !C)
2420 sfi = (sfi << (32-N+1)) | Q;
2421 ald = (alo << 1) | (sfi >> 31);
2423 /* 2nd - N-1th Loop */
2424 for (i = 2; i < N; i++)
2426 alt = Q ? ~als : als;
2427 alo = ald + alt + Q;
2428 C = (((alt >> 31) & (ald >> 31))
2429 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2432 R1 = (alo == 0) ? 0 : (R1 & Q);
2433 if ((S ^ (alo>>31)) && !C && !DBZ)
2438 sfi = (sfi << 1) | Q;
2439 ald = (alo << 1) | (sfi >> 31);
2443 alt = Q ? ~als : als;
2444 alo = ald + alt + Q;
2445 C = (((alt >> 31) & (ald >> 31))
2446 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2449 R1 = (alo == 0) ? 0 : (R1 & Q);
2450 if ((S ^ (alo>>31)) && !C)
2455 * quotient_ptr = (sfi << 1) | Q;
2456 * remainder_ptr = Q ? alo : (alo + als);
2457 * overflow_ptr = DBZ | R1;
2460 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2465 unsigned long int als,
2466 unsigned long int sfi,
2467 signed long int * quotient_ptr,
2468 signed long int * remainder_ptr,
2469 boolean * overflow_ptr
2472 unsigned long ald = (signed long) sfi >> (N - 1);
2473 unsigned long alo = als;
2474 unsigned int SS = als >> 31;
2475 unsigned int SD = sfi >> 31;
2476 unsigned int R1 = 1;
2478 unsigned int DBZ = als == 0 ? 1 : 0;
2479 unsigned int Q = ~(SS ^ SD) & 1;
2483 unsigned long alt = Q ? ~als : als;
2488 alo = ald + alt + Q;
2489 C = (((alt >> 31) & (ald >> 31))
2490 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2492 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2494 sfi = (sfi << (32-N+1)) | Q;
2495 ald = (alo << 1) | (sfi >> 31);
2496 if ((alo >> 31) ^ (ald >> 31))
2501 /* 2nd - N-1th Loop */
2503 for (i = 2; i < N; i++)
2505 alt = Q ? ~als : als;
2506 alo = ald + alt + Q;
2507 C = (((alt >> 31) & (ald >> 31))
2508 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2510 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2512 sfi = (sfi << 1) | Q;
2513 ald = (alo << 1) | (sfi >> 31);
2514 if ((alo >> 31) ^ (ald >> 31))
2521 alt = Q ? ~als : als;
2522 alo = ald + alt + Q;
2523 C = (((alt >> 31) & (ald >> 31))
2524 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2526 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2527 sfi = (sfi << (32-N+1));
2533 alt = Q ? ~als : als;
2534 alo = ald + alt + Q;
2536 R1 = R1 & ((~alo >> 31) ^ SD);
2537 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2539 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2541 ald = sfi = sfi | Q;
2543 OV = DBZ | ((alo == 0) ? 0 : R1);
2545 * remainder_ptr = alo;
2548 if (((alo != 0) && ((SS ^ SD) ^ R1))
2549 || ((alo == 0) && (SS ^ R1)))
2554 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2556 * quotient_ptr = alo;
2557 * overflow_ptr = OV;
2560 /* sdivun imm5, reg1, reg2, reg3 */
2564 unsigned long int quotient;
2565 unsigned long int remainder;
2566 unsigned long int divide_by;
2567 unsigned long int divide_this;
2568 boolean overflow = false;
2571 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2573 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2575 divide_by = State.regs[ OP[0] ];
2576 divide_this = State.regs[ OP[1] ] << imm5;
2578 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2580 State.regs[ OP[1] ] = quotient;
2581 State.regs[ OP[2] >> 11 ] = remainder;
2583 /* Set condition codes. */
2584 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2586 if (overflow) PSW |= PSW_OV;
2587 if (quotient == 0) PSW |= PSW_Z;
2588 if (quotient & 0x80000000) PSW |= PSW_S;
2590 trace_output (OP_IMM_REG_REG_REG);
2595 /* sdivn imm5, reg1, reg2, reg3 */
2599 signed long int quotient;
2600 signed long int remainder;
2601 signed long int divide_by;
2602 signed long int divide_this;
2603 boolean overflow = false;
2606 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2608 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2610 divide_by = State.regs[ OP[0] ];
2611 divide_this = State.regs[ OP[1] ] << imm5;
2613 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2615 State.regs[ OP[1] ] = quotient;
2616 State.regs[ OP[2] >> 11 ] = remainder;
2618 /* Set condition codes. */
2619 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2621 if (overflow) PSW |= PSW_OV;
2622 if (quotient == 0) PSW |= PSW_Z;
2623 if (quotient < 0) PSW |= PSW_S;
2625 trace_output (OP_IMM_REG_REG_REG);
2630 /* sdivhun imm5, reg1, reg2, reg3 */
2634 unsigned long int quotient;
2635 unsigned long int remainder;
2636 unsigned long int divide_by;
2637 unsigned long int divide_this;
2638 boolean overflow = false;
2641 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2643 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2645 divide_by = State.regs[ OP[0] ] & 0xffff;
2646 divide_this = State.regs[ OP[1] ] << imm5;
2648 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2650 State.regs[ OP[1] ] = quotient;
2651 State.regs[ OP[2] >> 11 ] = remainder;
2653 /* Set condition codes. */
2654 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2656 if (overflow) PSW |= PSW_OV;
2657 if (quotient == 0) PSW |= PSW_Z;
2658 if (quotient & 0x80000000) PSW |= PSW_S;
2660 trace_output (OP_IMM_REG_REG_REG);
2665 /* sdivhn imm5, reg1, reg2, reg3 */
2669 signed long int quotient;
2670 signed long int remainder;
2671 signed long int divide_by;
2672 signed long int divide_this;
2673 boolean overflow = false;
2676 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2678 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2680 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2681 divide_this = State.regs[ OP[1] ] << imm5;
2683 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2685 State.regs[ OP[1] ] = quotient;
2686 State.regs[ OP[2] >> 11 ] = remainder;
2688 /* Set condition codes. */
2689 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2691 if (overflow) PSW |= PSW_OV;
2692 if (quotient == 0) PSW |= PSW_Z;
2693 if (quotient < 0) PSW |= PSW_S;
2695 trace_output (OP_IMM_REG_REG_REG);
2700 /* end-sanitize-v850eq */
2701 /* start-sanitize-v850e */
2702 /* divu reg1, reg2, reg3 */
2706 unsigned long int quotient;
2707 unsigned long int remainder;
2708 unsigned long int divide_by;
2709 unsigned long int divide_this;
2710 boolean overflow = false;
2712 trace_input ("divu", OP_REG_REG_REG, 0);
2714 /* Compute the result. */
2716 divide_by = State.regs[ OP[0] ];
2717 divide_this = State.regs[ OP[1] ];
2725 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2726 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2728 /* Set condition codes. */
2729 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2731 if (overflow) PSW |= PSW_OV;
2732 if (quotient == 0) PSW |= PSW_Z;
2733 if (quotient & 0x80000000) PSW |= PSW_S;
2735 trace_output (OP_REG_REG_REG);
2740 /* end-sanitize-v850e */
2741 /* start-sanitize-v850e */
2742 /* div reg1, reg2, reg3 */
2746 signed long int quotient;
2747 signed long int remainder;
2748 signed long int divide_by;
2749 signed long int divide_this;
2750 boolean overflow = false;
2752 trace_input ("div", OP_REG_REG_REG, 0);
2754 /* Compute the result. */
2756 divide_by = State.regs[ OP[0] ];
2757 divide_this = State.regs[ OP[1] ];
2759 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2765 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2766 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2768 /* Set condition codes. */
2769 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2771 if (overflow) PSW |= PSW_OV;
2772 if (quotient == 0) PSW |= PSW_Z;
2773 if (quotient < 0) PSW |= PSW_S;
2775 trace_output (OP_REG_REG_REG);
2780 /* end-sanitize-v850e */
2781 /* start-sanitize-v850e */
2782 /* divhu reg1, reg2, reg3 */
2786 unsigned long int quotient;
2787 unsigned long int remainder;
2788 unsigned long int divide_by;
2789 unsigned long int divide_this;
2790 boolean overflow = false;
2792 trace_input ("divhu", OP_REG_REG_REG, 0);
2794 /* Compute the result. */
2796 divide_by = State.regs[ OP[0] ] & 0xffff;
2797 divide_this = State.regs[ OP[1] ];
2805 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2806 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2808 /* Set condition codes. */
2809 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2811 if (overflow) PSW |= PSW_OV;
2812 if (quotient == 0) PSW |= PSW_Z;
2813 if (quotient & 0x80000000) PSW |= PSW_S;
2815 trace_output (OP_REG_REG_REG);
2820 /* end-sanitize-v850e */
2821 /* start-sanitize-v850e */
2822 /* divh reg1, reg2, reg3 */
2826 signed long int quotient;
2827 signed long int remainder;
2828 signed long int divide_by;
2829 signed long int divide_this;
2830 boolean overflow = false;
2832 trace_input ("divh", OP_REG_REG_REG, 0);
2834 /* Compute the result. */
2836 divide_by = State.regs[ OP[0] ];
2837 divide_this = EXTEND16 (State.regs[ OP[1] ]);
2839 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2845 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2846 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2848 /* Set condition codes. */
2849 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2851 if (overflow) PSW |= PSW_OV;
2852 if (quotient == 0) PSW |= PSW_Z;
2853 if (quotient < 0) PSW |= PSW_S;
2855 trace_output (OP_REG_REG_REG);
2860 /* end-sanitize-v850e */
2861 /* start-sanitize-v850e */
2862 /* mulu imm9, reg2, reg3 */
2866 trace_input ("mulu", OP_IMM_REG_REG, 0);
2868 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2870 trace_output (OP_IMM_REG_REG);
2875 /* end-sanitize-v850e */
2876 /* start-sanitize-v850e */
2877 /* mul imm9, reg2, reg3 */
2881 trace_input ("mul", OP_IMM_REG_REG, 0);
2883 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2885 trace_output (OP_IMM_REG_REG);
2890 /* end-sanitize-v850e */
2891 /* start-sanitize-v850e */
2892 /* cmov imm5, reg2, reg3 */
2896 trace_input ("cmov", OP_IMM_REG_REG, 0);
2898 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
2900 trace_output (OP_IMM_REG_REG);
2906 /* end-sanitize-v850e */
2907 /* start-sanitize-v850e */
2912 trace_input ("ctret", OP_NONE, 0);
2917 trace_output (OP_NONE);
2922 /* end-sanitize-v850e */
2923 /* start-sanitize-v850e */
2928 unsigned long value;
2930 trace_input ("hsw", OP_REG_REG3, 0);
2932 value = State.regs[ OP[ 1 ] ];
2934 value |= (State.regs[ OP[ 1 ] ] << 16);
2936 State.regs[ OP[2] >> 11 ] = value;
2938 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
2940 if (value == 0) PSW |= PSW_Z;
2941 if (value & 0x80000000) PSW |= PSW_S;
2942 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
2944 trace_output (OP_REG_REG3);
2949 /* end-sanitize-v850e */
2950 /* start-sanitize-v850e */
2951 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
2957 unsigned long value;
2959 trace_input ("bsw", OP_REG_REG3, 0);
2961 value = State.regs[ OP[ 1 ] ];
2963 value |= (State.regs[ OP[ 1 ] ] << 24);
2964 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
2965 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
2967 State.regs[ OP[2] >> 11 ] = value;
2969 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
2971 if (value == 0) PSW |= PSW_Z;
2972 if (value & 0x80000000) PSW |= PSW_S;
2973 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
2975 trace_output (OP_REG_REG3);
2980 /* end-sanitize-v850e */
2981 /* start-sanitize-v850e */
2986 unsigned long value;
2988 trace_input ("bsh", OP_REG_REG3, 0);
2990 value = State.regs[ OP[ 1 ] ];
2992 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
2993 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
2995 State.regs[ OP[2] >> 11 ] = value;
2997 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
2999 if (value == 0) PSW |= PSW_Z;
3000 if (value & 0x80000000) PSW |= PSW_S;
3001 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
3003 trace_output (OP_REG_REG3);
3008 /* end-sanitize-v850e */
3009 /* start-sanitize-v850e */
3016 trace_input ("ld.hu", OP_LOAD32, 2);
3018 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
3021 State.regs[ OP[1] ] = load_mem (adr, 2);
3023 trace_output (OP_LOAD32);
3028 /* end-sanitize-v850e */
3029 /* start-sanitize-v850e */
3036 trace_input ("ld.bu", OP_LOAD32, 1);
3038 adr = (State.regs[ OP[0] ]
3039 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
3041 State.regs[ OP[1] ] = load_mem (adr, 1);
3043 trace_output (OP_LOAD32);
3048 /* prepare list12, imm5, imm32 */
3054 trace_input ("prepare", OP_PUSHPOP1, 0);
3056 /* Store the registers with lower number registers being placed at higher addresses. */
3057 for (i = 0; i < 12; i++)
3058 if ((OP[3] & (1 << type1_regs[ i ])))
3061 store_mem (SP, 4, State.regs[ 20 + i ]);
3064 SP -= (OP[3] & 0x3e) << 1;
3066 EP = load_mem (PC + 4, 4);
3068 trace_output (OP_PUSHPOP1);
3073 /* prepare list12, imm5, imm16-32 */
3079 trace_input ("prepare", OP_PUSHPOP1, 0);
3081 /* Store the registers with lower number registers being placed at higher addresses. */
3082 for (i = 0; i < 12; i++)
3083 if ((OP[3] & (1 << type1_regs[ i ])))
3086 store_mem (SP, 4, State.regs[ 20 + i ]);
3089 SP -= (OP[3] & 0x3e) << 1;
3091 EP = load_mem (PC + 4, 2) << 16;
3093 trace_output (OP_PUSHPOP1);
3098 /* prepare list12, imm5, imm16 */
3104 trace_input ("prepare", OP_PUSHPOP1, 0);
3106 /* Store the registers with lower number registers being placed at higher addresses. */
3107 for (i = 0; i < 12; i++)
3108 if ((OP[3] & (1 << type1_regs[ i ])))
3111 store_mem (SP, 4, State.regs[ 20 + i ]);
3114 SP -= (OP[3] & 0x3e) << 1;
3116 EP = EXTEND16 (load_mem (PC + 4, 2));
3118 trace_output (OP_PUSHPOP1);
3123 /* prepare list12, imm5, sp */
3129 trace_input ("prepare", OP_PUSHPOP1, 0);
3131 /* Store the registers with lower number registers being placed at higher addresses. */
3132 for (i = 0; i < 12; i++)
3133 if ((OP[3] & (1 << type1_regs[ i ])))
3136 store_mem (SP, 4, State.regs[ 20 + i ]);
3139 SP -= (OP[3] & 0x3e) << 1;
3143 trace_output (OP_PUSHPOP1);
3148 /* end-sanitize-v850e */
3149 /* start-sanitize-v850e */
3154 unsigned long result;
3156 result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
3158 /* start-sanitize-v850eq */
3161 trace_input ("sld.h", OP_LOAD16, 2);
3162 State.regs[ OP[1] ] = EXTEND16 (result);
3166 /* end-sanitize-v850eq */
3167 trace_input ("sld.hu", OP_LOAD16, 2);
3169 State.regs[ OP[1] ] = result;
3170 /* start-sanitize-v850eq */
3172 /* end-sanitize-v850eq */
3174 trace_output (OP_LOAD16);
3179 /* end-sanitize-v850e */
3180 /* start-sanitize-v850e */
3181 /* cmov reg1, reg2, reg3 */
3185 trace_input ("cmov", OP_REG_REG_REG, 0);
3187 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
3189 trace_output (OP_REG_REG_REG);
3194 /* end-sanitize-v850e */
3195 /* start-sanitize-v850e */
3196 /* mul reg1, reg2, reg3 */
3200 trace_input ("mul", OP_REG_REG_REG, 0);
3202 Multiply64 (true, State.regs[ OP[0] ]);
3204 trace_output (OP_REG_REG_REG);
3209 /* end-sanitize-v850e */
3210 /* start-sanitize-v850eq */
3218 trace_input ("popmh", OP_PUSHPOP2, 0);
3220 if (OP[3] & (1 << 19))
3222 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3224 FEPSW = load_mem ( SP & ~ 3, 4);
3225 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3229 EIPSW = load_mem ( SP & ~ 3, 4);
3230 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3236 /* Load the registers with lower number registers being retrieved from higher addresses. */
3238 if ((OP[3] & (1 << type2_regs[ i ])))
3240 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
3244 trace_output (OP_PUSHPOP2);
3255 trace_input ("popml", OP_PUSHPOP3, 0);
3257 if (OP[3] & (1 << 19))
3259 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3261 FEPSW = load_mem ( SP & ~ 3, 4);
3262 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3266 EIPSW = load_mem ( SP & ~ 3, 4);
3267 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3273 if (OP[3] & (1 << 3))
3275 PSW = load_mem (SP & ~ 3, 4);
3279 /* Load the registers with lower number registers being retrieved from higher addresses. */
3281 if ((OP[3] & (1 << type3_regs[ i ])))
3283 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
3287 trace_output (OP_PUSHPOP2);
3298 trace_input ("pushmh", OP_PUSHPOP2, 0);
3300 /* Store the registers with lower number registers being placed at higher addresses. */
3301 for (i = 0; i < 16; i++)
3302 if ((OP[3] & (1 << type2_regs[ i ])))
3305 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
3308 if (OP[3] & (1 << 19))
3312 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3314 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3315 store_mem ( SP & ~ 3, 4, FEPSW);
3319 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3320 store_mem ( SP & ~ 3, 4, EIPSW);
3324 trace_output (OP_PUSHPOP2);
3329 /* end-sanitize-v850eq */