130 unsigned int op0, op1, result, z, s, cy, ov;
132 /* Compute the result. */
133 op0 = State.regs[OP[0]];
134 op1 = State.regs[OP[1]];
137 /* Compute the condition codes. */
139 s = (result & 0x80000000);
140 cy = (result < op0 || result < op1);
141 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
142 && (op0 & 0x80000000) != (result & 0x80000000));
144 /* Store the result and condition codes. */
145 State.regs[OP[1]] = result;
146 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
147 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
148 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
151 /* add sign_extend(imm5), reg */
155 unsigned int op0, op1, result, z, s, cy, ov;
158 /* Compute the result. */
159 temp = (OP[0] & 0x1f);
160 temp = (temp << 27) >> 27;
162 op1 = State.regs[OP[1]];
165 /* Compute the condition codes. */
167 s = (result & 0x80000000);
168 cy = (result < op0 || result < op1);
169 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
170 && (op0 & 0x80000000) != (result & 0x80000000));
172 /* Store the result and condition codes. */
173 State.regs[OP[1]] = result;
174 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
175 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
176 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
179 /* addi sign_extend(imm16), reg, reg */
183 unsigned int op0, op1, result, z, s, cy, ov;
186 /* Compute the result. */
187 temp = (OP[0] & 0xffff);
188 temp = (temp << 16) >> 16;
190 op1 = State.regs[OP[1]];
193 /* Compute the condition codes. */
195 s = (result & 0x80000000);
196 cy = (result < op0 || result < op1);
197 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
198 && (op0 & 0x80000000) != (result & 0x80000000));
200 /* Store the result and condition codes. */
201 State.regs[OP[2]] = result;
202 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
203 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
204 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
211 unsigned int op0, op1, result, z, s, cy, ov;
213 /* Compute the result. */
214 op0 = State.regs[OP[0]];
215 op1 = State.regs[OP[1]];
218 /* Compute the condition codes. */
220 s = (result & 0x80000000);
221 cy = (result < -op0);
222 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
223 && (op1 & 0x80000000) != (result & 0x80000000));
225 /* Store the result and condition codes. */
226 State.regs[OP[1]] = result;
227 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
228 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
229 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
230 State.regs[OP[1]] = State.regs[OP[0]];
233 /* subr reg1, reg2 */
237 unsigned int op0, op1, result, z, s, cy, ov;
239 /* Compute the result. */
240 op0 = State.regs[OP[0]];
241 op1 = State.regs[OP[1]];
244 /* Compute the condition codes. */
246 s = (result & 0x80000000);
247 cy = (result < -op1);
248 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
249 && (op0 & 0x80000000) != (result & 0x80000000));
251 /* Store the result and condition codes. */
252 State.regs[OP[1]] = result;
253 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
254 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
255 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
258 /* mulh reg1, reg2 */
262 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
263 * (State.regs[OP[0]] & 0xffff));
266 /* mulh sign_extend(imm5), reg2
274 value = (value << 27) >> 27;
276 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
279 /* mulhi imm16, reg1, reg2 */
285 value = value & 0xffff;
287 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
290 /* divh reg1, reg2 */
294 unsigned int op0, op1, result, z, s, cy, ov;
297 /* Compute the result. */
298 temp = State.regs[OP[0]] & 0xffff;
299 temp = (temp << 16) >> 16;
301 op1 = State.regs[OP[1]];
303 if (op0 == 0xffffffff && op1 == 0x80000000)
316 /* Compute the condition codes. */
318 s = (result & 0x80000000);
320 /* Store the result and condition codes. */
321 State.regs[OP[1]] = result;
322 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
323 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
324 | (ov ? PSW_OV : 0));
361 State.regs[OP[1]] = State.regs[OP[0]];
364 /* mov sign_extend(imm5), reg */
370 value = (value << 27) >> 27;
371 State.regs[OP[1]] = value;
374 /* movea sign_extend(imm16), reg, reg */
381 value = (value << 16) >> 16;
383 State.regs[OP[2]] = State.regs[OP[1]] + value;
386 /* movhi imm16, reg, reg */
392 value = (value & 0xffff) << 16;
394 State.regs[OP[2]] = State.regs[OP[1]] + value;
432 /* sar zero_extend(imm5),reg1
434 XXX condition codes. */
438 int temp = State.regs[OP[1]];
440 temp >>= (OP[0] & 0x1f);
442 State.regs[OP[1]] = temp;
447 XXX condition codes. */
451 int temp = State.regs[OP[1]];
453 temp >>= (State.regs[OP[0]] & 0x1f);
455 State.regs[OP[1]] = temp;
458 /* shl zero_extend(imm5),reg1
460 XXX condition codes. */
464 State.regs[OP[1]] <<= (OP[0] & 0x1f);
469 XXX condition codes. */
473 State.regs[OP[1]] <<= (State.regs[OP[0]] & 0x1f);
476 /* shr zero_extend(imm5),reg1
478 XXX condition codes. */
482 State.regs[OP[1]] >>= (OP[0] & 0x1f);
487 XXX condition codes. */
491 State.regs[OP[1]] >>= (State.regs[OP[0]] & 0x1f);
513 unsigned int op0, op1, result, z, s, cy, ov;
515 /* Compute the result. */
516 op0 = State.regs[OP[0]];
517 op1 = State.regs[OP[1]];
520 /* Compute the condition codes. */
522 s = (result & 0x80000000);
524 /* Store the result and condition codes. */
525 State.regs[OP[1]] = result;
526 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
527 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
530 /* ori zero_extend(imm16), reg, reg */
534 unsigned int op0, op1, result, z, s, cy, ov;
536 op0 = OP[0] & 0xffff;
537 op1 = State.regs[OP[1]];
540 /* Compute the condition codes. */
542 s = (result & 0x80000000);
544 /* Store the result and condition codes. */
545 State.regs[OP[2]] = result;
546 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
547 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
548 State.psw |= (z ? PSW_Z : 0);
555 unsigned int op0, op1, result, z, s, cy, ov;
557 /* Compute the result. */
558 op0 = State.regs[OP[0]];
559 op1 = State.regs[OP[1]];
562 /* Compute the condition codes. */
564 s = (result & 0x80000000);
566 /* Store the result and condition codes. */
567 State.regs[OP[1]] = result;
568 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
569 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
572 /* andi zero_extend(imm16), reg, reg */
576 unsigned int op0, op1, result, z, s, cy, ov;
578 op0 = OP[0] & 0xffff;
579 op1 = State.regs[OP[1]];
582 /* Compute the condition codes. */
585 /* Store the result and condition codes. */
586 State.regs[OP[2]] = result;
587 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
588 State.psw |= (z ? PSW_Z : 0);
595 unsigned int op0, op1, result, z, s, cy, ov;
597 /* Compute the result. */
598 op0 = State.regs[OP[0]];
599 op1 = State.regs[OP[1]];
602 /* Compute the condition codes. */
604 s = (result & 0x80000000);
606 /* Store the result and condition codes. */
607 State.regs[OP[1]] = result;
608 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
609 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
612 /* xori zero_extend(imm16), reg, reg */
616 unsigned int op0, op1, result, z, s, cy, ov;
618 op0 = OP[0] & 0xffff;
619 op1 = State.regs[OP[1]];
622 /* Compute the condition codes. */
624 s = (result & 0x80000000);
626 /* Store the result and condition codes. */
627 State.regs[OP[2]] = result;
628 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
629 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
630 State.psw |= (z ? PSW_Z : 0);
637 unsigned int op0, result, z, s, cy, ov;
639 /* Compute the result. */
640 op0 = State.regs[OP[0]];
643 /* Compute the condition codes. */
645 s = (result & 0x80000000);
647 /* Store the result and condition codes. */
648 State.regs[OP[1]] = result;
649 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
650 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
673 /* di, not supported */
680 /* ei, not supported */
687 /* halt, not supported */
694 /* reti, not supported */
701 /* trap, not supportd */
708 /* ldsr, not supported */
715 /* stsr, not supported */