13 temp = (temp << 25) >> 25;
15 result = get_byte (State.mem + State.regs[30] + op2);
16 result = (result << 24) >> 24;
17 State.regs[OP[0]] = result;
28 temp = (temp << 25) >> 25;
30 result = get_half (State.mem + State.regs[30] + op2);
31 result = (result << 16) >> 16;
32 State.regs[OP[0]] = result;
43 temp = (temp << 25) >> 25;
45 result = get_word (State.mem + State.regs[30] + op2);
46 State.regs[OP[0]] = result;
53 unsigned int op0, op1;
56 op0 = State.regs[OP[0]];
58 temp = (temp << 25) >> 25;
60 put_byte (State.mem + State.regs[30] + op1, op0);
67 unsigned int op0, op1;
70 op0 = State.regs[OP[0]];
72 temp = (temp << 25) >> 25;
74 put_half (State.mem + State.regs[30] + op1, op0);
81 unsigned int op0, op1;
84 op0 = State.regs[OP[0]];
86 temp = (temp << 25) >> 25;
88 put_word (State.mem + State.regs[30] + op1, op0);
95 unsigned int op0, op2;
98 op0 = State.regs[OP[0]];
100 temp = (temp << 16) >> 16;
102 result = get_byte (State.mem + op0 + op2);
103 result = (result << 24) >> 24;
104 State.regs[OP[1]] = result;
111 unsigned int op0, op2;
114 op0 = State.regs[OP[0]];
116 temp = (temp << 16) >> 16;
119 result = get_half (State.mem + op0 + op2);
120 result = (result << 16) >> 16;
121 State.regs[OP[1]] = result;
128 unsigned int op0, op2;
131 op0 = State.regs[OP[0]];
133 temp = (temp << 16) >> 16;
136 result = get_word (State.mem + op0 + op2);
137 State.regs[OP[1]] = result;
144 unsigned int op0, op1, op2;
147 op0 = State.regs[OP[0]];
148 op1 = State.regs[OP[1]];
150 temp = (temp << 16) >> 16;
152 put_byte (State.mem + op0 + op2, op1);
159 unsigned int op0, op1, op2;
162 op0 = State.regs[OP[0]];
163 op1 = State.regs[OP[1]];
166 temp = (temp << 16) >> 16;
168 put_half (State.mem + op0 + op2, op1);
175 unsigned int op0, op1, op2;
178 op0 = State.regs[OP[0]];
179 op1 = State.regs[OP[1]];
182 temp = (temp << 16) >> 16;
184 put_word (State.mem + op0 + op2, op1);
191 unsigned int op0, psw;
193 op0 = ((signed)OP[0] << 23) >> 23;
194 psw = State.sregs[5];
196 if ((psw & PSW_OV) != 0)
206 unsigned int op0, psw;
208 op0 = ((signed)OP[0] << 23) >> 23;
209 psw = State.sregs[5];
211 if ((psw & PSW_CY) != 0)
221 unsigned int op0, psw;
223 op0 = ((signed)OP[0] << 23) >> 23;
224 psw = State.sregs[5];
226 if ((psw & PSW_Z) != 0)
236 unsigned int op0, psw;
238 op0 = ((signed)OP[0] << 23) >> 23;
239 psw = State.sregs[5];
241 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
251 unsigned int op0, psw;
253 op0 = ((signed)OP[0] << 23) >> 23;
254 psw = State.sregs[5];
256 if ((psw & PSW_S) != 0)
268 op0 = ((signed)OP[0] << 23) >> 23;
276 unsigned int op0, psw;
278 op0 = ((signed)OP[0] << 23) >> 23;
279 psw = State.sregs[5];
281 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
291 unsigned int op0, psw;
293 op0 = ((signed)OP[0] << 23) >> 23;
294 psw = State.sregs[5];
296 if ((((psw & PSW_Z) != 0)
297 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
307 unsigned int op0, psw;
309 op0 = ((signed)OP[0] << 23) >> 23;
310 psw = State.sregs[5];
312 if ((psw & PSW_OV) == 0)
322 unsigned int op0, psw;
324 op0 = ((signed)OP[0] << 23) >> 23;
325 psw = State.sregs[5];
327 if ((psw & PSW_CY) == 0)
337 unsigned int op0, psw;
339 op0 = ((signed)OP[0] << 23) >> 23;
340 psw = State.sregs[5];
342 if ((psw & PSW_Z) == 0)
352 unsigned int op0, psw;
354 op0 = ((signed)OP[0] << 23) >> 23;
355 psw = State.sregs[5];
357 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
367 unsigned int op0, psw;
369 op0 = ((signed)OP[0] << 23) >> 23;
370 psw = State.sregs[5];
372 if ((psw & PSW_S) == 0)
382 unsigned int op0, psw;
384 op0 = ((signed)OP[0] << 23) >> 23;
385 psw = State.sregs[5];
387 if ((psw & PSW_SAT) != 0)
397 unsigned int op0, psw;
399 op0 = ((signed)OP[0] << 23) >> 23;
400 psw = State.sregs[5];
402 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
412 unsigned int op0, psw;
414 op0 = ((signed)OP[0] << 23) >> 23;
415 psw = State.sregs[5];
417 if ((((psw & PSW_Z) != 0)
418 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
428 /* interp.c will bump this by +2, so correct for it here. */
429 State.pc = State.regs[OP[0]] - 2;
432 /* jarl disp22, reg */
436 unsigned int op0, opc;
440 temp = (temp << 10) >> 10;
446 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
448 State.regs[OP[1]] = opc + 4;
455 unsigned int op0, op1, result, z, s, cy, ov;
457 /* Compute the result. */
458 op0 = State.regs[OP[0]];
459 op1 = State.regs[OP[1]];
462 /* Compute the condition codes. */
464 s = (result & 0x80000000);
465 cy = (result < op0 || result < op1);
466 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
467 && (op0 & 0x80000000) != (result & 0x80000000));
469 /* According to the manual, 's' is inverted if 'ov'
473 /* Store the result and condition codes. */
474 State.regs[OP[1]] = result;
475 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
476 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
477 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
480 /* add sign_extend(imm5), reg */
484 unsigned int op0, op1, result, z, s, cy, ov;
487 /* Compute the result. */
488 temp = (OP[0] & 0x1f);
489 temp = (temp << 27) >> 27;
491 op1 = State.regs[OP[1]];
494 /* Compute the condition codes. */
496 s = (result & 0x80000000);
497 cy = (result < op0 || result < op1);
498 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
499 && (op0 & 0x80000000) != (result & 0x80000000));
501 /* According to the manual, 's' is inverted if 'ov'
505 /* Store the result and condition codes. */
506 State.regs[OP[1]] = result;
507 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
508 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
509 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
512 /* addi sign_extend(imm16), reg, reg */
516 unsigned int op0, op1, result, z, s, cy, ov;
519 /* Compute the result. */
520 temp = (OP[0] & 0xffff);
521 temp = (temp << 16) >> 16;
523 op1 = State.regs[OP[1]];
526 /* Compute the condition codes. */
528 s = (result & 0x80000000);
529 cy = (result < op0 || result < op1);
530 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
531 && (op0 & 0x80000000) != (result & 0x80000000));
533 /* According to the manual, 's' is inverted if 'ov'
537 /* Store the result and condition codes. */
538 State.regs[OP[2]] = result;
539 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
540 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
541 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
548 unsigned int op0, op1, result, z, s, cy, ov;
550 /* Compute the result. */
551 op0 = State.regs[OP[0]];
552 op1 = State.regs[OP[1]];
555 /* Compute the condition codes. */
557 s = (result & 0x80000000);
559 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
560 && (op1 & 0x80000000) != (result & 0x80000000));
562 /* According to the manual, 's' is inverted if 'ov'
566 /* Store the result and condition codes. */
567 State.regs[OP[1]] = result;
568 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
569 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
570 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
573 /* subr reg1, reg2 */
577 unsigned int op0, op1, result, z, s, cy, ov;
579 /* Compute the result. */
580 op0 = State.regs[OP[0]];
581 op1 = State.regs[OP[1]];
584 /* Compute the condition codes. */
586 s = (result & 0x80000000);
588 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
589 && (op0 & 0x80000000) != (result & 0x80000000));
591 /* According to the manual, 's' is inverted if 'ov'
595 /* Store the result and condition codes. */
596 State.regs[OP[1]] = result;
597 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
598 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
599 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
602 /* mulh reg1, reg2 */
606 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
607 * (State.regs[OP[0]] & 0xffff));
610 /* mulh sign_extend(imm5), reg2
618 value = (value << 27) >> 27;
620 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
623 /* mulhi imm16, reg1, reg2 */
629 value = value & 0xffff;
631 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
634 /* divh reg1, reg2 */
638 unsigned int op0, op1, result, ov, s, z;
641 /* Compute the result. */
642 temp = State.regs[OP[0]] & 0xffff;
643 temp = (temp << 16) >> 16;
645 op1 = State.regs[OP[1]];
647 if (op0 == 0xffffffff && op1 == 0x80000000)
663 /* Compute the condition codes. */
665 s = (result & 0x80000000);
667 /* Store the result and condition codes. */
668 State.regs[OP[1]] = result;
669 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
670 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
671 | (ov ? PSW_OV : 0));
678 unsigned int op0, op1, result, z, s, cy, ov;
680 /* Compute the result. */
681 op0 = State.regs[OP[0]];
682 op1 = State.regs[OP[1]];
685 /* Compute the condition codes. */
687 s = (result & 0x80000000);
689 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
690 && (op1 & 0x80000000) != (result & 0x80000000));
692 /* Set condition codes. */
693 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
694 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
695 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
698 /* cmp sign_extend(imm5), reg */
702 unsigned int op0, op1, result, z, s, cy, ov;
705 /* Compute the result. */
707 temp = (temp << 27) >> 27;
709 op1 = State.regs[OP[1]];
712 /* Compute the condition codes. */
714 s = (result & 0x80000000);
716 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
717 && (op1 & 0x80000000) != (result & 0x80000000));
719 /* Set condition codes. */
720 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
721 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
722 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
729 /* Hack alert. We turn off a bit in op0 since we really only
731 unsigned int op0, psw, result = 0;
734 psw = State.sregs[5];
739 result = ((psw & PSW_OV) != 0);
742 result = ((psw & PSW_CY) != 0);
745 result = ((psw & PSW_Z) != 0);
748 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
751 result = ((psw & PSW_S) != 0);
757 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
760 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
761 || ((psw & PSW_Z) != 0)) != 0);
764 result = ((psw & PSW_OV) == 0);
767 result = ((psw & PSW_CY) == 0);
770 result = ((psw & PSW_Z) == 0);
773 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
776 result = ((psw & PSW_S) == 0);
779 result = ((psw & PSW_SAT) != 0);
782 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
785 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
786 || ((psw & PSW_Z) != 0)) == 0);
790 State.regs[OP[1]] = result;
797 unsigned int op0, op1, result, z, s, cy, ov, sat;
799 /* Compute the result. */
800 op0 = State.regs[OP[0]];
801 op1 = State.regs[OP[1]];
804 /* Compute the condition codes. */
806 s = (result & 0x80000000);
807 cy = (result < op0 || result < op1);
808 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
809 && (op0 & 0x80000000) != (result & 0x80000000));
812 /* Store the result and condition codes. */
813 State.regs[OP[1]] = result;
814 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
815 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
816 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
817 | (sat ? PSW_SAT : 0));
819 /* Handle saturated results. */
821 State.regs[OP[1]] = 0x80000000;
823 State.regs[OP[1]] = 0x7fffffff;
826 /* satadd sign_extend(imm5), reg */
830 unsigned int op0, op1, result, z, s, cy, ov, sat;
834 /* Compute the result. */
835 temp = (OP[0] & 0x1f);
836 temp = (temp << 27) >> 27;
838 op1 = State.regs[OP[1]];
841 /* Compute the condition codes. */
843 s = (result & 0x80000000);
844 cy = (result < op0 || result < op1);
845 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
846 && (op0 & 0x80000000) != (result & 0x80000000));
849 /* Store the result and condition codes. */
850 State.regs[OP[1]] = result;
851 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
852 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
853 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
854 | (sat ? PSW_SAT : 0));
856 /* Handle saturated results. */
858 State.regs[OP[1]] = 0x80000000;
860 State.regs[OP[1]] = 0x7fffffff;
863 /* satsub reg1, reg2 */
867 unsigned int op0, op1, result, z, s, cy, ov, sat;
869 /* Compute the result. */
870 op0 = State.regs[OP[0]];
871 op1 = State.regs[OP[1]];
874 /* Compute the condition codes. */
876 s = (result & 0x80000000);
878 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
879 && (op1 & 0x80000000) != (result & 0x80000000));
882 /* Store the result and condition codes. */
883 State.regs[OP[1]] = result;
884 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
885 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
886 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
887 | (sat ? PSW_SAT : 0));
889 /* Handle saturated results. */
891 State.regs[OP[1]] = 0x80000000;
893 State.regs[OP[1]] = 0x7fffffff;
896 /* satsubi sign_extend(imm16), reg */
900 unsigned int op0, op1, result, z, s, cy, ov, sat;
903 /* Compute the result. */
904 temp = (OP[0] & 0xffff);
905 temp = (temp << 16) >> 16;
907 op1 = State.regs[OP[1]];
910 /* Compute the condition codes. */
912 s = (result & 0x80000000);
914 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
915 && (op1 & 0x80000000) != (result & 0x80000000));
918 /* Store the result and condition codes. */
919 State.regs[OP[1]] = result;
920 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
921 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
922 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
923 | (sat ? PSW_SAT : 0));
925 /* Handle saturated results. */
927 State.regs[OP[1]] = 0x80000000;
929 State.regs[OP[1]] = 0x7fffffff;
935 unsigned int op0, op1, result, z, s, cy, ov, sat;
937 /* Compute the result. */
938 op0 = State.regs[OP[0]];
939 op1 = State.regs[OP[1]];
942 /* Compute the condition codes. */
944 s = (result & 0x80000000);
946 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
947 && (op1 & 0x80000000) != (result & 0x80000000));
950 /* Store the result and condition codes. */
951 State.regs[OP[1]] = result;
952 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
953 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
954 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
955 | (sat ? PSW_SAT : 0));
957 /* Handle saturated results. */
959 State.regs[OP[1]] = 0x80000000;
961 State.regs[OP[1]] = 0x7fffffff;
968 unsigned int op0, op1, result, z, s;
970 /* Compute the result. */
971 op0 = State.regs[OP[0]];
972 op1 = State.regs[OP[1]];
975 /* Compute the condition codes. */
977 s = (result & 0x80000000);
979 /* Store the condition codes. */
980 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
981 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
988 State.regs[OP[1]] = State.regs[OP[0]];
991 /* mov sign_extend(imm5), reg */
997 value = (value << 27) >> 27;
998 State.regs[OP[1]] = value;
1001 /* movea sign_extend(imm16), reg, reg */
1008 value = (value << 16) >> 16;
1010 State.regs[OP[2]] = State.regs[OP[1]] + value;
1013 /* movhi imm16, reg, reg */
1019 value = (value & 0xffff) << 16;
1021 State.regs[OP[2]] = State.regs[OP[1]] + value;
1024 /* sar zero_extend(imm5),reg1 */
1028 unsigned int op0, op1, result, z, s, cy;
1031 op1 = State.regs[OP[1]];
1032 result = (signed)op1 >> op0;
1034 /* Compute the condition codes. */
1036 s = (result & 0x80000000);
1037 cy = (op1 & (1 << (op0 - 1)));
1039 /* Store the result and condition codes. */
1040 State.regs[OP[1]] = result;
1041 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1042 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1043 | (cy ? PSW_CY : 0));
1046 /* sar reg1, reg2 */
1050 unsigned int op0, op1, result, z, s, cy;
1052 op0 = State.regs[OP[0]] & 0x1f;
1053 op1 = State.regs[OP[1]];
1054 result = (signed)op1 >> op0;
1056 /* Compute the condition codes. */
1058 s = (result & 0x80000000);
1059 cy = (op1 & (1 << (op0 - 1)));
1061 /* Store the result and condition codes. */
1062 State.regs[OP[1]] = result;
1063 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1064 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1065 | (cy ? PSW_CY : 0));
1068 /* shl zero_extend(imm5),reg1 */
1072 unsigned int op0, op1, result, z, s, cy;
1075 op1 = State.regs[OP[1]];
1076 result = op1 << op0;
1078 /* Compute the condition codes. */
1080 s = (result & 0x80000000);
1081 cy = (op1 & (1 << (32 - op0)));
1083 /* Store the result and condition codes. */
1084 State.regs[OP[1]] = result;
1085 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1086 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1087 | (cy ? PSW_CY : 0));
1090 /* shl reg1, reg2 */
1094 unsigned int op0, op1, result, z, s, cy;
1096 op0 = State.regs[OP[0]] & 0x1f;
1097 op1 = State.regs[OP[1]];
1098 result = op1 << op0;
1100 /* Compute the condition codes. */
1102 s = (result & 0x80000000);
1103 cy = (op1 & (1 << (32 - op0)));
1105 /* Store the result and condition codes. */
1106 State.regs[OP[1]] = result;
1107 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1108 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1109 | (cy ? PSW_CY : 0));
1112 /* shr zero_extend(imm5),reg1 */
1116 unsigned int op0, op1, result, z, s, cy;
1119 op1 = State.regs[OP[1]];
1120 result = op1 >> op0;
1122 /* Compute the condition codes. */
1124 s = (result & 0x80000000);
1125 cy = (op1 & (1 << (op0 - 1)));
1127 /* Store the result and condition codes. */
1128 State.regs[OP[1]] = result;
1129 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1130 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1131 | (cy ? PSW_CY : 0));
1134 /* shr reg1, reg2 */
1138 unsigned int op0, op1, result, z, s, cy;
1140 op0 = State.regs[OP[0]] & 0x1f;
1141 op1 = State.regs[OP[1]];
1142 result = op1 >> op0;
1144 /* Compute the condition codes. */
1146 s = (result & 0x80000000);
1147 cy = (op1 & (1 << (op0 - 1)));
1149 /* Store the result and condition codes. */
1150 State.regs[OP[1]] = result;
1151 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1152 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1153 | (cy ? PSW_CY : 0));
1160 unsigned int op0, op1, result, z, s;
1162 /* Compute the result. */
1163 op0 = State.regs[OP[0]];
1164 op1 = State.regs[OP[1]];
1167 /* Compute the condition codes. */
1169 s = (result & 0x80000000);
1171 /* Store the result and condition codes. */
1172 State.regs[OP[1]] = result;
1173 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1174 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1177 /* ori zero_extend(imm16), reg, reg */
1181 unsigned int op0, op1, result, z, s;
1183 op0 = OP[0] & 0xffff;
1184 op1 = State.regs[OP[1]];
1187 /* Compute the condition codes. */
1189 s = (result & 0x80000000);
1191 /* Store the result and condition codes. */
1192 State.regs[OP[2]] = result;
1193 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1194 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1201 unsigned int op0, op1, result, z, s;
1203 /* Compute the result. */
1204 op0 = State.regs[OP[0]];
1205 op1 = State.regs[OP[1]];
1208 /* Compute the condition codes. */
1210 s = (result & 0x80000000);
1212 /* Store the result and condition codes. */
1213 State.regs[OP[1]] = result;
1214 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1215 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1218 /* andi zero_extend(imm16), reg, reg */
1222 unsigned int op0, op1, result, z;
1224 op0 = OP[0] & 0xffff;
1225 op1 = State.regs[OP[1]];
1228 /* Compute the condition codes. */
1231 /* Store the result and condition codes. */
1232 State.regs[OP[2]] = result;
1233 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1234 State.sregs[5] |= (z ? PSW_Z : 0);
1241 unsigned int op0, op1, result, z, s;
1243 /* Compute the result. */
1244 op0 = State.regs[OP[0]];
1245 op1 = State.regs[OP[1]];
1248 /* Compute the condition codes. */
1250 s = (result & 0x80000000);
1252 /* Store the result and condition codes. */
1253 State.regs[OP[1]] = result;
1254 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1255 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1258 /* xori zero_extend(imm16), reg, reg */
1262 unsigned int op0, op1, result, z, s;
1264 op0 = OP[0] & 0xffff;
1265 op1 = State.regs[OP[1]];
1268 /* Compute the condition codes. */
1270 s = (result & 0x80000000);
1272 /* Store the result and condition codes. */
1273 State.regs[OP[2]] = result;
1274 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1275 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1278 /* not reg1, reg2 */
1282 unsigned int op0, result, z, s;
1284 /* Compute the result. */
1285 op0 = State.regs[OP[0]];
1288 /* Compute the condition codes. */
1290 s = (result & 0x80000000);
1292 /* Store the result and condition codes. */
1293 State.regs[OP[1]] = result;
1294 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1295 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1302 unsigned int op0, op1, op2;
1305 op0 = State.regs[OP[0]];
1308 temp = (temp << 16) >> 16;
1310 temp = get_byte (State.mem + op0 + op2);
1311 State.sregs[5] &= ~PSW_Z;
1312 if ((temp & (1 << op1)) == 0)
1313 State.sregs[5] |= PSW_Z;
1315 put_byte (State.mem + op0 + op2, temp);
1322 unsigned int op0, op1, op2;
1325 op0 = State.regs[OP[0]];
1328 temp = (temp << 16) >> 16;
1330 temp = get_byte (State.mem + op0 + op2);
1331 State.sregs[5] &= ~PSW_Z;
1332 if ((temp & (1 << op1)) == 0)
1333 State.sregs[5] |= PSW_Z;
1335 put_byte (State.mem + op0 + op2, temp);
1342 unsigned int op0, op1, op2;
1345 op0 = State.regs[OP[0]];
1348 temp = (temp << 16) >> 16;
1350 temp = get_byte (State.mem + op0 + op2);
1351 State.sregs[5] &= ~PSW_Z;
1352 if ((temp & (1 << op1)) == 0)
1353 State.sregs[5] |= PSW_Z;
1354 temp &= ~(1 << op1);
1355 put_byte (State.mem + op0 + op2, temp);
1362 unsigned int op0, op1, op2;
1365 op0 = State.regs[OP[0]];
1368 temp = (temp << 16) >> 16;
1370 temp = get_byte (State.mem + op0 + op2);
1371 State.sregs[5] &= ~PSW_Z;
1372 if ((temp & (1 << op1)) == 0)
1373 State.sregs[5] |= PSW_Z;
1380 State.sregs[5] |= PSW_ID;
1387 State.sregs[5] &= ~PSW_ID;
1390 /* halt, not supported */
1394 State.exception = SIGQUIT;
1397 /* reti, not supported */
1404 /* trap, not supportd */
1410 /* Trap 0 is used for simulating low-level I/O */
1415 char *fstr = State.regs[2] + State.imem;
1416 printf (fstr,State.regs[3],State.regs[4],State.regs[5]);
1418 int save_errno = errno;
1421 /* Registers passed to trap 0 */
1423 #define FUNC State.regs[6] /* function number, return value */
1424 #define PARM1 State.regs[7] /* optional parm 1 */
1425 #define PARM2 State.regs[8] /* optional parm 2 */
1426 #define PARM3 State.regs[9] /* optional parm 3 */
1428 /* Registers set by trap 0 */
1430 #define RETVAL State.regs[10] /* return value */
1431 #define RETERR State.regs[11] /* return error code */
1433 /* Turn a pointer in a register into a pointer into real memory. */
1435 #define MEMPTR(x) ((char *)((x) + State.mem))
1441 #if !defined(__GO32__) && !defined(_WIN32)
1446 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
1447 (char **)MEMPTR (PARM3));
1450 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
1458 RETVAL = pipe (host_fd);
1459 SW (buf, host_fd[0]);
1460 buf += sizeof(uint16);
1461 SW (buf, host_fd[1]);
1469 RETVAL = wait (&status);
1476 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
1482 RETVAL = (int)v850_callback->write_stdout (v850_callback,
1483 MEMPTR (PARM2), PARM3);
1485 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
1486 MEMPTR (PARM2), PARM3);
1490 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
1493 RETVAL = v850_callback->close (v850_callback, PARM1);
1496 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
1500 /* EXIT - caller can look in PARM1 to work out the
1502 if (PARM1 == 0xdead || PARM1 == 0x1)
1503 State.exception = SIGABRT;
1505 State.exception = SIGQUIT;
1509 case SYS_stat: /* added at hmsi */
1510 /* stat system call */
1512 struct stat host_stat;
1515 RETVAL = stat (MEMPTR (PARM1), &host_stat);
1519 /* The hard-coded offsets and sizes were determined by using
1520 * the D10V compiler on a test program that used struct stat.
1522 SW (buf, host_stat.st_dev);
1523 SW (buf+2, host_stat.st_ino);
1524 SW (buf+4, host_stat.st_mode);
1525 SW (buf+6, host_stat.st_nlink);
1526 SW (buf+8, host_stat.st_uid);
1527 SW (buf+10, host_stat.st_gid);
1528 SW (buf+12, host_stat.st_rdev);
1529 SLW (buf+16, host_stat.st_size);
1530 SLW (buf+20, host_stat.st_atime);
1531 SLW (buf+28, host_stat.st_mtime);
1532 SLW (buf+36, host_stat.st_ctime);
1537 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
1540 RETVAL = chmod (MEMPTR (PARM1), PARM2);
1543 /* Cast the second argument to void *, to avoid type mismatch
1544 if a prototype is present. */
1545 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
1555 else if (OP[0] == 1 )
1557 char *fstr = State.regs[2] + State.mem;
1568 op0 = State.regs[OP[0]];
1569 State.sregs[OP[1]] = op0;
1572 /* stsr, not supported */
1578 op0 = State.sregs[OP[1]];
1579 State.regs[OP[0]] = op0;