9 unsigned int op0, op1, op2;
13 temp = (temp << 25) >> 25;
15 result = get_byte (State.mem + State.regs[30] + op2);
16 result = (result << 24) >> 24;
17 State.regs[OP[0]] = result;
24 unsigned int op0, op1, op2;
28 temp = (temp << 25) >> 25;
30 result = get_half (State.mem + State.regs[30] + op2);
31 result = (result << 16) >> 16;
32 State.regs[OP[0]] = result;
39 unsigned int op0, op1, op2;
43 temp = (temp << 25) >> 25;
45 result = get_word (State.mem + State.regs[30] + op2);
46 State.regs[OP[0]] = result;
53 unsigned int op0, op1, op2;
56 op0 = State.regs[OP[0]];
58 temp = (temp << 25) >> 25;
60 put_byte (State.mem + State.regs[30] + op1, op0);
67 unsigned int op0, op1, op2;
70 op0 = State.regs[OP[0]];
72 temp = (temp << 25) >> 25;
74 put_half (State.mem + State.regs[30] + op1, op0);
81 unsigned int op0, op1, op2;
84 op0 = State.regs[OP[0]];
86 temp = (temp << 25) >> 25;
88 put_word (State.mem + State.regs[30] + op1, op0);
95 unsigned int op0, op1, op2;
98 op0 = State.regs[OP[0]];
100 temp = (temp << 16) >> 16;
102 result = get_byte (State.mem + op0 + op2);
103 result = (result << 24) >> 24;
104 State.regs[OP[1]] = result;
111 unsigned int op0, op1, op2;
114 op0 = State.regs[OP[0]];
116 temp = (temp << 16) >> 16;
119 result = get_half (State.mem + op0 + op2);
120 result = (result << 16) >> 16;
121 State.regs[OP[1]] = result;
128 unsigned int op0, op1, op2;
131 op0 = State.regs[OP[0]];
133 temp = (temp << 16) >> 16;
136 result = get_word (State.mem + op0 + op2);
137 State.regs[OP[1]] = result;
144 unsigned int op0, op1, op2;
147 op0 = State.regs[OP[0]];
148 op1 = State.regs[OP[1]];
150 temp = (temp << 16) >> 16;
152 put_byte (State.mem + op0 + op2, op1);
159 unsigned int op0, op1, op2;
162 op0 = State.regs[OP[0]];
163 op1 = State.regs[OP[1]];
166 temp = (temp << 16) >> 16;
168 put_half (State.mem + op0 + op2, op1);
175 unsigned int op0, op1, op2;
178 op0 = State.regs[OP[0]];
179 op1 = State.regs[OP[1]];
182 temp = (temp << 16) >> 16;
184 put_word (State.mem + op0 + op2, op1);
191 unsigned int op0, psw;
194 temp = (State.regs[OP[0]] << 23) >> 23;
196 psw = State.sregs[5];
198 if ((psw & PSW_OV) != 0)
208 unsigned int op0, psw;
211 temp = (State.regs[OP[0]] << 23) >> 23;
213 psw = State.sregs[5];
215 if ((psw & PSW_CY) != 0)
225 unsigned int op0, psw;
228 temp = (State.regs[OP[0]] << 23) >> 23;
230 psw = State.sregs[5];
232 if ((psw & PSW_Z) != 0)
242 unsigned int op0, psw;
245 temp = (State.regs[OP[0]] << 23) >> 23;
247 psw = State.sregs[5];
249 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
259 unsigned int op0, psw;
262 temp = (State.regs[OP[0]] << 23) >> 23;
264 psw = State.sregs[5];
266 if ((psw & PSW_S) != 0)
279 temp = (State.regs[OP[0]] << 23) >> 23;
288 unsigned int op0, psw;
291 temp = (State.regs[OP[0]] << 23) >> 23;
293 psw = State.sregs[5];
295 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
305 unsigned int op0, psw;
308 temp = (State.regs[OP[0]] << 23) >> 23;
310 psw = State.sregs[5];
312 if ((((psw & PSW_Z) != 0)
313 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
323 unsigned int op0, psw;
326 temp = (State.regs[OP[0]] << 23) >> 23;
328 psw = State.sregs[5];
330 if ((psw & PSW_OV) == 0)
340 unsigned int op0, psw;
343 temp = (State.regs[OP[0]] << 23) >> 23;
345 psw = State.sregs[5];
347 if ((psw & PSW_CY) == 0)
357 unsigned int op0, psw;
360 temp = (State.regs[OP[0]] << 23) >> 23;
362 psw = State.sregs[5];
364 if ((psw & PSW_Z) == 0)
374 unsigned int op0, psw;
377 temp = (State.regs[OP[0]] << 23) >> 23;
379 psw = State.sregs[5];
381 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
391 unsigned int op0, psw;
394 temp = (State.regs[OP[0]] << 23) >> 23;
396 psw = State.sregs[5];
398 if ((psw & PSW_S) == 0)
408 unsigned int op0, psw;
411 temp = (State.regs[OP[0]] << 23) >> 23;
413 psw = State.sregs[5];
415 if ((psw & PSW_SAT) != 0)
425 unsigned int op0, psw;
428 temp = (State.regs[OP[0]] << 23) >> 23;
430 psw = State.sregs[5];
432 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
442 unsigned int op0, psw;
445 temp = (State.regs[OP[0]] << 23) >> 23;
447 psw = State.sregs[5];
449 if ((((psw & PSW_Z) != 0)
450 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
460 /* interp.c will bump this by +2, so correct for it here. */
461 State.pc = State.regs[OP[0]] - 2;
464 /* jarl disp22, reg */
468 unsigned int op0, opc;
472 temp = (temp << 10) >> 10;
478 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
480 State.regs[OP[1]] = opc + 4;
487 unsigned int op0, op1, result, z, s, cy, ov;
489 /* Compute the result. */
490 op0 = State.regs[OP[0]];
491 op1 = State.regs[OP[1]];
494 /* Compute the condition codes. */
496 s = (result & 0x80000000);
497 cy = (result < op0 || result < op1);
498 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
499 && (op0 & 0x80000000) != (result & 0x80000000));
501 /* Store the result and condition codes. */
502 State.regs[OP[1]] = result;
503 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
504 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
505 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
508 /* add sign_extend(imm5), reg */
512 unsigned int op0, op1, result, z, s, cy, ov;
515 /* Compute the result. */
516 temp = (OP[0] & 0x1f);
517 temp = (temp << 27) >> 27;
519 op1 = State.regs[OP[1]];
522 /* Compute the condition codes. */
524 s = (result & 0x80000000);
525 cy = (result < op0 || result < op1);
526 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
527 && (op0 & 0x80000000) != (result & 0x80000000));
529 /* Store the result and condition codes. */
530 State.regs[OP[1]] = result;
531 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
532 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
533 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
536 /* addi sign_extend(imm16), reg, reg */
540 unsigned int op0, op1, result, z, s, cy, ov;
543 /* Compute the result. */
544 temp = (OP[0] & 0xffff);
545 temp = (temp << 16) >> 16;
547 op1 = State.regs[OP[1]];
550 /* Compute the condition codes. */
552 s = (result & 0x80000000);
553 cy = (result < op0 || result < op1);
554 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
555 && (op0 & 0x80000000) != (result & 0x80000000));
557 /* Store the result and condition codes. */
558 State.regs[OP[2]] = result;
559 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
560 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
561 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
568 unsigned int op0, op1, result, z, s, cy, ov;
570 /* Compute the result. */
571 op0 = State.regs[OP[0]];
572 op1 = State.regs[OP[1]];
575 /* Compute the condition codes. */
577 s = (result & 0x80000000);
578 cy = (result < -op0);
579 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
580 && (op1 & 0x80000000) != (result & 0x80000000));
582 /* Store the result and condition codes. */
583 State.regs[OP[1]] = result;
584 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
585 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
586 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
589 /* subr reg1, reg2 */
593 unsigned int op0, op1, result, z, s, cy, ov;
595 /* Compute the result. */
596 op0 = State.regs[OP[0]];
597 op1 = State.regs[OP[1]];
600 /* Compute the condition codes. */
602 s = (result & 0x80000000);
603 cy = (result < -op1);
604 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
605 && (op0 & 0x80000000) != (result & 0x80000000));
607 /* Store the result and condition codes. */
608 State.regs[OP[1]] = result;
609 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
610 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
611 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
614 /* mulh reg1, reg2 */
618 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
619 * (State.regs[OP[0]] & 0xffff));
622 /* mulh sign_extend(imm5), reg2
630 value = (value << 27) >> 27;
632 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
635 /* mulhi imm16, reg1, reg2 */
641 value = value & 0xffff;
643 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
646 /* divh reg1, reg2 */
650 unsigned int op0, op1, result, z, s, cy, ov;
653 /* Compute the result. */
654 temp = State.regs[OP[0]] & 0xffff;
655 temp = (temp << 16) >> 16;
657 op1 = State.regs[OP[1]];
659 if (op0 == 0xffffffff && op1 == 0x80000000)
672 /* Compute the condition codes. */
674 s = (result & 0x80000000);
676 /* Store the result and condition codes. */
677 State.regs[OP[1]] = result;
678 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
679 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
680 | (ov ? PSW_OV : 0));
687 unsigned int op0, op1, result, z, s, cy, ov;
689 /* Compute the result. */
690 op0 = State.regs[OP[0]];
691 op1 = State.regs[OP[1]];
694 /* Compute the condition codes. */
696 s = (result & 0x80000000);
697 cy = (result < -op0);
698 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
699 && (op1 & 0x80000000) != (result & 0x80000000));
701 /* Set condition codes. */
702 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
703 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
704 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
707 /* cmp sign_extend(imm5), reg */
711 unsigned int op0, op1, result, z, s, cy, ov;
714 /* Compute the result. */
716 temp = (temp << 27) >> 27;
718 op1 = State.regs[OP[1]];
721 /* Compute the condition codes. */
723 s = (result & 0x80000000);
724 cy = (result < -op0);
725 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
726 && (op1 & 0x80000000) != (result & 0x80000000));
728 /* Set condition codes. */
729 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
730 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
731 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
738 /* Hack alert. We turn off a bit in op0 since we really only
740 unsigned int op0, psw, result;
743 psw = State.sregs[5];
748 result = ((psw & PSW_OV) != 0);
751 result = ((psw & PSW_CY) != 0);
754 result = ((psw & PSW_Z) != 0);
757 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
760 result = ((psw & PSW_S) != 0);
766 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
769 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
770 || ((psw & PSW_Z) != 0)) != 0);
773 result = ((psw & PSW_OV) == 0);
776 result = ((psw & PSW_CY) == 0);
779 result = ((psw & PSW_Z) == 0);
782 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
785 result = ((psw & PSW_S) == 0);
788 result = ((psw & PSW_SAT) != 0);
791 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
794 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
795 || ((psw & PSW_Z) != 0)) == 0);
799 State.regs[OP[1]] = result;
806 unsigned int op0, op1, result, z, s, cy, ov, sat;
808 /* Compute the result. */
809 op0 = State.regs[OP[0]];
810 op1 = State.regs[OP[1]];
813 /* Compute the condition codes. */
815 s = (result & 0x80000000);
816 cy = (result < op0 || result < op1);
817 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
818 && (op0 & 0x80000000) != (result & 0x80000000));
821 /* Store the result and condition codes. */
822 State.regs[OP[1]] = result;
823 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
824 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
825 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
826 | (sat ? PSW_SAT : 0));
828 /* Handle saturated results. */
830 State.regs[OP[1]] = 0x80000000;
832 State.regs[OP[1]] = 0x7fffffff;
835 /* satadd sign_extend(imm5), reg */
839 unsigned int op0, op1, result, z, s, cy, ov, sat;
843 /* Compute the result. */
844 temp = (OP[0] & 0x1f);
845 temp = (temp << 27) >> 27;
847 op1 = State.regs[OP[1]];
850 /* Compute the condition codes. */
852 s = (result & 0x80000000);
853 cy = (result < op0 || result < op1);
854 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
855 && (op0 & 0x80000000) != (result & 0x80000000));
858 /* Store the result and condition codes. */
859 State.regs[OP[1]] = result;
860 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
861 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
862 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
863 | (sat ? PSW_SAT : 0));
865 /* Handle saturated results. */
867 State.regs[OP[1]] = 0x80000000;
869 State.regs[OP[1]] = 0x7fffffff;
872 /* satsub reg1, reg2 */
876 unsigned int op0, op1, result, z, s, cy, ov, sat;
878 /* Compute the result. */
879 op0 = State.regs[OP[0]];
880 op1 = State.regs[OP[1]];
883 /* Compute the condition codes. */
885 s = (result & 0x80000000);
886 cy = (result < -op0);
887 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
888 && (op1 & 0x80000000) != (result & 0x80000000));
891 /* Store the result and condition codes. */
892 State.regs[OP[1]] = result;
893 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
894 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
895 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
896 | (sat ? PSW_SAT : 0));
898 /* Handle saturated results. */
900 State.regs[OP[1]] = 0x80000000;
902 State.regs[OP[1]] = 0x7fffffff;
905 /* satsubi sign_extend(imm16), reg */
909 unsigned int op0, op1, result, z, s, cy, ov, sat;
912 /* Compute the result. */
913 temp = (OP[0] & 0xffff);
914 temp = (temp << 16) >> 16;
916 op1 = State.regs[OP[1]];
919 /* Compute the condition codes. */
921 s = (result & 0x80000000);
922 cy = (result < -op0);
923 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
924 && (op1 & 0x80000000) != (result & 0x80000000));
927 /* Store the result and condition codes. */
928 State.regs[OP[1]] = result;
929 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
930 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
931 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
932 | (sat ? PSW_SAT : 0));
934 /* Handle saturated results. */
936 State.regs[OP[1]] = 0x80000000;
938 State.regs[OP[1]] = 0x7fffffff;
944 unsigned int op0, op1, result, z, s, cy, ov, sat;
946 /* Compute the result. */
947 op0 = State.regs[OP[0]];
948 op1 = State.regs[OP[1]];
951 /* Compute the condition codes. */
953 s = (result & 0x80000000);
954 cy = (result < -op0);
955 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
956 && (op1 & 0x80000000) != (result & 0x80000000));
959 /* Store the result and condition codes. */
960 State.regs[OP[1]] = result;
961 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
962 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
963 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
964 | (sat ? PSW_SAT : 0));
966 /* Handle saturated results. */
968 State.regs[OP[1]] = 0x80000000;
970 State.regs[OP[1]] = 0x7fffffff;
977 unsigned int op0, op1, result, z, s, cy, ov;
979 /* Compute the result. */
980 op0 = State.regs[OP[0]];
981 op1 = State.regs[OP[1]];
984 /* Compute the condition codes. */
986 s = (result & 0x80000000);
988 /* Store the condition codes. */
989 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
990 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
997 State.regs[OP[1]] = State.regs[OP[0]];
1000 /* mov sign_extend(imm5), reg */
1006 value = (value << 27) >> 27;
1007 State.regs[OP[1]] = value;
1010 /* movea sign_extend(imm16), reg, reg */
1017 value = (value << 16) >> 16;
1019 State.regs[OP[2]] = State.regs[OP[1]] + value;
1022 /* movhi imm16, reg, reg */
1028 value = (value & 0xffff) << 16;
1030 State.regs[OP[2]] = State.regs[OP[1]] + value;
1033 /* sar zero_extend(imm5),reg1 */
1037 unsigned int op0, op1, result, z, s, cy, ov;
1040 op1 = State.regs[OP[1]];
1041 result = (signed)op1 >> op0;
1043 /* Compute the condition codes. */
1045 s = (result & 0x80000000);
1046 cy = (op1 & (1 << (op0 - 1)));
1048 /* Store the result and condition codes. */
1049 State.regs[OP[1]] = result;
1050 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1051 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1052 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1055 /* sar reg1, reg2 */
1059 unsigned int op0, op1, result, z, s, cy, ov;
1061 op0 = State.regs[OP[0]] & 0x1f;
1062 op1 = State.regs[OP[1]];
1063 result = (signed)op1 >> op0;
1065 /* Compute the condition codes. */
1067 s = (result & 0x80000000);
1068 cy = (op1 & (1 << (op0 - 1)));
1070 /* Store the result and condition codes. */
1071 State.regs[OP[1]] = result;
1072 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1073 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1074 | (cy ? PSW_CY : 0));
1077 /* shl zero_extend(imm5),reg1 */
1081 unsigned int op0, op1, result, z, s, cy, ov;
1084 op1 = State.regs[OP[1]];
1085 result = op1 << op0;
1087 /* Compute the condition codes. */
1089 s = (result & 0x80000000);
1090 cy = (op1 & (1 << (32 - op0)));
1092 /* Store the result and condition codes. */
1093 State.regs[OP[1]] = result;
1094 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1095 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1096 | (cy ? PSW_CY : 0));
1099 /* shl reg1, reg2 */
1103 unsigned int op0, op1, result, z, s, cy, ov;
1105 op0 = State.regs[OP[0]] & 0x1f;
1106 op1 = State.regs[OP[1]];
1107 result = op1 << op0;
1109 /* Compute the condition codes. */
1111 s = (result & 0x80000000);
1112 cy = (op1 & (1 << (32 - op0)));
1114 /* Store the result and condition codes. */
1115 State.regs[OP[1]] = result;
1116 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1117 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1118 | (cy ? PSW_CY : 0));
1121 /* shr zero_extend(imm5),reg1 */
1125 unsigned int op0, op1, result, z, s, cy, ov;
1128 op1 = State.regs[OP[1]];
1129 result = op1 >> op0;
1131 /* Compute the condition codes. */
1133 s = (result & 0x80000000);
1134 cy = (op1 & (1 << (op0 - 1)));
1136 /* Store the result and condition codes. */
1137 State.regs[OP[1]] = result;
1138 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1139 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1140 | (cy ? PSW_CY : 0));
1143 /* shr reg1, reg2 */
1147 unsigned int op0, op1, result, z, s, cy, ov;
1149 op0 = State.regs[OP[0]] & 0x1f;
1150 op1 = State.regs[OP[1]];
1151 result = op1 >> op0;
1153 /* Compute the condition codes. */
1155 s = (result & 0x80000000);
1156 cy = (op1 & (1 << (op0 - 1)));
1158 /* Store the result and condition codes. */
1159 State.regs[OP[1]] = result;
1160 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1161 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1162 | (cy ? PSW_CY : 0));
1169 unsigned int op0, op1, result, z, s, cy, ov;
1171 /* Compute the result. */
1172 op0 = State.regs[OP[0]];
1173 op1 = State.regs[OP[1]];
1176 /* Compute the condition codes. */
1178 s = (result & 0x80000000);
1180 /* Store the result and condition codes. */
1181 State.regs[OP[1]] = result;
1182 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1183 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1186 /* ori zero_extend(imm16), reg, reg */
1190 unsigned int op0, op1, result, z, s, cy, ov;
1192 op0 = OP[0] & 0xffff;
1193 op1 = State.regs[OP[1]];
1196 /* Compute the condition codes. */
1198 s = (result & 0x80000000);
1200 /* Store the result and condition codes. */
1201 State.regs[OP[2]] = result;
1202 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1203 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1210 unsigned int op0, op1, result, z, s, cy, ov;
1212 /* Compute the result. */
1213 op0 = State.regs[OP[0]];
1214 op1 = State.regs[OP[1]];
1217 /* Compute the condition codes. */
1219 s = (result & 0x80000000);
1221 /* Store the result and condition codes. */
1222 State.regs[OP[1]] = result;
1223 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1224 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1227 /* andi zero_extend(imm16), reg, reg */
1231 unsigned int op0, op1, result, z, s, cy, ov;
1233 op0 = OP[0] & 0xffff;
1234 op1 = State.regs[OP[1]];
1237 /* Compute the condition codes. */
1240 /* Store the result and condition codes. */
1241 State.regs[OP[2]] = result;
1242 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1243 State.sregs[5] |= (z ? PSW_Z : 0);
1250 unsigned int op0, op1, result, z, s, cy, ov;
1252 /* Compute the result. */
1253 op0 = State.regs[OP[0]];
1254 op1 = State.regs[OP[1]];
1257 /* Compute the condition codes. */
1259 s = (result & 0x80000000);
1261 /* Store the result and condition codes. */
1262 State.regs[OP[1]] = result;
1263 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1264 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1267 /* xori zero_extend(imm16), reg, reg */
1271 unsigned int op0, op1, result, z, s, cy, ov;
1273 op0 = OP[0] & 0xffff;
1274 op1 = State.regs[OP[1]];
1277 /* Compute the condition codes. */
1279 s = (result & 0x80000000);
1281 /* Store the result and condition codes. */
1282 State.regs[OP[2]] = result;
1283 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1284 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1287 /* not reg1, reg2 */
1291 unsigned int op0, result, z, s, cy, ov;
1293 /* Compute the result. */
1294 op0 = State.regs[OP[0]];
1297 /* Compute the condition codes. */
1299 s = (result & 0x80000000);
1301 /* Store the result and condition codes. */
1302 State.regs[OP[1]] = result;
1303 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1304 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1311 unsigned int op0, op1, op2;
1314 op0 = State.regs[OP[0]];
1317 temp = (temp << 16) >> 16;
1319 temp = get_byte (State.mem + op0 + op2);
1320 State.sregs[5] &= ~PSW_Z;
1321 if ((temp & (1 << op1)) == 0)
1322 State.sregs[5] |= PSW_Z;
1324 put_byte (State.mem + op0 + op2, temp);
1331 unsigned int op0, op1, op2;
1334 op0 = State.regs[OP[0]];
1337 temp = (temp << 16) >> 16;
1339 temp = get_byte (State.mem + op0 + op2);
1340 State.sregs[5] &= ~PSW_Z;
1341 if ((temp & (1 << op1)) == 0)
1342 State.sregs[5] |= PSW_Z;
1344 put_byte (State.mem + op0 + op2, temp);
1351 unsigned int op0, op1, op2;
1354 op0 = State.regs[OP[0]];
1357 temp = (temp << 16) >> 16;
1359 temp = get_byte (State.mem + op0 + op2);
1360 State.sregs[5] &= ~PSW_Z;
1361 if ((temp & (1 << op1)) == 0)
1362 State.sregs[5] |= PSW_Z;
1363 temp &= ~(1 << op1);
1364 put_byte (State.mem + op0 + op2, temp);
1371 unsigned int op0, op1, op2;
1374 op0 = State.regs[OP[0]];
1377 temp = (temp << 16) >> 16;
1379 temp = get_byte (State.mem + op0 + op2);
1380 State.sregs[5] &= ~PSW_Z;
1381 if ((temp & (1 << op1)) == 0)
1382 State.sregs[5] |= PSW_Z;
1389 State.sregs[5] |= PSW_ID;
1396 State.sregs[5] &= ~PSW_ID;
1399 /* halt, not supported */
1406 /* reti, not supported */
1413 /* trap, not supportd */
1426 op0 = State.regs[OP[0]];
1427 State.sregs[OP[1]] = op0;
1430 /* stsr, not supported */
1436 op0 = State.sregs[OP[1]];
1437 State.regs[OP[0]] = op0;