4 #include "sys/syscall.h"
7 #if !defined(__GO32__) && !defined(_WIN32)
38 /* start-sanitize-v850e */
42 /* end-sanitize-v850e */
43 /* start-sanitize-v850eq */
48 /* end-sanitize-v850eq */
51 /* start-sanitize-v850e */
52 /* This is an array of the bit positions of registers r20 .. r31 in that order in a prepare/dispose instruction. */
53 static int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
54 /* end-sanitize-v850e */
55 /* start-sanitize-v850eq */
56 /* This is an array of the bit positions of registers r16 .. r31 in that order in a push/pop instruction. */
57 static int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
58 /* This is an array of the bit positions of registers r1 .. r15 in that order in a push/pop instruction. */
59 static int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
60 /* end-sanitize-v850eq */
63 static void trace_input PARAMS ((char *name, enum op_types type, int size));
64 static void trace_output PARAMS ((enum op_types result));
65 static int init_text_p = 0;
66 static asection *text;
67 static bfd_vma text_start;
68 static bfd_vma text_end;
71 #ifndef SIZE_INSTRUCTION
72 #define SIZE_INSTRUCTION 6
76 #define SIZE_OPERANDS 16
80 #define SIZE_VALUES 11
84 #define SIZE_LOCATION 40
89 trace_input (name, type, size)
100 const char *filename;
101 const char *functionname;
102 unsigned int linenumber;
104 if ((v850_debug & DEBUG_TRACE) == 0)
111 for (s = prog_bfd->sections; s; s = s->next)
112 if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
115 text_start = bfd_get_section_vma (prog_bfd, s);
116 text_end = text_start + bfd_section_size (prog_bfd, s);
121 if (text && PC >= text_start && PC < text_end)
123 filename = (const char *)0;
124 functionname = (const char *)0;
126 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
127 &filename, &functionname, &linenumber))
132 sprintf (p, "Line %5d ", linenumber);
138 sprintf (p, "Func %s ", functionname);
143 char *q = (char *) strrchr (filename, '/');
144 sprintf (p, "File %s ", (q) ? q+1 : filename);
153 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
155 SIZE_LOCATION, SIZE_LOCATION, buf,
156 SIZE_INSTRUCTION, name);
163 strcpy (buf, "unknown");
167 sprintf (buf, "%d", OP[0]);
171 sprintf (buf, "r%d", OP[0]);
176 case OP_REG_REG_MOVE:
177 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
182 case OP_IMM_REG_MOVE:
183 sprintf (buf, "%d,r%d", OP[0], OP[1]);
187 sprintf (buf, "%d", SEXT9 (OP[0]));
191 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
195 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
199 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
203 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
207 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
211 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
214 case OP_UIMM_REG_REG:
215 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
219 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
225 default: cond = "?"; break;
226 case 0x0: cond = "v"; break;
227 case 0x1: cond = "c"; break;
228 case 0x2: cond = "z"; break;
229 case 0x3: cond = "nh"; break;
230 case 0x4: cond = "s"; break;
231 case 0x5: cond = "t"; break;
232 case 0x6: cond = "lt"; break;
233 case 0x7: cond = "le"; break;
234 case 0x8: cond = "nv"; break;
235 case 0x9: cond = "nc"; break;
236 case 0xa: cond = "nz"; break;
237 case 0xb: cond = "h"; break;
238 case 0xc: cond = "ns"; break;
239 case 0xd: cond = "sa"; break;
240 case 0xe: cond = "ge"; break;
241 case 0xf: cond = "gt"; break;
244 sprintf (buf, "%s,r%d", cond, OP[1]);
253 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
257 for (i = 0; i < 12; i++)
258 if (OP[3] & (1 << type1_regs[i]))
259 strcat (buf, "r%d ", i + 20);
263 for (i = 0; i < 16; i++)
264 if (OP[3] & (1 << type2_regs[i]))
265 strcat (buf, "r%d ", i + 16);
266 if (OP[3] & (1 << 19))
267 strcat (buf, "F/EIPC, F/EIPSW " );
271 for (i = 0; i < 15; i++)
272 if (OP[3] & (1 << type3_regs[i]))
273 strcat (buf, "r%d ", i + 1);
274 if (OP[3] & (1 << 3))
275 strcat (buf, "PSW " );
276 if (OP[3] & (1 << 19))
277 strcat (buf, "F/EIPC, F/EIPSW " );
281 sprintf (buf, "r%d, [r%d]", OP[1], OP[0] );
285 if ((v850_debug & DEBUG_VALUES) == 0)
287 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
291 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
302 case OP_REG_REG_MOVE:
303 values[0] = State.regs[OP[0]];
310 values[0] = State.regs[OP[1]];
311 values[1] = State.regs[OP[0]];
317 values[0] = SEXT5 (OP[0]);
322 case OP_IMM_REG_MOVE:
323 values[0] = SEXT5 (OP[0]);
328 values[0] = State.pc;
329 values[1] = SEXT9 (OP[0]);
335 values[0] = OP[1] * size;
336 values[1] = State.regs[30];
341 values[0] = State.regs[OP[0]];
342 values[1] = OP[1] * size;
343 values[2] = State.regs[30];
348 values[0] = SEXT16 (OP[2]);
349 values[1] = State.regs[OP[0]];
354 values[0] = State.regs[OP[1]];
355 values[1] = SEXT16 (OP[2]);
356 values[2] = State.regs[OP[0]];
361 values[0] = SEXT22 (OP[0]);
362 values[1] = State.pc;
367 values[0] = SEXT16 (OP[0]) << size;
368 values[1] = State.regs[OP[1]];
372 case OP_UIMM_REG_REG:
373 values[0] = (OP[0] & 0xffff) << size;
374 values[1] = State.regs[OP[1]];
392 values[0] = State.regs[OP[0]];
397 values[0] = State.sregs[OP[1]];
401 for (i = 0; i < num_values; i++)
402 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
405 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
410 trace_output (result)
411 enum op_types result;
413 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
433 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
434 (unsigned long)State.regs[OP[0]]);
438 case OP_REG_REG_MOVE:
440 case OP_IMM_REG_MOVE:
443 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
444 (unsigned long)State.regs[OP[1]]);
448 case OP_UIMM_REG_REG:
449 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
450 (unsigned long)State.regs[OP[2]]);
455 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
456 (unsigned long)State.regs[OP[1]]);
460 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
461 (unsigned long)State.sregs[OP[1]]);
465 (*v850_callback->printf_filtered) (v850_callback, "\n");
470 #define trace_input(NAME, IN1, IN2)
471 #define trace_output(RESULT)
473 //#define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" );
478 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
480 condition_met (unsigned code)
482 unsigned int psw = PSW;
486 case 0x0: return ((psw & PSW_OV) != 0);
487 case 0x1: return ((psw & PSW_CY) != 0);
488 case 0x2: return ((psw & PSW_Z) != 0);
489 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
490 case 0x4: return ((psw & PSW_S) != 0);
491 /*case 0x5: return 1;*/
492 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
493 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
494 case 0x8: return ((psw & PSW_OV) == 0);
495 case 0x9: return ((psw & PSW_CY) == 0);
496 case 0xa: return ((psw & PSW_Z) == 0);
497 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
498 case 0xc: return ((psw & PSW_S) == 0);
499 case 0xd: return ((psw & PSW_SAT) != 0);
500 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
501 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
508 Add32 (unsigned long a1, unsigned long a2, int * carry)
510 unsigned long result = (a1 + a2);
512 * carry = (result < a1);
518 Multiply64 (boolean sign, unsigned long op0)
529 op1 = State.regs[ OP[1] ];
533 /* Compute sign of result and adjust operands if necessary. */
535 sign = (op0 ^ op1) & 0x80000000;
537 if (((signed long) op0) < 0)
540 if (((signed long) op1) < 0)
544 /* We can split the 32x32 into four 16x16 operations. This ensures
545 that we do not lose precision on 32bit only hosts: */
546 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
547 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
548 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
549 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
551 /* We now need to add all of these results together, taking care
552 to propogate the carries from the additions: */
553 RdLo = Add32 (lo, (mid1 << 16), & carry);
555 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
556 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
560 /* Negate result if necessary. */
564 if (RdLo == 0xFFFFFFFF)
573 State.regs[ OP[1] ] = RdLo;
574 State.regs[ OP[2] >> 11 ] = RdHi;
584 unsigned long result;
586 result = load_mem (State.regs[30] + (OP[3] & 0x7f), 1);
588 /* start-sanitize-v850eq */
590 trace_input ("sld.bu", OP_LOAD16, 1);
592 State.regs[ OP[1] ] = result;
594 /* end-sanitize-v850eq */
595 trace_input ("sld.b", OP_LOAD16, 1);
597 State.regs[ OP[1] ] = SEXT8 (result);
598 /* start-sanitize-v850eq */
600 /* end-sanitize-v850eq */
602 trace_output (OP_LOAD16);
611 unsigned long result;
613 result = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2);
615 /* start-sanitize-v850eq */
617 trace_input ("sld.hu", OP_LOAD16, 2);
619 State.regs[ OP[1] ] = result;
621 /* end-sanitize-v850eq */
622 trace_input ("sld.h", OP_LOAD16, 2);
624 State.regs[ OP[1] ] = SEXT16 (result);
625 /* start-sanitize-v850eq */
627 /* end-sanitize-v850eq */
629 trace_output (OP_LOAD16);
638 trace_input ("sld.w", OP_LOAD16, 4);
640 State.regs[ OP[1] ] = load_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 4);
642 trace_output (OP_LOAD16);
651 trace_input ("sst.b", OP_STORE16, 1);
653 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
655 trace_output (OP_STORE16);
664 trace_input ("sst.h", OP_STORE16, 2);
666 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
668 trace_output (OP_STORE16);
677 trace_input ("sst.w", OP_STORE16, 4);
679 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
681 trace_output (OP_STORE16);
692 trace_input ("ld.b", OP_LOAD32, 1);
694 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
696 State.regs[ OP[1] ] = SEXT8 (load_mem (adr, 1));
698 trace_output (OP_LOAD32);
709 trace_input ("ld.h", OP_LOAD32, 2);
711 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
714 State.regs[ OP[1] ] = SEXT16 (load_mem (adr, 2));
716 trace_output (OP_LOAD32);
727 trace_input ("ld.w", OP_LOAD32, 4);
729 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
732 State.regs[ OP[1] ] = load_mem (adr, 4);
734 trace_output (OP_LOAD32);
743 trace_input ("st.b", OP_STORE32, 1);
745 store_mem (State.regs[ OP[0] ] + SEXT16 (OP[2]), 1, State.regs[ OP[1] ]);
747 trace_output (OP_STORE32);
758 trace_input ("st.h", OP_STORE32, 2);
760 adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
763 store_mem (adr, 2, State.regs[ OP[1] ]);
765 trace_output (OP_STORE32);
776 trace_input ("st.w", OP_STORE32, 4);
778 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
781 store_mem (adr, 4, State.regs[ OP[1] ]);
783 trace_output (OP_STORE32);
794 trace_input ("Bcond", OP_COND_BR, 0);
795 trace_output (OP_COND_BR);
797 if (condition_met (code))
798 return SEXT9 (((OP[3] & 0x70) >> 3) | ((OP[3] & 0xf800) >> 7));
916 /* sld.bu disp4[ep], reg2 */
922 trace_input ("jmp", OP_REG, 0);
924 PC = State.regs[ OP[0] ];
926 trace_output (OP_REG);
928 return 0; /* Add nothing to the PC, we have already done it. */
930 /* start-sanitize-v850e */
933 unsigned long result;
935 result = load_mem (State.regs[30] + (OP[3] & 0xf), 1);
937 /* start-sanitize-v850eq */
939 trace_input ("sld.b", OP_LOAD16, 1);
941 State.regs[ OP[1] ] = SEXT8 (result);
943 /* end-sanitize-v850eq */
944 trace_input ("sld.bu", OP_LOAD16, 1);
946 State.regs[ OP[1] ] = result;
947 /* start-sanitize-v850eq */
949 /* end-sanitize-v850eq */
951 trace_output (OP_LOAD16);
955 /* end-sanitize-v850e */
958 /* jarl/jr disp22, reg */
962 trace_input ("jarl/jr", OP_JUMP, 0);
965 State.regs[ OP[1] ] = PC + 4;
967 trace_output (OP_JUMP);
969 return SEXT22 (((OP[3] & 0x3f) << 16) | OP[2]);
976 unsigned int op0, op1, result, z, s, cy, ov;
978 trace_input ("add", OP_REG_REG, 0);
980 /* Compute the result. */
982 op0 = State.regs[ OP[0] ];
983 op1 = State.regs[ OP[1] ];
987 /* Compute the condition codes. */
989 s = (result & 0x80000000);
990 cy = (result < op0 || result < op1);
991 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
992 && (op0 & 0x80000000) != (result & 0x80000000));
994 /* Store the result and condition codes. */
995 State.regs[OP[1]] = result;
996 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
997 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
998 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
999 trace_output (OP_REG_REG);
1004 /* add sign_extend(imm5), reg */
1008 unsigned int op0, op1, result, z, s, cy, ov;
1011 trace_input ("add", OP_IMM_REG, 0);
1013 /* Compute the result. */
1014 temp = SEXT5 (OP[0]);
1016 op1 = State.regs[OP[1]];
1019 /* Compute the condition codes. */
1021 s = (result & 0x80000000);
1022 cy = (result < op0 || result < op1);
1023 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1024 && (op0 & 0x80000000) != (result & 0x80000000));
1026 /* Store the result and condition codes. */
1027 State.regs[OP[1]] = result;
1028 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1029 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1030 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1031 trace_output (OP_IMM_REG);
1036 /* addi sign_extend(imm16), reg, reg */
1040 unsigned int op0, op1, result, z, s, cy, ov;
1042 trace_input ("addi", OP_IMM_REG_REG, 0);
1044 /* Compute the result. */
1046 op0 = SEXT16 (OP[2]);
1047 op1 = State.regs[ OP[0] ];
1050 /* Compute the condition codes. */
1052 s = (result & 0x80000000);
1053 cy = (result < op0 || result < op1);
1054 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1055 && (op0 & 0x80000000) != (result & 0x80000000));
1057 /* Store the result and condition codes. */
1058 State.regs[OP[1]] = result;
1059 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1060 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1061 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1062 trace_output (OP_IMM_REG_REG);
1067 /* sub reg1, reg2 */
1071 unsigned int op0, op1, result, z, s, cy, ov;
1073 trace_input ("sub", OP_REG_REG, 0);
1074 /* Compute the result. */
1075 op0 = State.regs[ OP[0] ];
1076 op1 = State.regs[ OP[1] ];
1079 /* Compute the condition codes. */
1081 s = (result & 0x80000000);
1083 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1084 && (op1 & 0x80000000) != (result & 0x80000000));
1086 /* Store the result and condition codes. */
1087 State.regs[OP[1]] = result;
1088 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1089 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1090 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1091 trace_output (OP_REG_REG);
1096 /* subr reg1, reg2 */
1100 unsigned int op0, op1, result, z, s, cy, ov;
1102 trace_input ("subr", OP_REG_REG, 0);
1103 /* Compute the result. */
1104 op0 = State.regs[ OP[0] ];
1105 op1 = State.regs[ OP[1] ];
1108 /* Compute the condition codes. */
1110 s = (result & 0x80000000);
1112 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1113 && (op0 & 0x80000000) != (result & 0x80000000));
1115 /* Store the result and condition codes. */
1116 State.regs[OP[1]] = result;
1117 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1118 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1119 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1120 trace_output (OP_REG_REG);
1126 /* mulh reg1, reg2 */
1130 /* start-sanitize-v850e */
1133 trace_input ("sxh", OP_REG, 0);
1135 State.regs[ OP[0] ] = SEXT16 (State.regs[ OP[0] ]);
1137 trace_output (OP_REG);
1140 /* end-sanitize-v850e */
1142 trace_input ("mulh", OP_REG_REG, 0);
1144 State.regs[ OP[1] ] = (SEXT16 (State.regs[ OP[1] ]) * SEXT16 (State.regs[ OP[0] ]));
1146 trace_output (OP_REG_REG);
1152 /* mulh sign_extend(imm5), reg2 */
1156 trace_input ("mulh", OP_IMM_REG, 0);
1158 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
1160 trace_output (OP_IMM_REG);
1165 /* mulhi imm16, reg1, reg2 */
1174 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1176 State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[0] ]) * SEXT16 (OP[2]);
1178 trace_output (OP_IMM_REG_REG);
1184 /* divh reg1, reg2 */
1189 /* start-sanitize-v850e */
1194 trace_input ("switch", OP_REG, 0);
1196 adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
1197 State.pc = State.pc + 2 + (SEXT16 (load_mem (adr, 2)) << 1);
1199 trace_output (OP_REG);
1202 /* end-sanitize-v850e */
1204 unsigned int op0, op1, result, ov, s, z;
1207 trace_input ("divh", OP_REG_REG, 0);
1209 /* Compute the result. */
1210 temp = SEXT16 (State.regs[ OP[0] ]);
1212 op1 = State.regs[OP[1]];
1214 if (op0 == 0xffffffff && op1 == 0x80000000)
1216 result = 0x80000000;
1230 /* Compute the condition codes. */
1232 s = (result & 0x80000000);
1234 /* Store the result and condition codes. */
1235 State.regs[OP[1]] = result;
1236 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1237 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1238 | (ov ? PSW_OV : 0));
1239 trace_output (OP_REG_REG);
1249 unsigned int op0, op1, result, z, s, cy, ov;
1251 trace_input ("cmp", OP_REG_REG_CMP, 0);
1252 /* Compute the result. */
1253 op0 = State.regs[ OP[0] ];
1254 op1 = State.regs[ OP[1] ];
1257 /* Compute the condition codes. */
1259 s = (result & 0x80000000);
1261 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1262 && (op1 & 0x80000000) != (result & 0x80000000));
1264 /* Set condition codes. */
1265 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1266 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1267 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1268 trace_output (OP_REG_REG_CMP);
1273 /* cmp sign_extend(imm5), reg */
1277 unsigned int op0, op1, result, z, s, cy, ov;
1280 /* Compute the result. */
1281 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1282 temp = SEXT5 (OP[0]);
1284 op1 = State.regs[OP[1]];
1287 /* Compute the condition codes. */
1289 s = (result & 0x80000000);
1291 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1292 && (op1 & 0x80000000) != (result & 0x80000000));
1294 /* Set condition codes. */
1295 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1296 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1297 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1298 trace_output (OP_IMM_REG_CMP);
1303 /* setf cccc,reg2 */
1307 trace_input ("setf", OP_EX1, 0);
1309 State.regs[ OP[1] ] = condition_met (OP[0]);
1311 trace_output (OP_EX1);
1317 /* satadd reg,reg */
1321 /* start-sanitize-v850e */
1324 trace_input ("zxh", OP_REG, 0);
1326 State.regs[ OP[0] ] &= 0xffff;
1328 trace_output (OP_REG);
1331 /* end-sanitize-v850e */
1333 unsigned int op0, op1, result, z, s, cy, ov, sat;
1335 trace_input ("satadd", OP_REG_REG, 0);
1336 /* Compute the result. */
1337 op0 = State.regs[ OP[0] ];
1338 op1 = State.regs[ OP[1] ];
1341 /* Compute the condition codes. */
1343 s = (result & 0x80000000);
1344 cy = (result < op0 || result < op1);
1345 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1346 && (op0 & 0x80000000) != (result & 0x80000000));
1349 /* Store the result and condition codes. */
1350 State.regs[OP[1]] = result;
1351 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1352 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1353 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1354 | (sat ? PSW_SAT : 0));
1356 /* Handle saturated results. */
1358 State.regs[OP[1]] = 0x80000000;
1360 State.regs[OP[1]] = 0x7fffffff;
1361 trace_output (OP_REG_REG);
1367 /* satadd sign_extend(imm5), reg */
1371 unsigned int op0, op1, result, z, s, cy, ov, sat;
1375 trace_input ("satadd", OP_IMM_REG, 0);
1377 /* Compute the result. */
1378 temp = SEXT5 (OP[0]);
1380 op1 = State.regs[OP[1]];
1383 /* Compute the condition codes. */
1385 s = (result & 0x80000000);
1386 cy = (result < op0 || result < op1);
1387 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1388 && (op0 & 0x80000000) != (result & 0x80000000));
1391 /* Store the result and condition codes. */
1392 State.regs[OP[1]] = result;
1393 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1394 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1395 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1396 | (sat ? PSW_SAT : 0));
1398 /* Handle saturated results. */
1400 State.regs[OP[1]] = 0x80000000;
1402 State.regs[OP[1]] = 0x7fffffff;
1403 trace_output (OP_IMM_REG);
1408 /* satsub reg1, reg2 */
1413 /* start-sanitize-v850e */
1416 trace_input ("sxb", OP_REG, 0);
1418 State.regs[ OP[0] ] = SEXT8 (State.regs[ OP[0] ]);
1420 trace_output (OP_REG);
1423 /* end-sanitize-v850e */
1425 unsigned int op0, op1, result, z, s, cy, ov, sat;
1427 trace_input ("satsub", OP_REG_REG, 0);
1429 /* Compute the result. */
1430 op0 = State.regs[ OP[0] ];
1431 op1 = State.regs[ OP[1] ];
1434 /* Compute the condition codes. */
1436 s = (result & 0x80000000);
1438 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1439 && (op1 & 0x80000000) != (result & 0x80000000));
1442 /* Store the result and condition codes. */
1443 State.regs[OP[1]] = result;
1444 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1445 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1446 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1447 | (sat ? PSW_SAT : 0));
1449 /* Handle saturated results. */
1451 State.regs[OP[1]] = 0x80000000;
1453 State.regs[OP[1]] = 0x7fffffff;
1454 trace_output (OP_REG_REG);
1460 /* satsubi sign_extend(imm16), reg */
1464 unsigned int op0, op1, result, z, s, cy, ov, sat;
1467 trace_input ("satsubi", OP_IMM_REG, 0);
1469 /* Compute the result. */
1470 temp = SEXT16 (OP[2]);
1472 op1 = State.regs[ OP[0] ];
1475 /* Compute the condition codes. */
1477 s = (result & 0x80000000);
1479 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1480 && (op1 & 0x80000000) != (result & 0x80000000));
1483 /* Store the result and condition codes. */
1484 State.regs[OP[1]] = result;
1485 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1486 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1487 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1488 | (sat ? PSW_SAT : 0));
1490 /* Handle saturated results. */
1492 State.regs[OP[1]] = 0x80000000;
1494 State.regs[OP[1]] = 0x7fffffff;
1495 trace_output (OP_IMM_REG);
1500 /* satsubr reg,reg */
1505 /* start-sanitize-v850e */
1508 trace_input ("zxb", OP_REG, 0);
1510 State.regs[ OP[0] ] &= 0xff;
1512 trace_output (OP_REG);
1515 /* end-sanitize-v850e */
1517 unsigned int op0, op1, result, z, s, cy, ov, sat;
1519 trace_input ("satsubr", OP_REG_REG, 0);
1521 /* Compute the result. */
1522 op0 = State.regs[ OP[0] ];
1523 op1 = State.regs[ OP[1] ];
1526 /* Compute the condition codes. */
1528 s = (result & 0x80000000);
1529 cy = (result < op0);
1530 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1531 && (op1 & 0x80000000) != (result & 0x80000000));
1534 /* Store the result and condition codes. */
1535 State.regs[OP[1]] = result;
1536 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1537 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1538 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1539 | (sat ? PSW_SAT : 0));
1541 /* Handle saturated results. */
1543 State.regs[OP[1]] = 0x80000000;
1545 State.regs[OP[1]] = 0x7fffffff;
1546 trace_output (OP_REG_REG);
1556 unsigned int op0, op1, result, z, s;
1558 trace_input ("tst", OP_REG_REG_CMP, 0);
1560 /* Compute the result. */
1561 op0 = State.regs[ OP[0] ];
1562 op1 = State.regs[ OP[1] ];
1565 /* Compute the condition codes. */
1567 s = (result & 0x80000000);
1569 /* Store the condition codes. */
1570 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1571 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1572 trace_output (OP_REG_REG_CMP);
1581 trace_input ("mov", OP_REG_REG_MOVE, 0);
1583 State.regs[ OP[1] ] = State.regs[ OP[0] ];
1585 trace_output (OP_REG_REG_MOVE);
1590 /* mov sign_extend(imm5), reg */
1595 /* start-sanitize-v850e */
1600 trace_input ("callt", OP_LOAD16, 1);
1605 adr = CTBP + ((OP[3] & 0x3f) << 1);
1607 PC = CTBP + load_mem (adr, 1);
1609 trace_output (OP_LOAD16);
1614 /* end-sanitize-v850e */
1616 int value = SEXT5 (OP[0]);
1618 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1620 State.regs[ OP[1] ] = value;
1622 trace_output (OP_IMM_REG_MOVE);
1628 /* mov imm32, reg1 */
1629 /* movea sign_extend(imm16), reg, reg */
1633 /* start-sanitize-v850e */
1636 trace_input ("mov", OP_IMM32_REG, 4);
1638 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
1640 trace_output (OP_IMM32_REG);
1645 /* end-sanitize-v850e */
1647 trace_input ("movea", OP_IMM_REG_REG, 0);
1649 State.regs[ OP[1] ] = State.regs[ OP[0] ] + SEXT16 (OP[2]);
1651 trace_output (OP_IMM_REG_REG);
1657 /* dispose imm5, list12 [, reg1] */
1658 /* movhi imm16, reg, reg */
1662 /* start-sanitize-v850e */
1668 trace_input ("dispose", OP_PUSHPOP1, 0);
1670 SP += (OP[3] & 0x3e) << 1;
1672 /* Load the registers with lower number registers being retrieved from lower addresses. */
1673 for (i = 0; i < 12; i++)
1674 if ((OP[3] & (1 << type1_regs[ i ])))
1676 State.regs[ 20 + i ] = load_mem (SP, 4);
1680 if ((OP[3] & 0x1f0000) != 0)
1682 PC = State.regs[ (OP[3] >> 16) & 0x1f];
1686 trace_output (OP_PUSHPOP1);
1689 /* end-sanitize-v850e */
1691 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1693 State.regs[ OP[1] ] = State.regs[ OP[0] ] + OP[2] << 16;
1695 trace_output (OP_UIMM_REG_REG);
1701 /* sar zero_extend(imm5),reg1 */
1705 unsigned int op0, op1, result, z, s, cy;
1707 trace_input ("sar", OP_IMM_REG, 0);
1709 op1 = State.regs[ OP[1] ];
1710 result = (signed)op1 >> op0;
1712 /* Compute the condition codes. */
1714 s = (result & 0x80000000);
1715 cy = (op1 & (1 << (op0 - 1)));
1717 /* Store the result and condition codes. */
1718 State.regs[ OP[1] ] = result;
1719 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1720 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1721 | (cy ? PSW_CY : 0));
1722 trace_output (OP_IMM_REG);
1727 /* sar reg1, reg2 */
1731 unsigned int op0, op1, result, z, s, cy;
1733 trace_input ("sar", OP_REG_REG, 0);
1735 op0 = State.regs[ OP[0] ] & 0x1f;
1736 op1 = State.regs[ OP[1] ];
1737 result = (signed)op1 >> op0;
1739 /* Compute the condition codes. */
1741 s = (result & 0x80000000);
1742 cy = (op1 & (1 << (op0 - 1)));
1744 /* Store the result and condition codes. */
1745 State.regs[OP[1]] = result;
1746 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1747 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1748 | (cy ? PSW_CY : 0));
1749 trace_output (OP_REG_REG);
1754 /* shl zero_extend(imm5),reg1 */
1758 unsigned int op0, op1, result, z, s, cy;
1760 trace_input ("shl", OP_IMM_REG, 0);
1762 op1 = State.regs[ OP[1] ];
1763 result = op1 << op0;
1765 /* Compute the condition codes. */
1767 s = (result & 0x80000000);
1768 cy = (op1 & (1 << (32 - op0)));
1770 /* Store the result and condition codes. */
1771 State.regs[OP[1]] = result;
1772 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1773 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1774 | (cy ? PSW_CY : 0));
1775 trace_output (OP_IMM_REG);
1780 /* shl reg1, reg2 */
1784 unsigned int op0, op1, result, z, s, cy;
1786 trace_input ("shl", OP_REG_REG, 0);
1787 op0 = State.regs[ OP[0] ] & 0x1f;
1788 op1 = State.regs[ OP[1] ];
1789 result = op1 << op0;
1791 /* Compute the condition codes. */
1793 s = (result & 0x80000000);
1794 cy = (op1 & (1 << (32 - op0)));
1796 /* Store the result and condition codes. */
1797 State.regs[OP[1]] = result;
1798 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1799 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1800 | (cy ? PSW_CY : 0));
1801 trace_output (OP_REG_REG);
1806 /* shr zero_extend(imm5),reg1 */
1810 unsigned int op0, op1, result, z, s, cy;
1812 trace_input ("shr", OP_IMM_REG, 0);
1814 op1 = State.regs[ OP[1] ];
1815 result = op1 >> op0;
1817 /* Compute the condition codes. */
1819 s = (result & 0x80000000);
1820 cy = (op1 & (1 << (op0 - 1)));
1822 /* Store the result and condition codes. */
1823 State.regs[OP[1]] = result;
1824 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1825 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1826 | (cy ? PSW_CY : 0));
1827 trace_output (OP_IMM_REG);
1832 /* shr reg1, reg2 */
1836 unsigned int op0, op1, result, z, s, cy;
1838 trace_input ("shr", OP_REG_REG, 0);
1839 op0 = State.regs[ OP[0] ] & 0x1f;
1840 op1 = State.regs[ OP[1] ];
1841 result = op1 >> op0;
1843 /* Compute the condition codes. */
1845 s = (result & 0x80000000);
1846 cy = (op1 & (1 << (op0 - 1)));
1848 /* Store the result and condition codes. */
1849 State.regs[OP[1]] = result;
1850 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1851 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1852 | (cy ? PSW_CY : 0));
1853 trace_output (OP_REG_REG);
1862 unsigned int op0, op1, result, z, s;
1864 trace_input ("or", OP_REG_REG, 0);
1866 /* Compute the result. */
1867 op0 = State.regs[ OP[0] ];
1868 op1 = State.regs[ OP[1] ];
1871 /* Compute the condition codes. */
1873 s = (result & 0x80000000);
1875 /* Store the result and condition codes. */
1876 State.regs[OP[1]] = result;
1877 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1878 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1879 trace_output (OP_REG_REG);
1884 /* ori zero_extend(imm16), reg, reg */
1888 unsigned int op0, op1, result, z, s;
1890 trace_input ("ori", OP_UIMM_REG_REG, 0);
1892 op1 = State.regs[ OP[0] ];
1895 /* Compute the condition codes. */
1897 s = (result & 0x80000000);
1899 /* Store the result and condition codes. */
1900 State.regs[OP[1]] = result;
1901 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1902 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1903 trace_output (OP_UIMM_REG_REG);
1912 unsigned int op0, op1, result, z, s;
1914 trace_input ("and", OP_REG_REG, 0);
1916 /* Compute the result. */
1917 op0 = State.regs[ OP[0] ];
1918 op1 = State.regs[ OP[1] ];
1921 /* Compute the condition codes. */
1923 s = (result & 0x80000000);
1925 /* Store the result and condition codes. */
1926 State.regs[OP[1]] = result;
1927 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1928 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1929 trace_output (OP_REG_REG);
1934 /* andi zero_extend(imm16), reg, reg */
1938 unsigned int result, z;
1940 trace_input ("andi", OP_UIMM_REG_REG, 0);
1942 result = OP[2] & State.regs[ OP[0] ];
1944 /* Compute the condition codes. */
1947 /* Store the result and condition codes. */
1948 State.regs[ OP[1] ] = result;
1950 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1951 PSW |= (z ? PSW_Z : 0);
1953 trace_output (OP_UIMM_REG_REG);
1962 unsigned int op0, op1, result, z, s;
1964 trace_input ("xor", OP_REG_REG, 0);
1966 /* Compute the result. */
1967 op0 = State.regs[ OP[0] ];
1968 op1 = State.regs[ OP[1] ];
1971 /* Compute the condition codes. */
1973 s = (result & 0x80000000);
1975 /* Store the result and condition codes. */
1976 State.regs[OP[1]] = result;
1977 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1978 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1979 trace_output (OP_REG_REG);
1984 /* xori zero_extend(imm16), reg, reg */
1988 unsigned int op0, op1, result, z, s;
1990 trace_input ("xori", OP_UIMM_REG_REG, 0);
1992 op1 = State.regs[ OP[0] ];
1995 /* Compute the condition codes. */
1997 s = (result & 0x80000000);
1999 /* Store the result and condition codes. */
2000 State.regs[OP[1]] = result;
2001 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2002 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2003 trace_output (OP_UIMM_REG_REG);
2008 /* not reg1, reg2 */
2012 unsigned int op0, result, z, s;
2014 trace_input ("not", OP_REG_REG_MOVE, 0);
2015 /* Compute the result. */
2016 op0 = State.regs[ OP[0] ];
2019 /* Compute the condition codes. */
2021 s = (result & 0x80000000);
2023 /* Store the result and condition codes. */
2024 State.regs[OP[1]] = result;
2025 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2026 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
2027 trace_output (OP_REG_REG_MOVE);
2036 unsigned int op0, op1, op2;
2039 trace_input ("set1", OP_BIT, 0);
2040 op0 = State.regs[ OP[0] ];
2042 temp = SEXT16 (OP[2]);
2044 temp = load_mem (op0 + op2, 1);
2046 if ((temp & (1 << op1)) == 0)
2049 store_mem (op0 + op2, 1, temp);
2050 trace_output (OP_BIT);
2059 unsigned int op0, op1, op2;
2062 trace_input ("not1", OP_BIT, 0);
2063 op0 = State.regs[ OP[0] ];
2065 temp = SEXT16 (OP[2]);
2067 temp = load_mem (op0 + op2, 1);
2069 if ((temp & (1 << op1)) == 0)
2072 store_mem (op0 + op2, 1, temp);
2073 trace_output (OP_BIT);
2082 unsigned int op0, op1, op2;
2085 trace_input ("clr1", OP_BIT, 0);
2086 op0 = State.regs[ OP[0] ];
2088 temp = SEXT16 (OP[2]);
2090 temp = load_mem (op0 + op2, 1);
2092 if ((temp & (1 << op1)) == 0)
2094 temp &= ~(1 << op1);
2095 store_mem (op0 + op2, 1, temp);
2096 trace_output (OP_BIT);
2105 unsigned int op0, op1, op2;
2108 trace_input ("tst1", OP_BIT, 0);
2109 op0 = State.regs[ OP[0] ];
2111 temp = SEXT16 (OP[2]);
2113 temp = load_mem (op0 + op2, 1);
2115 if ((temp & (1 << op1)) == 0)
2117 trace_output (OP_BIT);
2126 State.exception = SIGTRAP;
2134 trace_input ("di", OP_NONE, 0);
2136 trace_output (OP_NONE);
2145 trace_input ("ei", OP_NONE, 0);
2147 trace_output (OP_NONE);
2156 trace_input ("halt", OP_NONE, 0);
2157 /* FIXME this should put processor into a mode where NMI still handled */
2158 State.exception = SIGQUIT;
2159 trace_output (OP_NONE);
2168 trace_input ("reti", OP_NONE, 0);
2169 trace_output (OP_NONE);
2171 /* Restore for NMI if only NP on, otherwise is interrupt or exception. */
2172 if ((PSW & (PSW_NP | PSW_EP)) == PSW_NP)
2190 trace_input ("trap", OP_TRAP, 0);
2191 trace_output (OP_TRAP);
2193 /* Trap 31 is used for simulating OS I/O functions */
2197 int save_errno = errno;
2200 /* Registers passed to trap 0 */
2202 #define FUNC State.regs[6] /* function number, return value */
2203 #define PARM1 State.regs[7] /* optional parm 1 */
2204 #define PARM2 State.regs[8] /* optional parm 2 */
2205 #define PARM3 State.regs[9] /* optional parm 3 */
2207 /* Registers set by trap 0 */
2209 #define RETVAL State.regs[10] /* return value */
2210 #define RETERR State.regs[11] /* return error code */
2212 /* Turn a pointer in a register into a pointer into real memory. */
2214 #define MEMPTR(x) (map (x))
2218 #if !defined(__GO32__) && !defined(_WIN32)
2223 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2224 (char **)MEMPTR (PARM3));
2228 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2238 RETVAL = pipe (host_fd);
2239 SW (buf, host_fd[0]);
2240 buf += sizeof(uint16);
2241 SW (buf, host_fd[1]);
2249 RETVAL = wait (&status);
2257 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
2262 RETVAL = (int)v850_callback->write_stdout (v850_callback,
2263 MEMPTR (PARM2), PARM3);
2265 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
2266 MEMPTR (PARM2), PARM3);
2269 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
2272 RETVAL = v850_callback->close (v850_callback, PARM1);
2275 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
2278 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
2279 State.exception = PARM1 & 0xffff; /* get signal encoded by kill */
2280 else if (PARM1 == 0xdead)
2281 State.exception = SIGABRT; /* old libraries */
2283 State.exception = SIG_V850_EXIT; /* PARM1 has exit status encoded */
2286 #if !defined(__GO32__) && !defined(_WIN32)
2287 case SYS_stat: /* added at hmsi */
2288 /* stat system call */
2290 struct stat host_stat;
2293 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2297 /* Just wild-assed guesses. */
2298 store_mem (buf, 2, host_stat.st_dev);
2299 store_mem (buf + 2, 2, host_stat.st_ino);
2300 store_mem (buf + 4, 4, host_stat.st_mode);
2301 store_mem (buf + 8, 2, host_stat.st_nlink);
2302 store_mem (buf + 10, 2, host_stat.st_uid);
2303 store_mem (buf + 12, 2, host_stat.st_gid);
2304 store_mem (buf + 14, 2, host_stat.st_rdev);
2305 store_mem (buf + 16, 4, host_stat.st_size);
2306 store_mem (buf + 20, 4, host_stat.st_atime);
2307 store_mem (buf + 28, 4, host_stat.st_mtime);
2308 store_mem (buf + 36, 4, host_stat.st_ctime);
2313 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2316 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2322 RETVAL = time (&now);
2323 store_mem (PARM1, 4, now);
2331 RETVAL = times (&tms);
2332 store_mem (PARM1, 4, tms.tms_utime);
2333 store_mem (PARM1 + 4, 4, tms.tms_stime);
2334 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2335 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2339 case SYS_gettimeofday:
2343 RETVAL = gettimeofday (&t, &tz);
2344 store_mem (PARM1, 4, t.tv_sec);
2345 store_mem (PARM1 + 4, 4, t.tv_usec);
2346 store_mem (PARM2, 4, tz.tz_minuteswest);
2347 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2352 /* Cast the second argument to void *, to avoid type mismatch
2353 if a prototype is present. */
2354 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2367 { /* Trap 0 -> 30 */
2372 ECR |= 0x40 + OP[0];
2373 /* Flag that we are now doing exception processing. */
2374 PSW |= PSW_EP | PSW_ID;
2375 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2385 trace_input ("ldsr", OP_LDSR, 0);
2387 State.sregs[ OP[1] ] = State.regs[ OP[0] ];
2389 trace_output (OP_LDSR);
2400 trace_input ("stsr", OP_STSR, 0);
2402 State.regs[ OP[1] ] = State.sregs[ OP[0] ];
2404 trace_output (OP_STSR);
2409 /* tst1 reg2, [reg1] */
2415 trace_input ("tst1", OP_BIT_LOAD, 1);
2417 temp = load_mem (State.regs[ OP[0] ], 1);
2420 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
2423 trace_output (OP_BIT_LOAD);
2428 /* mulu reg1, reg2, reg3 */
2432 trace_input ("mulu", OP_REG_REG_REG, 0);
2434 Multiply64 (false, State.regs[ OP[0] ]);
2436 trace_output (OP_REG_REG_REG);
2441 /* start-sanitize-v850e */
2443 #define BIT_CHANGE_OP( name, binop ) \
2445 unsigned int temp; \
2447 trace_input (name, OP_BIT_CHANGE, 0); \
2449 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
2450 temp = load_mem (State.regs[ OP[0] ], 1); \
2453 if ((temp & bit) == 0) \
2457 store_mem (State.regs[ OP[0] ], 1, temp); \
2459 trace_output (OP_BIT_CHANGE); \
2463 /* clr1 reg2, [reg1] */
2467 BIT_CHANGE_OP ("clr1", &= ~ );
2470 /* not1 reg2, [reg1] */
2474 BIT_CHANGE_OP ("not1", ^= );
2481 BIT_CHANGE_OP ("set1", |= );
2488 trace_input ("sasf", OP_EX1, 0);
2490 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2492 trace_output (OP_EX1);
2496 /* end-sanitize-v850e */
2498 /* start-sanitize-v850eq */
2499 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2504 unsigned long int als,
2505 unsigned long int sfi,
2506 unsigned long int * quotient_ptr,
2507 unsigned long int * remainder_ptr,
2508 boolean * overflow_ptr
2511 unsigned long ald = sfi >> N - 1;
2512 unsigned long alo = als;
2517 unsigned int R1 = 1;
2519 unsigned int DBZ = (als == 0) ? 1 : 0;
2520 unsigned long alt = Q ? ~als : als;
2523 alo = ald + alt + Q;
2524 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2527 R1 = (alo == 0) ? 0 : (R1 & Q);
2528 if ((S ^ (alo>>31)) && !C)
2533 sfi = (sfi << (32-N+1)) | Q;
2534 ald = (alo << 1) | (sfi >> 31);
2536 /* 2nd - N-1th Loop */
2537 for (i = 2; i < N; i++)
2539 alt = Q ? ~als : als;
2540 alo = ald + alt + Q;
2541 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2544 R1 = (alo == 0) ? 0 : (R1 & Q);
2545 if ((S ^ (alo>>31)) && !C && !DBZ)
2550 sfi = (sfi << 1) | Q;
2551 ald = (alo << 1) | (sfi >> 31);
2555 alt = Q ? ~als : als;
2556 alo = ald + alt + Q;
2557 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2560 R1 = (alo == 0) ? 0 : (R1 & Q);
2561 if ((S ^ (alo>>31)) && !C)
2566 * quotient_ptr = (sfi << 1) | Q;
2567 * remainder_ptr = Q ? alo : (alo + als);
2568 * overflow_ptr = DBZ | R1;
2571 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2576 unsigned long int als,
2577 unsigned long int sfi,
2578 signed long int * quotient_ptr,
2579 signed long int * remainder_ptr,
2580 boolean * overflow_ptr
2583 unsigned long ald = (signed long) sfi >> (N - 1);
2584 unsigned long alo = als;
2585 unsigned int SS = als >> 31;
2586 unsigned int SD = sfi >> 31;
2587 unsigned int R1 = 1;
2589 unsigned int DBZ = als == 0 ? 1 : 0;
2590 unsigned int Q = ~(SS ^ SD) & 1;
2594 unsigned long alt = Q ? ~als : als;
2599 alo = ald + alt + Q;
2600 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2602 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2604 sfi = (sfi << (32-N+1)) | Q;
2605 ald = (alo << 1) | (sfi >> 31);
2606 if ((alo >> 31) ^ (ald >> 31))
2611 /* 2nd - N-1th Loop */
2613 for (i = 2; i < N; i++)
2615 alt = Q ? ~als : als;
2616 alo = ald + alt + Q;
2617 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2619 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2621 sfi = (sfi << 1) | Q;
2622 ald = (alo << 1) | (sfi >> 31);
2623 if ((alo >> 31) ^ (ald >> 31))
2630 alt = Q ? ~als : als;
2631 alo = ald + alt + Q;
2632 C = (alt >> 31) & (ald >> 31) | ((alt >> 31) ^ (ald >> 31)) & (~alo >> 31);
2634 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2635 sfi = (sfi << (32-N+1));
2641 alt = Q ? ~als : als;
2642 alo = ald + alt + Q;
2644 R1 = R1 & ((~alo >> 31) ^ SD);
2645 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2647 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2649 ald = sfi = sfi | Q;
2651 OV = DBZ | ((alo == 0) ? 0 : R1);
2653 * remainder_ptr = alo;
2656 if ((alo != 0) && ((SS ^ SD) ^ R1) || (alo == 0) && (SS ^ R1))
2661 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2663 * quotient_ptr = alo;
2664 * overflow_ptr = OV;
2667 /* sdivun imm5, reg1, reg2, reg3 */
2671 unsigned long int quotient;
2672 unsigned long int remainder;
2673 unsigned long int divide_by;
2674 unsigned long int divide_this;
2675 boolean overflow = false;
2678 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2680 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2682 divide_by = State.regs[ OP[0] ];
2683 divide_this = State.regs[ OP[1] ] << imm5;
2685 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2687 State.regs[ OP[1] ] = quotient;
2688 State.regs[ OP[2] >> 11 ] = remainder;
2690 /* Set condition codes. */
2691 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2693 if (overflow) PSW |= PSW_OV;
2694 if (quotient == 0) PSW |= PSW_Z;
2696 trace_output (OP_IMM_REG_REG_REG);
2701 /* sdivn imm5, reg1, reg2, reg3 */
2705 signed long int quotient;
2706 signed long int remainder;
2707 signed long int divide_by;
2708 signed long int divide_this;
2709 boolean overflow = false;
2712 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2714 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2716 divide_by = State.regs[ OP[0] ];
2717 divide_this = State.regs[ OP[1] ] << imm5;
2719 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2721 State.regs[ OP[1] ] = quotient;
2722 State.regs[ OP[2] >> 11 ] = remainder;
2724 /* Set condition codes. */
2725 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2727 if (overflow) PSW |= PSW_OV;
2728 if (quotient == 0) PSW |= PSW_Z;
2729 if (quotient < 0) PSW |= PSW_S;
2731 trace_output (OP_IMM_REG_REG_REG);
2736 /* sdivhun imm5, reg1, reg2, reg3 */
2740 unsigned long int quotient;
2741 unsigned long int remainder;
2742 unsigned long int divide_by;
2743 unsigned long int divide_this;
2744 boolean overflow = false;
2747 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2749 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2751 divide_by = State.regs[ OP[0] ] & 0xffff;
2752 divide_this = State.regs[ OP[1] ] << imm5;
2754 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2756 State.regs[ OP[1] ] = quotient;
2757 State.regs[ OP[2] >> 11 ] = remainder;
2759 /* Set condition codes. */
2760 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2762 if (overflow) PSW |= PSW_OV;
2763 if (quotient == 0) PSW |= PSW_Z;
2765 trace_output (OP_IMM_REG_REG_REG);
2770 /* sdivhn imm5, reg1, reg2, reg3 */
2774 signed long int quotient;
2775 signed long int remainder;
2776 signed long int divide_by;
2777 signed long int divide_this;
2778 boolean overflow = false;
2781 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2783 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2785 divide_by = SEXT16 (State.regs[ OP[0] ]);
2786 divide_this = State.regs[ OP[1] ] << imm5;
2788 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2790 State.regs[ OP[1] ] = quotient;
2791 State.regs[ OP[2] >> 11 ] = remainder;
2793 /* Set condition codes. */
2794 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2796 if (overflow) PSW |= PSW_OV;
2797 if (quotient == 0) PSW |= PSW_Z;
2798 if (quotient < 0) PSW |= PSW_S;
2800 trace_output (OP_IMM_REG_REG_REG);
2804 /* end-sanitize-v850eq */
2806 /* start-sanitize-v850e */
2807 /* divu reg1, reg2, reg3 */
2811 unsigned long int quotient;
2812 unsigned long int remainder;
2813 unsigned long int divide_by;
2814 unsigned long int divide_this;
2815 boolean overflow = false;
2817 if ((OP[3] & 0x3c0000) == 0)
2819 trace_input ("divu", OP_REG_REG_REG, 0);
2821 /* Compute the result. */
2823 divide_by = State.regs[ OP[0] ];
2824 divide_this = State.regs[ OP[1] ];
2832 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2833 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2835 /* Set condition codes. */
2836 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2838 if (overflow) PSW |= PSW_OV;
2839 if (quotient == 0) PSW |= PSW_Z;
2841 trace_output (OP_REG_REG_REG);
2843 /* start-sanitize-v850eq */
2844 /* divun imm5, reg1, reg2, reg3 */
2849 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
2851 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2853 divide_by = State.regs[ OP[0] ];
2854 divide_this = State.regs[ OP[1] ];
2856 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2858 State.regs[ OP[1] ] = quotient;
2859 State.regs[ OP[2] >> 11 ] = remainder;
2861 /* Set condition codes. */
2862 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2864 if (overflow) PSW |= PSW_OV;
2865 if (quotient == 0) PSW |= PSW_Z;
2867 trace_output (OP_IMM_REG_REG_REG);
2869 /* end-sanitize-v850eq */
2874 /* div reg1, reg2, reg3 */
2878 signed long int quotient;
2879 signed long int remainder;
2880 signed long int divide_by;
2881 signed long int divide_this;
2882 boolean overflow = false;
2884 if ((OP[3] & 0x3c0000) == 0)
2886 trace_input ("div", OP_REG_REG_REG, 0);
2888 /* Compute the result. */
2890 divide_by = State.regs[ OP[0] ];
2891 divide_this = State.regs[ OP[1] ];
2893 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2899 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2900 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2902 /* Set condition codes. */
2903 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2905 if (overflow) PSW |= PSW_OV;
2906 if (quotient == 0) PSW |= PSW_Z;
2907 if (quotient < 0) PSW |= PSW_S;
2909 trace_output (OP_REG_REG_REG);
2911 /* start-sanitize-v850eq */
2912 /* divn imm5, reg1, reg2, reg3 */
2917 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
2919 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2921 divide_by = State.regs[ OP[0] ];
2922 divide_this = State.regs[ OP[1] ];
2924 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2926 State.regs[ OP[1] ] = quotient;
2927 State.regs[ OP[2] >> 11 ] = remainder;
2929 /* Set condition codes. */
2930 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2932 if (overflow) PSW |= PSW_OV;
2933 if (quotient == 0) PSW |= PSW_Z;
2934 if (quotient < 0) PSW |= PSW_S;
2936 trace_output (OP_IMM_REG_REG_REG);
2938 /* end-sanitize-v850eq */
2943 /* divhu reg1, reg2, reg3 */
2947 unsigned long int quotient;
2948 unsigned long int remainder;
2949 unsigned long int divide_by;
2950 unsigned long int divide_this;
2951 boolean overflow = false;
2953 if ((OP[3] & 0x3c0000) == 0)
2955 trace_input ("divhu", OP_REG_REG_REG, 0);
2957 /* Compute the result. */
2959 divide_by = State.regs[ OP[0] ] & 0xffff;
2960 divide_this = State.regs[ OP[1] ];
2968 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2969 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2971 /* Set condition codes. */
2972 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2974 if (overflow) PSW |= PSW_OV;
2975 if (quotient == 0) PSW |= PSW_Z;
2977 trace_output (OP_REG_REG_REG);
2979 /* start-sanitize-v850eq */
2980 /* divhun imm5, reg1, reg2, reg3 */
2985 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
2987 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2989 divide_by = State.regs[ OP[0] ] & 0xffff;
2990 divide_this = State.regs[ OP[1] ];
2992 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2994 State.regs[ OP[1] ] = quotient;
2995 State.regs[ OP[2] >> 11 ] = remainder;
2997 /* Set condition codes. */
2998 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3000 if (overflow) PSW |= PSW_OV;
3001 if (quotient == 0) PSW |= PSW_Z;
3003 trace_output (OP_IMM_REG_REG_REG);
3005 /* end-sanitize-v850eq */
3010 /* divh reg1, reg2, reg3 */
3014 signed long int quotient;
3015 signed long int remainder;
3016 signed long int divide_by;
3017 signed long int divide_this;
3018 boolean overflow = false;
3020 if ((OP[3] & 0x3c0000) == 0)
3022 trace_input ("divh", OP_REG_REG_REG, 0);
3024 /* Compute the result. */
3026 divide_by = State.regs[ OP[0] ];
3027 divide_this = SEXT16 (State.regs[ OP[1] ]);
3029 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3035 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
3036 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
3038 /* Set condition codes. */
3039 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3041 if (overflow) PSW |= PSW_OV;
3042 if (quotient == 0) PSW |= PSW_Z;
3043 if (quotient < 0) PSW |= PSW_S;
3045 trace_output (OP_REG_REG_REG);
3047 /* start-sanitize-v850eq */
3048 /* divhn imm5, reg1, reg2, reg3 */
3053 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
3055 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
3057 divide_by = SEXT16 (State.regs[ OP[0] ]);
3058 divide_this = State.regs[ OP[1] ];
3060 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
3062 State.regs[ OP[1] ] = quotient;
3063 State.regs[ OP[2] >> 11 ] = remainder;
3065 /* Set condition codes. */
3066 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3068 if (overflow) PSW |= PSW_OV;
3069 if (quotient == 0) PSW |= PSW_Z;
3070 if (quotient < 0) PSW |= PSW_S;
3072 trace_output (OP_IMM_REG_REG_REG);
3074 /* end-sanitize-v850eq */
3079 /* mulu imm9, reg2, reg3 */
3083 trace_input ("mulu", OP_IMM_REG_REG, 0);
3085 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3087 trace_output (OP_IMM_REG_REG);
3092 /* mul imm9, reg2, reg3 */
3096 trace_input ("mul", OP_IMM_REG_REG, 0);
3098 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
3100 trace_output (OP_IMM_REG_REG);
3105 /* cmov imm5, reg2, reg3 */
3109 trace_input ("cmov", OP_IMM_REG_REG, 0);
3111 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
3113 trace_output (OP_IMM_REG_REG);
3123 trace_input ("ctret", OP_NONE, 0);
3128 trace_output (OP_NONE);
3137 unsigned long value;
3139 trace_input ("hsw", OP_REG_REG3, 0);
3141 value = State.regs[ OP[ 1 ] ];
3143 value |= (State.regs[ OP[ 1 ] ] << 16);
3145 State.regs[ OP[2] >> 11 ] = value;
3147 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3149 if (value == 0) PSW |= PSW_Z;
3150 if (value & 0x80000000) PSW |= PSW_S;
3151 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
3153 trace_output (OP_REG_REG3);
3158 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
3164 unsigned long value;
3166 trace_input ("bsw", OP_REG_REG3, 0);
3168 value = State.regs[ OP[ 1 ] ];
3170 value |= (State.regs[ OP[ 1 ] ] << 24);
3171 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0x00ff0000);
3172 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x0000ff00);
3174 State.regs[ OP[2] >> 11 ] = value;
3176 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3178 if (value == 0) PSW |= PSW_Z;
3179 if (value & 0x80000000) PSW |= PSW_S;
3180 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
3182 trace_output (OP_REG_REG3);
3191 unsigned long value;
3193 trace_input ("bsh", OP_REG_REG3, 0);
3195 value = State.regs[ OP[ 1 ] ];
3197 value |= ((State.regs[ OP[ 1 ] ] << 8) & 0xff00ff00);
3198 value |= ((State.regs[ OP[ 1 ] ] >> 8) & 0x000000ff);
3200 State.regs[ OP[2] >> 11 ] = value;
3202 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3204 if (value == 0) PSW |= PSW_Z;
3205 if (value & 0x80000000) PSW |= PSW_S;
3206 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
3208 trace_output (OP_REG_REG3);
3222 trace_input ("pushml", OP_PUSHPOP3, 0);
3224 if (OP[3] & (1 << 19))
3228 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3230 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3231 store_mem ( SP & ~ 3, 4, FEPSW);
3235 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3236 store_mem ( SP & ~ 3, 4, EIPSW);
3240 if (OP[3] & (1 << 3))
3244 store_mem (SP & ~ 3, 4, PSW);
3247 /* Store the registers with lower number registers being placed at lower addresses. */
3249 if ((OP[3] & (1 << type3_regs[ i ])))
3252 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
3255 trace_output (OP_PUSHPOP2);
3261 trace_input ("ld.hu", OP_LOAD32, 2);
3263 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
3266 State.regs[ OP[1] ] = load_mem (adr, 2);
3268 trace_output (OP_LOAD32);
3274 /* prepare list12, imm5 */
3283 trace_input ("prepare", OP_PUSHPOP1, 0);
3285 /* Store the registers with lower number registers being placed at lower addresses. */
3287 if ((OP[3] & (1 << type1_regs[ i ])))
3290 store_mem (SP, 4, State.regs[ 20 + i ]);
3293 SP -= (OP[3] & 0x3e) << 1;
3295 trace_output (OP_PUSHPOP1);
3301 trace_input ("ld.bu", OP_LOAD32, 1);
3303 adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1) | ((OP[3] >> 5) & 1);
3305 State.regs[ OP[1] ] = load_mem (adr, 1);
3307 trace_output (OP_LOAD32);
3313 /* prepare list12, imm5, imm32 */
3319 trace_input ("prepare", OP_PUSHPOP1, 0);
3321 /* Store the registers with lower number registers being placed at lower addresses. */
3323 if ((OP[3] & (1 << type1_regs[ i ])))
3326 store_mem (SP, 4, State.regs[ 20 + i ]);
3329 SP -= (OP[3] & 0x3e) << 1;
3331 EP = load_mem (PC + 4, 4);
3333 trace_output (OP_PUSHPOP1);
3338 /* prepare list12, imm5, imm16-32 */
3344 trace_input ("prepare", OP_PUSHPOP1, 0);
3346 /* Store the registers with lower number registers being placed at lower addresses. */
3348 if ((OP[3] & (1 << type1_regs[ i ])))
3351 store_mem (SP, 4, State.regs[ 20 + i ]);
3354 SP -= (OP[3] & 0x3e) << 1;
3356 EP = load_mem (PC + 4, 2) << 16;
3358 trace_output (OP_PUSHPOP1);
3363 /* prepare list12, imm5, imm16 */
3369 trace_input ("prepare", OP_PUSHPOP1, 0);
3371 /* Store the registers with lower number registers being placed at lower addresses. */
3373 if ((OP[3] & (1 << type1_regs[ i ])))
3376 store_mem (SP, 4, State.regs[ 20 + i ]);
3379 SP -= (OP[3] & 0x3e) << 1;
3381 EP = SEXT16 (load_mem (PC + 4, 2));
3383 trace_output (OP_PUSHPOP1);
3388 /* prepare list12, imm5, sp */
3394 trace_input ("prepare", OP_PUSHPOP1, 0);
3396 /* Store the registers with lower number registers being placed at lower addresses. */
3398 if ((OP[3] & (1 << type1_regs[ i ])))
3401 store_mem (SP, 4, State.regs[ 20 + i ]);
3404 SP -= (OP[3] & 0x3e) << 1;
3408 trace_output (OP_PUSHPOP1);
3417 unsigned long result;
3419 result = load_mem (State.regs[30] + ((OP[3] & 0xf) << 1), 2);
3421 /* start-sanitize-v850eq */
3423 trace_input ("sld.h", OP_LOAD16, 2);
3425 State.regs[ OP[1] ] = SEXT16 (result);
3427 /* end-sanitize-v850eq */
3428 trace_input ("sld.hu", OP_LOAD16, 2);
3430 State.regs[ OP[1] ] = result;
3431 /* start-sanitize-v850eq */
3433 /* end-sanitize-v850eq */
3435 trace_output (OP_LOAD16);
3440 /* cmov reg1, reg2, reg3 */
3444 trace_input ("cmov", OP_REG_REG_REG, 0);
3446 State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
3448 trace_output (OP_REG_REG_REG);
3453 /* mul reg1, reg2, reg3 */
3457 trace_input ("mul", OP_REG_REG_REG, 0);
3459 Multiply64 (true, State.regs[ OP[0] ]);
3461 trace_output (OP_REG_REG_REG);
3466 /* end-sanitize-v850e */
3467 /* start-sanitize-v850eq */
3475 trace_input ("popmh", OP_PUSHPOP2, 0);
3477 /* Load the registers with lower number registers being retrieved from lower addresses. */
3478 for (i = 0; i++; i < 16)
3479 if ((OP[3] & (1 << type2_regs[ i ])))
3481 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
3485 if (OP[3] & (1 << 19))
3487 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3489 FEPSW = load_mem ( SP & ~ 3, 4);
3490 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3494 EIPSW = load_mem ( SP & ~ 3, 4);
3495 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3501 trace_output (OP_PUSHPOP2);
3512 trace_input ("popml", OP_PUSHPOP3, 0);
3514 /* Load the registers with lower number registers being retrieved from lower addresses. */
3515 for (i = 0; i++; i < 15)
3516 if ((OP[3] & (1 << type3_regs[ i ])))
3518 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
3522 if (OP[3] & (1 << 3))
3524 PSW = load_mem (SP & ~ 3, 4);
3528 if (OP[3] & (1 << 19))
3530 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3532 FEPSW = load_mem ( SP & ~ 3, 4);
3533 FEPC = load_mem ((SP + 4) & ~ 3, 4);
3537 EIPSW = load_mem ( SP & ~ 3, 4);
3538 EIPC = load_mem ((SP + 4) & ~ 3, 4);
3544 trace_output (OP_PUSHPOP2);
3553 trace_input ("pushmh", OP_PUSHPOP2, 0);
3555 if (OP[3] & (1 << 19))
3559 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
3561 store_mem ((SP + 4) & ~ 3, 4, FEPC);
3562 store_mem ( SP & ~ 3, 4, FEPSW);
3566 store_mem ((SP + 4) & ~ 3, 4, EIPC);
3567 store_mem ( SP & ~ 3, 4, EIPSW);
3571 /* Store the registers with lower number registers being placed at lower addresses. */
3573 if ((OP[3] & (1 << type2_regs[ i ])))
3576 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
3579 trace_output (OP_PUSHPOP2);
3584 /* end-sanitize-v850eq */