24 unsigned int op0, psw;
27 temp = (State.regs[OP[0]] << 23) >> 23;
31 if ((psw & PSW_OV) != 0)
41 unsigned int op0, psw;
44 temp = (State.regs[OP[0]] << 23) >> 23;
48 if ((psw & PSW_CY) != 0)
58 unsigned int op0, psw;
61 temp = (State.regs[OP[0]] << 23) >> 23;
65 if ((psw & PSW_Z) != 0)
75 unsigned int op0, psw;
78 temp = (State.regs[OP[0]] << 23) >> 23;
82 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
92 unsigned int op0, psw;
95 temp = (State.regs[OP[0]] << 23) >> 23;
99 if ((psw & PSW_S) != 0)
112 temp = (State.regs[OP[0]] << 23) >> 23;
121 unsigned int op0, psw;
124 temp = (State.regs[OP[0]] << 23) >> 23;
126 psw = State.sregs[5];
128 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
138 unsigned int op0, psw;
141 temp = (State.regs[OP[0]] << 23) >> 23;
143 psw = State.sregs[5];
145 if ((((psw & PSW_Z) != 0)
146 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
156 unsigned int op0, psw;
159 temp = (State.regs[OP[0]] << 23) >> 23;
161 psw = State.sregs[5];
163 if ((psw & PSW_OV) == 0)
173 unsigned int op0, psw;
176 temp = (State.regs[OP[0]] << 23) >> 23;
178 psw = State.sregs[5];
180 if ((psw & PSW_CY) == 0)
190 unsigned int op0, psw;
193 temp = (State.regs[OP[0]] << 23) >> 23;
195 psw = State.sregs[5];
197 if ((psw & PSW_Z) == 0)
207 unsigned int op0, psw;
210 temp = (State.regs[OP[0]] << 23) >> 23;
212 psw = State.sregs[5];
214 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
224 unsigned int op0, psw;
227 temp = (State.regs[OP[0]] << 23) >> 23;
229 psw = State.sregs[5];
231 if ((psw & PSW_S) == 0)
241 unsigned int op0, psw;
244 temp = (State.regs[OP[0]] << 23) >> 23;
246 psw = State.sregs[5];
248 if ((psw & PSW_SAT) != 0)
258 unsigned int op0, psw;
261 temp = (State.regs[OP[0]] << 23) >> 23;
263 psw = State.sregs[5];
265 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
275 unsigned int op0, psw;
278 temp = (State.regs[OP[0]] << 23) >> 23;
280 psw = State.sregs[5];
282 if ((((psw & PSW_Z) != 0)
283 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
293 /* interp.c will bump this by +2, so correct for it here. */
294 State.pc = State.regs[OP[0]] - 2;
297 /* jarl disp22, reg */
301 unsigned int op0, opc;
305 temp = (temp << 10) >> 10;
311 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
313 State.regs[OP[1]] = opc + 4;
320 unsigned int op0, op1, result, z, s, cy, ov;
322 /* Compute the result. */
323 op0 = State.regs[OP[0]];
324 op1 = State.regs[OP[1]];
327 /* Compute the condition codes. */
329 s = (result & 0x80000000);
330 cy = (result < op0 || result < op1);
331 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
332 && (op0 & 0x80000000) != (result & 0x80000000));
334 /* Store the result and condition codes. */
335 State.regs[OP[1]] = result;
336 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
337 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
338 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
341 /* add sign_extend(imm5), reg */
345 unsigned int op0, op1, result, z, s, cy, ov;
348 /* Compute the result. */
349 temp = (OP[0] & 0x1f);
350 temp = (temp << 27) >> 27;
352 op1 = State.regs[OP[1]];
355 /* Compute the condition codes. */
357 s = (result & 0x80000000);
358 cy = (result < op0 || result < op1);
359 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
360 && (op0 & 0x80000000) != (result & 0x80000000));
362 /* Store the result and condition codes. */
363 State.regs[OP[1]] = result;
364 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
365 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
366 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
369 /* addi sign_extend(imm16), reg, reg */
373 unsigned int op0, op1, result, z, s, cy, ov;
376 /* Compute the result. */
377 temp = (OP[0] & 0xffff);
378 temp = (temp << 16) >> 16;
380 op1 = State.regs[OP[1]];
383 /* Compute the condition codes. */
385 s = (result & 0x80000000);
386 cy = (result < op0 || result < op1);
387 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
388 && (op0 & 0x80000000) != (result & 0x80000000));
390 /* Store the result and condition codes. */
391 State.regs[OP[2]] = result;
392 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
393 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
394 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
401 unsigned int op0, op1, result, z, s, cy, ov;
403 /* Compute the result. */
404 op0 = State.regs[OP[0]];
405 op1 = State.regs[OP[1]];
408 /* Compute the condition codes. */
410 s = (result & 0x80000000);
411 cy = (result < -op0);
412 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
413 && (op1 & 0x80000000) != (result & 0x80000000));
415 /* Store the result and condition codes. */
416 State.regs[OP[1]] = result;
417 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
418 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
419 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
422 /* subr reg1, reg2 */
426 unsigned int op0, op1, result, z, s, cy, ov;
428 /* Compute the result. */
429 op0 = State.regs[OP[0]];
430 op1 = State.regs[OP[1]];
433 /* Compute the condition codes. */
435 s = (result & 0x80000000);
436 cy = (result < -op1);
437 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
438 && (op0 & 0x80000000) != (result & 0x80000000));
440 /* Store the result and condition codes. */
441 State.regs[OP[1]] = result;
442 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
443 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
444 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
447 /* mulh reg1, reg2 */
451 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
452 * (State.regs[OP[0]] & 0xffff));
455 /* mulh sign_extend(imm5), reg2
463 value = (value << 27) >> 27;
465 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
468 /* mulhi imm16, reg1, reg2 */
474 value = value & 0xffff;
476 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
479 /* divh reg1, reg2 */
483 unsigned int op0, op1, result, z, s, cy, ov;
486 /* Compute the result. */
487 temp = State.regs[OP[0]] & 0xffff;
488 temp = (temp << 16) >> 16;
490 op1 = State.regs[OP[1]];
492 if (op0 == 0xffffffff && op1 == 0x80000000)
505 /* Compute the condition codes. */
507 s = (result & 0x80000000);
509 /* Store the result and condition codes. */
510 State.regs[OP[1]] = result;
511 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
512 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
513 | (ov ? PSW_OV : 0));
520 unsigned int op0, op1, result, z, s, cy, ov;
522 /* Compute the result. */
523 op0 = State.regs[OP[0]];
524 op1 = State.regs[OP[1]];
527 /* Compute the condition codes. */
529 s = (result & 0x80000000);
530 cy = (result < -op0);
531 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
532 && (op1 & 0x80000000) != (result & 0x80000000));
534 /* Set condition codes. */
535 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
536 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
537 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
540 /* cmp sign_extend(imm5), reg */
544 unsigned int op0, op1, result, z, s, cy, ov;
547 /* Compute the result. */
549 temp = (temp << 27) >> 27;
551 op1 = State.regs[OP[1]];
554 /* Compute the condition codes. */
556 s = (result & 0x80000000);
557 cy = (result < -op0);
558 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
559 && (op1 & 0x80000000) != (result & 0x80000000));
561 /* Set condition codes. */
562 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
563 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
564 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
571 /* Hack alert. We turn off a bit in op0 since we really only
573 unsigned int op0, psw, result;
576 psw = State.sregs[5];
581 result = ((psw & PSW_OV) != 0);
584 result = ((psw & PSW_CY) != 0);
587 result = ((psw & PSW_Z) != 0);
590 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
593 result = ((psw & PSW_S) != 0);
599 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
602 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
603 || ((psw & PSW_Z) != 0)) != 0);
606 result = ((psw & PSW_OV) == 0);
609 result = ((psw & PSW_CY) == 0);
612 result = ((psw & PSW_Z) == 0);
615 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
618 result = ((psw & PSW_S) == 0);
621 result = ((psw & PSW_SAT) != 0);
624 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
627 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
628 || ((psw & PSW_Z) != 0)) == 0);
632 State.regs[OP[1]] = result;
639 unsigned int op0, op1, result, z, s, cy, ov, sat;
641 /* Compute the result. */
642 op0 = State.regs[OP[0]];
643 op1 = State.regs[OP[1]];
646 /* Compute the condition codes. */
648 s = (result & 0x80000000);
649 cy = (result < op0 || result < op1);
650 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
651 && (op0 & 0x80000000) != (result & 0x80000000));
654 /* Store the result and condition codes. */
655 State.regs[OP[1]] = result;
656 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
657 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
658 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
659 | (sat ? PSW_SAT : 0));
661 /* Handle saturated results. */
662 if (sat && (op0 & 0x80000000))
663 State.regs[OP[1]] = 0x80000000;
665 State.regs[OP[1]] = 0x7fffffff;
668 /* satadd sign_extend(imm5), reg */
672 unsigned int op0, op1, result, z, s, cy, ov, sat;
676 /* Compute the result. */
677 temp = (OP[0] & 0x1f);
678 temp = (temp << 27) >> 27;
680 op1 = State.regs[OP[1]];
683 /* Compute the condition codes. */
685 s = (result & 0x80000000);
686 cy = (result < op0 || result < op1);
687 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
688 && (op0 & 0x80000000) != (result & 0x80000000));
691 /* Store the result and condition codes. */
692 State.regs[OP[1]] = result;
693 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
694 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
695 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
696 | (sat ? PSW_SAT : 0));
698 /* Handle saturated results. */
699 if (sat && (op0 & 0x80000000))
700 State.regs[OP[1]] = 0x80000000;
702 State.regs[OP[1]] = 0x7fffffff;
705 /* satsub reg1, reg2 */
709 unsigned int op0, op1, result, z, s, cy, ov, sat;
711 /* Compute the result. */
712 op0 = State.regs[OP[0]];
713 op1 = State.regs[OP[1]];
716 /* Compute the condition codes. */
718 s = (result & 0x80000000);
719 cy = (result < -op0);
720 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
721 && (op1 & 0x80000000) != (result & 0x80000000));
724 /* Store the result and condition codes. */
725 State.regs[OP[1]] = result;
726 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
727 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
728 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
729 | (sat ? PSW_SAT : 0));
731 /* Handle saturated results. */
732 if (sat && (op1 & 0x80000000))
733 State.regs[OP[1]] = 0x80000000;
735 State.regs[OP[1]] = 0x7fffffff;
738 /* satsubi sign_extend(imm16), reg */
742 unsigned int op0, op1, result, z, s, cy, ov, sat;
745 /* Compute the result. */
746 temp = (OP[0] & 0xffff);
747 temp = (temp << 16) >> 16;
749 op1 = State.regs[OP[1]];
752 /* Compute the condition codes. */
754 s = (result & 0x80000000);
755 cy = (result < -op0);
756 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
757 && (op1 & 0x80000000) != (result & 0x80000000));
760 /* Store the result and condition codes. */
761 State.regs[OP[1]] = result;
762 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
763 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
764 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
765 | (sat ? PSW_SAT : 0));
767 /* Handle saturated results. */
768 if (sat && (op1 & 0x80000000))
769 State.regs[OP[1]] = 0x80000000;
771 State.regs[OP[1]] = 0x7fffffff;
777 unsigned int op0, op1, result, z, s, cy, ov, sat;
779 /* Compute the result. */
780 op0 = State.regs[OP[0]];
781 op1 = State.regs[OP[1]];
784 /* Compute the condition codes. */
786 s = (result & 0x80000000);
787 cy = (result < -op0);
788 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
789 && (op1 & 0x80000000) != (result & 0x80000000));
792 /* Store the result and condition codes. */
793 State.regs[OP[1]] = result;
794 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
795 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
796 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
797 | (sat ? PSW_SAT : 0));
799 /* Handle saturated results. */
800 if (sat && (op0 & 0x80000000))
801 State.regs[OP[1]] = 0x80000000;
803 State.regs[OP[1]] = 0x7fffffff;
810 unsigned int op0, op1, result, z, s, cy, ov;
812 /* Compute the result. */
813 op0 = State.regs[OP[0]];
814 op1 = State.regs[OP[1]];
817 /* Compute the condition codes. */
819 s = (result & 0x80000000);
821 /* Store the condition codes. */
822 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
823 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
850 State.regs[OP[1]] = State.regs[OP[0]];
853 /* mov sign_extend(imm5), reg */
859 value = (value << 27) >> 27;
860 State.regs[OP[1]] = value;
863 /* movea sign_extend(imm16), reg, reg */
870 value = (value << 16) >> 16;
872 State.regs[OP[2]] = State.regs[OP[1]] + value;
875 /* movhi imm16, reg, reg */
881 value = (value & 0xffff) << 16;
883 State.regs[OP[2]] = State.regs[OP[1]] + value;
901 /* sar zero_extend(imm5),reg1 */
905 unsigned int op0, op1, result, z, s, cy, ov;
908 op1 = State.regs[OP[1]];
909 result = (signed)op1 >> op0;
911 /* Compute the condition codes. */
913 s = (result & 0x80000000);
914 cy = (op1 & (1 << (op0 - 1)));
916 /* Store the result and condition codes. */
917 State.regs[OP[1]] = result;
918 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
919 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
920 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
927 unsigned int op0, op1, result, z, s, cy, ov;
929 op0 = State.regs[OP[0]] & 0x1f;
930 op1 = State.regs[OP[1]];
931 result = (signed)op1 >> op0;
933 /* Compute the condition codes. */
935 s = (result & 0x80000000);
936 cy = (op1 & (1 << (op0 - 1)));
938 /* Store the result and condition codes. */
939 State.regs[OP[1]] = result;
940 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
941 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
942 | (cy ? PSW_CY : 0));
945 /* shl zero_extend(imm5),reg1 */
949 unsigned int op0, op1, result, z, s, cy, ov;
952 op1 = State.regs[OP[1]];
955 /* Compute the condition codes. */
957 s = (result & 0x80000000);
958 cy = (op1 & (1 << (32 - op0)));
960 /* Store the result and condition codes. */
961 State.regs[OP[1]] = result;
962 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
963 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
964 | (cy ? PSW_CY : 0));
971 unsigned int op0, op1, result, z, s, cy, ov;
973 op0 = State.regs[OP[0]] & 0x1f;
974 op1 = State.regs[OP[1]];
977 /* Compute the condition codes. */
979 s = (result & 0x80000000);
980 cy = (op1 & (1 << (32 - op0)));
982 /* Store the result and condition codes. */
983 State.regs[OP[1]] = result;
984 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
985 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
986 | (cy ? PSW_CY : 0));
989 /* shr zero_extend(imm5),reg1 */
993 unsigned int op0, op1, result, z, s, cy, ov;
996 op1 = State.regs[OP[1]];
999 /* Compute the condition codes. */
1001 s = (result & 0x80000000);
1002 cy = (op1 & (1 << (op0 - 1)));
1004 /* Store the result and condition codes. */
1005 State.regs[OP[1]] = result;
1006 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1007 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1008 | (cy ? PSW_CY : 0));
1011 /* shr reg1, reg2 */
1015 unsigned int op0, op1, result, z, s, cy, ov;
1017 op0 = State.regs[OP[0]] & 0x1f;
1018 op1 = State.regs[OP[1]];
1019 result = op1 >> op0;
1021 /* Compute the condition codes. */
1023 s = (result & 0x80000000);
1024 cy = (op1 & (1 << (op0 - 1)));
1026 /* Store the result and condition codes. */
1027 State.regs[OP[1]] = result;
1028 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1029 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1030 | (cy ? PSW_CY : 0));
1047 unsigned int op0, op1, result, z, s, cy, ov;
1049 /* Compute the result. */
1050 op0 = State.regs[OP[0]];
1051 op1 = State.regs[OP[1]];
1054 /* Compute the condition codes. */
1056 s = (result & 0x80000000);
1058 /* Store the result and condition codes. */
1059 State.regs[OP[1]] = result;
1060 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1061 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1064 /* ori zero_extend(imm16), reg, reg */
1068 unsigned int op0, op1, result, z, s, cy, ov;
1070 op0 = OP[0] & 0xffff;
1071 op1 = State.regs[OP[1]];
1074 /* Compute the condition codes. */
1076 s = (result & 0x80000000);
1078 /* Store the result and condition codes. */
1079 State.regs[OP[2]] = result;
1080 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1081 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1088 unsigned int op0, op1, result, z, s, cy, ov;
1090 /* Compute the result. */
1091 op0 = State.regs[OP[0]];
1092 op1 = State.regs[OP[1]];
1095 /* Compute the condition codes. */
1097 s = (result & 0x80000000);
1099 /* Store the result and condition codes. */
1100 State.regs[OP[1]] = result;
1101 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1102 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1105 /* andi zero_extend(imm16), reg, reg */
1109 unsigned int op0, op1, result, z, s, cy, ov;
1111 op0 = OP[0] & 0xffff;
1112 op1 = State.regs[OP[1]];
1115 /* Compute the condition codes. */
1118 /* Store the result and condition codes. */
1119 State.regs[OP[2]] = result;
1120 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1121 State.sregs[5] |= (z ? PSW_Z : 0);
1128 unsigned int op0, op1, result, z, s, cy, ov;
1130 /* Compute the result. */
1131 op0 = State.regs[OP[0]];
1132 op1 = State.regs[OP[1]];
1135 /* Compute the condition codes. */
1137 s = (result & 0x80000000);
1139 /* Store the result and condition codes. */
1140 State.regs[OP[1]] = result;
1141 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1142 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1145 /* xori zero_extend(imm16), reg, reg */
1149 unsigned int op0, op1, result, z, s, cy, ov;
1151 op0 = OP[0] & 0xffff;
1152 op1 = State.regs[OP[1]];
1155 /* Compute the condition codes. */
1157 s = (result & 0x80000000);
1159 /* Store the result and condition codes. */
1160 State.regs[OP[2]] = result;
1161 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1162 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1165 /* not reg1, reg2 */
1169 unsigned int op0, result, z, s, cy, ov;
1171 /* Compute the result. */
1172 op0 = State.regs[OP[0]];
1175 /* Compute the condition codes. */
1177 s = (result & 0x80000000);
1179 /* Store the result and condition codes. */
1180 State.regs[OP[1]] = result;
1181 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1182 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1204 State.sregs[5] |= PSW_ID;
1211 State.sregs[5] &= ~PSW_ID;
1214 /* halt, not supported */
1221 /* reti, not supported */
1228 /* trap, not supportd */
1241 op0 = State.regs[OP[0]];
1242 State.sregs[OP[1]] = op0;
1245 /* stsr, not supported */
1251 op0 = State.sregs[OP[1]];
1252 State.regs[OP[0]] = op0;