29 unsigned int op0, psw;
32 temp = (State.regs[OP[0]] << 23) >> 23;
36 if ((psw & PSW_OV) != 0)
46 unsigned int op0, psw;
49 temp = (State.regs[OP[0]] << 23) >> 23;
53 if ((psw & PSW_CY) != 0)
63 unsigned int op0, psw;
66 temp = (State.regs[OP[0]] << 23) >> 23;
70 if ((psw & PSW_Z) != 0)
80 unsigned int op0, psw;
83 temp = (State.regs[OP[0]] << 23) >> 23;
87 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
97 unsigned int op0, psw;
100 temp = (State.regs[OP[0]] << 23) >> 23;
104 if ((psw & PSW_S) != 0)
117 temp = (State.regs[OP[0]] << 23) >> 23;
126 unsigned int op0, psw;
129 temp = (State.regs[OP[0]] << 23) >> 23;
133 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
143 unsigned int op0, psw;
146 temp = (State.regs[OP[0]] << 23) >> 23;
150 if ((((psw & PSW_Z) != 0)
151 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
161 unsigned int op0, psw;
164 temp = (State.regs[OP[0]] << 23) >> 23;
168 if ((psw & PSW_OV) == 0)
178 unsigned int op0, psw;
181 temp = (State.regs[OP[0]] << 23) >> 23;
185 if ((psw & PSW_CY) == 0)
195 unsigned int op0, psw;
198 temp = (State.regs[OP[0]] << 23) >> 23;
202 if ((psw & PSW_Z) == 0)
212 unsigned int op0, psw;
215 temp = (State.regs[OP[0]] << 23) >> 23;
219 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
229 unsigned int op0, psw;
232 temp = (State.regs[OP[0]] << 23) >> 23;
236 if ((psw & PSW_S) == 0)
246 unsigned int op0, psw;
249 temp = (State.regs[OP[0]] << 23) >> 23;
253 if ((psw & PSW_SAT) != 0)
263 unsigned int op0, psw;
266 temp = (State.regs[OP[0]] << 23) >> 23;
270 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
280 unsigned int op0, psw;
283 temp = (State.regs[OP[0]] << 23) >> 23;
287 if ((((psw & PSW_Z) != 0)
288 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
304 unsigned int op0, op1, result, z, s, cy, ov;
306 /* Compute the result. */
307 op0 = State.regs[OP[0]];
308 op1 = State.regs[OP[1]];
311 /* Compute the condition codes. */
313 s = (result & 0x80000000);
314 cy = (result < op0 || result < op1);
315 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
316 && (op0 & 0x80000000) != (result & 0x80000000));
318 /* Store the result and condition codes. */
319 State.regs[OP[1]] = result;
320 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
321 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
322 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
325 /* add sign_extend(imm5), reg */
329 unsigned int op0, op1, result, z, s, cy, ov;
332 /* Compute the result. */
333 temp = (OP[0] & 0x1f);
334 temp = (temp << 27) >> 27;
336 op1 = State.regs[OP[1]];
339 /* Compute the condition codes. */
341 s = (result & 0x80000000);
342 cy = (result < op0 || result < op1);
343 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
344 && (op0 & 0x80000000) != (result & 0x80000000));
346 /* Store the result and condition codes. */
347 State.regs[OP[1]] = result;
348 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
349 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
350 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
353 /* addi sign_extend(imm16), reg, reg */
357 unsigned int op0, op1, result, z, s, cy, ov;
360 /* Compute the result. */
361 temp = (OP[0] & 0xffff);
362 temp = (temp << 16) >> 16;
364 op1 = State.regs[OP[1]];
367 /* Compute the condition codes. */
369 s = (result & 0x80000000);
370 cy = (result < op0 || result < op1);
371 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
372 && (op0 & 0x80000000) != (result & 0x80000000));
374 /* Store the result and condition codes. */
375 State.regs[OP[2]] = result;
376 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
377 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
378 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
385 unsigned int op0, op1, result, z, s, cy, ov;
387 /* Compute the result. */
388 op0 = State.regs[OP[0]];
389 op1 = State.regs[OP[1]];
392 /* Compute the condition codes. */
394 s = (result & 0x80000000);
395 cy = (result < -op0);
396 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
397 && (op1 & 0x80000000) != (result & 0x80000000));
399 /* Store the result and condition codes. */
400 State.regs[OP[1]] = result;
401 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
402 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
403 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
406 /* subr reg1, reg2 */
410 unsigned int op0, op1, result, z, s, cy, ov;
412 /* Compute the result. */
413 op0 = State.regs[OP[0]];
414 op1 = State.regs[OP[1]];
417 /* Compute the condition codes. */
419 s = (result & 0x80000000);
420 cy = (result < -op1);
421 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
422 && (op0 & 0x80000000) != (result & 0x80000000));
424 /* Store the result and condition codes. */
425 State.regs[OP[1]] = result;
426 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
427 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
428 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
431 /* mulh reg1, reg2 */
435 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
436 * (State.regs[OP[0]] & 0xffff));
439 /* mulh sign_extend(imm5), reg2
447 value = (value << 27) >> 27;
449 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
452 /* mulhi imm16, reg1, reg2 */
458 value = value & 0xffff;
460 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
463 /* divh reg1, reg2 */
467 unsigned int op0, op1, result, z, s, cy, ov;
470 /* Compute the result. */
471 temp = State.regs[OP[0]] & 0xffff;
472 temp = (temp << 16) >> 16;
474 op1 = State.regs[OP[1]];
476 if (op0 == 0xffffffff && op1 == 0x80000000)
489 /* Compute the condition codes. */
491 s = (result & 0x80000000);
493 /* Store the result and condition codes. */
494 State.regs[OP[1]] = result;
495 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
496 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
497 | (ov ? PSW_OV : 0));
504 unsigned int op0, op1, result, z, s, cy, ov;
506 /* Compute the result. */
507 op0 = State.regs[OP[0]];
508 op1 = State.regs[OP[1]];
511 /* Compute the condition codes. */
513 s = (result & 0x80000000);
514 cy = (result < -op0);
515 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
516 && (op1 & 0x80000000) != (result & 0x80000000));
518 /* Set condition codes. */
519 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
520 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
521 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
524 /* cmp sign_extend(imm5), reg */
528 unsigned int op0, op1, result, z, s, cy, ov;
531 /* Compute the result. */
533 temp = (temp << 27) >> 27;
535 op1 = State.regs[OP[1]];
538 /* Compute the condition codes. */
540 s = (result & 0x80000000);
541 cy = (result < -op0);
542 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
543 && (op1 & 0x80000000) != (result & 0x80000000));
545 /* Set condition codes. */
546 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
547 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
548 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
555 /* Hack alert. We turn off a bit in op0 since we really only
557 unsigned int op0, psw, result;
565 result = ((psw & PSW_OV) != 0);
568 result = ((psw & PSW_CY) != 0);
571 result = ((psw & PSW_Z) != 0);
574 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
577 result = ((psw & PSW_S) != 0);
583 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
586 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
587 || ((psw & PSW_Z) != 0)) != 0);
590 result = ((psw & PSW_OV) == 0);
593 result = ((psw & PSW_CY) == 0);
596 result = ((psw & PSW_Z) == 0);
599 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
602 result = ((psw & PSW_S) == 0);
605 result = ((psw & PSW_SAT) != 0);
608 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
611 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
612 || ((psw & PSW_Z) != 0)) == 0);
616 State.regs[OP[1]] = result;
623 unsigned int op0, op1, result, z, s, cy, ov;
625 /* Compute the result. */
626 op0 = State.regs[OP[0]];
627 op1 = State.regs[OP[1]];
630 /* Compute the condition codes. */
632 s = (result & 0x80000000);
634 /* Store the condition codes. */
635 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
636 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
673 State.regs[OP[1]] = State.regs[OP[0]];
676 /* mov sign_extend(imm5), reg */
682 value = (value << 27) >> 27;
683 State.regs[OP[1]] = value;
686 /* movea sign_extend(imm16), reg, reg */
693 value = (value << 16) >> 16;
695 State.regs[OP[2]] = State.regs[OP[1]] + value;
698 /* movhi imm16, reg, reg */
704 value = (value & 0xffff) << 16;
706 State.regs[OP[2]] = State.regs[OP[1]] + value;
734 /* sar zero_extend(imm5),reg1 */
738 unsigned int op0, op1, result, z, s, cy, ov;
741 op1 = State.regs[OP[1]];
742 result = (signed)op1 >> op0;
744 /* Compute the condition codes. */
746 s = (result & 0x80000000);
747 cy = (op1 & (1 << (op0 - 1)));
749 /* Store the result and condition codes. */
750 State.regs[OP[1]] = result;
751 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
752 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
753 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
760 unsigned int op0, op1, result, z, s, cy, ov;
762 op0 = State.regs[OP[0]] & 0x1f;
763 op1 = State.regs[OP[1]];
764 result = (signed)op1 >> op0;
766 /* Compute the condition codes. */
768 s = (result & 0x80000000);
769 cy = (op1 & (1 << (op0 - 1)));
771 /* Store the result and condition codes. */
772 State.regs[OP[1]] = result;
773 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
774 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
775 | (cy ? PSW_CY : 0));
778 /* shl zero_extend(imm5),reg1 */
782 unsigned int op0, op1, result, z, s, cy, ov;
785 op1 = State.regs[OP[1]];
788 /* Compute the condition codes. */
790 s = (result & 0x80000000);
791 cy = (op1 & (1 << (32 - op0)));
793 /* Store the result and condition codes. */
794 State.regs[OP[1]] = result;
795 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
796 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
797 | (cy ? PSW_CY : 0));
804 unsigned int op0, op1, result, z, s, cy, ov;
806 op0 = State.regs[OP[0]] & 0x1f;
807 op1 = State.regs[OP[1]];
810 /* Compute the condition codes. */
812 s = (result & 0x80000000);
813 cy = (op1 & (1 << (32 - op0)));
815 /* Store the result and condition codes. */
816 State.regs[OP[1]] = result;
817 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
818 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
819 | (cy ? PSW_CY : 0));
822 /* shr zero_extend(imm5),reg1 */
826 unsigned int op0, op1, result, z, s, cy, ov;
829 op1 = State.regs[OP[1]];
832 /* Compute the condition codes. */
834 s = (result & 0x80000000);
835 cy = (op1 & (1 << (op0 - 1)));
837 /* Store the result and condition codes. */
838 State.regs[OP[1]] = result;
839 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
840 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
841 | (cy ? PSW_CY : 0));
848 unsigned int op0, op1, result, z, s, cy, ov;
850 op0 = State.regs[OP[0]] & 0x1f;
851 op1 = State.regs[OP[1]];
854 /* Compute the condition codes. */
856 s = (result & 0x80000000);
857 cy = (op1 & (1 << (op0 - 1)));
859 /* Store the result and condition codes. */
860 State.regs[OP[1]] = result;
861 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
862 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
863 | (cy ? PSW_CY : 0));
880 unsigned int op0, op1, result, z, s, cy, ov;
882 /* Compute the result. */
883 op0 = State.regs[OP[0]];
884 op1 = State.regs[OP[1]];
887 /* Compute the condition codes. */
889 s = (result & 0x80000000);
891 /* Store the result and condition codes. */
892 State.regs[OP[1]] = result;
893 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
894 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
897 /* ori zero_extend(imm16), reg, reg */
901 unsigned int op0, op1, result, z, s, cy, ov;
903 op0 = OP[0] & 0xffff;
904 op1 = State.regs[OP[1]];
907 /* Compute the condition codes. */
909 s = (result & 0x80000000);
911 /* Store the result and condition codes. */
912 State.regs[OP[2]] = result;
913 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
914 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
921 unsigned int op0, op1, result, z, s, cy, ov;
923 /* Compute the result. */
924 op0 = State.regs[OP[0]];
925 op1 = State.regs[OP[1]];
928 /* Compute the condition codes. */
930 s = (result & 0x80000000);
932 /* Store the result and condition codes. */
933 State.regs[OP[1]] = result;
934 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
935 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
938 /* andi zero_extend(imm16), reg, reg */
942 unsigned int op0, op1, result, z, s, cy, ov;
944 op0 = OP[0] & 0xffff;
945 op1 = State.regs[OP[1]];
948 /* Compute the condition codes. */
951 /* Store the result and condition codes. */
952 State.regs[OP[2]] = result;
953 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
954 State.psw |= (z ? PSW_Z : 0);
961 unsigned int op0, op1, result, z, s, cy, ov;
963 /* Compute the result. */
964 op0 = State.regs[OP[0]];
965 op1 = State.regs[OP[1]];
968 /* Compute the condition codes. */
970 s = (result & 0x80000000);
972 /* Store the result and condition codes. */
973 State.regs[OP[1]] = result;
974 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
975 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
978 /* xori zero_extend(imm16), reg, reg */
982 unsigned int op0, op1, result, z, s, cy, ov;
984 op0 = OP[0] & 0xffff;
985 op1 = State.regs[OP[1]];
988 /* Compute the condition codes. */
990 s = (result & 0x80000000);
992 /* Store the result and condition codes. */
993 State.regs[OP[2]] = result;
994 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
995 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1002 unsigned int op0, result, z, s, cy, ov;
1004 /* Compute the result. */
1005 op0 = State.regs[OP[0]];
1008 /* Compute the condition codes. */
1010 s = (result & 0x80000000);
1012 /* Store the result and condition codes. */
1013 State.regs[OP[1]] = result;
1014 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
1015 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1042 State.psw |= PSW_ID;
1049 State.psw &= ~PSW_ID;
1052 /* halt, not supported */
1059 /* reti, not supported */
1066 /* trap, not supportd */
1073 /* ldsr, not supported */
1080 /* stsr, not supported */