45 unsigned int op0, op1, op2;
48 op0 = State.regs[OP[0]];
50 temp = (temp << 16) >> 16;
52 result = get_byte (State.mem + op0 + op2);
53 result = (result << 24) >> 24;
54 State.regs[OP[1]] = result;
61 unsigned int op0, op1, op2;
64 op0 = State.regs[OP[0]];
65 temp = (temp << 16) >> 16;
68 result = get_half (State.mem + op0 + op2);
69 result = (result << 16) >> 16;
70 State.regs[OP[1]] = result;
77 unsigned int op0, op1, op2;
80 op0 = State.regs[OP[0]];
81 temp = (temp << 16) >> 16;
84 result = get_word (State.mem + op0 + op2);
85 State.regs[OP[1]] = result;
92 unsigned int op0, op1, op2;
95 op0 = State.regs[OP[0]];
96 op1 = State.regs[OP[1]];
98 temp = (temp << 16) >> 16;
100 put_byte (State.mem + op0 + op2, op1);
107 unsigned int op0, op1, op2;
110 op0 = State.regs[OP[0]];
111 op1 = State.regs[OP[1]];
114 temp = (temp << 16) >> 16;
116 put_half (State.mem + op0 + op2, op1);
123 unsigned int op0, op1, op2;
126 op0 = State.regs[OP[0]];
127 op1 = State.regs[OP[1]];
130 temp = (temp << 16) >> 16;
132 put_word (State.mem + op0 + op2, op1);
139 unsigned int op0, psw;
142 temp = (State.regs[OP[0]] << 23) >> 23;
144 psw = State.sregs[5];
146 if ((psw & PSW_OV) != 0)
156 unsigned int op0, psw;
159 temp = (State.regs[OP[0]] << 23) >> 23;
161 psw = State.sregs[5];
163 if ((psw & PSW_CY) != 0)
173 unsigned int op0, psw;
176 temp = (State.regs[OP[0]] << 23) >> 23;
178 psw = State.sregs[5];
180 if ((psw & PSW_Z) != 0)
190 unsigned int op0, psw;
193 temp = (State.regs[OP[0]] << 23) >> 23;
195 psw = State.sregs[5];
197 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
207 unsigned int op0, psw;
210 temp = (State.regs[OP[0]] << 23) >> 23;
212 psw = State.sregs[5];
214 if ((psw & PSW_S) != 0)
227 temp = (State.regs[OP[0]] << 23) >> 23;
236 unsigned int op0, psw;
239 temp = (State.regs[OP[0]] << 23) >> 23;
241 psw = State.sregs[5];
243 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
253 unsigned int op0, psw;
256 temp = (State.regs[OP[0]] << 23) >> 23;
258 psw = State.sregs[5];
260 if ((((psw & PSW_Z) != 0)
261 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
271 unsigned int op0, psw;
274 temp = (State.regs[OP[0]] << 23) >> 23;
276 psw = State.sregs[5];
278 if ((psw & PSW_OV) == 0)
288 unsigned int op0, psw;
291 temp = (State.regs[OP[0]] << 23) >> 23;
293 psw = State.sregs[5];
295 if ((psw & PSW_CY) == 0)
305 unsigned int op0, psw;
308 temp = (State.regs[OP[0]] << 23) >> 23;
310 psw = State.sregs[5];
312 if ((psw & PSW_Z) == 0)
322 unsigned int op0, psw;
325 temp = (State.regs[OP[0]] << 23) >> 23;
327 psw = State.sregs[5];
329 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
339 unsigned int op0, psw;
342 temp = (State.regs[OP[0]] << 23) >> 23;
344 psw = State.sregs[5];
346 if ((psw & PSW_S) == 0)
356 unsigned int op0, psw;
359 temp = (State.regs[OP[0]] << 23) >> 23;
361 psw = State.sregs[5];
363 if ((psw & PSW_SAT) != 0)
373 unsigned int op0, psw;
376 temp = (State.regs[OP[0]] << 23) >> 23;
378 psw = State.sregs[5];
380 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
390 unsigned int op0, psw;
393 temp = (State.regs[OP[0]] << 23) >> 23;
395 psw = State.sregs[5];
397 if ((((psw & PSW_Z) != 0)
398 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
408 /* interp.c will bump this by +2, so correct for it here. */
409 State.pc = State.regs[OP[0]] - 2;
412 /* jarl disp22, reg */
416 unsigned int op0, opc;
420 temp = (temp << 10) >> 10;
426 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
428 State.regs[OP[1]] = opc + 4;
435 unsigned int op0, op1, result, z, s, cy, ov;
437 /* Compute the result. */
438 op0 = State.regs[OP[0]];
439 op1 = State.regs[OP[1]];
442 /* Compute the condition codes. */
444 s = (result & 0x80000000);
445 cy = (result < op0 || result < op1);
446 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
447 && (op0 & 0x80000000) != (result & 0x80000000));
449 /* Store the result and condition codes. */
450 State.regs[OP[1]] = result;
451 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
452 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
453 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
456 /* add sign_extend(imm5), reg */
460 unsigned int op0, op1, result, z, s, cy, ov;
463 /* Compute the result. */
464 temp = (OP[0] & 0x1f);
465 temp = (temp << 27) >> 27;
467 op1 = State.regs[OP[1]];
470 /* Compute the condition codes. */
472 s = (result & 0x80000000);
473 cy = (result < op0 || result < op1);
474 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
475 && (op0 & 0x80000000) != (result & 0x80000000));
477 /* Store the result and condition codes. */
478 State.regs[OP[1]] = result;
479 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
480 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
481 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
484 /* addi sign_extend(imm16), reg, reg */
488 unsigned int op0, op1, result, z, s, cy, ov;
491 /* Compute the result. */
492 temp = (OP[0] & 0xffff);
493 temp = (temp << 16) >> 16;
495 op1 = State.regs[OP[1]];
498 /* Compute the condition codes. */
500 s = (result & 0x80000000);
501 cy = (result < op0 || result < op1);
502 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
503 && (op0 & 0x80000000) != (result & 0x80000000));
505 /* Store the result and condition codes. */
506 State.regs[OP[2]] = result;
507 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
508 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
509 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
516 unsigned int op0, op1, result, z, s, cy, ov;
518 /* Compute the result. */
519 op0 = State.regs[OP[0]];
520 op1 = State.regs[OP[1]];
523 /* Compute the condition codes. */
525 s = (result & 0x80000000);
526 cy = (result < -op0);
527 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
528 && (op1 & 0x80000000) != (result & 0x80000000));
530 /* Store the result and condition codes. */
531 State.regs[OP[1]] = result;
532 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
533 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
534 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
537 /* subr reg1, reg2 */
541 unsigned int op0, op1, result, z, s, cy, ov;
543 /* Compute the result. */
544 op0 = State.regs[OP[0]];
545 op1 = State.regs[OP[1]];
548 /* Compute the condition codes. */
550 s = (result & 0x80000000);
551 cy = (result < -op1);
552 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
553 && (op0 & 0x80000000) != (result & 0x80000000));
555 /* Store the result and condition codes. */
556 State.regs[OP[1]] = result;
557 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
558 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
559 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
562 /* mulh reg1, reg2 */
566 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
567 * (State.regs[OP[0]] & 0xffff));
570 /* mulh sign_extend(imm5), reg2
578 value = (value << 27) >> 27;
580 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
583 /* mulhi imm16, reg1, reg2 */
589 value = value & 0xffff;
591 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
594 /* divh reg1, reg2 */
598 unsigned int op0, op1, result, z, s, cy, ov;
601 /* Compute the result. */
602 temp = State.regs[OP[0]] & 0xffff;
603 temp = (temp << 16) >> 16;
605 op1 = State.regs[OP[1]];
607 if (op0 == 0xffffffff && op1 == 0x80000000)
620 /* Compute the condition codes. */
622 s = (result & 0x80000000);
624 /* Store the result and condition codes. */
625 State.regs[OP[1]] = result;
626 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
627 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
628 | (ov ? PSW_OV : 0));
635 unsigned int op0, op1, result, z, s, cy, ov;
637 /* Compute the result. */
638 op0 = State.regs[OP[0]];
639 op1 = State.regs[OP[1]];
642 /* Compute the condition codes. */
644 s = (result & 0x80000000);
645 cy = (result < -op0);
646 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
647 && (op1 & 0x80000000) != (result & 0x80000000));
649 /* Set condition codes. */
650 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
651 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
652 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
655 /* cmp sign_extend(imm5), reg */
659 unsigned int op0, op1, result, z, s, cy, ov;
662 /* Compute the result. */
664 temp = (temp << 27) >> 27;
666 op1 = State.regs[OP[1]];
669 /* Compute the condition codes. */
671 s = (result & 0x80000000);
672 cy = (result < -op0);
673 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
674 && (op1 & 0x80000000) != (result & 0x80000000));
676 /* Set condition codes. */
677 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
678 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
679 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
686 /* Hack alert. We turn off a bit in op0 since we really only
688 unsigned int op0, psw, result;
691 psw = State.sregs[5];
696 result = ((psw & PSW_OV) != 0);
699 result = ((psw & PSW_CY) != 0);
702 result = ((psw & PSW_Z) != 0);
705 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
708 result = ((psw & PSW_S) != 0);
714 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
717 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
718 || ((psw & PSW_Z) != 0)) != 0);
721 result = ((psw & PSW_OV) == 0);
724 result = ((psw & PSW_CY) == 0);
727 result = ((psw & PSW_Z) == 0);
730 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
733 result = ((psw & PSW_S) == 0);
736 result = ((psw & PSW_SAT) != 0);
739 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
742 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
743 || ((psw & PSW_Z) != 0)) == 0);
747 State.regs[OP[1]] = result;
754 unsigned int op0, op1, result, z, s, cy, ov, sat;
756 /* Compute the result. */
757 op0 = State.regs[OP[0]];
758 op1 = State.regs[OP[1]];
761 /* Compute the condition codes. */
763 s = (result & 0x80000000);
764 cy = (result < op0 || result < op1);
765 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
766 && (op0 & 0x80000000) != (result & 0x80000000));
769 /* Store the result and condition codes. */
770 State.regs[OP[1]] = result;
771 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
772 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
773 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
774 | (sat ? PSW_SAT : 0));
776 /* Handle saturated results. */
777 if (sat && (op0 & 0x80000000))
778 State.regs[OP[1]] = 0x80000000;
780 State.regs[OP[1]] = 0x7fffffff;
783 /* satadd sign_extend(imm5), reg */
787 unsigned int op0, op1, result, z, s, cy, ov, sat;
791 /* Compute the result. */
792 temp = (OP[0] & 0x1f);
793 temp = (temp << 27) >> 27;
795 op1 = State.regs[OP[1]];
798 /* Compute the condition codes. */
800 s = (result & 0x80000000);
801 cy = (result < op0 || result < op1);
802 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
803 && (op0 & 0x80000000) != (result & 0x80000000));
806 /* Store the result and condition codes. */
807 State.regs[OP[1]] = result;
808 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
809 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
810 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
811 | (sat ? PSW_SAT : 0));
813 /* Handle saturated results. */
814 if (sat && (op0 & 0x80000000))
815 State.regs[OP[1]] = 0x80000000;
817 State.regs[OP[1]] = 0x7fffffff;
820 /* satsub reg1, reg2 */
824 unsigned int op0, op1, result, z, s, cy, ov, sat;
826 /* Compute the result. */
827 op0 = State.regs[OP[0]];
828 op1 = State.regs[OP[1]];
831 /* Compute the condition codes. */
833 s = (result & 0x80000000);
834 cy = (result < -op0);
835 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
836 && (op1 & 0x80000000) != (result & 0x80000000));
839 /* Store the result and condition codes. */
840 State.regs[OP[1]] = result;
841 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
842 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
843 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
844 | (sat ? PSW_SAT : 0));
846 /* Handle saturated results. */
847 if (sat && (op1 & 0x80000000))
848 State.regs[OP[1]] = 0x80000000;
850 State.regs[OP[1]] = 0x7fffffff;
853 /* satsubi sign_extend(imm16), reg */
857 unsigned int op0, op1, result, z, s, cy, ov, sat;
860 /* Compute the result. */
861 temp = (OP[0] & 0xffff);
862 temp = (temp << 16) >> 16;
864 op1 = State.regs[OP[1]];
867 /* Compute the condition codes. */
869 s = (result & 0x80000000);
870 cy = (result < -op0);
871 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
872 && (op1 & 0x80000000) != (result & 0x80000000));
875 /* Store the result and condition codes. */
876 State.regs[OP[1]] = result;
877 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
878 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
879 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
880 | (sat ? PSW_SAT : 0));
882 /* Handle saturated results. */
883 if (sat && (op1 & 0x80000000))
884 State.regs[OP[1]] = 0x80000000;
886 State.regs[OP[1]] = 0x7fffffff;
892 unsigned int op0, op1, result, z, s, cy, ov, sat;
894 /* Compute the result. */
895 op0 = State.regs[OP[0]];
896 op1 = State.regs[OP[1]];
899 /* Compute the condition codes. */
901 s = (result & 0x80000000);
902 cy = (result < -op0);
903 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
904 && (op1 & 0x80000000) != (result & 0x80000000));
907 /* Store the result and condition codes. */
908 State.regs[OP[1]] = result;
909 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
910 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
911 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
912 | (sat ? PSW_SAT : 0));
914 /* Handle saturated results. */
915 if (sat && (op0 & 0x80000000))
916 State.regs[OP[1]] = 0x80000000;
918 State.regs[OP[1]] = 0x7fffffff;
925 unsigned int op0, op1, result, z, s, cy, ov;
927 /* Compute the result. */
928 op0 = State.regs[OP[0]];
929 op1 = State.regs[OP[1]];
932 /* Compute the condition codes. */
934 s = (result & 0x80000000);
936 /* Store the condition codes. */
937 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
938 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
945 State.regs[OP[1]] = State.regs[OP[0]];
948 /* mov sign_extend(imm5), reg */
954 value = (value << 27) >> 27;
955 State.regs[OP[1]] = value;
958 /* movea sign_extend(imm16), reg, reg */
965 value = (value << 16) >> 16;
967 State.regs[OP[2]] = State.regs[OP[1]] + value;
970 /* movhi imm16, reg, reg */
976 value = (value & 0xffff) << 16;
978 State.regs[OP[2]] = State.regs[OP[1]] + value;
981 /* sar zero_extend(imm5),reg1 */
985 unsigned int op0, op1, result, z, s, cy, ov;
988 op1 = State.regs[OP[1]];
989 result = (signed)op1 >> op0;
991 /* Compute the condition codes. */
993 s = (result & 0x80000000);
994 cy = (op1 & (1 << (op0 - 1)));
996 /* Store the result and condition codes. */
997 State.regs[OP[1]] = result;
998 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
999 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1000 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1003 /* sar reg1, reg2 */
1007 unsigned int op0, op1, result, z, s, cy, ov;
1009 op0 = State.regs[OP[0]] & 0x1f;
1010 op1 = State.regs[OP[1]];
1011 result = (signed)op1 >> op0;
1013 /* Compute the condition codes. */
1015 s = (result & 0x80000000);
1016 cy = (op1 & (1 << (op0 - 1)));
1018 /* Store the result and condition codes. */
1019 State.regs[OP[1]] = result;
1020 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1021 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1022 | (cy ? PSW_CY : 0));
1025 /* shl zero_extend(imm5),reg1 */
1029 unsigned int op0, op1, result, z, s, cy, ov;
1032 op1 = State.regs[OP[1]];
1033 result = op1 << op0;
1035 /* Compute the condition codes. */
1037 s = (result & 0x80000000);
1038 cy = (op1 & (1 << (32 - op0)));
1040 /* Store the result and condition codes. */
1041 State.regs[OP[1]] = result;
1042 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1043 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1044 | (cy ? PSW_CY : 0));
1047 /* shl reg1, reg2 */
1051 unsigned int op0, op1, result, z, s, cy, ov;
1053 op0 = State.regs[OP[0]] & 0x1f;
1054 op1 = State.regs[OP[1]];
1055 result = op1 << op0;
1057 /* Compute the condition codes. */
1059 s = (result & 0x80000000);
1060 cy = (op1 & (1 << (32 - op0)));
1062 /* Store the result and condition codes. */
1063 State.regs[OP[1]] = result;
1064 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1065 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1066 | (cy ? PSW_CY : 0));
1069 /* shr zero_extend(imm5),reg1 */
1073 unsigned int op0, op1, result, z, s, cy, ov;
1076 op1 = State.regs[OP[1]];
1077 result = op1 >> op0;
1079 /* Compute the condition codes. */
1081 s = (result & 0x80000000);
1082 cy = (op1 & (1 << (op0 - 1)));
1084 /* Store the result and condition codes. */
1085 State.regs[OP[1]] = result;
1086 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1087 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1088 | (cy ? PSW_CY : 0));
1091 /* shr reg1, reg2 */
1095 unsigned int op0, op1, result, z, s, cy, ov;
1097 op0 = State.regs[OP[0]] & 0x1f;
1098 op1 = State.regs[OP[1]];
1099 result = op1 >> op0;
1101 /* Compute the condition codes. */
1103 s = (result & 0x80000000);
1104 cy = (op1 & (1 << (op0 - 1)));
1106 /* Store the result and condition codes. */
1107 State.regs[OP[1]] = result;
1108 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1109 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1110 | (cy ? PSW_CY : 0));
1117 unsigned int op0, op1, result, z, s, cy, ov;
1119 /* Compute the result. */
1120 op0 = State.regs[OP[0]];
1121 op1 = State.regs[OP[1]];
1124 /* Compute the condition codes. */
1126 s = (result & 0x80000000);
1128 /* Store the result and condition codes. */
1129 State.regs[OP[1]] = result;
1130 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1131 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1134 /* ori zero_extend(imm16), reg, reg */
1138 unsigned int op0, op1, result, z, s, cy, ov;
1140 op0 = OP[0] & 0xffff;
1141 op1 = State.regs[OP[1]];
1144 /* Compute the condition codes. */
1146 s = (result & 0x80000000);
1148 /* Store the result and condition codes. */
1149 State.regs[OP[2]] = result;
1150 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1151 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1158 unsigned int op0, op1, result, z, s, cy, ov;
1160 /* Compute the result. */
1161 op0 = State.regs[OP[0]];
1162 op1 = State.regs[OP[1]];
1165 /* Compute the condition codes. */
1167 s = (result & 0x80000000);
1169 /* Store the result and condition codes. */
1170 State.regs[OP[1]] = result;
1171 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1172 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1175 /* andi zero_extend(imm16), reg, reg */
1179 unsigned int op0, op1, result, z, s, cy, ov;
1181 op0 = OP[0] & 0xffff;
1182 op1 = State.regs[OP[1]];
1185 /* Compute the condition codes. */
1188 /* Store the result and condition codes. */
1189 State.regs[OP[2]] = result;
1190 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1191 State.sregs[5] |= (z ? PSW_Z : 0);
1198 unsigned int op0, op1, result, z, s, cy, ov;
1200 /* Compute the result. */
1201 op0 = State.regs[OP[0]];
1202 op1 = State.regs[OP[1]];
1205 /* Compute the condition codes. */
1207 s = (result & 0x80000000);
1209 /* Store the result and condition codes. */
1210 State.regs[OP[1]] = result;
1211 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1212 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1215 /* xori zero_extend(imm16), reg, reg */
1219 unsigned int op0, op1, result, z, s, cy, ov;
1221 op0 = OP[0] & 0xffff;
1222 op1 = State.regs[OP[1]];
1225 /* Compute the condition codes. */
1227 s = (result & 0x80000000);
1229 /* Store the result and condition codes. */
1230 State.regs[OP[2]] = result;
1231 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1232 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1235 /* not reg1, reg2 */
1239 unsigned int op0, result, z, s, cy, ov;
1241 /* Compute the result. */
1242 op0 = State.regs[OP[0]];
1245 /* Compute the condition codes. */
1247 s = (result & 0x80000000);
1249 /* Store the result and condition codes. */
1250 State.regs[OP[1]] = result;
1251 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1252 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1283 State.sregs[5] |= PSW_ID;
1290 State.sregs[5] &= ~PSW_ID;
1293 /* halt, not supported */
1300 /* reti, not supported */
1307 /* trap, not supportd */
1320 op0 = State.regs[OP[0]];
1321 State.sregs[OP[1]] = op0;
1324 /* stsr, not supported */
1330 op0 = State.sregs[OP[1]];
1331 State.regs[OP[0]] = op0;