29 unsigned int op0, psw;
32 temp = (State.regs[OP[0]] << 23) >> 23;
36 if ((psw & PSW_OV) != 0)
46 unsigned int op0, psw;
49 temp = (State.regs[OP[0]] << 23) >> 23;
53 if ((psw & PSW_CY) != 0)
63 unsigned int op0, psw;
66 temp = (State.regs[OP[0]] << 23) >> 23;
70 if ((psw & PSW_Z) != 0)
80 unsigned int op0, psw;
83 temp = (State.regs[OP[0]] << 23) >> 23;
87 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
97 unsigned int op0, psw;
100 temp = (State.regs[OP[0]] << 23) >> 23;
104 if ((psw & PSW_S) != 0)
117 temp = (State.regs[OP[0]] << 23) >> 23;
126 unsigned int op0, psw;
129 temp = (State.regs[OP[0]] << 23) >> 23;
133 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
143 unsigned int op0, psw;
146 temp = (State.regs[OP[0]] << 23) >> 23;
150 if ((((psw & PSW_Z) != 0)
151 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
161 unsigned int op0, psw;
164 temp = (State.regs[OP[0]] << 23) >> 23;
168 if ((psw & PSW_OV) == 0)
178 unsigned int op0, psw;
181 temp = (State.regs[OP[0]] << 23) >> 23;
185 if ((psw & PSW_CY) == 0)
195 unsigned int op0, psw;
198 temp = (State.regs[OP[0]] << 23) >> 23;
202 if ((psw & PSW_Z) == 0)
212 unsigned int op0, psw;
215 temp = (State.regs[OP[0]] << 23) >> 23;
219 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
229 unsigned int op0, psw;
232 temp = (State.regs[OP[0]] << 23) >> 23;
236 if ((psw & PSW_S) == 0)
246 unsigned int op0, psw;
249 temp = (State.regs[OP[0]] << 23) >> 23;
253 if ((psw & PSW_SAT) != 0)
263 unsigned int op0, psw;
266 temp = (State.regs[OP[0]] << 23) >> 23;
270 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
280 unsigned int op0, psw;
283 temp = (State.regs[OP[0]] << 23) >> 23;
287 if ((((psw & PSW_Z) != 0)
288 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
304 unsigned int op0, op1, result, z, s, cy, ov;
306 /* Compute the result. */
307 op0 = State.regs[OP[0]];
308 op1 = State.regs[OP[1]];
311 /* Compute the condition codes. */
313 s = (result & 0x80000000);
314 cy = (result < op0 || result < op1);
315 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
316 && (op0 & 0x80000000) != (result & 0x80000000));
318 /* Store the result and condition codes. */
319 State.regs[OP[1]] = result;
320 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
321 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
322 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
325 /* add sign_extend(imm5), reg */
329 unsigned int op0, op1, result, z, s, cy, ov;
332 /* Compute the result. */
333 temp = (OP[0] & 0x1f);
334 temp = (temp << 27) >> 27;
336 op1 = State.regs[OP[1]];
339 /* Compute the condition codes. */
341 s = (result & 0x80000000);
342 cy = (result < op0 || result < op1);
343 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
344 && (op0 & 0x80000000) != (result & 0x80000000));
346 /* Store the result and condition codes. */
347 State.regs[OP[1]] = result;
348 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
349 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
350 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
353 /* addi sign_extend(imm16), reg, reg */
357 unsigned int op0, op1, result, z, s, cy, ov;
360 /* Compute the result. */
361 temp = (OP[0] & 0xffff);
362 temp = (temp << 16) >> 16;
364 op1 = State.regs[OP[1]];
367 /* Compute the condition codes. */
369 s = (result & 0x80000000);
370 cy = (result < op0 || result < op1);
371 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
372 && (op0 & 0x80000000) != (result & 0x80000000));
374 /* Store the result and condition codes. */
375 State.regs[OP[2]] = result;
376 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
377 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
378 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
385 unsigned int op0, op1, result, z, s, cy, ov;
387 /* Compute the result. */
388 op0 = State.regs[OP[0]];
389 op1 = State.regs[OP[1]];
392 /* Compute the condition codes. */
394 s = (result & 0x80000000);
395 cy = (result < -op0);
396 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
397 && (op1 & 0x80000000) != (result & 0x80000000));
399 /* Store the result and condition codes. */
400 State.regs[OP[1]] = result;
401 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
402 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
403 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
404 State.regs[OP[1]] = State.regs[OP[0]];
407 /* subr reg1, reg2 */
411 unsigned int op0, op1, result, z, s, cy, ov;
413 /* Compute the result. */
414 op0 = State.regs[OP[0]];
415 op1 = State.regs[OP[1]];
418 /* Compute the condition codes. */
420 s = (result & 0x80000000);
421 cy = (result < -op1);
422 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
423 && (op0 & 0x80000000) != (result & 0x80000000));
425 /* Store the result and condition codes. */
426 State.regs[OP[1]] = result;
427 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
428 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
429 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
432 /* mulh reg1, reg2 */
436 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
437 * (State.regs[OP[0]] & 0xffff));
440 /* mulh sign_extend(imm5), reg2
448 value = (value << 27) >> 27;
450 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
453 /* mulhi imm16, reg1, reg2 */
459 value = value & 0xffff;
461 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
464 /* divh reg1, reg2 */
468 unsigned int op0, op1, result, z, s, cy, ov;
471 /* Compute the result. */
472 temp = State.regs[OP[0]] & 0xffff;
473 temp = (temp << 16) >> 16;
475 op1 = State.regs[OP[1]];
477 if (op0 == 0xffffffff && op1 == 0x80000000)
490 /* Compute the condition codes. */
492 s = (result & 0x80000000);
494 /* Store the result and condition codes. */
495 State.regs[OP[1]] = result;
496 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
497 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
498 | (ov ? PSW_OV : 0));
535 State.regs[OP[1]] = State.regs[OP[0]];
538 /* mov sign_extend(imm5), reg */
544 value = (value << 27) >> 27;
545 State.regs[OP[1]] = value;
548 /* movea sign_extend(imm16), reg, reg */
555 value = (value << 16) >> 16;
557 State.regs[OP[2]] = State.regs[OP[1]] + value;
560 /* movhi imm16, reg, reg */
566 value = (value & 0xffff) << 16;
568 State.regs[OP[2]] = State.regs[OP[1]] + value;
606 /* sar zero_extend(imm5),reg1 */
610 unsigned int op0, op1, result, z, s, cy, ov;
613 op1 = State.regs[OP[1]];
614 result = (signed)op1 >> op0;
616 /* Compute the condition codes. */
618 s = (result & 0x80000000);
619 cy = (op1 & (1 << (op0 - 1)));
621 /* Store the result and condition codes. */
622 State.regs[OP[1]] = result;
623 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
624 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
625 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
632 unsigned int op0, op1, result, z, s, cy, ov;
634 op0 = State.regs[OP[0]] & 0x1f;
635 op1 = State.regs[OP[1]];
636 result = (signed)op1 >> op0;
638 /* Compute the condition codes. */
640 s = (result & 0x80000000);
641 cy = (op1 & (1 << (op0 - 1)));
643 /* Store the result and condition codes. */
644 State.regs[OP[1]] = result;
645 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
646 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
647 | (cy ? PSW_CY : 0));
650 /* shl zero_extend(imm5),reg1 */
654 unsigned int op0, op1, result, z, s, cy, ov;
657 op1 = State.regs[OP[1]];
660 /* Compute the condition codes. */
662 s = (result & 0x80000000);
663 cy = (op1 & (1 << (32 - op0)));
665 /* Store the result and condition codes. */
666 State.regs[OP[1]] = result;
667 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
668 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
669 | (cy ? PSW_CY : 0));
676 unsigned int op0, op1, result, z, s, cy, ov;
678 op0 = State.regs[OP[0]] & 0x1f;
679 op1 = State.regs[OP[1]];
682 /* Compute the condition codes. */
684 s = (result & 0x80000000);
685 cy = (op1 & (1 << (32 - op0)));
687 /* Store the result and condition codes. */
688 State.regs[OP[1]] = result;
689 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
690 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
691 | (cy ? PSW_CY : 0));
694 /* shr zero_extend(imm5),reg1 */
698 unsigned int op0, op1, result, z, s, cy, ov;
701 op1 = State.regs[OP[1]];
704 /* Compute the condition codes. */
706 s = (result & 0x80000000);
707 cy = (op1 & (1 << (op0 - 1)));
709 /* Store the result and condition codes. */
710 State.regs[OP[1]] = result;
711 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
712 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
713 | (cy ? PSW_CY : 0));
720 unsigned int op0, op1, result, z, s, cy, ov;
722 op0 = State.regs[OP[0]] & 0x1f;
723 op1 = State.regs[OP[1]];
726 /* Compute the condition codes. */
728 s = (result & 0x80000000);
729 cy = (op1 & (1 << (op0 - 1)));
731 /* Store the result and condition codes. */
732 State.regs[OP[1]] = result;
733 State.psw &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
734 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
735 | (cy ? PSW_CY : 0));
757 unsigned int op0, op1, result, z, s, cy, ov;
759 /* Compute the result. */
760 op0 = State.regs[OP[0]];
761 op1 = State.regs[OP[1]];
764 /* Compute the condition codes. */
766 s = (result & 0x80000000);
768 /* Store the result and condition codes. */
769 State.regs[OP[1]] = result;
770 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
771 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
774 /* ori zero_extend(imm16), reg, reg */
778 unsigned int op0, op1, result, z, s, cy, ov;
780 op0 = OP[0] & 0xffff;
781 op1 = State.regs[OP[1]];
784 /* Compute the condition codes. */
786 s = (result & 0x80000000);
788 /* Store the result and condition codes. */
789 State.regs[OP[2]] = result;
790 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
791 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
798 unsigned int op0, op1, result, z, s, cy, ov;
800 /* Compute the result. */
801 op0 = State.regs[OP[0]];
802 op1 = State.regs[OP[1]];
805 /* Compute the condition codes. */
807 s = (result & 0x80000000);
809 /* Store the result and condition codes. */
810 State.regs[OP[1]] = result;
811 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
812 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
815 /* andi zero_extend(imm16), reg, reg */
819 unsigned int op0, op1, result, z, s, cy, ov;
821 op0 = OP[0] & 0xffff;
822 op1 = State.regs[OP[1]];
825 /* Compute the condition codes. */
828 /* Store the result and condition codes. */
829 State.regs[OP[2]] = result;
830 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
831 State.psw |= (z ? PSW_Z : 0);
838 unsigned int op0, op1, result, z, s, cy, ov;
840 /* Compute the result. */
841 op0 = State.regs[OP[0]];
842 op1 = State.regs[OP[1]];
845 /* Compute the condition codes. */
847 s = (result & 0x80000000);
849 /* Store the result and condition codes. */
850 State.regs[OP[1]] = result;
851 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
852 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
855 /* xori zero_extend(imm16), reg, reg */
859 unsigned int op0, op1, result, z, s, cy, ov;
861 op0 = OP[0] & 0xffff;
862 op1 = State.regs[OP[1]];
865 /* Compute the condition codes. */
867 s = (result & 0x80000000);
869 /* Store the result and condition codes. */
870 State.regs[OP[2]] = result;
871 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
872 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
879 unsigned int op0, result, z, s, cy, ov;
881 /* Compute the result. */
882 op0 = State.regs[OP[0]];
885 /* Compute the condition codes. */
887 s = (result & 0x80000000);
889 /* Store the result and condition codes. */
890 State.regs[OP[1]] = result;
891 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
892 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
915 /* di, not supported */
922 /* ei, not supported */
929 /* halt, not supported */
936 /* reti, not supported */
943 /* trap, not supportd */
950 /* ldsr, not supported */
957 /* stsr, not supported */