157 XXX condition codes. */
161 State.regs[OP[1]] += State.regs[OP[0]];
164 /* add sign_extend(imm5), reg
166 XXX condition codes. */
172 value = (value << 27) >> 27;
174 State.regs[OP[1]] += value;
177 /* addi sign_extend(imm16), reg, reg
179 XXX condition codes. */
185 value = (value << 16) >> 16;
187 State.regs[OP[2]] = State.regs[OP[1]] + value;
192 XXX condition codes */
196 State.regs[OP[1]] -= State.regs[OP[0]];
201 XXX condition codes */
205 State.regs[OP[1]] = State.regs[OP[0]] - State.regs[OP[1]];
267 State.regs[OP[1]] = State.regs[OP[0]];
270 /* mov sign_extend(imm5), reg */
276 value = (value << 27) >> 27;
277 State.regs[OP[1]] = value;
280 /* movea sign_extend(imm16), reg, reg */
287 value = (value << 16) >> 16;
289 State.regs[OP[2]] = State.regs[OP[1]] + value;
292 /* movhi imm16, reg, reg */
298 value = (value & 0xffff) << 16;
300 State.regs[OP[2]] = State.regs[OP[1]] + value;
350 XXX condition codes */
354 State.regs[OP[1]] = ~State.regs[OP[0]];
394 XXX condition codes. */
398 State.regs[OP[1]] |= State.regs[OP[0]];
401 /* ori zero_extend(imm16), reg, reg
403 XXX condition codes */
411 State.regs[OP[2]] = State.regs[OP[1]] | value;
416 XXX condition codes. */
420 State.regs[OP[1]] &= State.regs[OP[0]];
423 /* andi zero_extend(imm16), reg, reg
425 XXX condition codes. */
433 State.regs[OP[2]] = State.regs[OP[1]] & value;
438 XXX condition codes. */
442 State.regs[OP[1]] ^= State.regs[OP[0]];
445 /* xori zero_extend(imm16), reg, reg
447 XXX condition codes. */
455 State.regs[OP[2]] = State.regs[OP[1]] ^ value;