130 unsigned int op0, op1, result, z, s, cy, ov;
132 /* Compute the result. */
133 op0 = State.regs[OP[0]];
134 op1 = State.regs[OP[1]];
137 /* Compute the condition codes. */
139 s = (result & 0x80000000);
140 cy = (result < op0 || result < op1);
141 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
142 && (op0 & 0x80000000) != (result & 0x80000000));
144 /* Store the result and condition codes. */
145 State.regs[OP[1]] = result;
146 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
147 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
148 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
151 /* add sign_extend(imm5), reg */
155 unsigned int op0, op1, result, z, s, cy, ov;
158 /* Compute the result. */
159 temp = (OP[0] & 0x1f);
160 temp = (temp << 27) >> 27;
162 op1 = State.regs[OP[1]];
165 /* Compute the condition codes. */
167 s = (result & 0x80000000);
168 cy = (result < op0 || result < op1);
169 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
170 && (op0 & 0x80000000) != (result & 0x80000000));
172 /* Store the result and condition codes. */
173 State.regs[OP[1]] = result;
174 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
175 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
176 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
179 /* addi sign_extend(imm16), reg, reg */
183 unsigned int op0, op1, result, z, s, cy, ov;
186 /* Compute the result. */
187 temp = (OP[0] & 0xffff);
188 temp = (temp << 16) >> 16;
190 op1 = State.regs[OP[1]];
193 /* Compute the condition codes. */
195 s = (result & 0x80000000);
196 cy = (result < op0 || result < op1);
197 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
198 && (op0 & 0x80000000) != (result & 0x80000000));
200 /* Store the result and condition codes. */
201 State.regs[OP[2]] = result;
202 State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
203 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
204 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
209 XXX condition codes */
213 State.regs[OP[1]] -= State.regs[OP[0]];
218 XXX condition codes */
222 State.regs[OP[1]] = State.regs[OP[0]] - State.regs[OP[1]];
227 XXX condition codes */
231 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
232 * (State.regs[OP[0]] & 0xffff));
235 /* mulh sign_extend(imm5), reg2
243 value = (value << 27) >> 27;
245 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
248 /* mulhi imm16, reg1, reg2
250 XXX condition codes */
256 value = value & 0xffff;
258 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
264 XXX Is this signed or unsigned? */
268 State.regs[OP[1]] /= (State.regs[OP[0]] & 0xffff);
305 State.regs[OP[1]] = State.regs[OP[0]];
308 /* mov sign_extend(imm5), reg */
314 value = (value << 27) >> 27;
315 State.regs[OP[1]] = value;
318 /* movea sign_extend(imm16), reg, reg */
325 value = (value << 16) >> 16;
327 State.regs[OP[2]] = State.regs[OP[1]] + value;
330 /* movhi imm16, reg, reg */
336 value = (value & 0xffff) << 16;
338 State.regs[OP[2]] = State.regs[OP[1]] + value;
376 /* sar zero_extend(imm5),reg1
378 XXX condition codes. */
382 int temp = State.regs[OP[1]];
384 temp >>= (OP[0] & 0x1f);
386 State.regs[OP[1]] = temp;
391 XXX condition codes. */
395 int temp = State.regs[OP[1]];
397 temp >>= (State.regs[OP[0]] & 0x1f);
399 State.regs[OP[1]] = temp;
402 /* shl zero_extend(imm5),reg1
404 XXX condition codes. */
408 State.regs[OP[1]] <<= (OP[0] & 0x1f);
413 XXX condition codes. */
417 State.regs[OP[1]] <<= (State.regs[OP[0]] & 0x1f);
420 /* shr zero_extend(imm5),reg1
422 XXX condition codes. */
426 State.regs[OP[1]] >>= (OP[0] & 0x1f);
431 XXX condition codes. */
435 State.regs[OP[1]] >>= (State.regs[OP[0]] & 0x1f);
457 unsigned int op0, op1, result, z, s, cy, ov;
459 /* Compute the result. */
460 op0 = State.regs[OP[0]];
461 op1 = State.regs[OP[1]];
464 /* Compute the condition codes. */
466 s = (result & 0x80000000);
468 /* Store the result and condition codes. */
469 State.regs[OP[1]] = result;
470 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
471 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
474 /* ori zero_extend(imm16), reg, reg */
478 unsigned int op0, op1, result, z, s, cy, ov;
480 op0 = OP[0] & 0xffff;
481 op1 = State.regs[OP[1]];
484 /* Compute the condition codes. */
486 s = (result & 0x80000000);
488 /* Store the result and condition codes. */
489 State.regs[OP[2]] = result;
490 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
491 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
492 State.psw |= (z ? PSW_Z : 0);
499 unsigned int op0, op1, result, z, s, cy, ov;
501 /* Compute the result. */
502 op0 = State.regs[OP[0]];
503 op1 = State.regs[OP[1]];
506 /* Compute the condition codes. */
508 s = (result & 0x80000000);
510 /* Store the result and condition codes. */
511 State.regs[OP[1]] = result;
512 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
513 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
516 /* andi zero_extend(imm16), reg, reg */
520 unsigned int op0, op1, result, z, s, cy, ov;
522 op0 = OP[0] & 0xffff;
523 op1 = State.regs[OP[1]];
526 /* Compute the condition codes. */
529 /* Store the result and condition codes. */
530 State.regs[OP[2]] = result;
531 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
532 State.psw |= (z ? PSW_Z : 0);
539 unsigned int op0, op1, result, z, s, cy, ov;
541 /* Compute the result. */
542 op0 = State.regs[OP[0]];
543 op1 = State.regs[OP[1]];
546 /* Compute the condition codes. */
548 s = (result & 0x80000000);
550 /* Store the result and condition codes. */
551 State.regs[OP[1]] = result;
552 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
553 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
556 /* xori zero_extend(imm16), reg, reg */
560 unsigned int op0, op1, result, z, s, cy, ov;
562 op0 = OP[0] & 0xffff;
563 op1 = State.regs[OP[1]];
566 /* Compute the condition codes. */
568 s = (result & 0x80000000);
570 /* Store the result and condition codes. */
571 State.regs[OP[2]] = result;
572 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
573 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
574 State.psw |= (z ? PSW_Z : 0);
581 unsigned int op0, result, z, s, cy, ov;
583 /* Compute the result. */
584 op0 = State.regs[OP[0]];
587 /* Compute the condition codes. */
589 s = (result & 0x80000000);
591 /* Store the result and condition codes. */
592 State.regs[OP[1]] = result;
593 State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
594 State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
617 /* di, not supported */
624 /* ei, not supported */
631 /* halt, not supported */
638 /* reti, not supported */
645 /* trap, not supportd */
652 /* ldsr, not supported */
659 /* stsr, not supported */