25 #include "targ-vals.h"
27 #include "libiberty.h"
30 #if !defined(__GO32__) && !defined(_WIN32)
32 #include <sys/times.h>
36 /* This is an array of the bit positions of registers r20 .. r31 in
37 that order in a prepare/dispose instruction. */
38 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
39 /* This is an array of the bit positions of registers r16 .. r31 in
40 that order in a push/pop instruction. */
41 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
42 /* This is an array of the bit positions of registers r1 .. r15 in
43 that order in a push/pop instruction. */
44 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
47 #ifndef SIZE_INSTRUCTION
48 #define SIZE_INSTRUCTION 18
52 #define SIZE_VALUES 11
56 unsigned32 trace_values[3];
59 const char *trace_name;
64 trace_input (name, type, size)
70 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
75 trace_module = TRACE_ALU_IDX;
88 trace_values[0] = State.regs[OP[0]];
95 trace_values[0] = State.regs[OP[1]];
96 trace_values[1] = State.regs[OP[0]];
102 trace_values[0] = SEXT5 (OP[0]);
103 trace_values[1] = OP[1];
104 trace_num_values = 2;
107 case OP_IMM_REG_MOVE:
108 trace_values[0] = SEXT5 (OP[0]);
109 trace_num_values = 1;
113 trace_values[0] = State.pc;
114 trace_values[1] = SEXT9 (OP[0]);
115 trace_values[2] = PSW;
116 trace_num_values = 3;
120 trace_values[0] = OP[1] * size;
121 trace_values[1] = State.regs[30];
122 trace_num_values = 2;
126 trace_values[0] = State.regs[OP[0]];
127 trace_values[1] = OP[1] * size;
128 trace_values[2] = State.regs[30];
129 trace_num_values = 3;
133 trace_values[0] = EXTEND16 (OP[2]);
134 trace_values[1] = State.regs[OP[0]];
135 trace_num_values = 2;
139 trace_values[0] = State.regs[OP[1]];
140 trace_values[1] = EXTEND16 (OP[2]);
141 trace_values[2] = State.regs[OP[0]];
142 trace_num_values = 3;
146 trace_values[0] = SEXT22 (OP[0]);
147 trace_values[1] = State.pc;
148 trace_num_values = 2;
152 trace_values[0] = EXTEND16 (OP[0]) << size;
153 trace_values[1] = State.regs[OP[1]];
154 trace_num_values = 2;
157 case OP_IMM16_REG_REG:
158 trace_values[0] = EXTEND16 (OP[2]) << size;
159 trace_values[1] = State.regs[OP[1]];
160 trace_num_values = 2;
163 case OP_UIMM_REG_REG:
164 trace_values[0] = (OP[0] & 0xffff) << size;
165 trace_values[1] = State.regs[OP[1]];
166 trace_num_values = 2;
169 case OP_UIMM16_REG_REG:
170 trace_values[0] = (OP[2]) << size;
171 trace_values[1] = State.regs[OP[1]];
172 trace_num_values = 2;
176 trace_num_values = 0;
180 trace_values[0] = PSW;
181 trace_num_values = 1;
185 trace_num_values = 0;
189 trace_values[0] = State.regs[OP[0]];
190 trace_num_values = 1;
194 trace_values[0] = State.sregs[OP[1]];
195 trace_num_values = 1;
201 trace_result (int has_result, unsigned32 result)
209 /* write out the values saved during the trace_input call */
212 for (i = 0; i < trace_num_values; i++)
214 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "", trace_values[i]);
215 chp = strchr (chp, '\0');
219 sprintf (chp, "%*s", SIZE_VALUES, "");
220 chp = strchr (chp, '\0');
224 /* append any result to the end of the buffer */
226 sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
228 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf);
232 trace_output (result)
233 enum op_types result;
235 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
257 trace_result (1, State.regs[OP[0]]);
261 case OP_REG_REG_MOVE:
263 case OP_IMM_REG_MOVE:
266 trace_result (1, State.regs[OP[1]]);
270 case OP_UIMM_REG_REG:
271 case OP_IMM16_REG_REG:
272 case OP_UIMM16_REG_REG:
273 trace_result (1, State.regs[OP[1]]);
278 trace_result (1, State.regs[OP[1]]);
284 trace_result (1, State.sregs[OP[1]]);
291 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
293 condition_met (unsigned code)
295 unsigned int psw = PSW;
299 case 0x0: return ((psw & PSW_OV) != 0);
300 case 0x1: return ((psw & PSW_CY) != 0);
301 case 0x2: return ((psw & PSW_Z) != 0);
302 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
303 case 0x4: return ((psw & PSW_S) != 0);
304 /*case 0x5: return 1;*/
305 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
306 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
307 case 0x8: return ((psw & PSW_OV) == 0);
308 case 0x9: return ((psw & PSW_CY) == 0);
309 case 0xa: return ((psw & PSW_Z) == 0);
310 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
311 case 0xc: return ((psw & PSW_S) == 0);
312 case 0xd: return ((psw & PSW_SAT) != 0);
313 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
314 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
321 Add32 (unsigned long a1, unsigned long a2, int * carry)
323 unsigned long result = (a1 + a2);
325 * carry = (result < a1);
331 Multiply64 (boolean sign, unsigned long op0)
342 op1 = State.regs[ OP[1] ];
346 /* Compute sign of result and adjust operands if necessary. */
348 sign = (op0 ^ op1) & 0x80000000;
350 if (((signed long) op0) < 0)
353 if (((signed long) op1) < 0)
357 /* We can split the 32x32 into four 16x16 operations. This ensures
358 that we do not lose precision on 32bit only hosts: */
359 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
360 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
361 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
362 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
364 /* We now need to add all of these results together, taking care
365 to propogate the carries from the additions: */
366 RdLo = Add32 (lo, (mid1 << 16), & carry);
368 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
369 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
373 /* Negate result if necessary. */
377 if (RdLo == 0xFFFFFFFF)
386 /* Don't store into register 0. */
388 State.regs[ OP[1] ] = RdLo;
390 State.regs[ OP[2] >> 11 ] = RdHi;
396 /* Read a null terminated string from memory, return in a buffer */
404 while (sim_core_read_1 (STATE_CPU (sd, 0),
405 PC, read_map, addr + nr) != 0)
407 buf = NZALLOC (char, nr + 1);
408 sim_read (simulator, addr, buf, nr);
412 /* Read a null terminated argument vector from memory, return in a
415 fetch_argv (sd, addr)
421 char **buf = xmalloc (max_nr * sizeof (char*));
424 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
425 PC, read_map, addr + nr * 4);
427 buf[nr] = fetch_str (sd, a);
429 if (nr == max_nr - 1)
432 buf = xrealloc (buf, max_nr * sizeof (char*));
444 trace_input ("sst.b", OP_STORE16, 1);
446 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
448 trace_output (OP_STORE16);
457 trace_input ("sst.h", OP_STORE16, 2);
459 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
461 trace_output (OP_STORE16);
470 trace_input ("sst.w", OP_STORE16, 4);
472 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
474 trace_output (OP_STORE16);
485 trace_input ("ld.b", OP_LOAD32, 1);
487 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
489 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
491 trace_output (OP_LOAD32);
502 trace_input ("ld.h", OP_LOAD32, 2);
504 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
507 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
509 trace_output (OP_LOAD32);
520 trace_input ("ld.w", OP_LOAD32, 4);
522 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
525 State.regs[ OP[1] ] = load_mem (adr, 4);
527 trace_output (OP_LOAD32);
536 trace_input ("st.b", OP_STORE32, 1);
538 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
540 trace_output (OP_STORE32);
551 trace_input ("st.h", OP_STORE32, 2);
553 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
556 store_mem (adr, 2, State.regs[ OP[1] ]);
558 trace_output (OP_STORE32);
569 trace_input ("st.w", OP_STORE32, 4);
571 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
574 store_mem (adr, 4, State.regs[ OP[1] ]);
576 trace_output (OP_STORE32);
585 unsigned int op0, op1, result, z, s, cy, ov;
587 trace_input ("add", OP_REG_REG, 0);
589 /* Compute the result. */
591 op0 = State.regs[ OP[0] ];
592 op1 = State.regs[ OP[1] ];
596 /* Compute the condition codes. */
598 s = (result & 0x80000000);
599 cy = (result < op0 || result < op1);
600 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
601 && (op0 & 0x80000000) != (result & 0x80000000));
603 /* Store the result and condition codes. */
604 State.regs[OP[1]] = result;
605 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
606 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
607 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
608 trace_output (OP_REG_REG);
613 /* add sign_extend(imm5), reg */
617 unsigned int op0, op1, result, z, s, cy, ov;
620 trace_input ("add", OP_IMM_REG, 0);
622 /* Compute the result. */
623 temp = SEXT5 (OP[0]);
625 op1 = State.regs[OP[1]];
628 /* Compute the condition codes. */
630 s = (result & 0x80000000);
631 cy = (result < op0 || result < op1);
632 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
633 && (op0 & 0x80000000) != (result & 0x80000000));
635 /* Store the result and condition codes. */
636 State.regs[OP[1]] = result;
637 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
638 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
639 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
640 trace_output (OP_IMM_REG);
645 /* addi sign_extend(imm16), reg, reg */
649 unsigned int op0, op1, result, z, s, cy, ov;
651 trace_input ("addi", OP_IMM16_REG_REG, 0);
653 /* Compute the result. */
655 op0 = EXTEND16 (OP[2]);
656 op1 = State.regs[ OP[0] ];
659 /* Compute the condition codes. */
661 s = (result & 0x80000000);
662 cy = (result < op0 || result < op1);
663 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
664 && (op0 & 0x80000000) != (result & 0x80000000));
666 /* Store the result and condition codes. */
667 State.regs[OP[1]] = result;
668 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
669 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
670 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
671 trace_output (OP_IMM16_REG_REG);
680 unsigned int op0, op1, result, z, s, cy, ov;
682 trace_input ("sub", OP_REG_REG, 0);
683 /* Compute the result. */
684 op0 = State.regs[ OP[0] ];
685 op1 = State.regs[ OP[1] ];
688 /* Compute the condition codes. */
690 s = (result & 0x80000000);
692 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
693 && (op1 & 0x80000000) != (result & 0x80000000));
695 /* Store the result and condition codes. */
696 State.regs[OP[1]] = result;
697 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
698 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
699 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
700 trace_output (OP_REG_REG);
705 /* subr reg1, reg2 */
709 unsigned int op0, op1, result, z, s, cy, ov;
711 trace_input ("subr", OP_REG_REG, 0);
712 /* Compute the result. */
713 op0 = State.regs[ OP[0] ];
714 op1 = State.regs[ OP[1] ];
717 /* Compute the condition codes. */
719 s = (result & 0x80000000);
721 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
722 && (op0 & 0x80000000) != (result & 0x80000000));
724 /* Store the result and condition codes. */
725 State.regs[OP[1]] = result;
726 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
727 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
728 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
729 trace_output (OP_REG_REG);
738 trace_input ("mulh", OP_REG_REG, 0);
740 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
742 trace_output (OP_REG_REG);
747 /* mulh sign_extend(imm5), reg2 */
751 trace_input ("mulh", OP_IMM_REG, 0);
753 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
755 trace_output (OP_IMM_REG);
760 /* mulhi imm16, reg1, reg2 */
764 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
766 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
768 trace_output (OP_IMM16_REG_REG);
773 /* divh reg1, reg2 */
777 unsigned int op0, op1, result, ov, s, z;
780 trace_input ("divh", OP_REG_REG, 0);
782 /* Compute the result. */
783 temp = EXTEND16 (State.regs[ OP[0] ]);
785 op1 = State.regs[OP[1]];
787 if (op0 == 0xffffffff && op1 == 0x80000000)
803 /* Compute the condition codes. */
805 s = (result & 0x80000000);
807 /* Store the result and condition codes. */
808 State.regs[OP[1]] = result;
809 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
810 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
811 | (ov ? PSW_OV : 0));
812 trace_output (OP_REG_REG);
821 unsigned int op0, op1, result, z, s, cy, ov;
823 trace_input ("cmp", OP_REG_REG_CMP, 0);
824 /* Compute the result. */
825 op0 = State.regs[ OP[0] ];
826 op1 = State.regs[ OP[1] ];
829 /* Compute the condition codes. */
831 s = (result & 0x80000000);
833 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
834 && (op1 & 0x80000000) != (result & 0x80000000));
836 /* Set condition codes. */
837 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
838 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
839 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
840 trace_output (OP_REG_REG_CMP);
845 /* cmp sign_extend(imm5), reg */
849 unsigned int op0, op1, result, z, s, cy, ov;
852 /* Compute the result. */
853 trace_input ("cmp", OP_IMM_REG_CMP, 0);
854 temp = SEXT5 (OP[0]);
856 op1 = State.regs[OP[1]];
859 /* Compute the condition codes. */
861 s = (result & 0x80000000);
863 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
864 && (op1 & 0x80000000) != (result & 0x80000000));
866 /* Set condition codes. */
867 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
868 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
869 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
870 trace_output (OP_IMM_REG_CMP);
879 trace_input ("setf", OP_EX1, 0);
881 State.regs[ OP[1] ] = condition_met (OP[0]);
883 trace_output (OP_EX1);
892 unsigned int op0, op1, result, z, s, cy, ov, sat;
894 trace_input ("satadd", OP_REG_REG, 0);
895 /* Compute the result. */
896 op0 = State.regs[ OP[0] ];
897 op1 = State.regs[ OP[1] ];
900 /* Compute the condition codes. */
902 s = (result & 0x80000000);
903 cy = (result < op0 || result < op1);
904 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
905 && (op0 & 0x80000000) != (result & 0x80000000));
908 /* Store the result and condition codes. */
909 State.regs[OP[1]] = result;
910 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
911 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
912 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
913 | (sat ? PSW_SAT : 0));
915 /* Handle saturated results. */
917 State.regs[OP[1]] = 0x80000000;
919 State.regs[OP[1]] = 0x7fffffff;
920 trace_output (OP_REG_REG);
925 /* satadd sign_extend(imm5), reg */
929 unsigned int op0, op1, result, z, s, cy, ov, sat;
933 trace_input ("satadd", OP_IMM_REG, 0);
935 /* Compute the result. */
936 temp = SEXT5 (OP[0]);
938 op1 = State.regs[OP[1]];
941 /* Compute the condition codes. */
943 s = (result & 0x80000000);
944 cy = (result < op0 || result < op1);
945 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
946 && (op0 & 0x80000000) != (result & 0x80000000));
949 /* Store the result and condition codes. */
950 State.regs[OP[1]] = result;
951 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
952 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
953 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
954 | (sat ? PSW_SAT : 0));
956 /* Handle saturated results. */
958 State.regs[OP[1]] = 0x80000000;
960 State.regs[OP[1]] = 0x7fffffff;
961 trace_output (OP_IMM_REG);
966 /* satsub reg1, reg2 */
970 unsigned int op0, op1, result, z, s, cy, ov, sat;
972 trace_input ("satsub", OP_REG_REG, 0);
974 /* Compute the result. */
975 op0 = State.regs[ OP[0] ];
976 op1 = State.regs[ OP[1] ];
979 /* Compute the condition codes. */
981 s = (result & 0x80000000);
983 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
984 && (op1 & 0x80000000) != (result & 0x80000000));
987 /* Store the result and condition codes. */
988 State.regs[OP[1]] = result;
989 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
990 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
991 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
992 | (sat ? PSW_SAT : 0));
994 /* Handle saturated results. */
996 State.regs[OP[1]] = 0x80000000;
998 State.regs[OP[1]] = 0x7fffffff;
999 trace_output (OP_REG_REG);
1003 /* satsubi sign_extend(imm16), reg */
1007 unsigned int op0, op1, result, z, s, cy, ov, sat;
1010 trace_input ("satsubi", OP_IMM_REG, 0);
1012 /* Compute the result. */
1013 temp = EXTEND16 (OP[2]);
1015 op1 = State.regs[ OP[0] ];
1018 /* Compute the condition codes. */
1020 s = (result & 0x80000000);
1022 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1023 && (op1 & 0x80000000) != (result & 0x80000000));
1026 /* Store the result and condition codes. */
1027 State.regs[OP[1]] = result;
1028 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1029 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1030 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1031 | (sat ? PSW_SAT : 0));
1033 /* Handle saturated results. */
1035 State.regs[OP[1]] = 0x80000000;
1037 State.regs[OP[1]] = 0x7fffffff;
1038 trace_output (OP_IMM_REG);
1043 /* satsubr reg,reg */
1047 unsigned int op0, op1, result, z, s, cy, ov, sat;
1049 trace_input ("satsubr", OP_REG_REG, 0);
1051 /* Compute the result. */
1052 op0 = State.regs[ OP[0] ];
1053 op1 = State.regs[ OP[1] ];
1056 /* Compute the condition codes. */
1058 s = (result & 0x80000000);
1059 cy = (result < op0);
1060 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1061 && (op1 & 0x80000000) != (result & 0x80000000));
1064 /* Store the result and condition codes. */
1065 State.regs[OP[1]] = result;
1066 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1067 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1068 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1069 | (sat ? PSW_SAT : 0));
1071 /* Handle saturated results. */
1073 State.regs[OP[1]] = 0x80000000;
1075 State.regs[OP[1]] = 0x7fffffff;
1076 trace_output (OP_REG_REG);
1085 unsigned int op0, op1, result, z, s;
1087 trace_input ("tst", OP_REG_REG_CMP, 0);
1089 /* Compute the result. */
1090 op0 = State.regs[ OP[0] ];
1091 op1 = State.regs[ OP[1] ];
1094 /* Compute the condition codes. */
1096 s = (result & 0x80000000);
1098 /* Store the condition codes. */
1099 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1100 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1101 trace_output (OP_REG_REG_CMP);
1106 /* mov sign_extend(imm5), reg */
1110 int value = SEXT5 (OP[0]);
1112 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1114 State.regs[ OP[1] ] = value;
1116 trace_output (OP_IMM_REG_MOVE);
1121 /* movhi imm16, reg, reg */
1125 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1127 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1129 trace_output (OP_UIMM16_REG_REG);
1134 /* sar zero_extend(imm5),reg1 */
1138 unsigned int op0, op1, result, z, s, cy;
1140 trace_input ("sar", OP_IMM_REG, 0);
1142 op1 = State.regs[ OP[1] ];
1143 result = (signed)op1 >> op0;
1145 /* Compute the condition codes. */
1147 s = (result & 0x80000000);
1148 cy = (op1 & (1 << (op0 - 1)));
1150 /* Store the result and condition codes. */
1151 State.regs[ OP[1] ] = result;
1152 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1153 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1154 | (cy ? PSW_CY : 0));
1155 trace_output (OP_IMM_REG);
1160 /* sar reg1, reg2 */
1164 unsigned int op0, op1, result, z, s, cy;
1166 trace_input ("sar", OP_REG_REG, 0);
1168 op0 = State.regs[ OP[0] ] & 0x1f;
1169 op1 = State.regs[ OP[1] ];
1170 result = (signed)op1 >> op0;
1172 /* Compute the condition codes. */
1174 s = (result & 0x80000000);
1175 cy = (op1 & (1 << (op0 - 1)));
1177 /* Store the result and condition codes. */
1178 State.regs[OP[1]] = result;
1179 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1180 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1181 | (cy ? PSW_CY : 0));
1182 trace_output (OP_REG_REG);
1187 /* shl zero_extend(imm5),reg1 */
1191 unsigned int op0, op1, result, z, s, cy;
1193 trace_input ("shl", OP_IMM_REG, 0);
1195 op1 = State.regs[ OP[1] ];
1196 result = op1 << op0;
1198 /* Compute the condition codes. */
1200 s = (result & 0x80000000);
1201 cy = (op1 & (1 << (32 - op0)));
1203 /* Store the result and condition codes. */
1204 State.regs[OP[1]] = result;
1205 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1206 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1207 | (cy ? PSW_CY : 0));
1208 trace_output (OP_IMM_REG);
1213 /* shl reg1, reg2 */
1217 unsigned int op0, op1, result, z, s, cy;
1219 trace_input ("shl", OP_REG_REG, 0);
1220 op0 = State.regs[ OP[0] ] & 0x1f;
1221 op1 = State.regs[ OP[1] ];
1222 result = op1 << op0;
1224 /* Compute the condition codes. */
1226 s = (result & 0x80000000);
1227 cy = (op1 & (1 << (32 - op0)));
1229 /* Store the result and condition codes. */
1230 State.regs[OP[1]] = result;
1231 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1232 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1233 | (cy ? PSW_CY : 0));
1234 trace_output (OP_REG_REG);
1239 /* shr zero_extend(imm5),reg1 */
1243 unsigned int op0, op1, result, z, s, cy;
1245 trace_input ("shr", OP_IMM_REG, 0);
1247 op1 = State.regs[ OP[1] ];
1248 result = op1 >> op0;
1250 /* Compute the condition codes. */
1252 s = (result & 0x80000000);
1253 cy = (op1 & (1 << (op0 - 1)));
1255 /* Store the result and condition codes. */
1256 State.regs[OP[1]] = result;
1257 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1258 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1259 | (cy ? PSW_CY : 0));
1260 trace_output (OP_IMM_REG);
1265 /* shr reg1, reg2 */
1269 unsigned int op0, op1, result, z, s, cy;
1271 trace_input ("shr", OP_REG_REG, 0);
1272 op0 = State.regs[ OP[0] ] & 0x1f;
1273 op1 = State.regs[ OP[1] ];
1274 result = op1 >> op0;
1276 /* Compute the condition codes. */
1278 s = (result & 0x80000000);
1279 cy = (op1 & (1 << (op0 - 1)));
1281 /* Store the result and condition codes. */
1282 State.regs[OP[1]] = result;
1283 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1284 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1285 | (cy ? PSW_CY : 0));
1286 trace_output (OP_REG_REG);
1295 unsigned int op0, op1, result, z, s;
1297 trace_input ("or", OP_REG_REG, 0);
1299 /* Compute the result. */
1300 op0 = State.regs[ OP[0] ];
1301 op1 = State.regs[ OP[1] ];
1304 /* Compute the condition codes. */
1306 s = (result & 0x80000000);
1308 /* Store the result and condition codes. */
1309 State.regs[OP[1]] = result;
1310 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1311 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1312 trace_output (OP_REG_REG);
1317 /* ori zero_extend(imm16), reg, reg */
1321 unsigned int op0, op1, result, z, s;
1323 trace_input ("ori", OP_UIMM16_REG_REG, 0);
1325 op1 = State.regs[ OP[0] ];
1328 /* Compute the condition codes. */
1330 s = (result & 0x80000000);
1332 /* Store the result and condition codes. */
1333 State.regs[OP[1]] = result;
1334 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1335 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1336 trace_output (OP_UIMM16_REG_REG);
1345 unsigned int op0, op1, result, z, s;
1347 trace_input ("and", OP_REG_REG, 0);
1349 /* Compute the result. */
1350 op0 = State.regs[ OP[0] ];
1351 op1 = State.regs[ OP[1] ];
1354 /* Compute the condition codes. */
1356 s = (result & 0x80000000);
1358 /* Store the result and condition codes. */
1359 State.regs[OP[1]] = result;
1360 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1361 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1362 trace_output (OP_REG_REG);
1367 /* andi zero_extend(imm16), reg, reg */
1371 unsigned int result, z;
1373 trace_input ("andi", OP_UIMM16_REG_REG, 0);
1375 result = OP[2] & State.regs[ OP[0] ];
1377 /* Compute the condition codes. */
1380 /* Store the result and condition codes. */
1381 State.regs[ OP[1] ] = result;
1383 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1384 PSW |= (z ? PSW_Z : 0);
1386 trace_output (OP_UIMM16_REG_REG);
1395 unsigned int op0, op1, result, z, s;
1397 trace_input ("xor", OP_REG_REG, 0);
1399 /* Compute the result. */
1400 op0 = State.regs[ OP[0] ];
1401 op1 = State.regs[ OP[1] ];
1404 /* Compute the condition codes. */
1406 s = (result & 0x80000000);
1408 /* Store the result and condition codes. */
1409 State.regs[OP[1]] = result;
1410 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1411 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1412 trace_output (OP_REG_REG);
1417 /* xori zero_extend(imm16), reg, reg */
1421 unsigned int op0, op1, result, z, s;
1423 trace_input ("xori", OP_UIMM16_REG_REG, 0);
1425 op1 = State.regs[ OP[0] ];
1428 /* Compute the condition codes. */
1430 s = (result & 0x80000000);
1432 /* Store the result and condition codes. */
1433 State.regs[OP[1]] = result;
1434 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1435 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1436 trace_output (OP_UIMM16_REG_REG);
1441 /* not reg1, reg2 */
1445 unsigned int op0, result, z, s;
1447 trace_input ("not", OP_REG_REG_MOVE, 0);
1448 /* Compute the result. */
1449 op0 = State.regs[ OP[0] ];
1452 /* Compute the condition codes. */
1454 s = (result & 0x80000000);
1456 /* Store the result and condition codes. */
1457 State.regs[OP[1]] = result;
1458 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1459 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1460 trace_output (OP_REG_REG_MOVE);
1469 unsigned int op0, op1, op2;
1472 trace_input ("set1", OP_BIT, 0);
1473 op0 = State.regs[ OP[0] ];
1475 temp = EXTEND16 (OP[2]);
1477 temp = load_mem (op0 + op2, 1);
1479 if ((temp & (1 << op1)) == 0)
1482 store_mem (op0 + op2, 1, temp);
1483 trace_output (OP_BIT);
1492 unsigned int op0, op1, op2;
1495 trace_input ("not1", OP_BIT, 0);
1496 op0 = State.regs[ OP[0] ];
1498 temp = EXTEND16 (OP[2]);
1500 temp = load_mem (op0 + op2, 1);
1502 if ((temp & (1 << op1)) == 0)
1505 store_mem (op0 + op2, 1, temp);
1506 trace_output (OP_BIT);
1515 unsigned int op0, op1, op2;
1518 trace_input ("clr1", OP_BIT, 0);
1519 op0 = State.regs[ OP[0] ];
1521 temp = EXTEND16 (OP[2]);
1523 temp = load_mem (op0 + op2, 1);
1525 if ((temp & (1 << op1)) == 0)
1527 temp &= ~(1 << op1);
1528 store_mem (op0 + op2, 1, temp);
1529 trace_output (OP_BIT);
1538 unsigned int op0, op1, op2;
1541 trace_input ("tst1", OP_BIT, 0);
1542 op0 = State.regs[ OP[0] ];
1544 temp = EXTEND16 (OP[2]);
1546 temp = load_mem (op0 + op2, 1);
1548 if ((temp & (1 << op1)) == 0)
1550 trace_output (OP_BIT);
1559 trace_input ("di", OP_NONE, 0);
1561 trace_output (OP_NONE);
1570 trace_input ("ei", OP_NONE, 0);
1572 trace_output (OP_NONE);
1581 trace_input ("halt", OP_NONE, 0);
1582 /* FIXME this should put processor into a mode where NMI still handled */
1583 trace_output (OP_NONE);
1584 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1585 sim_stopped, SIM_SIGTRAP);
1593 trace_input ("trap", OP_TRAP, 0);
1594 trace_output (OP_TRAP);
1596 /* Trap 31 is used for simulating OS I/O functions */
1600 int save_errno = errno;
1603 /* Registers passed to trap 0 */
1605 #define FUNC State.regs[6] /* function number, return value */
1606 #define PARM1 State.regs[7] /* optional parm 1 */
1607 #define PARM2 State.regs[8] /* optional parm 2 */
1608 #define PARM3 State.regs[9] /* optional parm 3 */
1610 /* Registers set by trap 0 */
1612 #define RETVAL State.regs[10] /* return value */
1613 #define RETERR State.regs[11] /* return error code */
1615 /* Turn a pointer in a register into a pointer into real memory. */
1617 #define MEMPTR(x) (map (x))
1623 #ifdef TARGET_SYS_fork
1624 case TARGET_SYS_fork:
1631 #ifdef TARGET_SYS_execv
1632 case TARGET_SYS_execve:
1634 char *path = fetch_str (simulator, PARM1);
1635 char **argv = fetch_argv (simulator, PARM2);
1636 char **envp = fetch_argv (simulator, PARM3);
1637 RETVAL = execve (path, argv, envp);
1647 #ifdef TARGET_SYS_execv
1648 case TARGET_SYS_execv:
1650 char *path = fetch_str (simulator, PARM1);
1651 char **argv = fetch_argv (simulator, PARM2);
1652 RETVAL = execv (path, argv);
1661 #ifdef TARGET_SYS_pipe
1662 case TARGET_SYS_pipe:
1668 RETVAL = pipe (host_fd);
1669 SW (buf, host_fd[0]);
1670 buf += sizeof(uint16);
1671 SW (buf, host_fd[1]);
1678 #ifdef TARGET_SYS_wait
1679 case TARGET_SYS_wait:
1683 RETVAL = wait (&status);
1690 #ifdef TARGET_SYS_read
1691 case TARGET_SYS_read:
1693 char *buf = zalloc (PARM3);
1694 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1695 sim_write (simulator, PARM2, buf, PARM3);
1701 #ifdef TARGET_SYS_write
1702 case TARGET_SYS_write:
1704 char *buf = zalloc (PARM3);
1705 sim_read (simulator, PARM2, buf, PARM3);
1707 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1709 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1715 #ifdef TARGET_SYS_lseek
1716 case TARGET_SYS_lseek:
1717 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1721 #ifdef TARGET_SYS_close
1722 case TARGET_SYS_close:
1723 RETVAL = sim_io_close (simulator, PARM1);
1727 #ifdef TARGET_SYS_open
1728 case TARGET_SYS_open:
1730 char *buf = fetch_str (simulator, PARM1);
1731 RETVAL = sim_io_open (simulator, buf, PARM2);
1737 #ifdef TARGET_SYS_exit
1738 case TARGET_SYS_exit:
1739 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1740 /* get signal encoded by kill */
1741 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1742 sim_signalled, PARM1 & 0xffff);
1743 else if (PARM1 == 0xdead)
1745 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1746 sim_stopped, SIM_SIGABRT);
1748 /* PARM1 has exit status */
1749 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1754 #if !defined(__GO32__) && !defined(_WIN32)
1755 #ifdef TARGET_SYS_stat
1756 case TARGET_SYS_stat: /* added at hmsi */
1757 /* stat system call */
1759 struct stat host_stat;
1761 char *path = fetch_str (simulator, PARM1);
1763 RETVAL = stat (path, &host_stat);
1768 /* Just wild-assed guesses. */
1769 store_mem (buf, 2, host_stat.st_dev);
1770 store_mem (buf + 2, 2, host_stat.st_ino);
1771 store_mem (buf + 4, 4, host_stat.st_mode);
1772 store_mem (buf + 8, 2, host_stat.st_nlink);
1773 store_mem (buf + 10, 2, host_stat.st_uid);
1774 store_mem (buf + 12, 2, host_stat.st_gid);
1775 store_mem (buf + 14, 2, host_stat.st_rdev);
1776 store_mem (buf + 16, 4, host_stat.st_size);
1777 store_mem (buf + 20, 4, host_stat.st_atime);
1778 store_mem (buf + 28, 4, host_stat.st_mtime);
1779 store_mem (buf + 36, 4, host_stat.st_ctime);
1786 #ifdef TARGET_SYS_chown
1787 case TARGET_SYS_chown:
1789 char *path = fetch_str (simulator, PARM1);
1790 RETVAL = chown (path, PARM2, PARM3);
1798 #ifdef TARGET_SYS_chmod
1799 case TARGET_SYS_chmod:
1801 char *path = fetch_str (simulator, PARM1);
1802 RETVAL = chmod (path, PARM2);
1809 #ifdef TARGET_SYS_time
1811 case TARGET_SYS_time:
1814 RETVAL = time (&now);
1815 store_mem (PARM1, 4, now);
1821 #if !defined(__GO32__) && !defined(_WIN32)
1822 #ifdef TARGET_SYS_times
1823 case TARGET_SYS_times:
1826 RETVAL = times (&tms);
1827 store_mem (PARM1, 4, tms.tms_utime);
1828 store_mem (PARM1 + 4, 4, tms.tms_stime);
1829 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1830 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1836 #ifdef TARGET_SYS_gettimeofday
1837 #if !defined(__GO32__) && !defined(_WIN32)
1838 case TARGET_SYS_gettimeofday:
1842 RETVAL = gettimeofday (&t, &tz);
1843 store_mem (PARM1, 4, t.tv_sec);
1844 store_mem (PARM1 + 4, 4, t.tv_usec);
1845 store_mem (PARM2, 4, tz.tz_minuteswest);
1846 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1852 #ifdef TARGET_SYS_utime
1854 case TARGET_SYS_utime:
1856 /* Cast the second argument to void *, to avoid type mismatch
1857 if a prototype is present. */
1858 sim_io_error (simulator, "Utime not supported");
1859 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1874 { /* Trap 0 -> 30 */
1879 ECR |= 0x40 + OP[0];
1880 /* Flag that we are now doing exception processing. */
1881 PSW |= PSW_EP | PSW_ID;
1882 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
1888 /* tst1 reg2, [reg1] */
1894 trace_input ("tst1", OP_BIT, 1);
1896 temp = load_mem (State.regs[ OP[0] ], 1);
1899 if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
1902 trace_output (OP_BIT);
1907 /* mulu reg1, reg2, reg3 */
1911 trace_input ("mulu", OP_REG_REG_REG, 0);
1913 Multiply64 (false, State.regs[ OP[0] ]);
1915 trace_output (OP_REG_REG_REG);
1920 #define BIT_CHANGE_OP( name, binop ) \
1922 unsigned int temp; \
1924 trace_input (name, OP_BIT_CHANGE, 0); \
1926 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
1927 temp = load_mem (State.regs[ OP[0] ], 1); \
1930 if ((temp & bit) == 0) \
1934 store_mem (State.regs[ OP[0] ], 1, temp); \
1936 trace_output (OP_BIT_CHANGE); \
1940 /* clr1 reg2, [reg1] */
1944 BIT_CHANGE_OP ("clr1", &= ~ );
1947 /* not1 reg2, [reg1] */
1951 BIT_CHANGE_OP ("not1", ^= );
1958 BIT_CHANGE_OP ("set1", |= );
1965 trace_input ("sasf", OP_EX1, 0);
1967 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
1969 trace_output (OP_EX1);
1974 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
1975 (Soew_Tan@el.nec.com) */
1980 unsigned long int als,
1981 unsigned long int sfi,
1982 unsigned32 /*unsigned long int*/ * quotient_ptr,
1983 unsigned32 /*unsigned long int*/ * remainder_ptr,
1984 boolean * overflow_ptr
1987 unsigned long ald = sfi >> (N - 1);
1988 unsigned long alo = als;
1993 unsigned int R1 = 1;
1994 unsigned int DBZ = (als == 0) ? 1 : 0;
1995 unsigned long alt = Q ? ~als : als;
1998 alo = ald + alt + Q;
1999 C = (((alt >> 31) & (ald >> 31))
2000 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2003 R1 = (alo == 0) ? 0 : (R1 & Q);
2004 if ((S ^ (alo>>31)) && !C)
2009 sfi = (sfi << (32-N+1)) | Q;
2010 ald = (alo << 1) | (sfi >> 31);
2012 /* 2nd - N-1th Loop */
2013 for (i = 2; i < N; i++)
2015 alt = Q ? ~als : als;
2016 alo = ald + alt + Q;
2017 C = (((alt >> 31) & (ald >> 31))
2018 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2021 R1 = (alo == 0) ? 0 : (R1 & Q);
2022 if ((S ^ (alo>>31)) && !C && !DBZ)
2027 sfi = (sfi << 1) | Q;
2028 ald = (alo << 1) | (sfi >> 31);
2032 alt = Q ? ~als : als;
2033 alo = ald + alt + Q;
2034 C = (((alt >> 31) & (ald >> 31))
2035 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2038 R1 = (alo == 0) ? 0 : (R1 & Q);
2039 if ((S ^ (alo>>31)) && !C)
2044 * quotient_ptr = (sfi << 1) | Q;
2045 * remainder_ptr = Q ? alo : (alo + als);
2046 * overflow_ptr = DBZ | R1;
2049 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2054 unsigned long int als,
2055 unsigned long int sfi,
2056 signed32 /*signed long int*/ * quotient_ptr,
2057 signed32 /*signed long int*/ * remainder_ptr,
2058 boolean * overflow_ptr
2061 unsigned long ald = (signed long) sfi >> (N - 1);
2062 unsigned long alo = als;
2063 unsigned int SS = als >> 31;
2064 unsigned int SD = sfi >> 31;
2065 unsigned int R1 = 1;
2067 unsigned int DBZ = als == 0 ? 1 : 0;
2068 unsigned int Q = ~(SS ^ SD) & 1;
2072 unsigned long alt = Q ? ~als : als;
2077 alo = ald + alt + Q;
2078 C = (((alt >> 31) & (ald >> 31))
2079 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2081 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2083 sfi = (sfi << (32-N+1)) | Q;
2084 ald = (alo << 1) | (sfi >> 31);
2085 if ((alo >> 31) ^ (ald >> 31))
2090 /* 2nd - N-1th Loop */
2092 for (i = 2; i < N; i++)
2094 alt = Q ? ~als : als;
2095 alo = ald + alt + Q;
2096 C = (((alt >> 31) & (ald >> 31))
2097 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2099 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2101 sfi = (sfi << 1) | Q;
2102 ald = (alo << 1) | (sfi >> 31);
2103 if ((alo >> 31) ^ (ald >> 31))
2110 alt = Q ? ~als : als;
2111 alo = ald + alt + Q;
2112 C = (((alt >> 31) & (ald >> 31))
2113 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2115 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2116 sfi = (sfi << (32-N+1));
2122 alt = Q ? ~als : als;
2123 alo = ald + alt + Q;
2125 R1 = R1 & ((~alo >> 31) ^ SD);
2126 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2128 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2130 ald = sfi = sfi | Q;
2132 OV = DBZ | ((alo == 0) ? 0 : R1);
2134 * remainder_ptr = alo;
2137 if (((alo != 0) && ((SS ^ SD) ^ R1))
2138 || ((alo == 0) && (SS ^ R1)))
2143 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2145 * quotient_ptr = alo;
2146 * overflow_ptr = OV;
2149 /* sdivun imm5, reg1, reg2, reg3 */
2153 unsigned32 /*unsigned long int*/ quotient;
2154 unsigned32 /*unsigned long int*/ remainder;
2155 unsigned long int divide_by;
2156 unsigned long int divide_this;
2157 boolean overflow = false;
2160 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2162 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2164 divide_by = State.regs[ OP[0] ];
2165 divide_this = State.regs[ OP[1] ] << imm5;
2167 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2169 State.regs[ OP[1] ] = quotient;
2170 State.regs[ OP[2] >> 11 ] = remainder;
2172 /* Set condition codes. */
2173 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2175 if (overflow) PSW |= PSW_OV;
2176 if (quotient == 0) PSW |= PSW_Z;
2177 if (quotient & 0x80000000) PSW |= PSW_S;
2179 trace_output (OP_IMM_REG_REG_REG);
2184 /* sdivn imm5, reg1, reg2, reg3 */
2188 signed32 /*signed long int*/ quotient;
2189 signed32 /*signed long int*/ remainder;
2190 signed long int divide_by;
2191 signed long int divide_this;
2192 boolean overflow = false;
2195 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2197 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2199 divide_by = State.regs[ OP[0] ];
2200 divide_this = State.regs[ OP[1] ] << imm5;
2202 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2204 State.regs[ OP[1] ] = quotient;
2205 State.regs[ OP[2] >> 11 ] = remainder;
2207 /* Set condition codes. */
2208 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2210 if (overflow) PSW |= PSW_OV;
2211 if (quotient == 0) PSW |= PSW_Z;
2212 if (quotient < 0) PSW |= PSW_S;
2214 trace_output (OP_IMM_REG_REG_REG);
2219 /* sdivhun imm5, reg1, reg2, reg3 */
2223 unsigned32 /*unsigned long int*/ quotient;
2224 unsigned32 /*unsigned long int*/ remainder;
2225 unsigned long int divide_by;
2226 unsigned long int divide_this;
2227 boolean overflow = false;
2230 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2232 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2234 divide_by = State.regs[ OP[0] ] & 0xffff;
2235 divide_this = State.regs[ OP[1] ] << imm5;
2237 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2239 State.regs[ OP[1] ] = quotient;
2240 State.regs[ OP[2] >> 11 ] = remainder;
2242 /* Set condition codes. */
2243 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2245 if (overflow) PSW |= PSW_OV;
2246 if (quotient == 0) PSW |= PSW_Z;
2247 if (quotient & 0x80000000) PSW |= PSW_S;
2249 trace_output (OP_IMM_REG_REG_REG);
2254 /* sdivhn imm5, reg1, reg2, reg3 */
2258 signed32 /*signed long int*/ quotient;
2259 signed32 /*signed long int*/ remainder;
2260 signed long int divide_by;
2261 signed long int divide_this;
2262 boolean overflow = false;
2265 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2267 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2269 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2270 divide_this = State.regs[ OP[1] ] << imm5;
2272 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2274 State.regs[ OP[1] ] = quotient;
2275 State.regs[ OP[2] >> 11 ] = remainder;
2277 /* Set condition codes. */
2278 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2280 if (overflow) PSW |= PSW_OV;
2281 if (quotient == 0) PSW |= PSW_Z;
2282 if (quotient < 0) PSW |= PSW_S;
2284 trace_output (OP_IMM_REG_REG_REG);
2289 /* divu reg1, reg2, reg3 */
2293 unsigned long int quotient;
2294 unsigned long int remainder;
2295 unsigned long int divide_by;
2296 unsigned long int divide_this;
2297 boolean overflow = false;
2299 trace_input ("divu", OP_REG_REG_REG, 0);
2301 /* Compute the result. */
2303 divide_by = State.regs[ OP[0] ];
2304 divide_this = State.regs[ OP[1] ];
2312 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2313 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2315 /* Set condition codes. */
2316 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2318 if (overflow) PSW |= PSW_OV;
2319 if (quotient == 0) PSW |= PSW_Z;
2320 if (quotient & 0x80000000) PSW |= PSW_S;
2322 trace_output (OP_REG_REG_REG);
2327 /* div reg1, reg2, reg3 */
2331 signed long int quotient;
2332 signed long int remainder;
2333 signed long int divide_by;
2334 signed long int divide_this;
2335 boolean overflow = false;
2337 trace_input ("div", OP_REG_REG_REG, 0);
2339 /* Compute the result. */
2341 divide_by = State.regs[ OP[0] ];
2342 divide_this = State.regs[ OP[1] ];
2344 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2350 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2351 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2353 /* Set condition codes. */
2354 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2356 if (overflow) PSW |= PSW_OV;
2357 if (quotient == 0) PSW |= PSW_Z;
2358 if (quotient < 0) PSW |= PSW_S;
2360 trace_output (OP_REG_REG_REG);
2365 /* divhu reg1, reg2, reg3 */
2369 unsigned long int quotient;
2370 unsigned long int remainder;
2371 unsigned long int divide_by;
2372 unsigned long int divide_this;
2373 boolean overflow = false;
2375 trace_input ("divhu", OP_REG_REG_REG, 0);
2377 /* Compute the result. */
2379 divide_by = State.regs[ OP[0] ] & 0xffff;
2380 divide_this = State.regs[ OP[1] ];
2388 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2389 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2391 /* Set condition codes. */
2392 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2394 if (overflow) PSW |= PSW_OV;
2395 if (quotient == 0) PSW |= PSW_Z;
2396 if (quotient & 0x80000000) PSW |= PSW_S;
2398 trace_output (OP_REG_REG_REG);
2403 /* divh reg1, reg2, reg3 */
2407 signed long int quotient;
2408 signed long int remainder;
2409 signed long int divide_by;
2410 signed long int divide_this;
2411 boolean overflow = false;
2413 trace_input ("divh", OP_REG_REG_REG, 0);
2415 /* Compute the result. */
2417 divide_by = State.regs[ OP[0] ];
2418 divide_this = EXTEND16 (State.regs[ OP[1] ]);
2420 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
2426 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2427 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2429 /* Set condition codes. */
2430 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2432 if (overflow) PSW |= PSW_OV;
2433 if (quotient == 0) PSW |= PSW_Z;
2434 if (quotient < 0) PSW |= PSW_S;
2436 trace_output (OP_REG_REG_REG);
2441 /* mulu imm9, reg2, reg3 */
2445 trace_input ("mulu", OP_IMM_REG_REG, 0);
2447 Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2449 trace_output (OP_IMM_REG_REG);
2454 /* mul imm9, reg2, reg3 */
2458 trace_input ("mul", OP_IMM_REG_REG, 0);
2460 Multiply64 (true, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2462 trace_output (OP_IMM_REG_REG);
2473 trace_input ("ld.hu", OP_LOAD32, 2);
2475 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2478 State.regs[ OP[1] ] = load_mem (adr, 2);
2480 trace_output (OP_LOAD32);
2492 trace_input ("ld.bu", OP_LOAD32, 1);
2494 adr = (State.regs[ OP[0] ]
2495 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2497 State.regs[ OP[1] ] = load_mem (adr, 1);
2499 trace_output (OP_LOAD32);
2504 /* prepare list12, imm5, imm32 */
2510 trace_input ("prepare", OP_PUSHPOP1, 0);
2512 /* Store the registers with lower number registers being placed at higher addresses. */
2513 for (i = 0; i < 12; i++)
2514 if ((OP[3] & (1 << type1_regs[ i ])))
2517 store_mem (SP, 4, State.regs[ 20 + i ]);
2520 SP -= (OP[3] & 0x3e) << 1;
2522 EP = load_mem (PC + 4, 4);
2524 trace_output (OP_PUSHPOP1);
2529 /* prepare list12, imm5, imm16-32 */
2535 trace_input ("prepare", OP_PUSHPOP1, 0);
2537 /* Store the registers with lower number registers being placed at higher addresses. */
2538 for (i = 0; i < 12; i++)
2539 if ((OP[3] & (1 << type1_regs[ i ])))
2542 store_mem (SP, 4, State.regs[ 20 + i ]);
2545 SP -= (OP[3] & 0x3e) << 1;
2547 EP = load_mem (PC + 4, 2) << 16;
2549 trace_output (OP_PUSHPOP1);
2554 /* prepare list12, imm5, imm16 */
2560 trace_input ("prepare", OP_PUSHPOP1, 0);
2562 /* Store the registers with lower number registers being placed at higher addresses. */
2563 for (i = 0; i < 12; i++)
2564 if ((OP[3] & (1 << type1_regs[ i ])))
2567 store_mem (SP, 4, State.regs[ 20 + i ]);
2570 SP -= (OP[3] & 0x3e) << 1;
2572 EP = EXTEND16 (load_mem (PC + 4, 2));
2574 trace_output (OP_PUSHPOP1);
2579 /* prepare list12, imm5, sp */
2585 trace_input ("prepare", OP_PUSHPOP1, 0);
2587 /* Store the registers with lower number registers being placed at higher addresses. */
2588 for (i = 0; i < 12; i++)
2589 if ((OP[3] & (1 << type1_regs[ i ])))
2592 store_mem (SP, 4, State.regs[ 20 + i ]);
2595 SP -= (OP[3] & 0x3e) << 1;
2599 trace_output (OP_PUSHPOP1);
2604 /* mul reg1, reg2, reg3 */
2608 trace_input ("mul", OP_REG_REG_REG, 0);
2610 Multiply64 (true, State.regs[ OP[0] ]);
2612 trace_output (OP_REG_REG_REG);
2623 trace_input ("popmh", OP_PUSHPOP2, 0);
2625 if (OP[3] & (1 << 19))
2627 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2629 FEPSW = load_mem ( SP & ~ 3, 4);
2630 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2634 EIPSW = load_mem ( SP & ~ 3, 4);
2635 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2641 /* Load the registers with lower number registers being retrieved from higher addresses. */
2643 if ((OP[3] & (1 << type2_regs[ i ])))
2645 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2649 trace_output (OP_PUSHPOP2);
2660 trace_input ("popml", OP_PUSHPOP3, 0);
2662 if (OP[3] & (1 << 19))
2664 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2666 FEPSW = load_mem ( SP & ~ 3, 4);
2667 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2671 EIPSW = load_mem ( SP & ~ 3, 4);
2672 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2678 if (OP[3] & (1 << 3))
2680 PSW = load_mem (SP & ~ 3, 4);
2684 /* Load the registers with lower number registers being retrieved from higher addresses. */
2686 if ((OP[3] & (1 << type3_regs[ i ])))
2688 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2692 trace_output (OP_PUSHPOP2);
2703 trace_input ("pushmh", OP_PUSHPOP2, 0);
2705 /* Store the registers with lower number registers being placed at higher addresses. */
2706 for (i = 0; i < 16; i++)
2707 if ((OP[3] & (1 << type2_regs[ i ])))
2710 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2713 if (OP[3] & (1 << 19))
2717 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2719 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2720 store_mem ( SP & ~ 3, 4, FEPSW);
2724 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2725 store_mem ( SP & ~ 3, 4, EIPSW);
2729 trace_output (OP_PUSHPOP2);