27 #include "targ-vals.h"
29 #include "libiberty.h"
32 #if !defined(__GO32__) && !defined(_WIN32)
34 #include <sys/times.h>
38 /* This is an array of the bit positions of registers r20 .. r31 in
39 that order in a prepare/dispose instruction. */
40 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
41 /* This is an array of the bit positions of registers r16 .. r31 in
42 that order in a push/pop instruction. */
43 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
44 /* This is an array of the bit positions of registers r1 .. r15 in
45 that order in a push/pop instruction. */
46 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
49 #ifndef SIZE_INSTRUCTION
50 #define SIZE_INSTRUCTION 18
54 #define SIZE_VALUES 11
58 unsigned32 trace_values[3];
61 const char *trace_name;
66 trace_input (name, type, size)
72 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
77 trace_module = TRACE_ALU_IDX;
90 trace_values[0] = State.regs[OP[0]];
97 trace_values[0] = State.regs[OP[1]];
98 trace_values[1] = State.regs[OP[0]];
104 trace_values[0] = SEXT5 (OP[0]);
105 trace_values[1] = OP[1];
106 trace_num_values = 2;
109 case OP_IMM_REG_MOVE:
110 trace_values[0] = SEXT5 (OP[0]);
111 trace_num_values = 1;
115 trace_values[0] = State.pc;
116 trace_values[1] = SEXT9 (OP[0]);
117 trace_values[2] = PSW;
118 trace_num_values = 3;
122 trace_values[0] = OP[1] * size;
123 trace_values[1] = State.regs[30];
124 trace_num_values = 2;
128 trace_values[0] = State.regs[OP[0]];
129 trace_values[1] = OP[1] * size;
130 trace_values[2] = State.regs[30];
131 trace_num_values = 3;
135 trace_values[0] = EXTEND16 (OP[2]);
136 trace_values[1] = State.regs[OP[0]];
137 trace_num_values = 2;
141 trace_values[0] = State.regs[OP[1]];
142 trace_values[1] = EXTEND16 (OP[2]);
143 trace_values[2] = State.regs[OP[0]];
144 trace_num_values = 3;
148 trace_values[0] = SEXT22 (OP[0]);
149 trace_values[1] = State.pc;
150 trace_num_values = 2;
154 trace_values[0] = EXTEND16 (OP[0]) << size;
155 trace_values[1] = State.regs[OP[1]];
156 trace_num_values = 2;
159 case OP_IMM16_REG_REG:
160 trace_values[0] = EXTEND16 (OP[2]) << size;
161 trace_values[1] = State.regs[OP[1]];
162 trace_num_values = 2;
165 case OP_UIMM_REG_REG:
166 trace_values[0] = (OP[0] & 0xffff) << size;
167 trace_values[1] = State.regs[OP[1]];
168 trace_num_values = 2;
171 case OP_UIMM16_REG_REG:
172 trace_values[0] = (OP[2]) << size;
173 trace_values[1] = State.regs[OP[1]];
174 trace_num_values = 2;
178 trace_num_values = 0;
182 trace_values[0] = PSW;
183 trace_num_values = 1;
187 trace_num_values = 0;
191 trace_values[0] = State.regs[OP[0]];
192 trace_num_values = 1;
196 trace_values[0] = State.sregs[OP[1]];
197 trace_num_values = 1;
203 trace_result (int has_result, unsigned32 result)
211 /* write out the values saved during the trace_input call */
214 for (i = 0; i < trace_num_values; i++)
216 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "",
217 (long) trace_values[i]);
218 chp = strchr (chp, '\0');
222 sprintf (chp, "%*s", SIZE_VALUES, "");
223 chp = strchr (chp, '\0');
227 /* append any result to the end of the buffer */
229 sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
231 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf);
235 trace_output (result)
236 enum op_types result;
238 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
260 trace_result (1, State.regs[OP[0]]);
264 case OP_REG_REG_MOVE:
266 case OP_IMM_REG_MOVE:
269 trace_result (1, State.regs[OP[1]]);
273 case OP_UIMM_REG_REG:
274 case OP_IMM16_REG_REG:
275 case OP_UIMM16_REG_REG:
276 trace_result (1, State.regs[OP[1]]);
281 trace_result (1, State.regs[OP[1]]);
287 trace_result (1, State.sregs[OP[1]]);
294 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
296 condition_met (unsigned code)
298 unsigned int psw = PSW;
302 case 0x0: return ((psw & PSW_OV) != 0);
303 case 0x1: return ((psw & PSW_CY) != 0);
304 case 0x2: return ((psw & PSW_Z) != 0);
305 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
306 case 0x4: return ((psw & PSW_S) != 0);
307 /*case 0x5: return 1;*/
308 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
309 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
310 case 0x8: return ((psw & PSW_OV) == 0);
311 case 0x9: return ((psw & PSW_CY) == 0);
312 case 0xa: return ((psw & PSW_Z) == 0);
313 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
314 case 0xc: return ((psw & PSW_S) == 0);
315 case 0xd: return ((psw & PSW_SAT) != 0);
316 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
317 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
324 Add32 (unsigned long a1, unsigned long a2, int * carry)
326 unsigned long result = (a1 + a2);
328 * carry = (result < a1);
334 Multiply64 (int sign, unsigned long op0)
345 op1 = State.regs[ OP[1] ];
349 /* Compute sign of result and adjust operands if necessary. */
351 sign = (op0 ^ op1) & 0x80000000;
353 if (((signed long) op0) < 0)
356 if (((signed long) op1) < 0)
360 /* We can split the 32x32 into four 16x16 operations. This ensures
361 that we do not lose precision on 32bit only hosts: */
362 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
363 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
364 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
365 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
367 /* We now need to add all of these results together, taking care
368 to propogate the carries from the additions: */
369 RdLo = Add32 (lo, (mid1 << 16), & carry);
371 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
372 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
376 /* Negate result if necessary. */
380 if (RdLo == 0xFFFFFFFF)
389 /* Don't store into register 0. */
391 State.regs[ OP[1] ] = RdLo;
393 State.regs[ OP[2] >> 11 ] = RdHi;
399 /* Read a null terminated string from memory, return in a buffer */
407 while (sim_core_read_1 (STATE_CPU (sd, 0),
408 PC, read_map, addr + nr) != 0)
410 buf = NZALLOC (char, nr + 1);
411 sim_read (simulator, addr, buf, nr);
415 /* Read a null terminated argument vector from memory, return in a
418 fetch_argv (sd, addr)
424 char **buf = xmalloc (max_nr * sizeof (char*));
427 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
428 PC, read_map, addr + nr * 4);
430 buf[nr] = fetch_str (sd, a);
432 if (nr == max_nr - 1)
435 buf = xrealloc (buf, max_nr * sizeof (char*));
447 trace_input ("sst.b", OP_STORE16, 1);
449 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
451 trace_output (OP_STORE16);
460 trace_input ("sst.h", OP_STORE16, 2);
462 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
464 trace_output (OP_STORE16);
473 trace_input ("sst.w", OP_STORE16, 4);
475 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
477 trace_output (OP_STORE16);
488 trace_input ("ld.b", OP_LOAD32, 1);
490 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
492 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
494 trace_output (OP_LOAD32);
505 trace_input ("ld.h", OP_LOAD32, 2);
507 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
510 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
512 trace_output (OP_LOAD32);
523 trace_input ("ld.w", OP_LOAD32, 4);
525 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
528 State.regs[ OP[1] ] = load_mem (adr, 4);
530 trace_output (OP_LOAD32);
539 trace_input ("st.b", OP_STORE32, 1);
541 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
543 trace_output (OP_STORE32);
554 trace_input ("st.h", OP_STORE32, 2);
556 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
559 store_mem (adr, 2, State.regs[ OP[1] ]);
561 trace_output (OP_STORE32);
572 trace_input ("st.w", OP_STORE32, 4);
574 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
577 store_mem (adr, 4, State.regs[ OP[1] ]);
579 trace_output (OP_STORE32);
588 unsigned int op0, op1, result, z, s, cy, ov;
590 trace_input ("add", OP_REG_REG, 0);
592 /* Compute the result. */
594 op0 = State.regs[ OP[0] ];
595 op1 = State.regs[ OP[1] ];
599 /* Compute the condition codes. */
601 s = (result & 0x80000000);
602 cy = (result < op0 || result < op1);
603 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
604 && (op0 & 0x80000000) != (result & 0x80000000));
606 /* Store the result and condition codes. */
607 State.regs[OP[1]] = result;
608 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
609 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
610 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
611 trace_output (OP_REG_REG);
616 /* add sign_extend(imm5), reg */
620 unsigned int op0, op1, result, z, s, cy, ov;
623 trace_input ("add", OP_IMM_REG, 0);
625 /* Compute the result. */
626 temp = SEXT5 (OP[0]);
628 op1 = State.regs[OP[1]];
631 /* Compute the condition codes. */
633 s = (result & 0x80000000);
634 cy = (result < op0 || result < op1);
635 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
636 && (op0 & 0x80000000) != (result & 0x80000000));
638 /* Store the result and condition codes. */
639 State.regs[OP[1]] = result;
640 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
641 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
642 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
643 trace_output (OP_IMM_REG);
648 /* addi sign_extend(imm16), reg, reg */
652 unsigned int op0, op1, result, z, s, cy, ov;
654 trace_input ("addi", OP_IMM16_REG_REG, 0);
656 /* Compute the result. */
658 op0 = EXTEND16 (OP[2]);
659 op1 = State.regs[ OP[0] ];
662 /* Compute the condition codes. */
664 s = (result & 0x80000000);
665 cy = (result < op0 || result < op1);
666 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
667 && (op0 & 0x80000000) != (result & 0x80000000));
669 /* Store the result and condition codes. */
670 State.regs[OP[1]] = result;
671 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
672 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
673 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
674 trace_output (OP_IMM16_REG_REG);
683 unsigned int op0, op1, result, z, s, cy, ov;
685 trace_input ("sub", OP_REG_REG, 0);
686 /* Compute the result. */
687 op0 = State.regs[ OP[0] ];
688 op1 = State.regs[ OP[1] ];
691 /* Compute the condition codes. */
693 s = (result & 0x80000000);
695 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
696 && (op1 & 0x80000000) != (result & 0x80000000));
698 /* Store the result and condition codes. */
699 State.regs[OP[1]] = result;
700 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
701 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
702 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
703 trace_output (OP_REG_REG);
708 /* subr reg1, reg2 */
712 unsigned int op0, op1, result, z, s, cy, ov;
714 trace_input ("subr", OP_REG_REG, 0);
715 /* Compute the result. */
716 op0 = State.regs[ OP[0] ];
717 op1 = State.regs[ OP[1] ];
720 /* Compute the condition codes. */
722 s = (result & 0x80000000);
724 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
725 && (op0 & 0x80000000) != (result & 0x80000000));
727 /* Store the result and condition codes. */
728 State.regs[OP[1]] = result;
729 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
730 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
731 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
732 trace_output (OP_REG_REG);
741 trace_input ("mulh", OP_REG_REG, 0);
743 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
745 trace_output (OP_REG_REG);
750 /* mulh sign_extend(imm5), reg2 */
754 trace_input ("mulh", OP_IMM_REG, 0);
756 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
758 trace_output (OP_IMM_REG);
763 /* mulhi imm16, reg1, reg2 */
767 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
769 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
771 trace_output (OP_IMM16_REG_REG);
780 unsigned int op0, op1, result, z, s, cy, ov;
782 trace_input ("cmp", OP_REG_REG_CMP, 0);
783 /* Compute the result. */
784 op0 = State.regs[ OP[0] ];
785 op1 = State.regs[ OP[1] ];
788 /* Compute the condition codes. */
790 s = (result & 0x80000000);
792 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
793 && (op1 & 0x80000000) != (result & 0x80000000));
795 /* Set condition codes. */
796 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
797 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
798 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
799 trace_output (OP_REG_REG_CMP);
804 /* cmp sign_extend(imm5), reg */
808 unsigned int op0, op1, result, z, s, cy, ov;
811 /* Compute the result. */
812 trace_input ("cmp", OP_IMM_REG_CMP, 0);
813 temp = SEXT5 (OP[0]);
815 op1 = State.regs[OP[1]];
818 /* Compute the condition codes. */
820 s = (result & 0x80000000);
822 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
823 && (op1 & 0x80000000) != (result & 0x80000000));
825 /* Set condition codes. */
826 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
827 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
828 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
829 trace_output (OP_IMM_REG_CMP);
838 trace_input ("setf", OP_EX1, 0);
840 State.regs[ OP[1] ] = condition_met (OP[0]);
842 trace_output (OP_EX1);
851 unsigned int op0, op1, result, z, s, cy, ov, sat;
853 trace_input ("satadd", OP_REG_REG, 0);
854 /* Compute the result. */
855 op0 = State.regs[ OP[0] ];
856 op1 = State.regs[ OP[1] ];
859 /* Compute the condition codes. */
861 s = (result & 0x80000000);
862 cy = (result < op0 || result < op1);
863 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
864 && (op0 & 0x80000000) != (result & 0x80000000));
867 /* Handle saturated results. */
870 /* An overflow that results in a negative result implies that we
871 became too positive. */
877 /* Any other overflow must have thus been too negative. */
883 /* Store the result and condition codes. */
884 State.regs[OP[1]] = result;
885 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
886 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
887 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
888 | (sat ? PSW_SAT : 0));
890 trace_output (OP_REG_REG);
895 /* satadd sign_extend(imm5), reg */
899 unsigned int op0, op1, result, z, s, cy, ov, sat;
903 trace_input ("satadd", OP_IMM_REG, 0);
905 /* Compute the result. */
906 temp = SEXT5 (OP[0]);
908 op1 = State.regs[OP[1]];
911 /* Compute the condition codes. */
913 s = (result & 0x80000000);
914 cy = (result < op0 || result < op1);
915 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
916 && (op0 & 0x80000000) != (result & 0x80000000));
919 /* Handle saturated results. */
922 /* An overflow that results in a negative result implies that we
923 became too positive. */
929 /* Any other overflow must have thus been too negative. */
935 /* Store the result and condition codes. */
936 State.regs[OP[1]] = result;
937 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
938 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
939 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
940 | (sat ? PSW_SAT : 0));
941 trace_output (OP_IMM_REG);
946 /* satsub reg1, reg2 */
950 unsigned int op0, op1, result, z, s, cy, ov, sat;
952 trace_input ("satsub", OP_REG_REG, 0);
954 /* Compute the result. */
955 op0 = State.regs[ OP[0] ];
956 op1 = State.regs[ OP[1] ];
959 /* Compute the condition codes. */
961 s = (result & 0x80000000);
963 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
964 && (op1 & 0x80000000) != (result & 0x80000000));
967 /* Handle saturated results. */
970 /* An overflow that results in a negative result implies that we
971 became too positive. */
977 /* Any other overflow must have thus been too negative. */
983 /* Store the result and condition codes. */
984 State.regs[OP[1]] = result;
985 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
986 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
987 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
988 | (sat ? PSW_SAT : 0));
990 trace_output (OP_REG_REG);
994 /* satsubi sign_extend(imm16), reg */
998 unsigned int op0, op1, result, z, s, cy, ov, sat;
1001 trace_input ("satsubi", OP_IMM_REG, 0);
1003 /* Compute the result. */
1004 temp = EXTEND16 (OP[2]);
1006 op1 = State.regs[ OP[0] ];
1009 /* Compute the condition codes. */
1011 s = (result & 0x80000000);
1013 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1014 && (op1 & 0x80000000) != (result & 0x80000000));
1017 /* Handle saturated results. */
1020 /* An overflow that results in a negative result implies that we
1021 became too positive. */
1022 result = 0x7fffffff;
1027 /* Any other overflow must have thus been too negative. */
1028 result = 0x80000000;
1033 /* Store the result and condition codes. */
1034 State.regs[OP[1]] = result;
1035 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1036 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1037 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1038 | (sat ? PSW_SAT : 0));
1040 trace_output (OP_IMM_REG);
1045 /* satsubr reg,reg */
1049 unsigned int op0, op1, result, z, s, cy, ov, sat;
1051 trace_input ("satsubr", OP_REG_REG, 0);
1053 /* Compute the result. */
1054 op0 = State.regs[ OP[0] ];
1055 op1 = State.regs[ OP[1] ];
1058 /* Compute the condition codes. */
1060 s = (result & 0x80000000);
1062 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1063 && (op0 & 0x80000000) != (result & 0x80000000));
1066 /* Handle saturated results. */
1069 /* An overflow that results in a negative result implies that we
1070 became too positive. */
1071 result = 0x7fffffff;
1076 /* Any other overflow must have thus been too negative. */
1077 result = 0x80000000;
1082 /* Store the result and condition codes. */
1083 State.regs[OP[1]] = result;
1084 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1085 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1086 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1087 | (sat ? PSW_SAT : 0));
1089 trace_output (OP_REG_REG);
1098 unsigned int op0, op1, result, z, s;
1100 trace_input ("tst", OP_REG_REG_CMP, 0);
1102 /* Compute the result. */
1103 op0 = State.regs[ OP[0] ];
1104 op1 = State.regs[ OP[1] ];
1107 /* Compute the condition codes. */
1109 s = (result & 0x80000000);
1111 /* Store the condition codes. */
1112 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1113 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1114 trace_output (OP_REG_REG_CMP);
1119 /* mov sign_extend(imm5), reg */
1123 int value = SEXT5 (OP[0]);
1125 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1127 State.regs[ OP[1] ] = value;
1129 trace_output (OP_IMM_REG_MOVE);
1134 /* movhi imm16, reg, reg */
1138 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1140 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1142 trace_output (OP_UIMM16_REG_REG);
1147 /* sar zero_extend(imm5),reg1 */
1151 unsigned int op0, op1, result, z, s, cy;
1153 trace_input ("sar", OP_IMM_REG, 0);
1155 op1 = State.regs[ OP[1] ];
1156 result = (signed)op1 >> op0;
1158 /* Compute the condition codes. */
1160 s = (result & 0x80000000);
1161 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1163 /* Store the result and condition codes. */
1164 State.regs[ OP[1] ] = result;
1165 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1166 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1167 | (cy ? PSW_CY : 0));
1168 trace_output (OP_IMM_REG);
1173 /* sar reg1, reg2 */
1177 unsigned int op0, op1, result, z, s, cy;
1179 trace_input ("sar", OP_REG_REG, 0);
1181 op0 = State.regs[ OP[0] ] & 0x1f;
1182 op1 = State.regs[ OP[1] ];
1183 result = (signed)op1 >> op0;
1185 /* Compute the condition codes. */
1187 s = (result & 0x80000000);
1188 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1190 /* Store the result and condition codes. */
1191 State.regs[OP[1]] = result;
1192 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1193 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1194 | (cy ? PSW_CY : 0));
1195 trace_output (OP_REG_REG);
1200 /* shl zero_extend(imm5),reg1 */
1204 unsigned int op0, op1, result, z, s, cy;
1206 trace_input ("shl", OP_IMM_REG, 0);
1208 op1 = State.regs[ OP[1] ];
1209 result = op1 << op0;
1211 /* Compute the condition codes. */
1213 s = (result & 0x80000000);
1214 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1216 /* Store the result and condition codes. */
1217 State.regs[OP[1]] = result;
1218 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1219 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1220 | (cy ? PSW_CY : 0));
1221 trace_output (OP_IMM_REG);
1226 /* shl reg1, reg2 */
1230 unsigned int op0, op1, result, z, s, cy;
1232 trace_input ("shl", OP_REG_REG, 0);
1233 op0 = State.regs[ OP[0] ] & 0x1f;
1234 op1 = State.regs[ OP[1] ];
1235 result = op1 << op0;
1237 /* Compute the condition codes. */
1239 s = (result & 0x80000000);
1240 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1242 /* Store the result and condition codes. */
1243 State.regs[OP[1]] = result;
1244 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1245 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1246 | (cy ? PSW_CY : 0));
1247 trace_output (OP_REG_REG);
1252 /* shr zero_extend(imm5),reg1 */
1256 unsigned int op0, op1, result, z, s, cy;
1258 trace_input ("shr", OP_IMM_REG, 0);
1260 op1 = State.regs[ OP[1] ];
1261 result = op1 >> op0;
1263 /* Compute the condition codes. */
1265 s = (result & 0x80000000);
1266 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1268 /* Store the result and condition codes. */
1269 State.regs[OP[1]] = result;
1270 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1271 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1272 | (cy ? PSW_CY : 0));
1273 trace_output (OP_IMM_REG);
1278 /* shr reg1, reg2 */
1282 unsigned int op0, op1, result, z, s, cy;
1284 trace_input ("shr", OP_REG_REG, 0);
1285 op0 = State.regs[ OP[0] ] & 0x1f;
1286 op1 = State.regs[ OP[1] ];
1287 result = op1 >> op0;
1289 /* Compute the condition codes. */
1291 s = (result & 0x80000000);
1292 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1294 /* Store the result and condition codes. */
1295 State.regs[OP[1]] = result;
1296 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1297 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1298 | (cy ? PSW_CY : 0));
1299 trace_output (OP_REG_REG);
1308 unsigned int op0, op1, result, z, s;
1310 trace_input ("or", OP_REG_REG, 0);
1312 /* Compute the result. */
1313 op0 = State.regs[ OP[0] ];
1314 op1 = State.regs[ OP[1] ];
1317 /* Compute the condition codes. */
1319 s = (result & 0x80000000);
1321 /* Store the result and condition codes. */
1322 State.regs[OP[1]] = result;
1323 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1324 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1325 trace_output (OP_REG_REG);
1330 /* ori zero_extend(imm16), reg, reg */
1334 unsigned int op0, op1, result, z, s;
1336 trace_input ("ori", OP_UIMM16_REG_REG, 0);
1338 op1 = State.regs[ OP[0] ];
1341 /* Compute the condition codes. */
1343 s = (result & 0x80000000);
1345 /* Store the result and condition codes. */
1346 State.regs[OP[1]] = result;
1347 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1348 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1349 trace_output (OP_UIMM16_REG_REG);
1358 unsigned int op0, op1, result, z, s;
1360 trace_input ("and", OP_REG_REG, 0);
1362 /* Compute the result. */
1363 op0 = State.regs[ OP[0] ];
1364 op1 = State.regs[ OP[1] ];
1367 /* Compute the condition codes. */
1369 s = (result & 0x80000000);
1371 /* Store the result and condition codes. */
1372 State.regs[OP[1]] = result;
1373 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1374 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1375 trace_output (OP_REG_REG);
1380 /* andi zero_extend(imm16), reg, reg */
1384 unsigned int result, z;
1386 trace_input ("andi", OP_UIMM16_REG_REG, 0);
1388 result = OP[2] & State.regs[ OP[0] ];
1390 /* Compute the condition codes. */
1393 /* Store the result and condition codes. */
1394 State.regs[ OP[1] ] = result;
1396 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1397 PSW |= (z ? PSW_Z : 0);
1399 trace_output (OP_UIMM16_REG_REG);
1408 unsigned int op0, op1, result, z, s;
1410 trace_input ("xor", OP_REG_REG, 0);
1412 /* Compute the result. */
1413 op0 = State.regs[ OP[0] ];
1414 op1 = State.regs[ OP[1] ];
1417 /* Compute the condition codes. */
1419 s = (result & 0x80000000);
1421 /* Store the result and condition codes. */
1422 State.regs[OP[1]] = result;
1423 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1424 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1425 trace_output (OP_REG_REG);
1430 /* xori zero_extend(imm16), reg, reg */
1434 unsigned int op0, op1, result, z, s;
1436 trace_input ("xori", OP_UIMM16_REG_REG, 0);
1438 op1 = State.regs[ OP[0] ];
1441 /* Compute the condition codes. */
1443 s = (result & 0x80000000);
1445 /* Store the result and condition codes. */
1446 State.regs[OP[1]] = result;
1447 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1448 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1449 trace_output (OP_UIMM16_REG_REG);
1454 /* not reg1, reg2 */
1458 unsigned int op0, result, z, s;
1460 trace_input ("not", OP_REG_REG_MOVE, 0);
1461 /* Compute the result. */
1462 op0 = State.regs[ OP[0] ];
1465 /* Compute the condition codes. */
1467 s = (result & 0x80000000);
1469 /* Store the result and condition codes. */
1470 State.regs[OP[1]] = result;
1471 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1472 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1473 trace_output (OP_REG_REG_MOVE);
1482 unsigned int op0, op1, op2;
1485 trace_input ("set1", OP_BIT, 0);
1486 op0 = State.regs[ OP[0] ];
1488 temp = EXTEND16 (OP[2]);
1490 temp = load_mem (op0 + op2, 1);
1492 if ((temp & (1 << op1)) == 0)
1495 store_mem (op0 + op2, 1, temp);
1496 trace_output (OP_BIT);
1505 unsigned int op0, op1, op2;
1508 trace_input ("not1", OP_BIT, 0);
1509 op0 = State.regs[ OP[0] ];
1511 temp = EXTEND16 (OP[2]);
1513 temp = load_mem (op0 + op2, 1);
1515 if ((temp & (1 << op1)) == 0)
1518 store_mem (op0 + op2, 1, temp);
1519 trace_output (OP_BIT);
1528 unsigned int op0, op1, op2;
1531 trace_input ("clr1", OP_BIT, 0);
1532 op0 = State.regs[ OP[0] ];
1534 temp = EXTEND16 (OP[2]);
1536 temp = load_mem (op0 + op2, 1);
1538 if ((temp & (1 << op1)) == 0)
1540 temp &= ~(1 << op1);
1541 store_mem (op0 + op2, 1, temp);
1542 trace_output (OP_BIT);
1551 unsigned int op0, op1, op2;
1554 trace_input ("tst1", OP_BIT, 0);
1555 op0 = State.regs[ OP[0] ];
1557 temp = EXTEND16 (OP[2]);
1559 temp = load_mem (op0 + op2, 1);
1561 if ((temp & (1 << op1)) == 0)
1563 trace_output (OP_BIT);
1572 trace_input ("di", OP_NONE, 0);
1574 trace_output (OP_NONE);
1583 trace_input ("ei", OP_NONE, 0);
1585 trace_output (OP_NONE);
1594 trace_input ("halt", OP_NONE, 0);
1595 /* FIXME this should put processor into a mode where NMI still handled */
1596 trace_output (OP_NONE);
1597 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1598 sim_stopped, SIM_SIGTRAP);
1606 trace_input ("trap", OP_TRAP, 0);
1607 trace_output (OP_TRAP);
1609 /* Trap 31 is used for simulating OS I/O functions */
1613 int save_errno = errno;
1616 /* Registers passed to trap 0 */
1618 #define FUNC State.regs[6] /* function number, return value */
1619 #define PARM1 State.regs[7] /* optional parm 1 */
1620 #define PARM2 State.regs[8] /* optional parm 2 */
1621 #define PARM3 State.regs[9] /* optional parm 3 */
1623 /* Registers set by trap 0 */
1625 #define RETVAL State.regs[10] /* return value */
1626 #define RETERR State.regs[11] /* return error code */
1628 /* Turn a pointer in a register into a pointer into real memory. */
1630 #define MEMPTR(x) (map (x))
1638 #ifdef TARGET_SYS_fork
1639 case TARGET_SYS_fork:
1647 #ifdef TARGET_SYS_execv
1648 case TARGET_SYS_execve:
1650 char *path = fetch_str (simulator, PARM1);
1651 char **argv = fetch_argv (simulator, PARM2);
1652 char **envp = fetch_argv (simulator, PARM3);
1653 RETVAL = execve (path, argv, envp);
1664 #ifdef TARGET_SYS_execv
1665 case TARGET_SYS_execv:
1667 char *path = fetch_str (simulator, PARM1);
1668 char **argv = fetch_argv (simulator, PARM2);
1669 RETVAL = execv (path, argv);
1679 #ifdef TARGET_SYS_pipe
1680 case TARGET_SYS_pipe:
1686 RETVAL = pipe (host_fd);
1687 SW (buf, host_fd[0]);
1688 buf += sizeof(uint16);
1689 SW (buf, host_fd[1]);
1697 #ifdef TARGET_SYS_wait
1698 case TARGET_SYS_wait:
1702 RETVAL = wait (&status);
1710 #ifdef TARGET_SYS_read
1711 case TARGET_SYS_read:
1713 char *buf = zalloc (PARM3);
1714 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1715 sim_write (simulator, PARM2, buf, PARM3);
1717 if ((int) RETVAL < 0)
1718 RETERR = sim_io_get_errno (simulator);
1723 #ifdef TARGET_SYS_write
1724 case TARGET_SYS_write:
1726 char *buf = zalloc (PARM3);
1727 sim_read (simulator, PARM2, buf, PARM3);
1729 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1731 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1733 if ((int) RETVAL < 0)
1734 RETERR = sim_io_get_errno (simulator);
1739 #ifdef TARGET_SYS_lseek
1740 case TARGET_SYS_lseek:
1741 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1742 if ((int) RETVAL < 0)
1743 RETERR = sim_io_get_errno (simulator);
1747 #ifdef TARGET_SYS_close
1748 case TARGET_SYS_close:
1749 RETVAL = sim_io_close (simulator, PARM1);
1750 if ((int) RETVAL < 0)
1751 RETERR = sim_io_get_errno (simulator);
1755 #ifdef TARGET_SYS_open
1756 case TARGET_SYS_open:
1758 char *buf = fetch_str (simulator, PARM1);
1759 RETVAL = sim_io_open (simulator, buf, PARM2);
1761 if ((int) RETVAL < 0)
1762 RETERR = sim_io_get_errno (simulator);
1767 #ifdef TARGET_SYS_exit
1768 case TARGET_SYS_exit:
1769 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1770 /* get signal encoded by kill */
1771 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1772 sim_signalled, PARM1 & 0xffff);
1773 else if (PARM1 == 0xdead)
1775 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1776 sim_stopped, SIM_SIGABRT);
1778 /* PARM1 has exit status */
1779 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1784 #ifdef TARGET_SYS_stat
1785 case TARGET_SYS_stat: /* added at hmsi */
1786 /* stat system call */
1788 struct stat host_stat;
1790 char *path = fetch_str (simulator, PARM1);
1792 RETVAL = sim_io_stat (simulator, path, &host_stat);
1797 /* Just wild-assed guesses. */
1798 store_mem (buf, 2, host_stat.st_dev);
1799 store_mem (buf + 2, 2, host_stat.st_ino);
1800 store_mem (buf + 4, 4, host_stat.st_mode);
1801 store_mem (buf + 8, 2, host_stat.st_nlink);
1802 store_mem (buf + 10, 2, host_stat.st_uid);
1803 store_mem (buf + 12, 2, host_stat.st_gid);
1804 store_mem (buf + 14, 2, host_stat.st_rdev);
1805 store_mem (buf + 16, 4, host_stat.st_size);
1806 store_mem (buf + 20, 4, host_stat.st_atime);
1807 store_mem (buf + 28, 4, host_stat.st_mtime);
1808 store_mem (buf + 36, 4, host_stat.st_ctime);
1810 if ((int) RETVAL < 0)
1811 RETERR = sim_io_get_errno (simulator);
1816 #ifdef TARGET_SYS_fstat
1817 case TARGET_SYS_fstat:
1818 /* fstat system call */
1820 struct stat host_stat;
1823 RETVAL = sim_io_fstat (simulator, PARM1, &host_stat);
1827 /* Just wild-assed guesses. */
1828 store_mem (buf, 2, host_stat.st_dev);
1829 store_mem (buf + 2, 2, host_stat.st_ino);
1830 store_mem (buf + 4, 4, host_stat.st_mode);
1831 store_mem (buf + 8, 2, host_stat.st_nlink);
1832 store_mem (buf + 10, 2, host_stat.st_uid);
1833 store_mem (buf + 12, 2, host_stat.st_gid);
1834 store_mem (buf + 14, 2, host_stat.st_rdev);
1835 store_mem (buf + 16, 4, host_stat.st_size);
1836 store_mem (buf + 20, 4, host_stat.st_atime);
1837 store_mem (buf + 28, 4, host_stat.st_mtime);
1838 store_mem (buf + 36, 4, host_stat.st_ctime);
1840 if ((int) RETVAL < 0)
1841 RETERR = sim_io_get_errno (simulator);
1846 #ifdef TARGET_SYS_rename
1847 case TARGET_SYS_rename:
1849 char *oldpath = fetch_str (simulator, PARM1);
1850 char *newpath = fetch_str (simulator, PARM2);
1851 RETVAL = sim_io_rename (simulator, oldpath, newpath);
1854 if ((int) RETVAL < 0)
1855 RETERR = sim_io_get_errno (simulator);
1860 #ifdef TARGET_SYS_unlink
1861 case TARGET_SYS_unlink:
1863 char *path = fetch_str (simulator, PARM1);
1864 RETVAL = sim_io_unlink (simulator, path);
1866 if ((int) RETVAL < 0)
1867 RETERR = sim_io_get_errno (simulator);
1873 #ifdef TARGET_SYS_chown
1874 case TARGET_SYS_chown:
1876 char *path = fetch_str (simulator, PARM1);
1877 RETVAL = chown (path, PARM2, PARM3);
1886 #ifdef TARGET_SYS_chmod
1887 case TARGET_SYS_chmod:
1889 char *path = fetch_str (simulator, PARM1);
1890 RETVAL = chmod (path, PARM2);
1898 #ifdef TARGET_SYS_time
1900 case TARGET_SYS_time:
1903 RETVAL = time (&now);
1904 store_mem (PARM1, 4, now);
1911 #if !defined(__GO32__) && !defined(_WIN32)
1912 #ifdef TARGET_SYS_times
1913 case TARGET_SYS_times:
1916 RETVAL = times (&tms);
1917 store_mem (PARM1, 4, tms.tms_utime);
1918 store_mem (PARM1 + 4, 4, tms.tms_stime);
1919 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1920 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1927 #ifdef TARGET_SYS_gettimeofday
1928 #if !defined(__GO32__) && !defined(_WIN32)
1929 case TARGET_SYS_gettimeofday:
1933 RETVAL = gettimeofday (&t, &tz);
1934 store_mem (PARM1, 4, t.tv_sec);
1935 store_mem (PARM1 + 4, 4, t.tv_usec);
1936 store_mem (PARM2, 4, tz.tz_minuteswest);
1937 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1944 #ifdef TARGET_SYS_utime
1946 case TARGET_SYS_utime:
1948 /* Cast the second argument to void *, to avoid type mismatch
1949 if a prototype is present. */
1950 sim_io_error (simulator, "Utime not supported");
1951 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1965 { /* Trap 0 -> 30 */
1970 ECR |= 0x40 + OP[0];
1971 /* Flag that we are now doing exception processing. */
1972 PSW |= PSW_EP | PSW_ID;
1973 PC = (OP[0] < 0x10) ? 0x40 : 0x50;
1979 /* tst1 reg2, [reg1] */
1985 trace_input ("tst1", OP_BIT, 1);
1987 temp = load_mem (State.regs[ OP[0] ], 1);
1990 if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0)
1993 trace_output (OP_BIT);
1998 /* mulu reg1, reg2, reg3 */
2002 trace_input ("mulu", OP_REG_REG_REG, 0);
2004 Multiply64 (0, State.regs[ OP[0] ]);
2006 trace_output (OP_REG_REG_REG);
2011 #define BIT_CHANGE_OP( name, binop ) \
2013 unsigned int temp; \
2015 trace_input (name, OP_BIT_CHANGE, 0); \
2017 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
2018 temp = load_mem (State.regs[ OP[0] ], 1); \
2021 if ((temp & bit) == 0) \
2025 store_mem (State.regs[ OP[0] ], 1, temp); \
2027 trace_output (OP_BIT_CHANGE); \
2031 /* clr1 reg2, [reg1] */
2035 BIT_CHANGE_OP ("clr1", &= ~ );
2038 /* not1 reg2, [reg1] */
2042 BIT_CHANGE_OP ("not1", ^= );
2049 BIT_CHANGE_OP ("set1", |= );
2056 trace_input ("sasf", OP_EX1, 0);
2058 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2060 trace_output (OP_EX1);
2065 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
2066 (Soew_Tan@el.nec.com) */
2071 unsigned long int als,
2072 unsigned long int sfi,
2073 unsigned32 /*unsigned long int*/ * quotient_ptr,
2074 unsigned32 /*unsigned long int*/ * remainder_ptr,
2078 unsigned long ald = sfi >> (N - 1);
2079 unsigned long alo = als;
2084 unsigned int R1 = 1;
2085 unsigned int DBZ = (als == 0) ? 1 : 0;
2086 unsigned long alt = Q ? ~als : als;
2089 alo = ald + alt + Q;
2090 C = (((alt >> 31) & (ald >> 31))
2091 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2094 R1 = (alo == 0) ? 0 : (R1 & Q);
2095 if ((S ^ (alo>>31)) && !C)
2100 sfi = (sfi << (32-N+1)) | Q;
2101 ald = (alo << 1) | (sfi >> 31);
2103 /* 2nd - N-1th Loop */
2104 for (i = 2; i < N; i++)
2106 alt = Q ? ~als : als;
2107 alo = ald + alt + Q;
2108 C = (((alt >> 31) & (ald >> 31))
2109 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2112 R1 = (alo == 0) ? 0 : (R1 & Q);
2113 if ((S ^ (alo>>31)) && !C && !DBZ)
2118 sfi = (sfi << 1) | Q;
2119 ald = (alo << 1) | (sfi >> 31);
2123 alt = Q ? ~als : als;
2124 alo = ald + alt + Q;
2125 C = (((alt >> 31) & (ald >> 31))
2126 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2129 R1 = (alo == 0) ? 0 : (R1 & Q);
2130 if ((S ^ (alo>>31)) && !C)
2135 * quotient_ptr = (sfi << 1) | Q;
2136 * remainder_ptr = Q ? alo : (alo + als);
2137 * overflow_ptr = DBZ | R1;
2140 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2145 unsigned long int als,
2146 unsigned long int sfi,
2147 signed32 /*signed long int*/ * quotient_ptr,
2148 signed32 /*signed long int*/ * remainder_ptr,
2152 unsigned long ald = (signed long) sfi >> (N - 1);
2153 unsigned long alo = als;
2154 unsigned int SS = als >> 31;
2155 unsigned int SD = sfi >> 31;
2156 unsigned int R1 = 1;
2158 unsigned int DBZ = als == 0 ? 1 : 0;
2159 unsigned int Q = ~(SS ^ SD) & 1;
2163 unsigned long alt = Q ? ~als : als;
2168 alo = ald + alt + Q;
2169 C = (((alt >> 31) & (ald >> 31))
2170 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2172 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2174 sfi = (sfi << (32-N+1)) | Q;
2175 ald = (alo << 1) | (sfi >> 31);
2176 if ((alo >> 31) ^ (ald >> 31))
2181 /* 2nd - N-1th Loop */
2183 for (i = 2; i < N; i++)
2185 alt = Q ? ~als : als;
2186 alo = ald + alt + Q;
2187 C = (((alt >> 31) & (ald >> 31))
2188 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2190 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2192 sfi = (sfi << 1) | Q;
2193 ald = (alo << 1) | (sfi >> 31);
2194 if ((alo >> 31) ^ (ald >> 31))
2201 alt = Q ? ~als : als;
2202 alo = ald + alt + Q;
2203 C = (((alt >> 31) & (ald >> 31))
2204 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2206 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2207 sfi = (sfi << (32-N+1));
2213 alt = Q ? ~als : als;
2214 alo = ald + alt + Q;
2216 R1 = R1 & ((~alo >> 31) ^ SD);
2217 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2219 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2221 ald = sfi = sfi | Q;
2223 OV = DBZ | ((alo == 0) ? 0 : R1);
2225 * remainder_ptr = alo;
2228 if (((alo != 0) && ((SS ^ SD) ^ R1))
2229 || ((alo == 0) && (SS ^ R1)))
2234 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2236 * quotient_ptr = alo;
2237 * overflow_ptr = OV;
2240 /* sdivun imm5, reg1, reg2, reg3 */
2244 unsigned32 /*unsigned long int*/ quotient;
2245 unsigned32 /*unsigned long int*/ remainder;
2246 unsigned long int divide_by;
2247 unsigned long int divide_this;
2251 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2253 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2255 divide_by = State.regs[ OP[0] ];
2256 divide_this = State.regs[ OP[1] ] << imm5;
2258 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2260 State.regs[ OP[1] ] = quotient;
2261 State.regs[ OP[2] >> 11 ] = remainder;
2263 /* Set condition codes. */
2264 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2266 if (overflow) PSW |= PSW_OV;
2267 if (quotient == 0) PSW |= PSW_Z;
2268 if (quotient & 0x80000000) PSW |= PSW_S;
2270 trace_output (OP_IMM_REG_REG_REG);
2275 /* sdivn imm5, reg1, reg2, reg3 */
2279 signed32 /*signed long int*/ quotient;
2280 signed32 /*signed long int*/ remainder;
2281 signed long int divide_by;
2282 signed long int divide_this;
2286 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2288 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2290 divide_by = (signed32) State.regs[ OP[0] ];
2291 divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
2293 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2295 State.regs[ OP[1] ] = quotient;
2296 State.regs[ OP[2] >> 11 ] = remainder;
2298 /* Set condition codes. */
2299 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2301 if (overflow) PSW |= PSW_OV;
2302 if (quotient == 0) PSW |= PSW_Z;
2303 if (quotient < 0) PSW |= PSW_S;
2305 trace_output (OP_IMM_REG_REG_REG);
2310 /* sdivhun imm5, reg1, reg2, reg3 */
2314 unsigned32 /*unsigned long int*/ quotient;
2315 unsigned32 /*unsigned long int*/ remainder;
2316 unsigned long int divide_by;
2317 unsigned long int divide_this;
2321 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2323 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2325 divide_by = State.regs[ OP[0] ] & 0xffff;
2326 divide_this = State.regs[ OP[1] ] << imm5;
2328 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2330 State.regs[ OP[1] ] = quotient;
2331 State.regs[ OP[2] >> 11 ] = remainder;
2333 /* Set condition codes. */
2334 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2336 if (overflow) PSW |= PSW_OV;
2337 if (quotient == 0) PSW |= PSW_Z;
2338 if (quotient & 0x80000000) PSW |= PSW_S;
2340 trace_output (OP_IMM_REG_REG_REG);
2345 /* sdivhn imm5, reg1, reg2, reg3 */
2349 signed32 /*signed long int*/ quotient;
2350 signed32 /*signed long int*/ remainder;
2351 signed long int divide_by;
2352 signed long int divide_this;
2356 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2358 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2360 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2361 divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
2363 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2365 State.regs[ OP[1] ] = quotient;
2366 State.regs[ OP[2] >> 11 ] = remainder;
2368 /* Set condition codes. */
2369 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2371 if (overflow) PSW |= PSW_OV;
2372 if (quotient == 0) PSW |= PSW_Z;
2373 if (quotient < 0) PSW |= PSW_S;
2375 trace_output (OP_IMM_REG_REG_REG);
2380 /* divu reg1, reg2, reg3 */
2384 unsigned long int quotient;
2385 unsigned long int remainder;
2386 unsigned long int divide_by;
2387 unsigned long int divide_this;
2390 trace_input ("divu", OP_REG_REG_REG, 0);
2392 /* Compute the result. */
2394 divide_by = State.regs[ OP[0] ];
2395 divide_this = State.regs[ OP[1] ];
2403 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2404 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2406 /* Set condition codes. */
2407 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2409 if (overflow) PSW |= PSW_OV;
2410 if (quotient == 0) PSW |= PSW_Z;
2411 if (quotient & 0x80000000) PSW |= PSW_S;
2414 trace_output (OP_REG_REG_REG);
2419 /* div reg1, reg2, reg3 */
2423 signed long int quotient;
2424 signed long int remainder;
2425 signed long int divide_by;
2426 signed long int divide_this;
2428 trace_input ("div", OP_REG_REG_REG, 0);
2430 /* Compute the result. */
2432 divide_by = (signed32) State.regs[ OP[0] ];
2433 divide_this = State.regs[ OP[1] ];
2439 else if (divide_by == -1 && divide_this == (1L << 31))
2442 PSW |= PSW_OV | PSW_S;
2443 State.regs[ OP[1] ] = (1 << 31);
2444 State.regs[ OP[2] >> 11 ] = 0;
2448 divide_this = (signed32) divide_this;
2449 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2450 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2452 /* Set condition codes. */
2453 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2455 if (quotient == 0) PSW |= PSW_Z;
2456 if (quotient < 0) PSW |= PSW_S;
2459 trace_output (OP_REG_REG_REG);
2464 /* divhu reg1, reg2, reg3 */
2468 unsigned long int quotient;
2469 unsigned long int remainder;
2470 unsigned long int divide_by;
2471 unsigned long int divide_this;
2474 trace_input ("divhu", OP_REG_REG_REG, 0);
2476 /* Compute the result. */
2478 divide_by = State.regs[ OP[0] ] & 0xffff;
2479 divide_this = State.regs[ OP[1] ];
2487 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2488 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2490 /* Set condition codes. */
2491 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2493 if (overflow) PSW |= PSW_OV;
2494 if (quotient == 0) PSW |= PSW_Z;
2495 if (quotient & 0x80000000) PSW |= PSW_S;
2498 trace_output (OP_REG_REG_REG);
2503 /* divh reg1, reg2, reg3 */
2507 signed long int quotient;
2508 signed long int remainder;
2509 signed long int divide_by;
2510 signed long int divide_this;
2513 trace_input ("divh", OP_REG_REG_REG, 0);
2515 /* Compute the result. */
2517 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2518 divide_this = State.regs[ OP[1] ];
2524 else if (divide_by == -1 && divide_this == (1L << 31))
2527 PSW |= PSW_OV | PSW_S;
2528 State.regs[ OP[1] ] = (1 << 31);
2529 State.regs[ OP[2] >> 11 ] = 0;
2533 divide_this = (signed32) divide_this;
2534 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2535 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2537 /* Set condition codes. */
2538 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2540 if (quotient == 0) PSW |= PSW_Z;
2541 if (quotient < 0) PSW |= PSW_S;
2544 trace_output (OP_REG_REG_REG);
2549 /* mulu imm9, reg2, reg3 */
2553 trace_input ("mulu", OP_IMM_REG_REG, 0);
2555 Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2557 trace_output (OP_IMM_REG_REG);
2562 /* mul imm9, reg2, reg3 */
2566 trace_input ("mul", OP_IMM_REG_REG, 0);
2568 Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
2570 trace_output (OP_IMM_REG_REG);
2581 trace_input ("ld.hu", OP_LOAD32, 2);
2583 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2586 State.regs[ OP[1] ] = load_mem (adr, 2);
2588 trace_output (OP_LOAD32);
2600 trace_input ("ld.bu", OP_LOAD32, 1);
2602 adr = (State.regs[ OP[0] ]
2603 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2605 State.regs[ OP[1] ] = load_mem (adr, 1);
2607 trace_output (OP_LOAD32);
2612 /* prepare list12, imm5, imm32 */
2618 trace_input ("prepare", OP_PUSHPOP1, 0);
2620 /* Store the registers with lower number registers being placed at higher addresses. */
2621 for (i = 0; i < 12; i++)
2622 if ((OP[3] & (1 << type1_regs[ i ])))
2625 store_mem (SP, 4, State.regs[ 20 + i ]);
2628 SP -= (OP[3] & 0x3e) << 1;
2630 EP = load_mem (PC + 4, 4);
2632 trace_output (OP_PUSHPOP1);
2637 /* prepare list12, imm5, imm16-32 */
2643 trace_input ("prepare", OP_PUSHPOP1, 0);
2645 /* Store the registers with lower number registers being placed at higher addresses. */
2646 for (i = 0; i < 12; i++)
2647 if ((OP[3] & (1 << type1_regs[ i ])))
2650 store_mem (SP, 4, State.regs[ 20 + i ]);
2653 SP -= (OP[3] & 0x3e) << 1;
2655 EP = load_mem (PC + 4, 2) << 16;
2657 trace_output (OP_PUSHPOP1);
2662 /* prepare list12, imm5, imm16 */
2668 trace_input ("prepare", OP_PUSHPOP1, 0);
2670 /* Store the registers with lower number registers being placed at higher addresses. */
2671 for (i = 0; i < 12; i++)
2672 if ((OP[3] & (1 << type1_regs[ i ])))
2675 store_mem (SP, 4, State.regs[ 20 + i ]);
2678 SP -= (OP[3] & 0x3e) << 1;
2680 EP = EXTEND16 (load_mem (PC + 4, 2));
2682 trace_output (OP_PUSHPOP1);
2687 /* prepare list12, imm5, sp */
2693 trace_input ("prepare", OP_PUSHPOP1, 0);
2695 /* Store the registers with lower number registers being placed at higher addresses. */
2696 for (i = 0; i < 12; i++)
2697 if ((OP[3] & (1 << type1_regs[ i ])))
2700 store_mem (SP, 4, State.regs[ 20 + i ]);
2703 SP -= (OP[3] & 0x3e) << 1;
2707 trace_output (OP_PUSHPOP1);
2712 /* mul reg1, reg2, reg3 */
2716 trace_input ("mul", OP_REG_REG_REG, 0);
2718 Multiply64 (1, State.regs[ OP[0] ]);
2720 trace_output (OP_REG_REG_REG);
2731 trace_input ("popmh", OP_PUSHPOP2, 0);
2733 if (OP[3] & (1 << 19))
2735 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2737 FEPSW = load_mem ( SP & ~ 3, 4);
2738 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2742 EIPSW = load_mem ( SP & ~ 3, 4);
2743 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2749 /* Load the registers with lower number registers being retrieved from higher addresses. */
2751 if ((OP[3] & (1 << type2_regs[ i ])))
2753 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2757 trace_output (OP_PUSHPOP2);
2768 trace_input ("popml", OP_PUSHPOP3, 0);
2770 if (OP[3] & (1 << 19))
2772 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2774 FEPSW = load_mem ( SP & ~ 3, 4);
2775 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2779 EIPSW = load_mem ( SP & ~ 3, 4);
2780 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2786 if (OP[3] & (1 << 3))
2788 PSW = load_mem (SP & ~ 3, 4);
2792 /* Load the registers with lower number registers being retrieved from higher addresses. */
2794 if ((OP[3] & (1 << type3_regs[ i ])))
2796 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2800 trace_output (OP_PUSHPOP2);
2811 trace_input ("pushmh", OP_PUSHPOP2, 0);
2813 /* Store the registers with lower number registers being placed at higher addresses. */
2814 for (i = 0; i < 16; i++)
2815 if ((OP[3] & (1 << type2_regs[ i ])))
2818 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2821 if (OP[3] & (1 << 19))
2825 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2827 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2828 store_mem ( SP & ~ 3, 4, FEPSW);
2832 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2833 store_mem ( SP & ~ 3, 4, EIPSW);
2837 trace_output (OP_PUSHPOP2);
2842 /* V850E2R FPU functions */
2844 sim_fpu_status_invalid_snan = 1, -V--- (sim spec.)
2845 sim_fpu_status_invalid_qnan = 2, ----- (sim spec.)
2846 sim_fpu_status_invalid_isi = 4, (inf - inf) -V---
2847 sim_fpu_status_invalid_idi = 8, (inf / inf) -V---
2848 sim_fpu_status_invalid_zdz = 16, (0 / 0) -V---
2849 sim_fpu_status_invalid_imz = 32, (inf * 0) -V---
2850 sim_fpu_status_invalid_cvi = 64, convert to integer -V---
2851 sim_fpu_status_invalid_div0 = 128, (X / 0) --Z--
2852 sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.)
2853 sim_fpu_status_invalid_sqrt = 512, -V---
2854 sim_fpu_status_rounded = 1024, I----
2855 sim_fpu_status_inexact = 2048, I---- (sim spec.)
2856 sim_fpu_status_overflow = 4096, I--O-
2857 sim_fpu_status_underflow = 8192, I---U
2858 sim_fpu_status_denorm = 16384, ----U (sim spec.)
2861 void update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p)
2863 unsigned int fpsr = FPSR & mask;
2865 unsigned int flags = 0;
2868 && ((status & (sim_fpu_status_rounded
2869 | sim_fpu_status_overflow
2870 | sim_fpu_status_inexact))
2871 || (status & sim_fpu_status_underflow
2872 && (fpsr & (FPSR_XEU | FPSR_XEI)) == 0
2873 && fpsr & FPSR_FS)))
2875 flags |= FPSR_XCI | FPSR_XPI;
2879 && (status & (sim_fpu_status_invalid_isi
2880 | sim_fpu_status_invalid_imz
2881 | sim_fpu_status_invalid_zdz
2882 | sim_fpu_status_invalid_idi
2883 | sim_fpu_status_invalid_cvi
2884 | sim_fpu_status_invalid_sqrt
2885 | sim_fpu_status_invalid_snan)))
2887 flags |= FPSR_XCV | FPSR_XPV;
2891 && (status & sim_fpu_status_invalid_div0))
2893 flags |= FPSR_XCV | FPSR_XPV;
2897 && (status & sim_fpu_status_overflow))
2899 flags |= FPSR_XCO | FPSR_XPO;
2902 if (((fpsr & FPSR_XEU) || (fpsr & FPSR_FS) == 0)
2903 && (status & (sim_fpu_status_underflow
2904 | sim_fpu_status_denorm)))
2906 flags |= FPSR_XCU | FPSR_XPU;
2914 SignalExceptionFPE(sd, double_op_p);
2922 void SignalException(SIM_DESC sd)
2926 PSW = PSW & ~(PSW_NPV | PSW_DMP | PSW_IMP);
2930 void SignalExceptionFPE(SIM_DESC sd, unsigned int double_op_p)
2932 if (((PSW & (PSW_NP|PSW_ID)) == 0)
2933 || !(FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM)))
2937 EIIC = (FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM))
2939 PSW |= (PSW_EP | PSW_ID);
2942 SignalException(sd);
2947 void check_invalid_snan(SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p)
2949 if ((FPSR & FPSR_XEI)
2950 && (status & sim_fpu_status_invalid_snan))
2955 SignalExceptionFPE(sd, double_op_p);
2959 int v850_float_compare(SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p)
2963 if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
2967 if (FPSR & FPSR_XEV)
2969 FPSR |= FPSR_XCV | FPSR_XPV;
2970 SignalExceptionFPE(sd, double_op_p);
3028 else if (sim_fpu_is_infinity(&wop1) && sim_fpu_is_infinity(&wop2)
3029 && sim_fpu_sign(&wop1) == sim_fpu_sign(&wop2))
3087 int gt = 0,lt = 0,eq = 0, status;
3089 status = sim_fpu_cmp( &wop1, &wop2 );
3092 case SIM_FPU_IS_SNAN:
3093 case SIM_FPU_IS_QNAN:
3097 case SIM_FPU_IS_NINF:
3100 case SIM_FPU_IS_PINF:
3103 case SIM_FPU_IS_NNUMBER:
3106 case SIM_FPU_IS_PNUMBER:
3109 case SIM_FPU_IS_NDENORM:
3112 case SIM_FPU_IS_PDENORM:
3115 case SIM_FPU_IS_NZERO:
3116 case SIM_FPU_IS_PZERO:
3174 ASSERT(result != -1);
3178 void v850_div(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3180 signed long int quotient;
3181 signed long int remainder;
3182 signed long int divide_by;
3183 signed long int divide_this;
3184 bfd_boolean overflow = FALSE;
3186 /* Compute the result. */
3190 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3196 quotient = divide_this / divide_by;
3197 remainder = divide_this % divide_by;
3199 /* Set condition codes. */
3200 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3202 if (overflow) PSW |= PSW_OV;
3203 if (quotient == 0) PSW |= PSW_Z;
3204 if (quotient < 0) PSW |= PSW_S;
3210 void v850_divu(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3212 unsigned long int quotient;
3213 unsigned long int remainder;
3214 unsigned long int divide_by;
3215 unsigned long int divide_this;
3216 bfd_boolean overflow = FALSE;
3218 /* Compute the result. */
3229 quotient = divide_this / divide_by;
3230 remainder = divide_this % divide_by;
3232 /* Set condition codes. */
3233 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3235 if (overflow) PSW |= PSW_OV;
3236 if (quotient == 0) PSW |= PSW_Z;
3237 if (quotient & 0x80000000) PSW |= PSW_S;
3244 void v850_sar(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3246 unsigned int result, z, s, cy;
3249 result = (signed)op1 >> op0;
3251 /* Compute the condition codes. */
3253 s = (result & 0x80000000);
3254 cy = (op1 & (1 << (op0 - 1)));
3256 /* Store the result and condition codes. */
3257 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3258 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3259 | (cy ? PSW_CY : 0));
3264 void v850_shl(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3266 unsigned int result, z, s, cy;
3269 result = op1 << op0;
3271 /* Compute the condition codes. */
3273 s = (result & 0x80000000);
3274 cy = (op1 & (1 << (32 - op0)));
3276 /* Store the result and condition codes. */
3277 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3278 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3279 | (cy ? PSW_CY : 0));
3285 v850_rotl (SIM_DESC sd, unsigned int amount, unsigned int src, unsigned int * dest)
3287 unsigned int result, z, s, cy;
3290 result = src << amount;
3291 result |= src >> (32 - amount);
3293 /* Compute the condition codes. */
3295 s = (result & 0x80000000);
3296 cy = ! (result & 1);
3298 /* Store the result and condition codes. */
3299 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3300 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3301 | (cy ? PSW_CY : 0));
3307 v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb,
3308 unsigned int * dest)
3311 unsigned int result, pos, width;
3315 width = (msb - lsb) + 1;
3317 mask = ~ (-1 << width);
3320 result = (* dest) & ~ mask;
3321 result |= source << pos;
3323 /* Compute the condition codes. */
3325 s = result & 0x80000000;
3327 /* Store the result and condition codes. */
3328 PSW &= ~(PSW_Z | PSW_S | PSW_OV );
3329 PSW |= (z ? PSW_Z : 0) | (s ? PSW_S : 0);
3334 void v850_shr(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3336 unsigned int result, z, s, cy;
3339 result = op1 >> op0;
3341 /* Compute the condition codes. */
3343 s = (result & 0x80000000);
3344 cy = (op1 & (1 << (op0 - 1)));
3346 /* Store the result and condition codes. */
3347 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3348 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3349 | (cy ? PSW_CY : 0));
3354 void v850_satadd(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3356 unsigned int result, z, s, cy, ov, sat;
3360 /* Compute the condition codes. */
3362 s = (result & 0x80000000);
3363 cy = (result < op0 || result < op1);
3364 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
3365 && (op0 & 0x80000000) != (result & 0x80000000));
3368 /* Store the result and condition codes. */
3369 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3370 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3371 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3372 | (sat ? PSW_SAT : 0));
3374 /* Handle saturated results. */
3377 result = 0x7fffffff;
3382 result = 0x80000000;
3389 void v850_satsub(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3391 unsigned int result, z, s, cy, ov, sat;
3393 /* Compute the result. */
3396 /* Compute the condition codes. */
3398 s = (result & 0x80000000);
3400 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
3401 && (op1 & 0x80000000) != (result & 0x80000000));
3404 /* Store the result and condition codes. */
3405 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3406 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3407 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3408 | (sat ? PSW_SAT : 0));
3410 /* Handle saturated results. */
3413 result = 0x7fffffff;
3418 result = 0x80000000;
3426 load_data_mem(sd, addr, len)
3436 data = sim_core_read_unaligned_1 (STATE_CPU (sd, 0),
3437 PC, read_map, addr);
3440 data = sim_core_read_unaligned_2 (STATE_CPU (sd, 0),
3441 PC, read_map, addr);
3444 data = sim_core_read_unaligned_4 (STATE_CPU (sd, 0),
3445 PC, read_map, addr);
3454 store_data_mem(sd, addr, len, data)
3463 store_mem(addr, 1, data);
3466 store_mem(addr, 2, data);
3469 store_mem(addr, 4, data);
3476 int mpu_load_mem_test(SIM_DESC sd, unsigned int addr, int size, int base_reg)
3482 if (IPE0 && addr >= IPA2ADDR(IPA0L) && addr <= IPA2ADDR(IPA0L) && IPR0)
3486 else if (IPE1 && addr >= IPA2ADDR(IPA1L) && addr <= IPA2ADDR(IPA1L) && IPR1)
3490 else if (IPE2 && addr >= IPA2ADDR(IPA2L) && addr <= IPA2ADDR(IPA2L) && IPR2)
3494 else if (IPE3 && addr >= IPA2ADDR(IPA3L) && addr <= IPA2ADDR(IPA3L) && IPR3)
3498 else if (addr >= PPA2ADDR(PPA & ~PPM) && addr <= DPA2ADDR(PPA | PPM))
3500 /* preifarallel area */
3502 else if (addr >= PPA2ADDR(SPAL) && addr <= DPA2ADDR(SPAU))
3506 else if (DPE0 && addr >= DPA2ADDR(DPA0L) && addr <= DPA2ADDR(DPA0L) && DPR0
3507 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3511 else if (DPE1 && addr >= DPA2ADDR(DPA1L) && addr <= DPA2ADDR(DPA1L) && DPR1
3512 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3516 else if (DPE2 && addr >= DPA2ADDR(DPA2L) && addr <= DPA2ADDR(DPA2L) && DPR2
3517 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3521 else if (DPE3 && addr >= DPA2ADDR(DPA3L) && addr <= DPA2ADDR(DPA3L) && DPR3
3522 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3528 VMECR &= ~(VMECR_VMW | VMECR_VMX);
3536 SignalException(sd);
3544 int mpu_store_mem_test(SIM_DESC sd, unsigned int addr, int size, int base_reg)
3550 if (addr >= PPA2ADDR(PPA & ~PPM) && addr <= DPA2ADDR(PPA | PPM))
3552 /* preifarallel area */
3554 else if (addr >= PPA2ADDR(SPAL) && addr <= DPA2ADDR(SPAU))
3558 else if (DPE0 && addr >= DPA2ADDR(DPA0L) && addr <= DPA2ADDR(DPA0L) && DPW0
3559 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3563 else if (DPE1 && addr >= DPA2ADDR(DPA1L) && addr <= DPA2ADDR(DPA1L) && DPW1
3564 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3568 else if (DPE2 && addr >= DPA2ADDR(DPA2L) && addr <= DPA2ADDR(DPA2L) && DPW2
3569 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3573 else if (DPE3 && addr >= DPA2ADDR(DPA3L) && addr <= DPA2ADDR(DPA3L) && DPW3
3574 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3580 if (addr >= PPA2ADDR(PPA & ~PPM) && addr <= DPA2ADDR(PPA | PPM))
3595 VMECR &= ~(VMECR_VMW | VMECR_VMX);