27 #include "targ-vals.h"
29 #include "libiberty.h"
32 #if !defined(__GO32__) && !defined(_WIN32)
34 #include <sys/times.h>
38 /* This is an array of the bit positions of registers r20 .. r31 in
39 that order in a prepare/dispose instruction. */
40 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
41 /* This is an array of the bit positions of registers r16 .. r31 in
42 that order in a push/pop instruction. */
43 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
44 /* This is an array of the bit positions of registers r1 .. r15 in
45 that order in a push/pop instruction. */
46 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
49 #ifndef SIZE_INSTRUCTION
50 #define SIZE_INSTRUCTION 18
54 #define SIZE_VALUES 11
58 unsigned32 trace_values[3];
61 const char * trace_name;
66 trace_input (char *name, enum op_types type, int size)
68 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
73 trace_module = TRACE_ALU_IDX;
86 trace_values[0] = State.regs[OP[0]];
93 trace_values[0] = State.regs[OP[1]];
94 trace_values[1] = State.regs[OP[0]];
100 trace_values[0] = SEXT5 (OP[0]);
101 trace_values[1] = OP[1];
102 trace_num_values = 2;
105 case OP_IMM_REG_MOVE:
106 trace_values[0] = SEXT5 (OP[0]);
107 trace_num_values = 1;
111 trace_values[0] = State.pc;
112 trace_values[1] = SEXT9 (OP[0]);
113 trace_values[2] = PSW;
114 trace_num_values = 3;
118 trace_values[0] = OP[1] * size;
119 trace_values[1] = State.regs[30];
120 trace_num_values = 2;
124 trace_values[0] = State.regs[OP[0]];
125 trace_values[1] = OP[1] * size;
126 trace_values[2] = State.regs[30];
127 trace_num_values = 3;
131 trace_values[0] = EXTEND16 (OP[2]);
132 trace_values[1] = State.regs[OP[0]];
133 trace_num_values = 2;
137 trace_values[0] = State.regs[OP[1]];
138 trace_values[1] = EXTEND16 (OP[2]);
139 trace_values[2] = State.regs[OP[0]];
140 trace_num_values = 3;
144 trace_values[0] = SEXT22 (OP[0]);
145 trace_values[1] = State.pc;
146 trace_num_values = 2;
150 trace_values[0] = EXTEND16 (OP[0]) << size;
151 trace_values[1] = State.regs[OP[1]];
152 trace_num_values = 2;
155 case OP_IMM16_REG_REG:
156 trace_values[0] = EXTEND16 (OP[2]) << size;
157 trace_values[1] = State.regs[OP[1]];
158 trace_num_values = 2;
161 case OP_UIMM_REG_REG:
162 trace_values[0] = (OP[0] & 0xffff) << size;
163 trace_values[1] = State.regs[OP[1]];
164 trace_num_values = 2;
167 case OP_UIMM16_REG_REG:
168 trace_values[0] = (OP[2]) << size;
169 trace_values[1] = State.regs[OP[1]];
170 trace_num_values = 2;
174 trace_num_values = 0;
178 trace_values[0] = PSW;
179 trace_num_values = 1;
183 trace_num_values = 0;
187 trace_values[0] = State.regs[OP[0]];
188 trace_num_values = 1;
192 trace_values[0] = State.sregs[OP[1]];
193 trace_num_values = 1;
199 trace_result (int has_result, unsigned32 result)
207 /* write out the values saved during the trace_input call */
210 for (i = 0; i < trace_num_values; i++)
212 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "",
213 (long) trace_values[i]);
214 chp = strchr (chp, '\0');
218 sprintf (chp, "%*s", SIZE_VALUES, "");
219 chp = strchr (chp, '\0');
223 /* append any result to the end of the buffer */
225 sprintf (chp, " :: 0x%.8lx", (unsigned long) result);
227 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, "%s", buf);
231 trace_output (enum op_types result)
233 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
255 trace_result (1, State.regs[OP[0]]);
259 case OP_REG_REG_MOVE:
261 case OP_IMM_REG_MOVE:
264 trace_result (1, State.regs[OP[1]]);
268 case OP_UIMM_REG_REG:
269 case OP_IMM16_REG_REG:
270 case OP_UIMM16_REG_REG:
271 trace_result (1, State.regs[OP[1]]);
276 trace_result (1, State.regs[OP[1]]);
282 trace_result (1, State.sregs[OP[1]]);
289 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
291 condition_met (unsigned code)
293 unsigned int psw = PSW;
297 case 0x0: return ((psw & PSW_OV) != 0);
298 case 0x1: return ((psw & PSW_CY) != 0);
299 case 0x2: return ((psw & PSW_Z) != 0);
300 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
301 case 0x4: return ((psw & PSW_S) != 0);
302 /*case 0x5: return 1;*/
303 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
304 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
305 case 0x8: return ((psw & PSW_OV) == 0);
306 case 0x9: return ((psw & PSW_CY) == 0);
307 case 0xa: return ((psw & PSW_Z) == 0);
308 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
309 case 0xc: return ((psw & PSW_S) == 0);
310 case 0xd: return ((psw & PSW_SAT) != 0);
311 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
312 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
319 Add32 (unsigned long a1, unsigned long a2, int * carry)
321 unsigned long result = (a1 + a2);
323 * carry = (result < a1);
329 Multiply64 (int sign, unsigned long op0)
340 op1 = State.regs[ OP[1] ];
344 /* Compute sign of result and adjust operands if necessary. */
346 sign = (op0 ^ op1) & 0x80000000;
348 if (((signed long) op0) < 0)
351 if (((signed long) op1) < 0)
355 /* We can split the 32x32 into four 16x16 operations. This ensures
356 that we do not lose precision on 32bit only hosts: */
357 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
358 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
359 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
360 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
362 /* We now need to add all of these results together, taking care
363 to propogate the carries from the additions: */
364 RdLo = Add32 (lo, (mid1 << 16), & carry);
366 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
367 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
371 /* Negate result if necessary. */
375 if (RdLo == 0xFFFFFFFF)
384 /* Don't store into register 0. */
386 State.regs[ OP[1] ] = RdLo;
388 State.regs[ OP[2] >> 11 ] = RdHi;
394 /* Read a null terminated string from memory, return in a buffer. */
397 fetch_str (SIM_DESC sd, address_word addr)
402 while (sim_core_read_1 (STATE_CPU (sd, 0),
403 PC, read_map, addr + nr) != 0)
406 buf = NZALLOC (char, nr + 1);
407 sim_read (simulator, addr, (unsigned char *) buf, nr);
412 /* Read a null terminated argument vector from memory, return in a
416 fetch_argv (SIM_DESC sd, address_word addr)
420 char **buf = xmalloc (max_nr * sizeof (char*));
424 unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
425 PC, read_map, addr + nr * 4);
427 buf[nr] = fetch_str (sd, a);
429 if (nr == max_nr - 1)
432 buf = xrealloc (buf, max_nr * sizeof (char*));
444 trace_input ("sst.b", OP_STORE16, 1);
446 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
448 trace_output (OP_STORE16);
457 trace_input ("sst.h", OP_STORE16, 2);
459 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
461 trace_output (OP_STORE16);
470 trace_input ("sst.w", OP_STORE16, 4);
472 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
474 trace_output (OP_STORE16);
485 trace_input ("ld.b", OP_LOAD32, 1);
487 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
489 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
491 trace_output (OP_LOAD32);
502 trace_input ("ld.h", OP_LOAD32, 2);
504 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
507 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
509 trace_output (OP_LOAD32);
520 trace_input ("ld.w", OP_LOAD32, 4);
522 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
525 State.regs[ OP[1] ] = load_mem (adr, 4);
527 trace_output (OP_LOAD32);
536 trace_input ("st.b", OP_STORE32, 1);
538 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
540 trace_output (OP_STORE32);
551 trace_input ("st.h", OP_STORE32, 2);
553 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
556 store_mem (adr, 2, State.regs[ OP[1] ]);
558 trace_output (OP_STORE32);
569 trace_input ("st.w", OP_STORE32, 4);
571 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
574 store_mem (adr, 4, State.regs[ OP[1] ]);
576 trace_output (OP_STORE32);
585 unsigned int op0, op1, result, z, s, cy, ov;
587 trace_input ("add", OP_REG_REG, 0);
589 /* Compute the result. */
591 op0 = State.regs[ OP[0] ];
592 op1 = State.regs[ OP[1] ];
596 /* Compute the condition codes. */
598 s = (result & 0x80000000);
599 cy = (result < op0 || result < op1);
600 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
601 && (op0 & 0x80000000) != (result & 0x80000000));
603 /* Store the result and condition codes. */
604 State.regs[OP[1]] = result;
605 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
606 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
607 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
608 trace_output (OP_REG_REG);
613 /* add sign_extend(imm5), reg */
617 unsigned int op0, op1, result, z, s, cy, ov;
620 trace_input ("add", OP_IMM_REG, 0);
622 /* Compute the result. */
623 temp = SEXT5 (OP[0]);
625 op1 = State.regs[OP[1]];
628 /* Compute the condition codes. */
630 s = (result & 0x80000000);
631 cy = (result < op0 || result < op1);
632 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
633 && (op0 & 0x80000000) != (result & 0x80000000));
635 /* Store the result and condition codes. */
636 State.regs[OP[1]] = result;
637 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
638 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
639 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
640 trace_output (OP_IMM_REG);
645 /* addi sign_extend(imm16), reg, reg */
649 unsigned int op0, op1, result, z, s, cy, ov;
651 trace_input ("addi", OP_IMM16_REG_REG, 0);
653 /* Compute the result. */
655 op0 = EXTEND16 (OP[2]);
656 op1 = State.regs[ OP[0] ];
659 /* Compute the condition codes. */
661 s = (result & 0x80000000);
662 cy = (result < op0 || result < op1);
663 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
664 && (op0 & 0x80000000) != (result & 0x80000000));
666 /* Store the result and condition codes. */
667 State.regs[OP[1]] = result;
668 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
669 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
670 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
671 trace_output (OP_IMM16_REG_REG);
680 unsigned int op0, op1, result, z, s, cy, ov;
682 trace_input ("sub", OP_REG_REG, 0);
683 /* Compute the result. */
684 op0 = State.regs[ OP[0] ];
685 op1 = State.regs[ OP[1] ];
688 /* Compute the condition codes. */
690 s = (result & 0x80000000);
692 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
693 && (op1 & 0x80000000) != (result & 0x80000000));
695 /* Store the result and condition codes. */
696 State.regs[OP[1]] = result;
697 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
698 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
699 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
700 trace_output (OP_REG_REG);
705 /* subr reg1, reg2 */
709 unsigned int op0, op1, result, z, s, cy, ov;
711 trace_input ("subr", OP_REG_REG, 0);
712 /* Compute the result. */
713 op0 = State.regs[ OP[0] ];
714 op1 = State.regs[ OP[1] ];
717 /* Compute the condition codes. */
719 s = (result & 0x80000000);
721 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
722 && (op0 & 0x80000000) != (result & 0x80000000));
724 /* Store the result and condition codes. */
725 State.regs[OP[1]] = result;
726 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
727 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
728 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
729 trace_output (OP_REG_REG);
738 trace_input ("mulh", OP_REG_REG, 0);
740 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
742 trace_output (OP_REG_REG);
747 /* mulh sign_extend(imm5), reg2 */
751 trace_input ("mulh", OP_IMM_REG, 0);
753 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
755 trace_output (OP_IMM_REG);
760 /* mulhi imm16, reg1, reg2 */
764 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
766 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
768 trace_output (OP_IMM16_REG_REG);
777 unsigned int op0, op1, result, z, s, cy, ov;
779 trace_input ("cmp", OP_REG_REG_CMP, 0);
780 /* Compute the result. */
781 op0 = State.regs[ OP[0] ];
782 op1 = State.regs[ OP[1] ];
785 /* Compute the condition codes. */
787 s = (result & 0x80000000);
789 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
790 && (op1 & 0x80000000) != (result & 0x80000000));
792 /* Set condition codes. */
793 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
794 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
795 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
796 trace_output (OP_REG_REG_CMP);
801 /* cmp sign_extend(imm5), reg */
805 unsigned int op0, op1, result, z, s, cy, ov;
808 /* Compute the result. */
809 trace_input ("cmp", OP_IMM_REG_CMP, 0);
810 temp = SEXT5 (OP[0]);
812 op1 = State.regs[OP[1]];
815 /* Compute the condition codes. */
817 s = (result & 0x80000000);
819 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
820 && (op1 & 0x80000000) != (result & 0x80000000));
822 /* Set condition codes. */
823 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
824 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
825 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
826 trace_output (OP_IMM_REG_CMP);
835 trace_input ("setf", OP_EX1, 0);
837 State.regs[ OP[1] ] = condition_met (OP[0]);
839 trace_output (OP_EX1);
848 unsigned int op0, op1, result, z, s, cy, ov, sat;
850 trace_input ("satadd", OP_REG_REG, 0);
851 /* Compute the result. */
852 op0 = State.regs[ OP[0] ];
853 op1 = State.regs[ OP[1] ];
856 /* Compute the condition codes. */
858 s = (result & 0x80000000);
859 cy = (result < op0 || result < op1);
860 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
861 && (op0 & 0x80000000) != (result & 0x80000000));
864 /* Handle saturated results. */
867 /* An overflow that results in a negative result implies that we
868 became too positive. */
874 /* Any other overflow must have thus been too negative. */
880 /* Store the result and condition codes. */
881 State.regs[OP[1]] = result;
882 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
883 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
884 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
885 | (sat ? PSW_SAT : 0));
887 trace_output (OP_REG_REG);
892 /* satadd sign_extend(imm5), reg */
896 unsigned int op0, op1, result, z, s, cy, ov, sat;
900 trace_input ("satadd", OP_IMM_REG, 0);
902 /* Compute the result. */
903 temp = SEXT5 (OP[0]);
905 op1 = State.regs[OP[1]];
908 /* Compute the condition codes. */
910 s = (result & 0x80000000);
911 cy = (result < op0 || result < op1);
912 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
913 && (op0 & 0x80000000) != (result & 0x80000000));
916 /* Handle saturated results. */
919 /* An overflow that results in a negative result implies that we
920 became too positive. */
926 /* Any other overflow must have thus been too negative. */
932 /* Store the result and condition codes. */
933 State.regs[OP[1]] = result;
934 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
935 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
936 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
937 | (sat ? PSW_SAT : 0));
938 trace_output (OP_IMM_REG);
943 /* satsub reg1, reg2 */
947 unsigned int op0, op1, result, z, s, cy, ov, sat;
949 trace_input ("satsub", OP_REG_REG, 0);
951 /* Compute the result. */
952 op0 = State.regs[ OP[0] ];
953 op1 = State.regs[ OP[1] ];
956 /* Compute the condition codes. */
958 s = (result & 0x80000000);
960 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
961 && (op1 & 0x80000000) != (result & 0x80000000));
964 /* Handle saturated results. */
967 /* An overflow that results in a negative result implies that we
968 became too positive. */
974 /* Any other overflow must have thus been too negative. */
980 /* Store the result and condition codes. */
981 State.regs[OP[1]] = result;
982 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
983 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
984 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
985 | (sat ? PSW_SAT : 0));
987 trace_output (OP_REG_REG);
991 /* satsubi sign_extend(imm16), reg */
995 unsigned int op0, op1, result, z, s, cy, ov, sat;
998 trace_input ("satsubi", OP_IMM_REG, 0);
1000 /* Compute the result. */
1001 temp = EXTEND16 (OP[2]);
1003 op1 = State.regs[ OP[0] ];
1006 /* Compute the condition codes. */
1008 s = (result & 0x80000000);
1010 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1011 && (op1 & 0x80000000) != (result & 0x80000000));
1014 /* Handle saturated results. */
1017 /* An overflow that results in a negative result implies that we
1018 became too positive. */
1019 result = 0x7fffffff;
1024 /* Any other overflow must have thus been too negative. */
1025 result = 0x80000000;
1030 /* Store the result and condition codes. */
1031 State.regs[OP[1]] = result;
1032 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1033 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1034 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1035 | (sat ? PSW_SAT : 0));
1037 trace_output (OP_IMM_REG);
1042 /* satsubr reg,reg */
1046 unsigned int op0, op1, result, z, s, cy, ov, sat;
1048 trace_input ("satsubr", OP_REG_REG, 0);
1050 /* Compute the result. */
1051 op0 = State.regs[ OP[0] ];
1052 op1 = State.regs[ OP[1] ];
1055 /* Compute the condition codes. */
1057 s = (result & 0x80000000);
1059 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1060 && (op0 & 0x80000000) != (result & 0x80000000));
1063 /* Handle saturated results. */
1066 /* An overflow that results in a negative result implies that we
1067 became too positive. */
1068 result = 0x7fffffff;
1073 /* Any other overflow must have thus been too negative. */
1074 result = 0x80000000;
1079 /* Store the result and condition codes. */
1080 State.regs[OP[1]] = result;
1081 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1082 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1083 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1084 | (sat ? PSW_SAT : 0));
1086 trace_output (OP_REG_REG);
1095 unsigned int op0, op1, result, z, s;
1097 trace_input ("tst", OP_REG_REG_CMP, 0);
1099 /* Compute the result. */
1100 op0 = State.regs[ OP[0] ];
1101 op1 = State.regs[ OP[1] ];
1104 /* Compute the condition codes. */
1106 s = (result & 0x80000000);
1108 /* Store the condition codes. */
1109 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1110 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1111 trace_output (OP_REG_REG_CMP);
1116 /* mov sign_extend(imm5), reg */
1120 int value = SEXT5 (OP[0]);
1122 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1124 State.regs[ OP[1] ] = value;
1126 trace_output (OP_IMM_REG_MOVE);
1131 /* movhi imm16, reg, reg */
1135 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1137 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1139 trace_output (OP_UIMM16_REG_REG);
1144 /* sar zero_extend(imm5),reg1 */
1148 unsigned int op0, op1, result, z, s, cy;
1150 trace_input ("sar", OP_IMM_REG, 0);
1152 op1 = State.regs[ OP[1] ];
1153 result = (signed)op1 >> op0;
1155 /* Compute the condition codes. */
1157 s = (result & 0x80000000);
1158 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1160 /* Store the result and condition codes. */
1161 State.regs[ OP[1] ] = result;
1162 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1163 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1164 | (cy ? PSW_CY : 0));
1165 trace_output (OP_IMM_REG);
1170 /* sar reg1, reg2 */
1174 unsigned int op0, op1, result, z, s, cy;
1176 trace_input ("sar", OP_REG_REG, 0);
1178 op0 = State.regs[ OP[0] ] & 0x1f;
1179 op1 = State.regs[ OP[1] ];
1180 result = (signed)op1 >> op0;
1182 /* Compute the condition codes. */
1184 s = (result & 0x80000000);
1185 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1187 /* Store the result and condition codes. */
1188 State.regs[OP[1]] = result;
1189 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1190 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1191 | (cy ? PSW_CY : 0));
1192 trace_output (OP_REG_REG);
1197 /* shl zero_extend(imm5),reg1 */
1201 unsigned int op0, op1, result, z, s, cy;
1203 trace_input ("shl", OP_IMM_REG, 0);
1205 op1 = State.regs[ OP[1] ];
1206 result = op1 << op0;
1208 /* Compute the condition codes. */
1210 s = (result & 0x80000000);
1211 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1213 /* Store the result and condition codes. */
1214 State.regs[OP[1]] = result;
1215 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1216 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1217 | (cy ? PSW_CY : 0));
1218 trace_output (OP_IMM_REG);
1223 /* shl reg1, reg2 */
1227 unsigned int op0, op1, result, z, s, cy;
1229 trace_input ("shl", OP_REG_REG, 0);
1230 op0 = State.regs[ OP[0] ] & 0x1f;
1231 op1 = State.regs[ OP[1] ];
1232 result = op1 << op0;
1234 /* Compute the condition codes. */
1236 s = (result & 0x80000000);
1237 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1239 /* Store the result and condition codes. */
1240 State.regs[OP[1]] = result;
1241 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1242 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1243 | (cy ? PSW_CY : 0));
1244 trace_output (OP_REG_REG);
1249 /* shr zero_extend(imm5),reg1 */
1253 unsigned int op0, op1, result, z, s, cy;
1255 trace_input ("shr", OP_IMM_REG, 0);
1257 op1 = State.regs[ OP[1] ];
1258 result = op1 >> op0;
1260 /* Compute the condition codes. */
1262 s = (result & 0x80000000);
1263 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1265 /* Store the result and condition codes. */
1266 State.regs[OP[1]] = result;
1267 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1268 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1269 | (cy ? PSW_CY : 0));
1270 trace_output (OP_IMM_REG);
1275 /* shr reg1, reg2 */
1279 unsigned int op0, op1, result, z, s, cy;
1281 trace_input ("shr", OP_REG_REG, 0);
1282 op0 = State.regs[ OP[0] ] & 0x1f;
1283 op1 = State.regs[ OP[1] ];
1284 result = op1 >> op0;
1286 /* Compute the condition codes. */
1288 s = (result & 0x80000000);
1289 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1291 /* Store the result and condition codes. */
1292 State.regs[OP[1]] = result;
1293 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1294 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1295 | (cy ? PSW_CY : 0));
1296 trace_output (OP_REG_REG);
1305 unsigned int op0, op1, result, z, s;
1307 trace_input ("or", OP_REG_REG, 0);
1309 /* Compute the result. */
1310 op0 = State.regs[ OP[0] ];
1311 op1 = State.regs[ OP[1] ];
1314 /* Compute the condition codes. */
1316 s = (result & 0x80000000);
1318 /* Store the result and condition codes. */
1319 State.regs[OP[1]] = result;
1320 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1321 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1322 trace_output (OP_REG_REG);
1327 /* ori zero_extend(imm16), reg, reg */
1331 unsigned int op0, op1, result, z, s;
1333 trace_input ("ori", OP_UIMM16_REG_REG, 0);
1335 op1 = State.regs[ OP[0] ];
1338 /* Compute the condition codes. */
1340 s = (result & 0x80000000);
1342 /* Store the result and condition codes. */
1343 State.regs[OP[1]] = result;
1344 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1345 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1346 trace_output (OP_UIMM16_REG_REG);
1355 unsigned int op0, op1, result, z, s;
1357 trace_input ("and", OP_REG_REG, 0);
1359 /* Compute the result. */
1360 op0 = State.regs[ OP[0] ];
1361 op1 = State.regs[ OP[1] ];
1364 /* Compute the condition codes. */
1366 s = (result & 0x80000000);
1368 /* Store the result and condition codes. */
1369 State.regs[OP[1]] = result;
1370 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1371 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1372 trace_output (OP_REG_REG);
1377 /* andi zero_extend(imm16), reg, reg */
1381 unsigned int result, z;
1383 trace_input ("andi", OP_UIMM16_REG_REG, 0);
1385 result = OP[2] & State.regs[ OP[0] ];
1387 /* Compute the condition codes. */
1390 /* Store the result and condition codes. */
1391 State.regs[ OP[1] ] = result;
1393 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1394 PSW |= (z ? PSW_Z : 0);
1396 trace_output (OP_UIMM16_REG_REG);
1405 unsigned int op0, op1, result, z, s;
1407 trace_input ("xor", OP_REG_REG, 0);
1409 /* Compute the result. */
1410 op0 = State.regs[ OP[0] ];
1411 op1 = State.regs[ OP[1] ];
1414 /* Compute the condition codes. */
1416 s = (result & 0x80000000);
1418 /* Store the result and condition codes. */
1419 State.regs[OP[1]] = result;
1420 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1421 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1422 trace_output (OP_REG_REG);
1427 /* xori zero_extend(imm16), reg, reg */
1431 unsigned int op0, op1, result, z, s;
1433 trace_input ("xori", OP_UIMM16_REG_REG, 0);
1435 op1 = State.regs[ OP[0] ];
1438 /* Compute the condition codes. */
1440 s = (result & 0x80000000);
1442 /* Store the result and condition codes. */
1443 State.regs[OP[1]] = result;
1444 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1445 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1446 trace_output (OP_UIMM16_REG_REG);
1451 /* not reg1, reg2 */
1455 unsigned int op0, result, z, s;
1457 trace_input ("not", OP_REG_REG_MOVE, 0);
1458 /* Compute the result. */
1459 op0 = State.regs[ OP[0] ];
1462 /* Compute the condition codes. */
1464 s = (result & 0x80000000);
1466 /* Store the result and condition codes. */
1467 State.regs[OP[1]] = result;
1468 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1469 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1470 trace_output (OP_REG_REG_MOVE);
1479 unsigned int op0, op1, op2;
1482 trace_input ("set1", OP_BIT, 0);
1483 op0 = State.regs[ OP[0] ];
1485 temp = EXTEND16 (OP[2]);
1487 temp = load_mem (op0 + op2, 1);
1489 if ((temp & (1 << op1)) == 0)
1492 store_mem (op0 + op2, 1, temp);
1493 trace_output (OP_BIT);
1502 unsigned int op0, op1, op2;
1505 trace_input ("not1", OP_BIT, 0);
1506 op0 = State.regs[ OP[0] ];
1508 temp = EXTEND16 (OP[2]);
1510 temp = load_mem (op0 + op2, 1);
1512 if ((temp & (1 << op1)) == 0)
1515 store_mem (op0 + op2, 1, temp);
1516 trace_output (OP_BIT);
1525 unsigned int op0, op1, op2;
1528 trace_input ("clr1", OP_BIT, 0);
1529 op0 = State.regs[ OP[0] ];
1531 temp = EXTEND16 (OP[2]);
1533 temp = load_mem (op0 + op2, 1);
1535 if ((temp & (1 << op1)) == 0)
1537 temp &= ~(1 << op1);
1538 store_mem (op0 + op2, 1, temp);
1539 trace_output (OP_BIT);
1548 unsigned int op0, op1, op2;
1551 trace_input ("tst1", OP_BIT, 0);
1552 op0 = State.regs[ OP[0] ];
1554 temp = EXTEND16 (OP[2]);
1556 temp = load_mem (op0 + op2, 1);
1558 if ((temp & (1 << op1)) == 0)
1560 trace_output (OP_BIT);
1569 trace_input ("di", OP_NONE, 0);
1571 trace_output (OP_NONE);
1580 trace_input ("ei", OP_NONE, 0);
1582 trace_output (OP_NONE);
1591 trace_input ("halt", OP_NONE, 0);
1592 /* FIXME this should put processor into a mode where NMI still handled */
1593 trace_output (OP_NONE);
1594 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1595 sim_stopped, SIM_SIGTRAP);
1603 trace_input ("trap", OP_TRAP, 0);
1604 trace_output (OP_TRAP);
1606 /* Trap 31 is used for simulating OS I/O functions */
1610 int save_errno = errno;
1613 /* Registers passed to trap 0 */
1615 #define FUNC State.regs[6] /* function number, return value */
1616 #define PARM1 State.regs[7] /* optional parm 1 */
1617 #define PARM2 State.regs[8] /* optional parm 2 */
1618 #define PARM3 State.regs[9] /* optional parm 3 */
1620 /* Registers set by trap 0 */
1622 #define RETVAL State.regs[10] /* return value */
1623 #define RETERR State.regs[11] /* return error code */
1625 /* Turn a pointer in a register into a pointer into real memory. */
1627 #define MEMPTR(x) (map (x))
1635 #ifdef TARGET_SYS_fork
1636 case TARGET_SYS_fork:
1644 #ifdef TARGET_SYS_execv
1645 case TARGET_SYS_execve:
1647 char *path = fetch_str (simulator, PARM1);
1648 char **argv = fetch_argv (simulator, PARM2);
1649 char **envp = fetch_argv (simulator, PARM3);
1650 RETVAL = execve (path, argv, envp);
1661 #ifdef TARGET_SYS_execv
1662 case TARGET_SYS_execv:
1664 char *path = fetch_str (simulator, PARM1);
1665 char **argv = fetch_argv (simulator, PARM2);
1666 RETVAL = execv (path, argv);
1676 #ifdef TARGET_SYS_pipe
1677 case TARGET_SYS_pipe:
1683 RETVAL = pipe (host_fd);
1684 SW (buf, host_fd[0]);
1685 buf += sizeof (uint16);
1686 SW (buf, host_fd[1]);
1694 #ifdef TARGET_SYS_wait
1695 case TARGET_SYS_wait:
1699 RETVAL = wait (&status);
1707 #ifdef TARGET_SYS_read
1708 case TARGET_SYS_read:
1710 char *buf = zalloc (PARM3);
1711 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1712 sim_write (simulator, PARM2, (unsigned char *) buf, PARM3);
1714 if ((int) RETVAL < 0)
1715 RETERR = sim_io_get_errno (simulator);
1720 #ifdef TARGET_SYS_write
1721 case TARGET_SYS_write:
1723 char *buf = zalloc (PARM3);
1724 sim_read (simulator, PARM2, (unsigned char *) buf, PARM3);
1726 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1728 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1730 if ((int) RETVAL < 0)
1731 RETERR = sim_io_get_errno (simulator);
1736 #ifdef TARGET_SYS_lseek
1737 case TARGET_SYS_lseek:
1738 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1739 if ((int) RETVAL < 0)
1740 RETERR = sim_io_get_errno (simulator);
1744 #ifdef TARGET_SYS_close
1745 case TARGET_SYS_close:
1746 RETVAL = sim_io_close (simulator, PARM1);
1747 if ((int) RETVAL < 0)
1748 RETERR = sim_io_get_errno (simulator);
1752 #ifdef TARGET_SYS_open
1753 case TARGET_SYS_open:
1755 char *buf = fetch_str (simulator, PARM1);
1756 RETVAL = sim_io_open (simulator, buf, PARM2);
1758 if ((int) RETVAL < 0)
1759 RETERR = sim_io_get_errno (simulator);
1764 #ifdef TARGET_SYS_exit
1765 case TARGET_SYS_exit:
1766 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1767 /* get signal encoded by kill */
1768 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1769 sim_signalled, PARM1 & 0xffff);
1770 else if (PARM1 == 0xdead)
1772 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1773 sim_stopped, SIM_SIGABRT);
1775 /* PARM1 has exit status */
1776 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1781 #ifdef TARGET_SYS_stat
1782 case TARGET_SYS_stat: /* added at hmsi */
1783 /* stat system call */
1785 struct stat host_stat;
1787 char *path = fetch_str (simulator, PARM1);
1789 RETVAL = sim_io_stat (simulator, path, &host_stat);
1794 /* Just wild-assed guesses. */
1795 store_mem (buf, 2, host_stat.st_dev);
1796 store_mem (buf + 2, 2, host_stat.st_ino);
1797 store_mem (buf + 4, 4, host_stat.st_mode);
1798 store_mem (buf + 8, 2, host_stat.st_nlink);
1799 store_mem (buf + 10, 2, host_stat.st_uid);
1800 store_mem (buf + 12, 2, host_stat.st_gid);
1801 store_mem (buf + 14, 2, host_stat.st_rdev);
1802 store_mem (buf + 16, 4, host_stat.st_size);
1803 store_mem (buf + 20, 4, host_stat.st_atime);
1804 store_mem (buf + 28, 4, host_stat.st_mtime);
1805 store_mem (buf + 36, 4, host_stat.st_ctime);
1807 if ((int) RETVAL < 0)
1808 RETERR = sim_io_get_errno (simulator);
1813 #ifdef TARGET_SYS_fstat
1814 case TARGET_SYS_fstat:
1815 /* fstat system call */
1817 struct stat host_stat;
1820 RETVAL = sim_io_fstat (simulator, PARM1, &host_stat);
1824 /* Just wild-assed guesses. */
1825 store_mem (buf, 2, host_stat.st_dev);
1826 store_mem (buf + 2, 2, host_stat.st_ino);
1827 store_mem (buf + 4, 4, host_stat.st_mode);
1828 store_mem (buf + 8, 2, host_stat.st_nlink);
1829 store_mem (buf + 10, 2, host_stat.st_uid);
1830 store_mem (buf + 12, 2, host_stat.st_gid);
1831 store_mem (buf + 14, 2, host_stat.st_rdev);
1832 store_mem (buf + 16, 4, host_stat.st_size);
1833 store_mem (buf + 20, 4, host_stat.st_atime);
1834 store_mem (buf + 28, 4, host_stat.st_mtime);
1835 store_mem (buf + 36, 4, host_stat.st_ctime);
1837 if ((int) RETVAL < 0)
1838 RETERR = sim_io_get_errno (simulator);
1843 #ifdef TARGET_SYS_rename
1844 case TARGET_SYS_rename:
1846 char *oldpath = fetch_str (simulator, PARM1);
1847 char *newpath = fetch_str (simulator, PARM2);
1848 RETVAL = sim_io_rename (simulator, oldpath, newpath);
1851 if ((int) RETVAL < 0)
1852 RETERR = sim_io_get_errno (simulator);
1857 #ifdef TARGET_SYS_unlink
1858 case TARGET_SYS_unlink:
1860 char *path = fetch_str (simulator, PARM1);
1861 RETVAL = sim_io_unlink (simulator, path);
1863 if ((int) RETVAL < 0)
1864 RETERR = sim_io_get_errno (simulator);
1870 #ifdef TARGET_SYS_chown
1871 case TARGET_SYS_chown:
1873 char *path = fetch_str (simulator, PARM1);
1874 RETVAL = chown (path, PARM2, PARM3);
1883 #ifdef TARGET_SYS_chmod
1884 case TARGET_SYS_chmod:
1886 char *path = fetch_str (simulator, PARM1);
1887 RETVAL = chmod (path, PARM2);
1895 #ifdef TARGET_SYS_time
1897 case TARGET_SYS_time:
1900 RETVAL = time (&now);
1901 store_mem (PARM1, 4, now);
1908 #if !defined(__GO32__) && !defined(_WIN32)
1909 #ifdef TARGET_SYS_times
1910 case TARGET_SYS_times:
1913 RETVAL = times (&tms);
1914 store_mem (PARM1, 4, tms.tms_utime);
1915 store_mem (PARM1 + 4, 4, tms.tms_stime);
1916 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1917 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1924 #ifdef TARGET_SYS_gettimeofday
1925 #if !defined(__GO32__) && !defined(_WIN32)
1926 case TARGET_SYS_gettimeofday:
1930 RETVAL = gettimeofday (&t, &tz);
1931 store_mem (PARM1, 4, t.tv_sec);
1932 store_mem (PARM1 + 4, 4, t.tv_usec);
1933 store_mem (PARM2, 4, tz.tz_minuteswest);
1934 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1941 #ifdef TARGET_SYS_utime
1943 case TARGET_SYS_utime:
1945 /* Cast the second argument to void *, to avoid type mismatch
1946 if a prototype is present. */
1947 sim_io_error (simulator, "Utime not supported");
1948 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1962 { /* Trap 0 -> 30 */
1967 ECR |= 0x40 + OP[0];
1968 /* Flag that we are now doing exception processing. */
1969 PSW |= PSW_EP | PSW_ID;
1970 PC = (OP[0] < 0x10) ? 0x40 : 0x50;
1976 /* tst1 reg2, [reg1] */
1982 trace_input ("tst1", OP_BIT, 1);
1984 temp = load_mem (State.regs[ OP[0] ], 1);
1987 if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0)
1990 trace_output (OP_BIT);
1995 /* mulu reg1, reg2, reg3 */
1999 trace_input ("mulu", OP_REG_REG_REG, 0);
2001 Multiply64 (0, State.regs[ OP[0] ]);
2003 trace_output (OP_REG_REG_REG);
2008 #define BIT_CHANGE_OP( name, binop ) \
2010 unsigned int temp; \
2012 trace_input (name, OP_BIT_CHANGE, 0); \
2014 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
2015 temp = load_mem (State.regs[ OP[0] ], 1); \
2018 if ((temp & bit) == 0) \
2022 store_mem (State.regs[ OP[0] ], 1, temp); \
2024 trace_output (OP_BIT_CHANGE); \
2028 /* clr1 reg2, [reg1] */
2032 BIT_CHANGE_OP ("clr1", &= ~ );
2035 /* not1 reg2, [reg1] */
2039 BIT_CHANGE_OP ("not1", ^= );
2046 BIT_CHANGE_OP ("set1", |= );
2053 trace_input ("sasf", OP_EX1, 0);
2055 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2057 trace_output (OP_EX1);
2062 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
2063 (Soew_Tan@el.nec.com) */
2068 unsigned long int als,
2069 unsigned long int sfi,
2070 unsigned32 /*unsigned long int*/ * quotient_ptr,
2071 unsigned32 /*unsigned long int*/ * remainder_ptr,
2075 unsigned long ald = sfi >> (N - 1);
2076 unsigned long alo = als;
2081 unsigned int R1 = 1;
2082 unsigned int DBZ = (als == 0) ? 1 : 0;
2083 unsigned long alt = Q ? ~als : als;
2086 alo = ald + alt + Q;
2087 C = (((alt >> 31) & (ald >> 31))
2088 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2091 R1 = (alo == 0) ? 0 : (R1 & Q);
2092 if ((S ^ (alo>>31)) && !C)
2097 sfi = (sfi << (32-N+1)) | Q;
2098 ald = (alo << 1) | (sfi >> 31);
2100 /* 2nd - N-1th Loop */
2101 for (i = 2; i < N; i++)
2103 alt = Q ? ~als : als;
2104 alo = ald + alt + Q;
2105 C = (((alt >> 31) & (ald >> 31))
2106 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2109 R1 = (alo == 0) ? 0 : (R1 & Q);
2110 if ((S ^ (alo>>31)) && !C && !DBZ)
2115 sfi = (sfi << 1) | Q;
2116 ald = (alo << 1) | (sfi >> 31);
2120 alt = Q ? ~als : als;
2121 alo = ald + alt + Q;
2122 C = (((alt >> 31) & (ald >> 31))
2123 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2126 R1 = (alo == 0) ? 0 : (R1 & Q);
2127 if ((S ^ (alo>>31)) && !C)
2132 * quotient_ptr = (sfi << 1) | Q;
2133 * remainder_ptr = Q ? alo : (alo + als);
2134 * overflow_ptr = DBZ | R1;
2137 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2142 unsigned long int als,
2143 unsigned long int sfi,
2144 signed32 /*signed long int*/ * quotient_ptr,
2145 signed32 /*signed long int*/ * remainder_ptr,
2149 unsigned long ald = (signed long) sfi >> (N - 1);
2150 unsigned long alo = als;
2151 unsigned int SS = als >> 31;
2152 unsigned int SD = sfi >> 31;
2153 unsigned int R1 = 1;
2155 unsigned int DBZ = als == 0 ? 1 : 0;
2156 unsigned int Q = ~(SS ^ SD) & 1;
2160 unsigned long alt = Q ? ~als : als;
2165 alo = ald + alt + Q;
2166 C = (((alt >> 31) & (ald >> 31))
2167 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2169 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2171 sfi = (sfi << (32-N+1)) | Q;
2172 ald = (alo << 1) | (sfi >> 31);
2173 if ((alo >> 31) ^ (ald >> 31))
2178 /* 2nd - N-1th Loop */
2180 for (i = 2; i < N; i++)
2182 alt = Q ? ~als : als;
2183 alo = ald + alt + Q;
2184 C = (((alt >> 31) & (ald >> 31))
2185 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2187 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2189 sfi = (sfi << 1) | Q;
2190 ald = (alo << 1) | (sfi >> 31);
2191 if ((alo >> 31) ^ (ald >> 31))
2198 alt = Q ? ~als : als;
2199 alo = ald + alt + Q;
2200 C = (((alt >> 31) & (ald >> 31))
2201 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2203 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2204 sfi = (sfi << (32-N+1));
2210 alt = Q ? ~als : als;
2211 alo = ald + alt + Q;
2213 R1 = R1 & ((~alo >> 31) ^ SD);
2214 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2216 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2218 ald = sfi = sfi | Q;
2220 OV = DBZ | ((alo == 0) ? 0 : R1);
2222 * remainder_ptr = alo;
2225 if (((alo != 0) && ((SS ^ SD) ^ R1))
2226 || ((alo == 0) && (SS ^ R1)))
2231 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2233 * quotient_ptr = alo;
2234 * overflow_ptr = OV;
2237 /* sdivun imm5, reg1, reg2, reg3 */
2241 unsigned32 /*unsigned long int*/ quotient;
2242 unsigned32 /*unsigned long int*/ remainder;
2243 unsigned long int divide_by;
2244 unsigned long int divide_this;
2248 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2250 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2252 divide_by = State.regs[ OP[0] ];
2253 divide_this = State.regs[ OP[1] ] << imm5;
2255 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2257 State.regs[ OP[1] ] = quotient;
2258 State.regs[ OP[2] >> 11 ] = remainder;
2260 /* Set condition codes. */
2261 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2263 if (overflow) PSW |= PSW_OV;
2264 if (quotient == 0) PSW |= PSW_Z;
2265 if (quotient & 0x80000000) PSW |= PSW_S;
2267 trace_output (OP_IMM_REG_REG_REG);
2272 /* sdivn imm5, reg1, reg2, reg3 */
2276 signed32 /*signed long int*/ quotient;
2277 signed32 /*signed long int*/ remainder;
2278 signed long int divide_by;
2279 signed long int divide_this;
2283 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2285 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2287 divide_by = (signed32) State.regs[ OP[0] ];
2288 divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
2290 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2292 State.regs[ OP[1] ] = quotient;
2293 State.regs[ OP[2] >> 11 ] = remainder;
2295 /* Set condition codes. */
2296 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2298 if (overflow) PSW |= PSW_OV;
2299 if (quotient == 0) PSW |= PSW_Z;
2300 if (quotient < 0) PSW |= PSW_S;
2302 trace_output (OP_IMM_REG_REG_REG);
2307 /* sdivhun imm5, reg1, reg2, reg3 */
2311 unsigned32 /*unsigned long int*/ quotient;
2312 unsigned32 /*unsigned long int*/ remainder;
2313 unsigned long int divide_by;
2314 unsigned long int divide_this;
2318 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2320 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2322 divide_by = State.regs[ OP[0] ] & 0xffff;
2323 divide_this = State.regs[ OP[1] ] << imm5;
2325 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2327 State.regs[ OP[1] ] = quotient;
2328 State.regs[ OP[2] >> 11 ] = remainder;
2330 /* Set condition codes. */
2331 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2333 if (overflow) PSW |= PSW_OV;
2334 if (quotient == 0) PSW |= PSW_Z;
2335 if (quotient & 0x80000000) PSW |= PSW_S;
2337 trace_output (OP_IMM_REG_REG_REG);
2342 /* sdivhn imm5, reg1, reg2, reg3 */
2346 signed32 /*signed long int*/ quotient;
2347 signed32 /*signed long int*/ remainder;
2348 signed long int divide_by;
2349 signed long int divide_this;
2353 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2355 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2357 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2358 divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
2360 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2362 State.regs[ OP[1] ] = quotient;
2363 State.regs[ OP[2] >> 11 ] = remainder;
2365 /* Set condition codes. */
2366 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2368 if (overflow) PSW |= PSW_OV;
2369 if (quotient == 0) PSW |= PSW_Z;
2370 if (quotient < 0) PSW |= PSW_S;
2372 trace_output (OP_IMM_REG_REG_REG);
2377 /* divu reg1, reg2, reg3 */
2381 unsigned long int quotient;
2382 unsigned long int remainder;
2383 unsigned long int divide_by;
2384 unsigned long int divide_this;
2387 trace_input ("divu", OP_REG_REG_REG, 0);
2389 /* Compute the result. */
2391 divide_by = State.regs[ OP[0] ];
2392 divide_this = State.regs[ OP[1] ];
2400 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2401 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2403 /* Set condition codes. */
2404 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2406 if (overflow) PSW |= PSW_OV;
2407 if (quotient == 0) PSW |= PSW_Z;
2408 if (quotient & 0x80000000) PSW |= PSW_S;
2411 trace_output (OP_REG_REG_REG);
2416 /* div reg1, reg2, reg3 */
2420 signed long int quotient;
2421 signed long int remainder;
2422 signed long int divide_by;
2423 signed long int divide_this;
2425 trace_input ("div", OP_REG_REG_REG, 0);
2427 /* Compute the result. */
2429 divide_by = (signed32) State.regs[ OP[0] ];
2430 divide_this = State.regs[ OP[1] ];
2436 else if (divide_by == -1 && divide_this == (1L << 31))
2439 PSW |= PSW_OV | PSW_S;
2440 State.regs[ OP[1] ] = (1 << 31);
2441 State.regs[ OP[2] >> 11 ] = 0;
2445 divide_this = (signed32) divide_this;
2446 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2447 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2449 /* Set condition codes. */
2450 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2452 if (quotient == 0) PSW |= PSW_Z;
2453 if (quotient < 0) PSW |= PSW_S;
2456 trace_output (OP_REG_REG_REG);
2461 /* divhu reg1, reg2, reg3 */
2465 unsigned long int quotient;
2466 unsigned long int remainder;
2467 unsigned long int divide_by;
2468 unsigned long int divide_this;
2471 trace_input ("divhu", OP_REG_REG_REG, 0);
2473 /* Compute the result. */
2475 divide_by = State.regs[ OP[0] ] & 0xffff;
2476 divide_this = State.regs[ OP[1] ];
2484 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2485 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2487 /* Set condition codes. */
2488 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2490 if (overflow) PSW |= PSW_OV;
2491 if (quotient == 0) PSW |= PSW_Z;
2492 if (quotient & 0x80000000) PSW |= PSW_S;
2495 trace_output (OP_REG_REG_REG);
2500 /* divh reg1, reg2, reg3 */
2504 signed long int quotient;
2505 signed long int remainder;
2506 signed long int divide_by;
2507 signed long int divide_this;
2510 trace_input ("divh", OP_REG_REG_REG, 0);
2512 /* Compute the result. */
2514 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2515 divide_this = State.regs[ OP[1] ];
2521 else if (divide_by == -1 && divide_this == (1L << 31))
2524 PSW |= PSW_OV | PSW_S;
2525 State.regs[ OP[1] ] = (1 << 31);
2526 State.regs[ OP[2] >> 11 ] = 0;
2530 divide_this = (signed32) divide_this;
2531 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2532 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2534 /* Set condition codes. */
2535 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2537 if (quotient == 0) PSW |= PSW_Z;
2538 if (quotient < 0) PSW |= PSW_S;
2541 trace_output (OP_REG_REG_REG);
2546 /* mulu imm9, reg2, reg3 */
2550 trace_input ("mulu", OP_IMM_REG_REG, 0);
2552 Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2554 trace_output (OP_IMM_REG_REG);
2559 /* mul imm9, reg2, reg3 */
2563 trace_input ("mul", OP_IMM_REG_REG, 0);
2565 Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
2567 trace_output (OP_IMM_REG_REG);
2578 trace_input ("ld.hu", OP_LOAD32, 2);
2580 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2583 State.regs[ OP[1] ] = load_mem (adr, 2);
2585 trace_output (OP_LOAD32);
2597 trace_input ("ld.bu", OP_LOAD32, 1);
2599 adr = (State.regs[ OP[0] ]
2600 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2602 State.regs[ OP[1] ] = load_mem (adr, 1);
2604 trace_output (OP_LOAD32);
2609 /* prepare list12, imm5, imm32 */
2615 trace_input ("prepare", OP_PUSHPOP1, 0);
2617 /* Store the registers with lower number registers being placed at higher addresses. */
2618 for (i = 0; i < 12; i++)
2619 if ((OP[3] & (1 << type1_regs[ i ])))
2622 store_mem (SP, 4, State.regs[ 20 + i ]);
2625 SP -= (OP[3] & 0x3e) << 1;
2627 EP = load_mem (PC + 4, 4);
2629 trace_output (OP_PUSHPOP1);
2634 /* prepare list12, imm5, imm16-32 */
2640 trace_input ("prepare", OP_PUSHPOP1, 0);
2642 /* Store the registers with lower number registers being placed at higher addresses. */
2643 for (i = 0; i < 12; i++)
2644 if ((OP[3] & (1 << type1_regs[ i ])))
2647 store_mem (SP, 4, State.regs[ 20 + i ]);
2650 SP -= (OP[3] & 0x3e) << 1;
2652 EP = load_mem (PC + 4, 2) << 16;
2654 trace_output (OP_PUSHPOP1);
2659 /* prepare list12, imm5, imm16 */
2665 trace_input ("prepare", OP_PUSHPOP1, 0);
2667 /* Store the registers with lower number registers being placed at higher addresses. */
2668 for (i = 0; i < 12; i++)
2669 if ((OP[3] & (1 << type1_regs[ i ])))
2672 store_mem (SP, 4, State.regs[ 20 + i ]);
2675 SP -= (OP[3] & 0x3e) << 1;
2677 EP = EXTEND16 (load_mem (PC + 4, 2));
2679 trace_output (OP_PUSHPOP1);
2684 /* prepare list12, imm5, sp */
2690 trace_input ("prepare", OP_PUSHPOP1, 0);
2692 /* Store the registers with lower number registers being placed at higher addresses. */
2693 for (i = 0; i < 12; i++)
2694 if ((OP[3] & (1 << type1_regs[ i ])))
2697 store_mem (SP, 4, State.regs[ 20 + i ]);
2700 SP -= (OP[3] & 0x3e) << 1;
2704 trace_output (OP_PUSHPOP1);
2709 /* mul reg1, reg2, reg3 */
2713 trace_input ("mul", OP_REG_REG_REG, 0);
2715 Multiply64 (1, State.regs[ OP[0] ]);
2717 trace_output (OP_REG_REG_REG);
2728 trace_input ("popmh", OP_PUSHPOP2, 0);
2730 if (OP[3] & (1 << 19))
2732 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2734 FEPSW = load_mem ( SP & ~ 3, 4);
2735 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2739 EIPSW = load_mem ( SP & ~ 3, 4);
2740 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2746 /* Load the registers with lower number registers being retrieved from higher addresses. */
2748 if ((OP[3] & (1 << type2_regs[ i ])))
2750 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2754 trace_output (OP_PUSHPOP2);
2765 trace_input ("popml", OP_PUSHPOP3, 0);
2767 if (OP[3] & (1 << 19))
2769 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2771 FEPSW = load_mem ( SP & ~ 3, 4);
2772 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2776 EIPSW = load_mem ( SP & ~ 3, 4);
2777 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2783 if (OP[3] & (1 << 3))
2785 PSW = load_mem (SP & ~ 3, 4);
2789 /* Load the registers with lower number registers being retrieved from higher addresses. */
2791 if ((OP[3] & (1 << type3_regs[ i ])))
2793 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2797 trace_output (OP_PUSHPOP2);
2808 trace_input ("pushmh", OP_PUSHPOP2, 0);
2810 /* Store the registers with lower number registers being placed at higher addresses. */
2811 for (i = 0; i < 16; i++)
2812 if ((OP[3] & (1 << type2_regs[ i ])))
2815 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2818 if (OP[3] & (1 << 19))
2822 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2824 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2825 store_mem ( SP & ~ 3, 4, FEPSW);
2829 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2830 store_mem ( SP & ~ 3, 4, EIPSW);
2834 trace_output (OP_PUSHPOP2);
2839 /* V850E2R FPU functions */
2841 sim_fpu_status_invalid_snan = 1, -V--- (sim spec.)
2842 sim_fpu_status_invalid_qnan = 2, ----- (sim spec.)
2843 sim_fpu_status_invalid_isi = 4, (inf - inf) -V---
2844 sim_fpu_status_invalid_idi = 8, (inf / inf) -V---
2845 sim_fpu_status_invalid_zdz = 16, (0 / 0) -V---
2846 sim_fpu_status_invalid_imz = 32, (inf * 0) -V---
2847 sim_fpu_status_invalid_cvi = 64, convert to integer -V---
2848 sim_fpu_status_invalid_div0 = 128, (X / 0) --Z--
2849 sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.)
2850 sim_fpu_status_invalid_sqrt = 512, -V---
2851 sim_fpu_status_rounded = 1024, I----
2852 sim_fpu_status_inexact = 2048, I---- (sim spec.)
2853 sim_fpu_status_overflow = 4096, I--O-
2854 sim_fpu_status_underflow = 8192, I---U
2855 sim_fpu_status_denorm = 16384, ----U (sim spec.)
2859 update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p)
2861 unsigned int fpsr = FPSR & mask;
2863 unsigned int flags = 0;
2866 && ((status & (sim_fpu_status_rounded
2867 | sim_fpu_status_overflow
2868 | sim_fpu_status_inexact))
2869 || (status & sim_fpu_status_underflow
2870 && (fpsr & (FPSR_XEU | FPSR_XEI)) == 0
2871 && fpsr & FPSR_FS)))
2873 flags |= FPSR_XCI | FPSR_XPI;
2877 && (status & (sim_fpu_status_invalid_isi
2878 | sim_fpu_status_invalid_imz
2879 | sim_fpu_status_invalid_zdz
2880 | sim_fpu_status_invalid_idi
2881 | sim_fpu_status_invalid_cvi
2882 | sim_fpu_status_invalid_sqrt
2883 | sim_fpu_status_invalid_snan)))
2885 flags |= FPSR_XCV | FPSR_XPV;
2889 && (status & sim_fpu_status_invalid_div0))
2891 flags |= FPSR_XCV | FPSR_XPV;
2895 && (status & sim_fpu_status_overflow))
2897 flags |= FPSR_XCO | FPSR_XPO;
2900 if (((fpsr & FPSR_XEU) || (fpsr & FPSR_FS) == 0)
2901 && (status & (sim_fpu_status_underflow
2902 | sim_fpu_status_denorm)))
2904 flags |= FPSR_XCU | FPSR_XPU;
2912 SignalExceptionFPE (sd, double_op_p);
2919 SignalException (SIM_DESC sd)
2923 PSW = PSW & ~(PSW_NPV | PSW_DMP | PSW_IMP);
2928 SignalExceptionFPE (SIM_DESC sd, unsigned int double_op_p)
2930 if (((PSW & (PSW_NP|PSW_ID)) == 0)
2931 || !(FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM)))
2935 EIIC = (FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM))
2937 PSW |= (PSW_EP | PSW_ID);
2940 SignalException (sd);
2945 check_invalid_snan (SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p)
2947 if ((FPSR & FPSR_XEI)
2948 && (status & sim_fpu_status_invalid_snan))
2953 SignalExceptionFPE (sd, double_op_p);
2958 v850_float_compare (SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p)
2962 if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2))
2966 if (FPSR & FPSR_XEV)
2968 FPSR |= FPSR_XCV | FPSR_XPV;
2969 SignalExceptionFPE (sd, double_op_p);
3027 else if (sim_fpu_is_infinity (&wop1) && sim_fpu_is_infinity (&wop2)
3028 && sim_fpu_sign (&wop1) == sim_fpu_sign (&wop2))
3086 int gt = 0,lt = 0,eq = 0, status;
3088 status = sim_fpu_cmp (&wop1, &wop2);
3092 case SIM_FPU_IS_SNAN:
3093 case SIM_FPU_IS_QNAN:
3097 case SIM_FPU_IS_NINF:
3100 case SIM_FPU_IS_PINF:
3103 case SIM_FPU_IS_NNUMBER:
3106 case SIM_FPU_IS_PNUMBER:
3109 case SIM_FPU_IS_NDENORM:
3112 case SIM_FPU_IS_PDENORM:
3115 case SIM_FPU_IS_NZERO:
3116 case SIM_FPU_IS_PZERO:
3174 ASSERT (result != -1);
3179 v850_div (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3181 signed long int quotient;
3182 signed long int remainder;
3183 signed long int divide_by;
3184 signed long int divide_this;
3185 bfd_boolean overflow = FALSE;
3187 /* Compute the result. */
3191 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3197 quotient = divide_this / divide_by;
3198 remainder = divide_this % divide_by;
3200 /* Set condition codes. */
3201 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3203 if (overflow) PSW |= PSW_OV;
3204 if (quotient == 0) PSW |= PSW_Z;
3205 if (quotient < 0) PSW |= PSW_S;
3212 v850_divu (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3214 unsigned long int quotient;
3215 unsigned long int remainder;
3216 unsigned long int divide_by;
3217 unsigned long int divide_this;
3218 bfd_boolean overflow = FALSE;
3220 /* Compute the result. */
3231 quotient = divide_this / divide_by;
3232 remainder = divide_this % divide_by;
3234 /* Set condition codes. */
3235 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3237 if (overflow) PSW |= PSW_OV;
3238 if (quotient == 0) PSW |= PSW_Z;
3239 if (quotient & 0x80000000) PSW |= PSW_S;
3246 v850_sar (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3248 unsigned int result, z, s, cy;
3251 result = (signed)op1 >> op0;
3253 /* Compute the condition codes. */
3255 s = (result & 0x80000000);
3256 cy = (op1 & (1 << (op0 - 1)));
3258 /* Store the result and condition codes. */
3259 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3260 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3261 | (cy ? PSW_CY : 0));
3267 v850_shl (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3269 unsigned int result, z, s, cy;
3272 result = op1 << op0;
3274 /* Compute the condition codes. */
3276 s = (result & 0x80000000);
3277 cy = (op1 & (1 << (32 - op0)));
3279 /* Store the result and condition codes. */
3280 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3281 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3282 | (cy ? PSW_CY : 0));
3288 v850_rotl (SIM_DESC sd, unsigned int amount, unsigned int src, unsigned int * dest)
3290 unsigned int result, z, s, cy;
3293 result = src << amount;
3294 result |= src >> (32 - amount);
3296 /* Compute the condition codes. */
3298 s = (result & 0x80000000);
3299 cy = ! (result & 1);
3301 /* Store the result and condition codes. */
3302 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3303 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3304 | (cy ? PSW_CY : 0));
3310 v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb,
3311 unsigned int * dest)
3314 unsigned int result, pos, width;
3318 width = (msb - lsb) + 1;
3320 mask = ~ (-(1 << width));
3323 result = (* dest) & ~ mask;
3324 result |= source << pos;
3326 /* Compute the condition codes. */
3328 s = result & 0x80000000;
3330 /* Store the result and condition codes. */
3331 PSW &= ~(PSW_Z | PSW_S | PSW_OV );
3332 PSW |= (z ? PSW_Z : 0) | (s ? PSW_S : 0);
3338 v850_shr (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3340 unsigned int result, z, s, cy;
3343 result = op1 >> op0;
3345 /* Compute the condition codes. */
3347 s = (result & 0x80000000);
3348 cy = (op1 & (1 << (op0 - 1)));
3350 /* Store the result and condition codes. */
3351 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3352 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3353 | (cy ? PSW_CY : 0));
3359 v850_satadd (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3361 unsigned int result, z, s, cy, ov, sat;
3365 /* Compute the condition codes. */
3367 s = (result & 0x80000000);
3368 cy = (result < op0 || result < op1);
3369 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
3370 && (op0 & 0x80000000) != (result & 0x80000000));
3373 /* Store the result and condition codes. */
3374 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3375 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3376 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3377 | (sat ? PSW_SAT : 0));
3379 /* Handle saturated results. */
3382 result = 0x7fffffff;
3387 result = 0x80000000;
3395 v850_satsub (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3397 unsigned int result, z, s, cy, ov, sat;
3399 /* Compute the result. */
3402 /* Compute the condition codes. */
3404 s = (result & 0x80000000);
3406 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
3407 && (op1 & 0x80000000) != (result & 0x80000000));
3410 /* Store the result and condition codes. */
3411 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3412 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3413 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3414 | (sat ? PSW_SAT : 0));
3416 /* Handle saturated results. */
3419 result = 0x7fffffff;
3424 result = 0x80000000;
3432 load_data_mem (SIM_DESC sd,
3441 data = sim_core_read_unaligned_1 (STATE_CPU (sd, 0),
3442 PC, read_map, addr);
3445 data = sim_core_read_unaligned_2 (STATE_CPU (sd, 0),
3446 PC, read_map, addr);
3449 data = sim_core_read_unaligned_4 (STATE_CPU (sd, 0),
3450 PC, read_map, addr);
3459 store_data_mem (SIM_DESC sd,
3467 store_mem (addr, 1, data);
3470 store_mem (addr, 2, data);
3473 store_mem (addr, 4, data);
3481 mpu_load_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
3487 if (IPE0 && addr >= IPA2ADDR (IPA0L) && addr <= IPA2ADDR (IPA0L) && IPR0)
3491 else if (IPE1 && addr >= IPA2ADDR (IPA1L) && addr <= IPA2ADDR (IPA1L) && IPR1)
3495 else if (IPE2 && addr >= IPA2ADDR (IPA2L) && addr <= IPA2ADDR (IPA2L) && IPR2)
3499 else if (IPE3 && addr >= IPA2ADDR (IPA3L) && addr <= IPA2ADDR (IPA3L) && IPR3)
3503 else if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3505 /* preifarallel area */
3507 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
3511 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPR0
3512 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3516 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPR1
3517 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3521 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPR2
3522 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3526 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPR3
3527 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3533 VMECR &= ~(VMECR_VMW | VMECR_VMX);
3541 SignalException (sd);
3550 mpu_store_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
3556 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3558 /* preifarallel area */
3560 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
3564 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPW0
3565 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3569 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPW1
3570 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3574 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPW2
3575 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3579 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPW3
3580 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3586 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3601 VMECR &= ~(VMECR_VMW | VMECR_VMX);