1 # Hitachi H8 testcase 'sub.l'
2 # mach(): h8300h h8300s h8sx
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
15 .if (sim_cpu == h8sx) ;
16 sub_l_imm3: ; 3-bit immediate mode only for h8sx
17 set_grs_a5a5 ; Fill all general regs with a fixed pattern
20 ;; sub.l #xx:3,eRd ; Immediate 3-bit operand
23 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
24 test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7
25 test_gr_a5a5 1 ; Make sure other general regs not disturbed
33 sub_l_imm16: ; sub immediate 16-bit value
34 set_grs_a5a5 ; Fill all general regs with a fixed pattern
37 ;; sub.l #xx:16,eRd ; Immediate 16-bit operand
40 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
41 test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111
42 test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111
43 test_gr_a5a5 1 ; Make sure other general regs not disturbed
54 ;; sub.l immediate not available in h8300 mode.
55 set_grs_a5a5 ; Fill all general regs with a fixed pattern
59 sub.l #0x11111111, er0 ; Immediate 32-bit operand
61 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
62 test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
63 test_gr_a5a5 1 ; Make sure other general regs not disturbed
72 set_grs_a5a5 ; Fill all general regs with a fixed pattern
76 mov.l #0x11111111, er1
77 sub.l er1, er0 ; Register operand
79 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
80 test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111
81 test_h_gr32 0x11111111 er1
82 test_gr_a5a5 2 ; Make sure other general regs not disturbed