1 # Hitachi H8 testcase 'stc'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
44 ldc #0xff, ccr ; test value
45 stc ccr, r0h ; copy test value to r0h
47 test_h_gr16 0xffa5 r0 ; ff in r0h, a5 in r0l
48 .if (sim_cpu) ; h/s/sx
49 test_h_gr32 0xa5a5ffa5 er0 ; ff in r0h, a5 everywhere else
51 test_gr_a5a5 1 ; Make sure other general regs not disturbed
59 .if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
64 ldc #0x87, exr ; set exr to 0x87
65 stc exr, r0l ; retrieve and check exr value
70 test_h_gr32 0xa5a5a587 er0 ; Register 0 modified by test procedure.
71 test_gr_a5a5 1 ; Make sure other general regs not disturbed
84 stc ccr, @byte_dest1:16 ; abs16 dest
86 test_gr_a5a5 0 ; Make sure other general regs not disturbed
100 stc exr, @byte_dest2:16 ; abs16 dest
102 test_gr_a5a5 0 ; Make sure other general regs not disturbed
116 stc ccr, @byte_dest3:32 ; abs32 dest
118 test_gr_a5a5 0 ; Make sure other general regs not disturbed
132 stc exr, @byte_dest4:32 ; abs32 dest
134 test_gr_a5a5 0 ; Make sure other general regs not disturbed
149 stc ccr, @(1:16,er1) ; disp16 dest (5)
151 test_h_gr32 byte_dest4, er1 ; er1 still contains address
153 test_gr_a5a5 0 ; Make sure other general regs not disturbed
167 stc exr, @(-1:16,er1) ; disp16 dest (6)
169 test_h_gr32 byte_dest7, er1 ; er1 still contains address
171 test_gr_a5a5 0 ; Make sure other general regs not disturbed
185 stc ccr, @(1:32,er1) ; disp32 dest (7)
187 test_h_gr32 byte_dest6, er1 ; er1 still contains address
189 test_gr_a5a5 0 ; Make sure other general regs not disturbed
203 stc exr, @(-1:32,er1) ; disp16 dest (8)
205 test_h_gr32 byte_dest9, er1 ; er1 still contains address
207 test_gr_a5a5 2 ; Make sure other general regs not disturbed
218 mov #byte_dest10, er1
220 stc ccr, @-er1 ; predecr dest (9)
222 test_h_gr32 byte_dest9, er1 ; er1 still contains address
224 test_gr_a5a5 0 ; Make sure other general regs not disturbed
236 mov #byte_dest11, er1
238 stc exr, @-er1 ; predecr dest (10)
240 test_h_gr32 byte_dest10, er1 ; er1 still contains address
242 test_gr_a5a5 0 ; Make sure other general regs not disturbed
254 mov #byte_dest11, er1
256 stc ccr, @er1 ; postinc dest (11)
258 test_h_gr32 byte_dest11, er1 ; er1 still contains address
260 test_gr_a5a5 0 ; Make sure other general regs not disturbed
272 mov #byte_dest12, er1
274 stc exr, @er1, exr ; postinc dest (12)
276 test_h_gr32 byte_dest12, er1 ; er1 still contains address
278 test_gr_a5a5 0 ; Make sure other general regs not disturbed
288 .if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
294 ldc er0, sbr ; set sbr to 0xaaaaaaaa
295 stc sbr, er1 ; retreive and check sbr value
297 test_h_gr32 0xaaaaaaaa er1
298 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
299 test_gr_a5a5 2 ; Make sure other general regs not disturbed
311 ldc er0, vbr ; set sbr to 0xaaaaaaaa
312 stc vbr, er1 ; retreive and check sbr value
314 test_h_gr32 0xaaaaaaaa er1
315 test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
316 test_gr_a5a5 2 ; Make sure other general regs not disturbed
330 .L1: mov @byte_dest2, r0h
335 .L2: mov @byte_dest3, r0h
340 .L3: mov @byte_dest4, r0h
345 .L4: mov @byte_dest5, r0h
350 .L5: mov @byte_dest6, r0h
355 .L6: mov @byte_dest7, r0h
360 .L7: mov @byte_dest8, r0h
365 .L8: mov @byte_dest9, r0h
370 .L9: mov @byte_dest10, r0h
375 .L10: mov @byte_dest11, r0h
380 .L11: mov @byte_dest12, r0h