1 # Hitachi H8 testcase 'shal'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
18 word_dest: .word 0xa5a5
20 long_dest: .long 0xa5a5a5a5
25 set_grs_a5a5 ; Fill all general regs with a fixed pattern
28 shal.b r0l ; shift left arithmetic by one
31 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
33 ; test_ovf_clear ; FIXME
35 test_h_gr16 0xa54a r0 ; 1010 0101 -> 0100 1010
37 test_h_gr32 0xa5a5a54a er0
39 test_gr_a5a5 1 ; Make sure other general regs not disturbed
48 set_grs_a5a5 ; Fill all general regs with a fixed pattern
51 shal.b #2, r0l ; shift left arithmetic by two
54 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
56 ; test_ovf_clear ; FIXME
59 test_h_gr16 0xa594 r0 ; 1010 0101 -> 1001 0100
61 test_h_gr32 0xa5a5a594 er0
63 test_gr_a5a5 1 ; Make sure other general regs not disturbed
71 .if (sim_cpu) ; Not available in h8300 mode
73 set_grs_a5a5 ; Fill all general regs with a fixed pattern
76 shal.w r0 ; shift left arithmetic by one
79 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
81 ; test_ovf_clear ; FIXME
83 test_h_gr16 0x4b4a r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1010
84 test_h_gr32 0xa5a54b4a er0
86 test_gr_a5a5 1 ; Make sure other general regs not disturbed
95 set_grs_a5a5 ; Fill all general regs with a fixed pattern
98 shal.w #2, r0 ; shift left arithmetic by two
101 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
103 ; test_ovf_clear ; FIXME
105 test_h_gr16 0x9694 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0100
106 test_h_gr32 0xa5a59694 er0
108 test_gr_a5a5 1 ; Make sure other general regs not disturbed
117 set_grs_a5a5 ; Fill all general regs with a fixed pattern
120 shal.l er0 ; shift left arithmetic by one
123 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
125 ; test_ovf_clear ; FIXME
127 ; 1010 0101 1010 0101 1010 0101 1010 0101
128 ; -> 0100 1011 0100 1011 0100 1011 0100 1010
129 test_h_gr32 0x4b4b4b4a er0
131 test_gr_a5a5 1 ; Make sure other general regs not disturbed
140 set_grs_a5a5 ; Fill all general regs with a fixed pattern
143 shal.l #2, er0 ; shift left arithmetic by two
146 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
148 ; test_ovf_clear ; FIXME
150 ; 1010 0101 1010 0101 1010 0101 1010 0101
151 ; -> 1001 0110 1001 0110 1001 0110 1001 0100
152 test_h_gr32 0x96969694 er0
154 test_gr_a5a5 1 ; Make sure other general regs not disturbed