1 # Hitachi H8 testcase 'rotl'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
18 word_dest: .word 0xa5a5
20 long_dest: .long 0xa5a5a5a5
25 set_grs_a5a5 ; Fill all general regs with a fixed pattern
28 rotl.b r0l ; shift left arithmetic by one
30 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
34 test_h_gr16 0xa54b r0 ; 1010 0101 -> 0100 1011
36 test_h_gr32 0xa5a5a54b er0
38 test_gr_a5a5 1 ; Make sure other general regs not disturbed
48 set_grs_a5a5 ; Fill all general regs with a fixed pattern
52 rotl.b @er0 ; shift right arithmetic by one, indirect
54 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
59 test_h_gr32 byte_dest er0
60 test_gr_a5a5 1 ; Make sure other general regs not disturbed
67 ; 1010 0101 -> 0100 1011
68 cmp.b #0x4b, @byte_dest
72 mov.b #0xa5, @byte_dest
75 set_grs_a5a5 ; Fill all general regs with a fixed pattern
79 rotl.b @(byte_dest-5:16, r0.b) ; indexed byte/byte
81 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
86 test_h_gr32 0xa5a5a505 er0
87 test_gr_a5a5 1 ; Make sure other general regs not disturbed
94 ; 1010 0101 -> 0100 1011
95 cmp.b #0x4b, @byte_dest
99 mov.b #0xa5, @byte_dest
102 set_grs_a5a5 ; Fill all general regs with a fixed pattern
106 rotl.b @(byte_dest-256:16, r0.w) ; indexed byte/word
108 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
113 test_h_gr32 0xa5a50100 er0
114 test_gr_a5a5 1 ; Make sure other general regs not disturbed
121 ; 1010 0101 -> 0100 1011
122 cmp.b #0x4b, @byte_dest
126 mov.b #0xa5, @byte_dest
129 set_grs_a5a5 ; Fill all general regs with a fixed pattern
132 mov.l #0xffffffff, er0
133 rotl.b @(byte_dest+1:16, er0.l) ; indexed byte/long
135 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
140 test_h_gr32 0xffffffff er0
141 test_gr_a5a5 1 ; Make sure other general regs not disturbed
148 ; 1010 0101 -> 0100 1011
149 cmp.b #0x4b, @byte_dest
153 mov.b #0xa5, @byte_dest
156 set_grs_a5a5 ; Fill all general regs with a fixed pattern
160 rotl.b @(byte_dest-5:32, r1.b) ; indexed byte/byte
162 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
167 test_h_gr32 0xa5a5a505 er1
168 test_gr_a5a5 0 ; Make sure other general regs not disturbed
175 ; 1010 0101 -> 0100 1011
176 cmp.b #0x4b, @byte_dest
180 mov.b #0xa5, @byte_dest
183 set_grs_a5a5 ; Fill all general regs with a fixed pattern
187 rotl.b @(byte_dest-256:32, r1.w) ; indexed byte/word
189 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
194 test_h_gr32 0xa5a50100 er1
195 test_gr_a5a5 0 ; Make sure other general regs not disturbed
202 ; 1010 0101 -> 0100 1011
203 cmp.b #0x4b, @byte_dest
207 mov.b #0xa5, @byte_dest
210 set_grs_a5a5 ; Fill all general regs with a fixed pattern
213 mov.l #0xffffffff, er1
214 rotl.b @(byte_dest+1:32, er1.l) ; indexed byte/long
216 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
221 test_h_gr32 0xffffffff er1
222 test_gr_a5a5 0 ; Make sure other general regs not disturbed
229 ; 1010 0101 -> 0100 1011
230 cmp.b #0x4b, @byte_dest
234 mov.b #0xa5, @byte_dest
239 set_grs_a5a5 ; Fill all general regs with a fixed pattern
242 rotl.b #2, r0l ; shift left arithmetic by two
244 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
249 test_h_gr16 0xa596 r0 ; 1010 0101 -> 1001 0110
251 test_h_gr32 0xa5a5a596 er0
253 test_gr_a5a5 1 ; Make sure other general regs not disturbed
261 .if (sim_cpu == h8sx)
263 set_grs_a5a5 ; Fill all general regs with a fixed pattern
267 rotl.b #2, @er0 ; shift right arithmetic by one, indirect
269 test_carry_clear ; H=0 N=1 Z=0 C=0
274 test_h_gr32 byte_dest er0
275 test_gr_a5a5 1 ; Make sure other general regs not disturbed
282 ; 1010 0101 -> 1001 0110
283 cmp.b #0x96, @byte_dest
287 mov.b #0xa5, @byte_dest
290 set_grs_a5a5 ; Fill all general regs with a fixed pattern
294 rotl.b #2, @(byte_dest-5:16, r0.b) ; indexed byte/byte
296 test_carry_clear ; H=0 N=1 Z=0 C=0
301 test_h_gr32 0xa5a5a505 er0
302 test_gr_a5a5 1 ; Make sure other general regs not disturbed
309 ; 1010 0101 -> 1001 0110
310 cmp.b #0x96, @byte_dest
314 mov.b #0xa5, @byte_dest
317 set_grs_a5a5 ; Fill all general regs with a fixed pattern
321 rotl.b #2, @(byte_dest-256:16, r0.w) ; indexed byte/word
323 test_carry_clear ; H=0 N=1 Z=0 C=0
328 test_h_gr32 0xa5a50100 er0
329 test_gr_a5a5 1 ; Make sure other general regs not disturbed
336 ; 1010 0101 -> 1001 0110
337 cmp.b #0x96, @byte_dest
341 mov.b #0xa5, @byte_dest
344 set_grs_a5a5 ; Fill all general regs with a fixed pattern
347 mov.l #0xffffffff, er0
348 rotl.b #2, @(byte_dest+1:16, er0.l) ; indexed byte/long
350 test_carry_clear ; H=0 N=1 Z=0 C=0
355 test_h_gr32 0xffffffff er0
356 test_gr_a5a5 1 ; Make sure other general regs not disturbed
363 ; 1010 0101 -> 1001 0110
364 cmp.b #0x96, @byte_dest
368 mov.b #0xa5, @byte_dest
371 set_grs_a5a5 ; Fill all general regs with a fixed pattern
375 rotl.b #2, @(byte_dest-5:32, r1.b) ; indexed byte/byte
377 test_carry_clear ; H=0 N=1 Z=0 C=0
382 test_h_gr32 0xa5a5a505 er1
383 test_gr_a5a5 0 ; Make sure other general regs not disturbed
390 ; 1010 0101 -> 1001 0110
391 cmp.b #0x96, @byte_dest
395 mov.b #0xa5, @byte_dest
398 set_grs_a5a5 ; Fill all general regs with a fixed pattern
402 rotl.b #2, @(byte_dest-256:32, r1.w) ; indexed byte/word
404 test_carry_clear ; H=0 N=1 Z=0 C=0
409 test_h_gr32 0xa5a50100 er1
410 test_gr_a5a5 0 ; Make sure other general regs not disturbed
417 ; 1010 0101 -> 1001 0110
418 cmp.b #0x96, @byte_dest
422 mov.b #0xa5, @byte_dest
425 set_grs_a5a5 ; Fill all general regs with a fixed pattern
428 mov.l #0xffffffff, er1
429 rotl.b #2, @(byte_dest+1:32, er1.l) ; indexed byte/long
431 test_carry_clear ; H=0 N=1 Z=0 C=0
436 test_h_gr32 0xffffffff er1
437 test_gr_a5a5 0 ; Make sure other general regs not disturbed
444 ; 1010 0101 -> 1001 0110
445 cmp.b #0x96, @byte_dest
449 mov.b #0xa5, @byte_dest
453 .if (sim_cpu) ; Not available in h8300 mode
455 set_grs_a5a5 ; Fill all general regs with a fixed pattern
458 rotl.w r0 ; shift left arithmetic by one
460 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
464 test_h_gr16 0x4b4b r0 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
465 test_h_gr32 0xa5a54b4b er0
467 test_gr_a5a5 1 ; Make sure other general regs not disturbed
475 .if (sim_cpu == h8sx)
477 set_grs_a5a5 ; Fill all general regs with a fixed pattern
481 rotl.w @(word_dest-10:16, r0.b) ; indexed word/byte
483 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
488 test_h_gr32 0xa5a5a505 er0
489 test_gr_a5a5 1 ; Make sure other general regs not disturbed
496 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
497 cmp.w #0x4b4b, @word_dest
501 mov.w #0xa5a5, @word_dest
504 set_grs_a5a5 ; Fill all general regs with a fixed pattern
508 rotl.w @(word_dest-512:16, r0.w) ; indexed word/word
510 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
515 test_h_gr32 0xa5a50100 er0
516 test_gr_a5a5 1 ; Make sure other general regs not disturbed
523 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
524 cmp.w #0x4b4b, @word_dest
528 mov.w #0xa5a5, @word_dest
531 set_grs_a5a5 ; Fill all general regs with a fixed pattern
534 mov.l #0xffffffff, er0
535 rotl.w @(word_dest+2:16, er0.l) ; indexed word/long
537 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
542 test_h_gr32 0xffffffff er0
543 test_gr_a5a5 1 ; Make sure other general regs not disturbed
550 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
551 cmp.w #0x4b4b, @word_dest
555 mov.w #0xa5a5, @word_dest
558 set_grs_a5a5 ; Fill all general regs with a fixed pattern
562 rotl.w @(word_dest-10:32, r1.b) ; indexed word/byte
564 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
569 test_h_gr32 0xa5a5a505 er1
570 test_gr_a5a5 0 ; Make sure other general regs not disturbed
577 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
578 cmp.w #0x4b4b, @word_dest
582 mov.w #0xa5a5, @word_dest
585 set_grs_a5a5 ; Fill all general regs with a fixed pattern
589 rotl.w @(word_dest-512:32, r1.w) ; indexed word/byte
591 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
596 test_h_gr32 0xa5a50100 er1
597 test_gr_a5a5 0 ; Make sure other general regs not disturbed
604 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
605 cmp.w #0x4b4b, @word_dest
609 mov.w #0xa5a5, @word_dest
612 set_grs_a5a5 ; Fill all general regs with a fixed pattern
615 mov.l #0xffffffff, er1
616 rotl.w @(word_dest+2:32, er1.l) ; indexed word/byte
618 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
623 test_h_gr32 0xffffffff er1
624 test_gr_a5a5 0 ; Make sure other general regs not disturbed
631 ; 1010 0101 1010 0101 -> 0100 1011 0100 1011
632 cmp.w #0x4b4b, @word_dest
636 mov.w #0xa5a5, @word_dest
640 set_grs_a5a5 ; Fill all general regs with a fixed pattern
643 rotl.w #2, r0 ; shift left arithmetic by two
645 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
649 test_h_gr16 0x9696 r0 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
650 test_h_gr32 0xa5a59696 er0
652 test_gr_a5a5 1 ; Make sure other general regs not disturbed
660 .if (sim_cpu == h8sx)
662 set_grs_a5a5 ; Fill all general regs with a fixed pattern
666 rotl.w #2, @(word_dest-10:16, r0.b) ; indexed word/byte
668 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
673 test_h_gr32 0xa5a5a505 er0
674 test_gr_a5a5 1 ; Make sure other general regs not disturbed
681 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
682 cmp.w #0x9696, @word_dest
686 mov.w #0xa5a5, @word_dest
689 set_grs_a5a5 ; Fill all general regs with a fixed pattern
693 rotl.w #2, @(word_dest-512:16, r0.w) ; indexed word/word
695 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
700 test_h_gr32 0xa5a50100 er0
701 test_gr_a5a5 1 ; Make sure other general regs not disturbed
708 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
709 cmp.w #0x9696, @word_dest
713 mov.w #0xa5a5, @word_dest
716 set_grs_a5a5 ; Fill all general regs with a fixed pattern
719 mov.l #0xffffffff, er0
720 rotl.w #2, @(word_dest+2:16, er0.l) ; indexed word/long
722 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
727 test_h_gr32 0xffffffff er0
728 test_gr_a5a5 1 ; Make sure other general regs not disturbed
735 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
736 cmp.w #0x9696, @word_dest
740 mov.w #0xa5a5, @word_dest
743 set_grs_a5a5 ; Fill all general regs with a fixed pattern
747 rotl.w #2, @(word_dest-10:32, r1.b) ; indexed word/byte
749 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
754 test_h_gr32 0xa5a5a505 er1
755 test_gr_a5a5 0 ; Make sure other general regs not disturbed
762 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
763 cmp.w #0x9696, @word_dest
767 mov.w #0xa5a5, @word_dest
770 set_grs_a5a5 ; Fill all general regs with a fixed pattern
774 rotl.w #2, @(word_dest-512:32, r1.w) ; indexed word/byte
776 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
781 test_h_gr32 0xa5a50100 er1
782 test_gr_a5a5 0 ; Make sure other general regs not disturbed
789 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
790 cmp.w #0x9696, @word_dest
794 mov.w #0xa5a5, @word_dest
797 set_grs_a5a5 ; Fill all general regs with a fixed pattern
800 mov.l #0xffffffff, er1
801 rotl.w #2, @(word_dest+2:32, er1.l) ; indexed word/byte
803 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
808 test_h_gr32 0xffffffff er1
809 test_gr_a5a5 0 ; Make sure other general regs not disturbed
816 ; 1010 0101 1010 0101 -> 1001 0110 1001 0110
817 cmp.w #0x9696, @word_dest
821 mov.w #0xa5a5, @word_dest
825 set_grs_a5a5 ; Fill all general regs with a fixed pattern
828 rotl.l er0 ; shift left arithmetic by one
830 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
834 ; 1010 0101 1010 0101 1010 0101 1010 0101
835 ; -> 0100 1011 0100 1011 0100 1011 0100 1011
836 test_h_gr32 0x4b4b4b4b er0
838 test_gr_a5a5 1 ; Make sure other general regs not disturbed
846 .if (sim_cpu == h8sx)
848 set_grs_a5a5 ; Fill all general regs with a fixed pattern
852 rotl.l @(long_dest-20:16, er0.b) ; indexed long/byte
854 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
859 test_h_gr32 0xa5a5a505 er0
860 test_gr_a5a5 1 ; Make sure other general regs not disturbed
867 ; 1010 0101 1010 0101 1010 0101 1010 0101
868 ; -> 0100 1011 0100 1011 0100 1011 0100 1011
869 cmp.l #0x4b4b4b4b, @long_dest
873 mov.l #0xa5a5a5a5, @long_dest
876 set_grs_a5a5 ; Fill all general regs with a fixed pattern
880 rotl.l @(long_dest-1024:16, er0.w) ; indexed long/word
882 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
887 test_h_gr32 0xa5a50100 er0
888 test_gr_a5a5 1 ; Make sure other general regs not disturbed
895 ; 1010 0101 1010 0101 1010 0101 1010 0101
896 ; -> 0100 1011 0100 1011 0100 1011 0100 1011
897 cmp.l #0x4b4b4b4b, @long_dest
901 mov.l #0xa5a5a5a5, @long_dest
904 set_grs_a5a5 ; Fill all general regs with a fixed pattern
907 mov.l #0xffffffff, er0
908 rotl.l @(long_dest+4:16, er0.l) ; indexed long/long
910 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
915 test_h_gr32 0xffffffff er0
916 test_gr_a5a5 1 ; Make sure other general regs not disturbed
923 ; 1010 0101 1010 0101 1010 0101 1010 0101
924 ; -> 0100 1011 0100 1011 0100 1011 0100 1011
925 cmp.l #0x4b4b4b4b, @long_dest
929 mov.l #0xa5a5a5a5, @long_dest
932 set_grs_a5a5 ; Fill all general regs with a fixed pattern
936 rotl.l @(long_dest-20:32, er1.b) ; indexed long/byte
938 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
943 test_h_gr32 0xa5a5a505 er1
944 test_gr_a5a5 0 ; Make sure other general regs not disturbed
951 ; 1010 0101 1010 0101 1010 0101 1010 0101
952 ; -> 0100 1011 0100 1011 0100 1011 0100 1011
953 cmp.l #0x4b4b4b4b, @long_dest
957 mov.l #0xa5a5a5a5, @long_dest
960 set_grs_a5a5 ; Fill all general regs with a fixed pattern
964 rotl.l @(long_dest-1024:32, er1.w) ; indexed long/byte
966 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
971 test_h_gr32 0xa5a50100 er1
972 test_gr_a5a5 0 ; Make sure other general regs not disturbed
979 ; 1010 0101 1010 0101 1010 0101 1010 0101
980 ; -> 0100 1011 0100 1011 0100 1011 0100 1011
981 cmp.l #0x4b4b4b4b, @long_dest
985 mov.l #0xa5a5a5a5, @long_dest
988 set_grs_a5a5 ; Fill all general regs with a fixed pattern
991 mov.l #0xffffffff, er1
992 rotl.l @(long_dest+4:32, er1.l) ; indexed long/byte
994 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
999 test_h_gr32 0xffffffff er1
1000 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1007 ; 1010 0101 1010 0101 1010 0101 1010 0101
1008 ; -> 0100 1011 0100 1011 0100 1011 0100 1011
1009 cmp.l #0x4b4b4b4b, @long_dest
1013 mov.l #0xa5a5a5a5, @long_dest
1017 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1020 rotl.l #2, er0 ; shift left arithmetic by two
1022 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1026 ; 1010 0101 1010 0101 1010 0101 1010 0101
1027 ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1028 test_h_gr32 0x96969696 er0
1030 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1038 .if (sim_cpu == h8sx)
1040 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1044 rotl.l #2, @(long_dest-20:16, er0.b) ; indexed long/byte
1046 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1051 test_h_gr32 0xa5a5a505 er0
1052 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1059 ; 1010 0101 1010 0101 1010 0101 1010 0101
1060 ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1061 cmp.l #0x96969696, @long_dest
1065 mov.l #0xa5a5a5a5, @long_dest
1068 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1072 rotl.l #2, @(long_dest-1024:16, er0.w) ; indexed long/word
1074 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1079 test_h_gr32 0xa5a50100 er0
1080 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1087 ; 1010 0101 1010 0101 1010 0101 1010 0101
1088 ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1089 cmp.l #0x96969696, @long_dest
1093 mov.l #0xa5a5a5a5, @long_dest
1096 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1099 mov.l #0xffffffff, er0
1100 rotl.l #2, @(long_dest+4:16, er0.l) ; indexed long/long
1102 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1107 test_h_gr32 0xffffffff er0
1108 test_gr_a5a5 1 ; Make sure other general regs not disturbed
1115 ; 1010 0101 1010 0101 1010 0101 1010 0101
1116 ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1117 cmp.l #0x96969696, @long_dest
1121 mov.l #0xa5a5a5a5, @long_dest
1124 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1128 rotl.l #2, @(long_dest-20:32, er1.b) ; indexed long/byte
1130 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1135 test_h_gr32 0xa5a5a505 er1
1136 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1143 ; 1010 0101 1010 0101 1010 0101 1010 0101
1144 ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1145 cmp.l #0x96969696, @long_dest
1149 mov.l #0xa5a5a5a5, @long_dest
1152 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1156 rotl.l #2, @(long_dest-1024:32, er1.w) ; indexed long/byte
1158 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1163 test_h_gr32 0xa5a50100 er1
1164 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1171 ; 1010 0101 1010 0101 1010 0101 1010 0101
1172 ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1173 cmp.l #0x96969696, @long_dest
1177 mov.l #0xa5a5a5a5, @long_dest
1180 set_grs_a5a5 ; Fill all general regs with a fixed pattern
1183 mov.l #0xffffffff, er1
1184 rotl.l #2, @(long_dest+4:32, er1.l) ; indexed long/byte
1186 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
1191 test_h_gr32 0xffffffff er1
1192 test_gr_a5a5 0 ; Make sure other general regs not disturbed
1199 ; 1010 0101 1010 0101 1010 0101 1010 0101
1200 ; -> 1001 0110 1001 0110 1001 0110 1001 0110
1201 cmp.l #0x96969696, @long_dest
1205 mov.l #0xa5a5a5a5, @long_dest