1 # Hitachi H8 testcase 'or.w'
2 # mach(): h8300h h8300s h8sx
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
15 .if (sim_cpu) ; non-zero means h8300h, s, or sx
17 set_grs_a5a5 ; Fill all general regs with a fixed pattern
21 or.w #0xaaaa, r0 ; Immediate 16-bit operand
23 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
24 test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa
25 .if (sim_cpu) ; non-zero means h8300h, s, or sx
26 test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa
28 test_gr_a5a5 1 ; Make sure other general regs not disturbed
38 set_grs_a5a5 ; Fill all general regs with a fixed pattern
43 or.w r1, r0 ; Register operand
45 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
46 test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa
47 test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged
48 .if (sim_cpu) ; non-zero means h8300h, s, or sx
49 test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa
50 test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged
52 test_gr_a5a5 2 ; Make sure other general regs not disturbed