1 # Hitachi H8 testcase 'or.b'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
13 # Instructions tested:
14 # or.b #xx:8, rd ; c rd xxxxxxxx
15 # or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx
16 # or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx
17 # or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx
18 # or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx
19 # or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx
20 # or.b rs, rd ; 1 4 rs rd
21 # or.b reg8, @erd ; 7 d rd ???? 1 4 rs ????
22 # or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs
23 # or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs
24 # or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs
25 # or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs
42 set_grs_a5a5 ; Fill all general regs with a fixed pattern
46 or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest
48 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
49 test_h_gr16 0xa5af r0 ; or result: a5 | aa
50 .if (sim_cpu) ; non-zero means h8300h, s, or sx
51 test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa
53 test_gr_a5a5 1 ; Make sure other general regs not disturbed
67 set_grs_a5a5 ; Fill all general regs with a fixed pattern
72 or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst
76 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
81 test_h_gr32 byte_dest, er0 ; er0 still contains address
82 test_gr_a5a5 1 ; Make sure other general regs not disturbed
90 ;; Now check the result of the or to memory.
103 set_grs_a5a5 ; Fill all general regs with a fixed pattern
108 or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
113 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
118 test_h_gr32 post_byte, er0 ; er0 contains address plus one
119 test_gr_a5a5 1 ; Make sure other general regs not disturbed
127 ;; Now check the result of the or to memory.
129 mov.b @byte_dest, r0l
140 set_grs_a5a5 ; Fill all general regs with a fixed pattern
145 or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest
150 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
155 test_h_gr32 pre_byte, er0 ; er0 contains address minus one
156 test_gr_a5a5 1 ; Make sure other general regs not disturbed
164 ;; Now check the result of the or to memory.
166 mov.b @byte_dest, r0l
177 set_grs_a5a5 ; Fill all general regs with a fixed pattern
182 or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest
187 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
192 test_h_gr32 byte_dest, er0 ; er0 contains destination address
193 test_gr_a5a5 1 ; Make sure other general regs not disturbed
201 ;; Now check the result of the or to memory.
203 mov.b @byte_dest, r0l
214 set_grs_a5a5 ; Fill all general regs with a fixed pattern
219 or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest
224 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
229 test_h_gr32 byte_dest, er0 ; er0 contains destination address
230 test_gr_a5a5 1 ; Make sure other general regs not disturbed
238 ;; Now check the result of the or to memory.
240 mov.b @byte_dest, r0l
250 set_grs_a5a5 ; Fill all general regs with a fixed pattern
255 or.b r0h, r0l ; Reg8 src, reg8 dest
257 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
258 test_h_gr16 0xaaaf r0 ; or result: a5 | aa
259 .if (sim_cpu) ; non-zero means h8300h, s, or sx
260 test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa
262 test_gr_a5a5 1 ; Make sure other general regs not disturbed
270 .if (sim_cpu == h8sx)
276 set_grs_a5a5 ; Fill all general regs with a fixed pattern
279 ;; or.b rs8,@eRd ; or reg8 to register indirect
282 or.b r1l, @er0 ; reg8 src, reg indirect dest
286 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
291 test_h_gr32 byte_dest er0 ; er0 still contains address
292 test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
294 test_gr_a5a5 2 ; Make sure other general regs not disturbed
301 ;; Now check the result of the or to memory.
303 mov.b @byte_dest, r0l
314 set_grs_a5a5 ; Fill all general regs with a fixed pattern
317 ;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment
320 or.b r1l, @er0+ ; reg8 src, reg post-incr dest
324 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
329 test_h_gr32 post_byte er0 ; er0 contains address plus one
330 test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
332 test_gr_a5a5 2 ; Make sure other general regs not disturbed
339 ;; Now check the result of the or to memory.
341 mov.b @byte_dest, r0l
352 set_grs_a5a5 ; Fill all general regs with a fixed pattern
355 ;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement
358 or.b r1l, @er0- ; reg8 src, reg post-decr dest
362 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
367 test_h_gr32 pre_byte er0 ; er0 contains address minus one
368 test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
370 test_gr_a5a5 2 ; Make sure other general regs not disturbed
377 ;; Now check the result of the or to memory.
379 mov.b @byte_dest, r0l
390 set_grs_a5a5 ; Fill all general regs with a fixed pattern
393 ;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment
396 or.b r1l, @+er0 ; reg8 src, reg pre-incr dest
400 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
405 test_h_gr32 byte_dest er0 ; er0 contains destination address
406 test_h_gr32 0xa5a5a555 er1 ; er1 has the test load
408 test_gr_a5a5 2 ; Make sure other general regs not disturbed
415 ;; Now check the result of the or to memory.
417 mov.b @byte_dest, r0l
428 set_grs_a5a5 ; Fill all general regs with a fixed pattern
431 ;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement
434 or.b r1l, @-er0 ; reg8 src, reg pre-decr dest
438 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
443 test_h_gr32 byte_dest er0 ; er0 contains destination address
444 test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load
446 test_gr_a5a5 2 ; Make sure other general regs not disturbed
453 ;; Now check the result of the or to memory.
455 mov.b @byte_dest, r0l
464 set_grs_a5a5 ; Fill all general regs with a fixed pattern
470 orc #0x8, ccr ; Immediate 8-bit operand (neg flag)
474 orc #0x4, ccr ; Immediate 8-bit operand (zero flag)
478 orc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
482 orc #0x1, ccr ; Immediate 8-bit operand (carry flag)
485 test_gr_a5a5 0 ; Make sure other general regs not disturbed
494 .if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
496 set_grs_a5a5 ; Fill all general regs with a fixed pattern
520 test_h_gr32 0xa5a5a587 er0
521 test_gr_a5a5 1 ; Make sure other general regs not disturbed
528 .endif ; not h8300 or h8300h