1 # Hitachi H8 testcase 'neg.b, neg.w, neg.l'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
13 # Instructions tested:
15 # neg.b @erd ; 7 d rd ???? 1 7 8 ignore
16 # neg.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 8 ignore
17 # neg.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 8 ignore
18 # neg.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 8 ignore
19 # neg.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 8 ignore
20 # neg.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 8 ignore
21 # neg.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 8 ignore
22 # neg.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 8 ignore
23 # neg.b @aa:16 ; 6 a 1 1??? aa:16 1 7 8 ignore
24 # neg.b @aa:32 ; 6 a 3 1??? aa:32 1 7 8 ignore
29 # neg.b @aa:8 ; 7 f aaaaaaaa 1 7 8 ignore
35 word_dest: .word 0xa5a5
37 long_dest: .long 0xa5a5a5a5
41 # Note: apparently carry is set for neg of anything except zero.
45 # 8-bit byte operations
49 set_grs_a5a5 ; Fill all general regs with a fixed pattern
53 neg r0l ; 8-bit register
56 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
61 cmp.b #0x5b, r0l ; result of "neg 0xa5"
65 test_h_gr16 0xa55b r0 ; r0 changed by 'neg'
66 .if (sim_cpu) ; non-zero means h8300h, s, or sx
67 test_h_gr32 0xa5a5a55b er0 ; er0 changed by 'neg'
69 test_gr_a5a5 1 ; Make sure other general regs not disturbed
79 set_grs_a5a5 ; Fill all general regs with a fixed pattern
84 neg.b @er0 ; register indirect operand
88 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
93 test_h_gr32 byte_dest er0 ; er0 still contains address
94 cmp.b #0x5b, @er0 ; memory contents changed
98 test_gr_a5a5 1 ; Make sure other general regs not disturbed
107 set_grs_a5a5 ; Fill all general regs with a fixed pattern
111 mov #byte_dest, er0 ; register post-increment operand
117 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
122 test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one
127 test_gr_a5a5 1 ; Make sure other general regs not disturbed
136 set_grs_a5a5 ; Fill all general regs with a fixed pattern
140 mov #byte_dest, er0 ; register post-decrement operand
146 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
151 test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
156 test_gr_a5a5 1 ; Make sure other general regs not disturbed
165 set_grs_a5a5 ; Fill all general regs with a fixed pattern
169 mov #byte_dest-1, er0
170 neg.b @+er0 ; reg pre-increment operand
175 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
184 test_h_gr32 byte_dest er0 ; er0 contains destination address
185 test_gr_a5a5 1 ; Make sure other general regs not disturbed
194 set_grs_a5a5 ; Fill all general regs with a fixed pattern
198 mov #byte_dest+1, er0
199 neg.b @-er0 ; reg pre-decr operand
204 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
213 test_h_gr32 byte_dest er0 ; er0 contains destination address
214 test_gr_a5a5 1 ; Make sure other general regs not disturbed
223 set_grs_a5a5 ; Fill all general regs with a fixed pattern
226 ;; neg.b @(dd:2, erd)
227 mov #byte_dest-1, er0
228 neg.b @(1:2, er0) ; reg plus 2-bit displacement
233 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
242 test_h_gr32 byte_dest er0 ; er0 contains destination address
243 test_gr_a5a5 1 ; Make sure other general regs not disturbed
252 set_grs_a5a5 ; Fill all general regs with a fixed pattern
255 ;; neg.b @(dd:16, erd)
256 mov #byte_dest+100, er0
257 neg.b @(-100:16, er0) ; reg plus 16-bit displacement
263 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
268 cmp.b #0x5b, @byte_dest
272 test_h_gr32 byte_dest+100 er0 ; er0 contains destination address
273 test_gr_a5a5 1 ; Make sure other general regs not disturbed
282 set_grs_a5a5 ; Fill all general regs with a fixed pattern
285 ;; neg.b @(dd:32, erd)
286 mov #byte_dest-0xfffff, er0
287 neg.b @(0xfffff:32, er0) ; reg plus 32-bit displacement
293 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
298 cmp.b #0xa5, @byte_dest
302 test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address
303 test_gr_a5a5 1 ; Make sure other general regs not disturbed
312 set_grs_a5a5 ; Fill all general regs with a fixed pattern
316 neg.b @byte_dest:16 ; 16-bit absolute address
321 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
326 cmp.b #0x5b, @byte_dest
330 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
340 set_grs_a5a5 ; Fill all general regs with a fixed pattern
344 neg.b @byte_dest:32 ; 32-bit absolute address
349 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
354 cmp.b #0xa5, @byte_dest
358 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
369 # 16-bit word operations
372 .if (sim_cpu) ; any except plain-vanilla h8/300
374 set_grs_a5a5 ; Fill all general regs with a fixed pattern
378 neg r1 ; 16-bit register operand
381 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
386 cmp.w #0x5a5b, r1 ; result of "neg 0xa5a5"
390 test_h_gr32 0xa5a55a5b er1 ; er1 changed by 'neg'
391 test_gr_a5a5 0 ; Make sure other general regs not disturbed
399 .if (sim_cpu == h8sx)
401 set_grs_a5a5 ; Fill all general regs with a fixed pattern
406 neg.w @er1 ; register indirect operand
411 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
416 cmp.w #0x5a5b, @word_dest ; memory contents changed
420 test_h_gr32 word_dest er1 ; er1 still contains address
421 test_gr_a5a5 0 ; Make sure other general regs not disturbed
430 set_grs_a5a5 ; Fill all general regs with a fixed pattern
434 mov #word_dest, er1 ; register post-increment operand
440 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
445 cmp.w #0xa5a5, @word_dest
449 test_h_gr32 word_dest+2 er1 ; er1 contains address plus two
450 test_gr_a5a5 0 ; Make sure other general regs not disturbed
459 set_grs_a5a5 ; Fill all general regs with a fixed pattern
469 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
474 cmp.w #0x5a5b, @word_dest
478 test_h_gr32 word_dest-2 er1 ; er1 contains address minus two
479 test_gr_a5a5 0 ; Make sure other general regs not disturbed
488 set_grs_a5a5 ; Fill all general regs with a fixed pattern
492 mov #word_dest-2, er1
493 neg.w @+er1 ; reg pre-increment operand
498 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
503 cmp.w #0xa5a5, @word_dest
507 test_h_gr32 word_dest er1 ; er1 contains destination address
508 test_gr_a5a5 0 ; Make sure other general regs not disturbed
517 set_grs_a5a5 ; Fill all general regs with a fixed pattern
521 mov #word_dest+2, er1
522 neg.w @-er1 ; reg pre-decr operand
527 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
532 cmp.w #0x5a5b, @word_dest
536 test_h_gr32 word_dest er1 ; er1 contains destination address
537 test_gr_a5a5 0 ; Make sure other general regs not disturbed
546 set_grs_a5a5 ; Fill all general regs with a fixed pattern
549 ;; neg.w @(dd:2, erd)
550 mov #word_dest-2, er1
551 neg.w @(2:2, er1) ; reg plus 2-bit displacement
556 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
561 cmp.w #0xa5a5, @word_dest
565 test_h_gr32 word_dest-2 er1 ; er1 contains address minus one
566 test_gr_a5a5 0 ; Make sure other general regs not disturbed
575 set_grs_a5a5 ; Fill all general regs with a fixed pattern
578 ;; neg.w @(dd:16, erd)
579 mov #word_dest+100, er1
580 neg.w @(-100:16, er1) ; reg plus 16-bit displacement
586 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
591 cmp.w #0x5a5b, @word_dest
595 test_h_gr32 word_dest+100 er1 ; er1 contains destination address
596 test_gr_a5a5 0 ; Make sure other general regs not disturbed
605 set_grs_a5a5 ; Fill all general regs with a fixed pattern
608 ;; neg.w @(dd:32, erd)
609 mov #word_dest-0xfffff, er1
610 neg.w @(0xfffff:32, er1) ; reg plus 32-bit displacement
616 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
621 cmp.w #0xa5a5, @word_dest
625 test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address
626 test_gr_a5a5 0 ; Make sure other general regs not disturbed
635 set_grs_a5a5 ; Fill all general regs with a fixed pattern
639 neg.w @word_dest:16 ; 16-bit absolute address
644 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
649 cmp.w #0x5a5b, @word_dest
653 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
663 set_grs_a5a5 ; Fill all general regs with a fixed pattern
667 neg.w @word_dest:32 ; 32-bit absolute address
672 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
677 cmp.w #0xa5a5, @word_dest
681 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
694 # 32-bit word operations
697 .if (sim_cpu) ; any except plain-vanilla h8/300
699 set_grs_a5a5 ; Fill all general regs with a fixed pattern
703 neg er1 ; 32-bit register operand
706 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
711 cmp.l #0x5a5a5a5b, er1 ; result of "neg 0xa5a5a5a5"
715 test_h_gr32 0x5a5a5a5b er1 ; er1 changed by 'neg'
716 test_gr_a5a5 0 ; Make sure other general regs not disturbed
724 .if (sim_cpu == h8sx)
726 set_grs_a5a5 ; Fill all general regs with a fixed pattern
731 neg.l @er1 ; register indirect operand
736 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
741 cmp.l #0x5a5a5a5b, @long_dest ; memory contents changed
745 test_h_gr32 long_dest er1 ; er1 still contains address
746 test_gr_a5a5 0 ; Make sure other general regs not disturbed
755 set_grs_a5a5 ; Fill all general regs with a fixed pattern
759 mov #long_dest, er1 ; register post-increment operand
765 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
770 cmp.l #0xa5a5a5a5, @long_dest
774 test_h_gr32 long_dest+4 er1 ; er1 contains address plus two
775 test_gr_a5a5 0 ; Make sure other general regs not disturbed
784 set_grs_a5a5 ; Fill all general regs with a fixed pattern
794 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
799 cmp.l #0x5a5a5a5b, @long_dest
803 test_h_gr32 long_dest-4 er1 ; er1 contains address minus two
804 test_gr_a5a5 0 ; Make sure other general regs not disturbed
813 set_grs_a5a5 ; Fill all general regs with a fixed pattern
817 mov #long_dest-4, er1
818 neg.l @+er1 ; reg pre-increment operand
823 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
828 cmp.l #0xa5a5a5a5, @long_dest
832 test_h_gr32 long_dest er1 ; er1 contains destination address
833 test_gr_a5a5 0 ; Make sure other general regs not disturbed
842 set_grs_a5a5 ; Fill all general regs with a fixed pattern
846 mov #long_dest+4, er1
847 neg.l @-er1 ; reg pre-decr operand
852 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
857 cmp.l #0x5a5a5a5b, @long_dest
861 test_h_gr32 long_dest er1 ; er1 contains destination address
862 test_gr_a5a5 0 ; Make sure other general regs not disturbed
871 set_grs_a5a5 ; Fill all general regs with a fixed pattern
874 ;; neg.l @(dd:2, erd)
875 mov #long_dest-4, er1
876 neg.l @(4:2, er1) ; reg plus 2-bit displacement
881 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
886 cmp.l #0xa5a5a5a5, @long_dest
890 test_h_gr32 long_dest-4 er1 ; er1 contains address minus one
891 test_gr_a5a5 0 ; Make sure other general regs not disturbed
900 set_grs_a5a5 ; Fill all general regs with a fixed pattern
903 ;; neg.l @(dd:16, erd)
904 mov #long_dest+100, er1
905 neg.l @(-100:16, er1) ; reg plus 16-bit displacement
911 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
916 cmp.l #0x5a5a5a5b, @long_dest
920 test_h_gr32 long_dest+100 er1 ; er1 contains destination address
921 test_gr_a5a5 0 ; Make sure other general regs not disturbed
930 set_grs_a5a5 ; Fill all general regs with a fixed pattern
933 ;; neg.l @(dd:32, erd)
934 mov #long_dest-0xfffff, er1
935 neg.l @(0xfffff:32, er1) ; reg plus 32-bit displacement
941 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
946 cmp.l #0xa5a5a5a5, @long_dest
950 test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address
951 test_gr_a5a5 0 ; Make sure other general regs not disturbed
960 set_grs_a5a5 ; Fill all general regs with a fixed pattern
964 neg.l @long_dest:16 ; 16-bit absolute address
970 test_carry_set ; H=0 N=0 Z=0 V=0 C=1
975 cmp.l #0x5a5a5a5b, @long_dest
979 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
989 set_grs_a5a5 ; Fill all general regs with a fixed pattern
993 neg.l @long_dest:32 ; 32-bit absolute address
999 test_carry_set ; H=0 N=1 Z=0 V=0 C=1
1004 cmp.l #0xa5a5a5a5, @long_dest
1008 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed