1 # Hitachi H8 testcase 'inc, inc.w, inc.l'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
16 set_grs_a5a5 ; Fill all general regs with a fixed pattern
20 inc.b r0h ; Increment 8-bit reg by one
22 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
23 test_h_gr16 0xa6a5 r0 ; inc result: a6|a5
24 .if (sim_cpu) ; non-zero means h8300h, s, or sx
25 test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5
27 test_gr_a5a5 1 ; Make sure other general regs not disturbed
35 .if (sim_cpu) ; non-zero means h8300h, s, or sx
37 set_grs_a5a5 ; Fill all general regs with a fixed pattern
41 inc.w #1, r0 ; Increment 16-bit reg by one
43 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
44 test_h_gr16 0xa5a6 r0 ; inc result: a5|a6
46 test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
48 test_gr_a5a5 1 ; Make sure other general regs not disturbed
57 set_grs_a5a5 ; Fill all general regs with a fixed pattern
61 inc.w #2, r0 ; Increment 16-bit reg by two
63 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
64 test_h_gr16 0xa5a7 r0 ; inc result: a5|a7
66 test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
68 test_gr_a5a5 1 ; Make sure other general regs not disturbed
77 set_grs_a5a5 ; Fill all general regs with a fixed pattern
81 inc.l #1, er0 ; Increment 32-bit reg by one
83 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
85 test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6
87 test_gr_a5a5 1 ; Make sure other general regs not disturbed
96 set_grs_a5a5 ; Fill all general regs with a fixed pattern
100 inc.l #2, er0 ; Increment 32-bit reg by two
102 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
104 test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7
106 test_gr_a5a5 1 ; Make sure other general regs not disturbed