1 # Hitachi H8 testcase 'cmp.w'
2 # mach(): h8300h h8300s h8sx
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
15 .if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
17 set_grs_a5a5 ; Fill all general regs with a fixed pattern
20 ;; cmp.l #xx:3,eRd ; Immediate 3-bit operand
35 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
37 test_h_gr32 0x00000005 er0 ; er0 unchanged
38 test_gr_a5a5 1 ; Make sure other general regs not disturbed
48 set_grs_a5a5 ; Fill all general regs with a fixed pattern
52 cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand
55 eqi: cmp.l #0xa5a5a5a6, er0
58 lti: cmp.l #0xa5a5a5a4, er0
62 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
64 test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged
66 test_gr_a5a5 1 ; Make sure other general regs not disturbed
75 set_grs_a5a5 ; Fill all general regs with a fixed pattern
79 mov.l #0xa5a5a5a5, er1
80 cmp.l er1, er0 ; Register operand
83 eqr: mov.l #0xa5a5a5a6, er1
87 ltr: mov.l #0xa5a5a5a4, er1
92 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
94 test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged
95 test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged
97 test_gr_a5a5 2 ; Make sure other general regs not disturbed